IDT IDT7035S High-speed 8k x 18 dual-port static ram Datasheet

HIGH-SPEED
8K x 18 DUAL-PORT
STATIC RAM
Features
◆
◆
◆
◆
◆
True Dual-Ported memory cells which allow simultaneous
reads of the same memory location
High-speed access
– Commercial: 15/20ns (max.)
Low-power operation
– IDT7035S
Active: 800mW (typ.)
Standby: 5mW (typ.)
– IDT7035L
Active: 800mW (typ.)
Standby: 1mW (typ.)
Separate upper-byte and lower-byte control for multiplexed
bus compatibility
IDT7035 easily expands data bus width to 36 bits or more
◆
◆
◆
◆
◆
◆
◆
◆
IDT7035S/L
using the Master/Slave select when cascading more than
one device
M/S = H for BUSY output flag on Master
M/S = L for BUSY input on Slave
Interrupt Flag
On-chip port arbitration logic
Full on-chip hardware support of semaphore signaling
between ports
Fully asynchronous operation from either port
Battery backup operation—2V data retention
TTL-compatible, single 5V (±10%) power supply
Available in 100-pin Thin Quad Flatpack
Industrial temperature range (–40°C to +85°C) is available
for selected speeds
Functional Block Diagram
R/WL
R/WR
LBL
CEL
OEL
LBR
CER
OER
UBL
UBR
I/O9L-I/O17L
I/O9R-I/O17R
I/O
Control
I/O0L-I/O8L
I/O
Control
I/O0R-I/O8R
(1,2)
(1,2)
BUSYL
A12L
A0L
BUSYR
Address
Decoder
MEMORY
ARRAY
13
CEL
OEL
R/WL
SEML
(2)
INTL
Address
Decoder
A12R
A0R
13
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
M/S
CER
OER
R/WR
SEMR
INTR (2)
4088 drw 01
NOTES:
1. (MASTER): BUSY is output; (SLAVE): BUSY is input.
2. BUSY outputs and INT outputs are non-tri-stated push-pull.
SEPTEMBER 1999
1
©1999 Integrated Device Technology, Inc.
DSC 4088/5
IDT7035S/L
High-Speed 8K x 18 Dual-Port Static RAM
Description
Industrial and Commercial Temperature Ranges
The IDT7035 is a high-speed 8K x 18 Dual-Port Static RAM. The
IDT7035 is designed to be used as a stand-alone 144K-bit Dual-Port RAM
or as a combination MASTER/SLAVE Dual-Port RAM for 36-bit or more
word systems. Using the IDT MASTER/SLAVE Dual-Port RAM approach
in 36-bit or wider memory system applications results in full-speed, errorfree operation without the need for additional discrete logic.
This device provides two independent ports with separate control,
address, and I/O pins that permit independent, asynchronous access for
reads or writes to any location in memory. An automatic power down
feature controlled by Chip Enable (CE) permits the on-chip circuitry of each
port to enter a very low standby power mode.
The IDT7035 utilizes a 18-bit wide data path to alow for parity at the
user's option. This feature is especially useful in data communications
applications where it is necessary to use a parity bit for transmission/
reception error checking.
Fabricated using IDT’s CMOS high-performance technology, these
devices typically operate on only 800mW of power. Low-power (L)
versions offer battery backup data retention capability with typical power
consumption of 500µW from a 2V battery.
I/O10L
I/O9L
I/O7L
I/O6L
I/O5L
I/O4L
I/O3L
I/O2L
GND
I/O1L
I/O0L
OEL
VCC
R/WL
SEML
CEL
UBL
LBL
A12L
A11L
A10L
A9L
A8L
A7L
A6L
Pin Configurations(1,2,3)
Index
2
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
75
74
3
73
4
72
5
71
6
70
7
69
8
68
9
67
1
10
11
12
13
14
IDT7035PF
PN100-1(4)
100-Pin TQFP
Top View(5)
66
65
64
63
62
15
61
16
60
17
59
18
58
19
57
20
56
21
55
22
54
23
53
24
52
51
25
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
I/O7R
I/O9R
I/O10R
I/O11R
I/O12R
I/O13R
I/O14R
I/O15R
GND
I/O16R
OER
R/WR
GND
SEMR
CER
UBR
LBR
A12R
A11R
A10R
A9R
A8R
A7R
A6R
A5R
N/C
N/C
I/O8L
I/O17L
I/O11L
I/O12L
I/O13L
I/O14L
GND
I/O15L
I/O16L
VCC
GND
I/O0R
I/O1R
I/O2R
VCC
I/O3R
I/O4R
I/O5R
I/O6R
I/O8R
I/O17R
N/C
N/C
NOTES:
1. All VCC pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. Package body is approximately 14mm x 14mm x 1.4mm.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
6.42
2
N/C
N/C
N/C
N/C
A5L
A4L
A3L
A2L
A1L
A0L
INTL
BUSYL
GND
M/S
BUSYR
INTR
A0R
A1R
A2R
A3R
A4R
N/C
N/C
N/C
N/C
4088 drw 02
.
IDT7035S/L
High-Speed 8K x 18 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Pin Names
Left Port
Right Port
Names
CEL
CER
Chip Enable
R/WL
R/WR
Read/Write Enable
OEL
OER
Output Enable
A0L - A12L
A0R - A12R
Address
I/O0L - I/O17L
I/O0R - I/O17R
Data Input/Output
SEML
SEMR
Semaphore Enable
UBL
UBR
Upper Byte Select
LBL
LBR
Lower Byte Select
INTL
INTR
Interrupt Flag
BUSYL
BUSYR
Busy Flag
M/S
Master or Slave Select
VCC
Power
GND
Ground
4088 tbl 01
Truth Table I: Non-Contention Read/Write Control
Inputs(1)
Outputs
CE
R/W
OE
UB
LB
SEM
I/O9-17
I/O0-8
Mode
H
X
X
X
X
H
High-Z
High-Z
Deselected: Power-Down
X
X
X
H
H
H
High-Z
High-Z
Both Bytes Deselected
L
L
X
L
H
H
DATAIN
High-Z
Write to Upper Byte Only
L
L
X
H
L
H
High-Z
DATA IN
Write to Lower Byte Only
L
L
X
L
L
H
DATAIN
DATA IN
Write to Both Bytes
L
H
L
L
H
H
DATAOUT
High-Z
Read Upper Byte Only
L
H
L
H
L
H
High-Z
DATAOUT
Read Lower Byte Only
L
H
L
L
L
H
DATAOUT
DATA OUT
Read Both Bytes
X
X
H
X
X
X
High-Z
High-Z
Outputs Disabled
4088 tbl 02
NOTE:
1. A0L — A12L ≠ A0R — A12R
3
6.42
IDT7035S/L
High-Speed 8K x 18 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Truth Table II: Semaphore Read/Write Control(1)
Inputs
Outputs
CE
R/W
OE
UB
LB
SEM
I/O9-17
I/O0-8
Mode
H
H
L
X
X
L
DATA OUT
DATA OUT
Read Data in Semaphore Flag
X
H
L
H
H
L
DATA OUT
DATA OUT
Read Data in Semaphore Flag
H
↑
X
X
X
L
DATA IN
DATA IN
Write I/O0 into Semaphore Flag
X
↑
X
H
H
L
DATA IN
DATA IN
Write I/O0 into Semaphore Flag
L
X
X
L
X
L
______
______
Not Allowed
L
X
X
X
L
L
______
______
Not Allowed
4088 tbl 03
NOTE:
1. There are eight semaphore flags written to via I/O0 and read from I/O0 - I/O17. These eight semaphores are addressed by A0 - A2.
Maximum Operating
Temperature and Supply Voltage(1,2)
Absolute Maximum Ratings(1)
Symbol
VTERM(2)
Rating
Commercial
& Industrial
Unit
Terminal Voltage
with Respect
to GND
-0.5 to +7.0
V
Grade
Commercial
TBIAS
Temperature
Under Bias
-55 to +125
o
TSTG
Storage
Temperature
-55 to +125
o
IOUT
DC Output
Current
Industrial
C
50
C
mA
Capacitance (TA = +25°C, f = 1.0MHz) (1)
CIN
COUT
Input Capacitance
Output
Capacitance
Vcc
0OC to +70OC
0V
5.0V + 10%
-40 C to +85 C
0V
5.0V + 10%
O
O
4088 tbl 05
4088 tbl 04
Parameter
GND
NOTES:
1. This is the parameter TA.
2. Industrial temperature: for specific speeds, packages and powers contact your
sales office.
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect
reliability.
2. VTERM must not exceed Vcc + 10% for more than 25% of the cycle time or 10ns
maximum, and is limited to < 20 mA for the period over VTERM > Vcc + 10%.
Symbol
Ambient
Temperature
Conditions(2)
Max.
Unit
VIN = 3dV
9
pF
VOUT = 3dV
10
pF
Recommended DC Operating
Conditions
Symbol
Parameter
VCC
Supply Voltage
GND
Ground
4088 tbl 07
6.42
4
Typ.
Max.
Unit
4.5
5.0
5.5
V
0
0
0
V
VIH
Input High Voltage
2.2
____
VIL
Input Low Voltage
-0.5(1)
____
NOTES:
1. VIL > -1.5V for pulse width less than 10ns.
2. VTERM must not exceed Vcc + 10%.
NOTES:
1. This parameter is determined by device characterization but is not production
tested. For TQFP Package Only.
2. 3dV references the interpolated capacitance when the input and output signals
switch from 0V to 3V or from 3V to 0V.
Min.
(2)
6.0
0.8
V
V
4088 tbl 06
IDT7035S/L
High-Speed 8K x 18 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VCC = 5.0V ± 10%)
7035S
Symbol
Parameter
Test Conditions
7035L
Min.
Max.
Min.
Max.
Unit
|ILI|
Input Leakage Current(1)
VCC = 5.5V, VIN = 0V to V CC
___
10
___
5
µA
|ILO|
Output Leakage Current
CE = VIH, VOUT = 0V to V CC
___
10
___
5
µA
VOL
Output Low Voltage
IOL = 4mA
___
0.4
___
0.4
V
VOH
Output High Voltage
IOH = -4mA
2.4
___
2.4
___
V
4088 tbl 08
NOTE:
1. At Vcc < 2.0V input leakages are undefined.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(1,6) (VCC = 5.0V ± 10%)
Symbol
ICC
ISB1
ISB2
ISB3
ISB4
Parameter
Dynamic Operating Current
(Both Ports Active)
Standby Current
(Both Ports - TTL Level
Inputs)
Standby Current
(One Port - TTL Level Inputs)
Full Standby Current (Both
Ports - All CMOS Level
Inputs)
Full Standby Current
(One Port - All CMOS Level
Inputs)
Test Condition
CE = VIL, Outputs Open
SEM = VIH
f = fMAX(3)
CEL = CER = VIH
SEMR = SEML = VIH
f = fMAX(3)
CE"A" = VIL and CE"B" = VIH(5)
Active Port Outputs Open,
f=fMAX(3)
SEMR = SEML = VIH
Both Ports CEL and
CER > VCC - 0.2V
VIN > VCC - 0.2V or
VIN < 0.2V, f = 0(4)
SEMR = SEML > VCC - 0.2V
CE"A" < 0.2V and
CE"B" > VCC - 0.2V(5)
SEMR = SEML > VCC - 0.2V
VIN > VCC - 0.2V or V IN < 0.2V
Active Port Outputs Open
f = fMAX(3)
Version
7035X15
Com'l Only
Typ.(2) Max.
7035X20
Com'l Only
Typ.(2) Max.
COM'L
S
L
170
170
310
260
160
160
290
240
IND
S
L
____
____
____
____
160
160
370
320
COM'L
S
L
20
20
60
50
20
20
60
50
IND
S
L
____
____
____
____
20
20
90
70
COM'L
S
L
105
105
190
160
95
95
180
150
IND
S
L
____
____
____
____
95
95
240
210
COM'L
S
L
1.0
0.2
15
5
1.0
0.2
15
5
IND
S
L
____
____
____
____
1.0
0.2
30
10
COM'L
S
L
100
100
170
140
90
90
155
130
IND
S
L
____
____
____
____
90
90
225
200
Unit
mA
mA
mA
mA
mA
4088 tbl 09
NOTES:
1. 'X' in part numbers indicates power rating (S or L)
2. VCC = 5V, TA = +25°C, and are not production tested. Icc dc = 120mA (TYP)
3. At f = f MAX , address and I/O'S are cycling at the maximum frequency read cycle of 1/t RC , and using “AC Test Conditions” of input levels of
GND to 3V.
4. f = 0 means no address or control lines change.
5. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
6. Industrial temperature: for specific speeds, packages and powers contact your sales office.
5
6.42
IDT7035S/L
High-Speed 8K x 18 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Data retention Characteristics Over All Temperature Ranges
(L Version Only) (VLC = 0.2V, VHC = VCC - 0.2V)(4)
Symbol
Parameter
Test Condition
Min.
Typ.(1)
Max.
Unit
2.0
___
___
V
µA
VDR
VCC for Data Retention
VCC = 2V
ICCDR
Data Retention Current
CE > VHC
IND.
___
100
4000
VIN > VHC or < VLC
COM'L.
___
100
1500
0
___
___
ns
tRC(2)
___
___
ns
tCDR(3)
Chip Deselect to Data Retention Time
tR(3)
Operation Recovery Time
SEM > VHC
4088 tbl 10
NOTES:
1. TA = +25°C, VCC = 2V, not production tested.
2. tRC = Read Cycle Time
3. This parameter is guaranteed by characterization, but is not production tested.
4. At Vcc < 2.0V input leakages are undefined.
Data Retention Waveform
DATA RETENTION MODE
VDR ≥ 2V
4.5V
VCC
4.5V
tCDR
CE
tR
VDR
VIH
VIH
4088 drw 03
AC Test Conditions
Input Pulse Levels
Input Rise/Fall Times
5ns Max.
Input Timing Reference Levels
1.5V
Output Reference Levels
1.5V
Output Load
5V
5V
GND to 3.0V
893Ω
893Ω
DATAOUT
BUSY
INT
DATAOUT
347Ω
30pF
347Ω
5pF*
Figures 1 and 2
4088 tbl 11
4088 drw 04
Figure 1. AC Output Test Load
Figure 2. Output Test Load
( for tLZ, tHZ, tWZ, tOW)
* including scope and jig.
6.42
6
IDT7035S/L
High-Speed 8K x 18 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range(4,5)
7035X15
Com'l Only
Symbol
Parameter
7035X20
Com'l Only
Min.
Max.
Min.
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
15
____
20
____
ns
tAA
Address Access Time
____
15
____
20
ns
tACE
Chip Enable Access Time
(3)
____
15
____
20
ns
tABE
Byte Enable Access Time (3)
____
15
____
20
ns
tAOE
Output Enable Access Time
____
10
____
12
ns
tOH
Output Hold from Address Change
3
____
3
____
ns
3
____
3
____
ns
____
10
____
12
ns
0
____
0
____
ns
____
15
____
20
ns
10
____
10
____
ns
____
15
____
20
ns
tLZ
Output Low-Z Time
(1,2)
(1,2)
tHZ
Output High-Z Time
tPU
Chip Enable to Power Up Time (2)
tPD
Chip Disable to Power Down Time (2)
tSOP
tSAA
(3)
Semaphore Flag Update Pulse (OE or SEM)
Semaphore Address Access Time
(3)
4088 tbl 12
NOTES:
1. Transition is measured ±500mV from Low or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. To access RAM, CE = VIL, UB or LB = VIL, and SEM = VIH. To access semaphore, CE = VIH or UB & LB = VIH, and SEM = VIL.
4. 'X' in part numbers indicates power rating (S or L).
5. Industrial temperature: for specific speeds, packages and powers contact your sales office.
Waveform of Read Cycles(5)
tRC
ADDR
(4)
CE
tAA
(4)
tACE
tAOE
(4)
OE
tABE
(4)
UB, LB
R/W
tLZ
DATAOUT
tOH
(1)
VALID DATA
(4)
tHZ
(2)
BUSYOUT
tBDD
(3,4)
4088 drw 05
NOTES:
1. Timing depends on which signal is asserted last, OE, CE, LB, or UB.
2. Timing depends on which signal is de-asserted first, CE, OE, LB, or UB.
3. tBDD delay is required only in case where opposite port is completing a write operation to the same address location for simultaneous read operations BUSY has
no relation to valid output data.
4. Start of valid data depends on which timing becomes effective last tABE, tAOE, tACE, tAA or tBDD.
5. SEM = VIH.
7
6.42
IDT7035S/L
High-Speed 8K x 18 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing of Power-Up Power-Down
CE
tPU
ICC
tPD
50%
50%
ISB
4088 drw 06
.
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage(5,6)
7035X15
Com'l Only
Symbol
Parameter
7035X20
Com'l Only
Min.
Max.
Min.
Max.
Unit
15
____
20
____
ns
tEW
Chip Enable to End-of-Write
(3)
12
____
15
____
ns
tAW
Address Valid to End-of-Write
12
____
15
____
ns
0
____
0
____
ns
WRITE CYCLE
tWC
Write Cycle Time
(3)
tAS
Address Set-up Time
tWP
Write Pulse Width
12
____
15
____
ns
tWR
Write Recovery Time
0
____
0
____
ns
tDW
Data Valid to End-of-Write
10
____
15
____
ns
____
10
____
12
ns
0
____
0
____
ns
____
10
____
12
ns
0
____
0
____
ns
5
____
ns
5
____
ns
(1,2)
tHZ
Output High-Z Time
tDH
Data Hold Time (4)
tWZ
Write Enable to Output in High-Z (1,2)
tOW
Output Active from End-of-Write
(1,2,4)
tSWRD
SEM Flag Write to Read Time
5
____
tSPS
SEM Flag Contention Window
5
____
4088 tbl 13
NOTES:
1. Transition is measured ±500mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. To access RAM, CE = VIL, UB or LB = VIL, SEM = VIH. To access semaphore, CE = VIH or UB & LB = VIH, and SEM = VIL. Either condition must be valid for the
entire tEW time.
4. The specification for tDH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tOW values will vary over voltage
and temperature, the actual tDH will always be smaller than the actual tOW.
5. 'X' in part numbers indicates power rating (S or L).
6. Industrial temperature: for specific speeds, packages and powers contact your sales office.
6.42
8
IDT7035S/L
High-Speed 8K x 18 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Write Cycle No. 1, R/W Controlled Timing(1,5,8)
tWC
ADDRESS
tHZ
(7)
OE
tAW
CE or SEM
UB or LB
(9)
(9)
tAS (6)
tWP
(3)
(2)
tWR
R/W
tWZ
(7)
tOW
(4)
DATAOUT
(4)
tDW
tDH
DATAIN
4088 drw 07
Timing Waveform of Write Cycle No. 2, CE, UB, LB Controlled Timing(1,5)
tWC
ADDRESS
tAW
(9)
CE or SEM
tAS (6)
tWR(3)
tEW (2)
(9)
UB or LB
R/W
tDW
tDH
DATAIN
4088 drw 08
NOTES:
1. R/W or CE or UB & LB must be HIGH during all address transitions.
2. A write occurs during the overlap (tEW or tWP) of a LOW UB or LB and a LOW CE and a LOW R/W for memory array writing cycle.
3. tWR is measured from the earlier of CE or R/W (or SEM or R/W) going HIGH to the end-of-write cycle.
4. During this period, the I/O pins are in the output state and input signals must not be applied.
5. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high-impedance state.
6. Timing depends on which enable signal is asserted last, CE, R/W, or byte control.
7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured ±500mV from steady state with Output Test Load
(Figure 2).
8. If OE is LOW during R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off and data to be
placed on the bus for the required tDW. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as
the specified tWP.
9. To access RAM, CE = VIL, UB or LB = VIL, and SEM = VIH. To access semaphore, CE = VIH or UB & LB = VIH, and SEM = VIL. tEW must be met
for either condition.
9
6.42
IDT7035S/L
High-Speed 8K x 18 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Semaphore Read after Write Timing, Either Side(1)
tOH
tSAA
A0 - A2
VALID ADDRESS
tAW
VALID ADDRESS
tWR
tACE
tEW
SEM
tSOP
tDW
DATA0
DATA OUT
VALID(2)
DATAIN VALID
tAS
tWP
tDH
R/W
tSWRD
OE
tAOE
tSOP
Write Cycle
Read Cycle
4088 drw 09
NOTE:
1. CE = VIH or UB & LB = VIH for the duration of the above timing (both write and read cycle).
2. "DATAOUT VALID' represents all I/Os (I/O0-I/O17) equal to the semaphore value.
Timing Waveform of Semaphore Write Contention(1,3,4)
A0"A"-A2"A"
(2)
SIDE
"A"
MATCH
R/W"A"
SEM"A"
tSPS
A0"B"-A2"B"
(2)
SIDE
"B"
MATCH
R/W"B"
SEM"B"
4088 drw 10
NOTES:
1. DOR = DOL = VIL, CER = CEL = VIH, or both UB & LB = VIH.
2. All timing is the same for left and right port. Port “A” may be either left or right port. Port “B” is the opposite from port “A”.
3. This parameter is measured from R/W"A" or SEM"A" going HIGH to R/W"B" or SEM"B" going HIGH.
4. If tSPS is not satisfied, there is no guarantee which side will obtain the semaphore flag.
6.42
10
IDT7035S/L
High-Speed 8K x 18 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range(6,7)
7035X15
Com'l Only
Symbol
Parameter
7035X20
Com'l Only
Min.
Max.
Min.
Max.
Unit
BUSY TIMING (M/S=VIH)
tBAA
BUSY Access Time from Address Match
____
15
____
20
ns
tBDA
BUSY Disable Time from Address Not Matched
____
15
____
20
ns
tBAC
BUSY Acce ss Time from Chip Enable Low
____
15
____
20
ns
tBDC
BUSY Acce ss Time from Chip Enable High
____
15
____
17
ns
tAPS
Arbitration Priority Set-up Time (2)
5
____
5
____
ns
tBDD
BUSY Disable to Valid Data(3)
____
18
____
30
ns
12
____
15
____
ns
tWH
(5)
Write Hold After BUSY
BUSY TIMING (M/S=VIL)
tWB
BUSY Input to Write (4)
0
____
0
____
ns
tWH
Write Hold After BUSY(5)
12
____
15
____
ns
____
30
____
45
ns
____
25
____
30
ns
PORT-TO-PORT DELAY TIMING
tWDD
tDDD
Write Pulse to Data Delay(1)
Write Data Valid to Read Data Delay
(1)
4088 tbl 14
NOTES:
1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Read With BUSY (M/S = VIH)" or "Timing Waveform of Write with
Port-To-Port Delay (M/S = VIH)".
2. To ensure that the earlier of the two ports wins.
3. tBDD is a calculated parameter and is the greater of 0ns, tWDD – tWP (actual) or tDDD – tDW (actual).
4. To ensure that the write cycle is inhibited on Port "B" during contention with Port "A".
5. To ensure that a write cycle is completed on Port "B" after contention with Port "A".
6. 'X' in part numbers indicates power rating (S or L).
7. Industrial temperature: for specific speeds, packages and powers contact your sales office.
11
6.42
IDT7035S/L
High-Speed 8K x 18 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Write Port-to-Port Read and BUSY(2,5) (M/S = VIH)(4)
tWC
ADDR"A"
MATCH
tWP
R/W"A"
tDW
DATAIN "A"
tDH
VALID
tAPS
(1)
ADDR"B"
MATCH
tBAA
tBDA
tBDD
BUSY"B"
tWDD
DATAOUT "B"
VALID
tDDD
(3)
4088 drw 11
NOTES:
1. To ensure that the earlier of the two ports wins. tAPS is ignored for M/S = VIL (slave).
2. CEL = CER = VIL.
3. OE = VIL for the reading port.
4. If M/S = VIL (SLAVE) then BUSY is an input BUSY"A" = VIL and BUSY"B" = "don't care."
5. All timing is the same for left and right ports. Port "A" may be either the left of right port. Port "B" is the opposite port from Port "A".
Timing Waveform of Write with BUSY
tWP
R/W"A"
BUSY"B"
tWB(3)
tWH(1)
R/W"B"
,
(2)
4088 drw 12
NOTES:
1. tWH must be met for both BUSY input (slave) output master.
2. BUSY is asserted on port "B" Blocking R/W"B", until BUSY"B" goes HIGH
3. tWB is only for the 'Slave' Version.
6.42
12
IDT7035S/L
High-Speed 8K x 18 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Waveform of BUSY Arbitration Controlled by CE Timing(1) (M/S = VIH)
ADDR"A"
and "B"
ADDRESSES MATCH
CE"A"
(2)
tAPS
CE"B"
tBAC
tBDC
BUSY"B"
4088 drw 13
Waveform of BUSY Arbitration Cycle Controlled by Address Match
Timing(1) (M/S = VIH)
ADDR"A"
ADDRESS "N"
tAPS (2)
ADDR"B"
MATCHING ADDRESS "N"
tBAA
tBDA
BUSY"B"
4088 drw 14
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”.
2. If tAPS is not satisfied, the BUSY signal will be asserted on one side or another but there is no guarantee on which side BUSY will be asserted.
AC Electrical Characteristics Over the
Operating Temperature and Supply VoltageRange(1,2)
7035X15
Com'l Only
Symbol
Parameter
7035X20
Com'l Only
Min.
Max.
Min.
Max.
Unit
INTERRUPT TIMING
tAS
Address Set-up Time
0
____
0
____
ns
tWR
Write Recovery Time
0
____
0
____
ns
tINS
Interrupt Set Time
____
15
____
20
ns
tINR
Interrupt Reset Time
____
15
____
20
ns
NOTES:
1. 'X' in part numbers indicates power rating (S or L).
2. Industrial temperature: for specific speeds, packages and powers contact your sales office.
13
6.42
4088 tbl 15
IDT7035S/L
High-Speed 8K x 18 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Waveform of Interrupt Timing(1)
tWC
ADDR"A"
INTERRUPT SET ADDRESS
tAS
(2)
(3)
tWR
(4)
CE"A"
R/W"A"
(3)
tINS
INT"B"
4088 drw 15
tRC
INTERRUPT CLEAR ADDRESS
ADDR"B"
tAS
(2)
(3)
CE"B"
OE"B"
(3)
tINR
INT"B"
4088 drw 16
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”.
2. See Interrupt Flag Truth Table III.
3. Timing depends on which enable signal (CE or R/W) is asserted last.
4. Timing depends on which enable signal (CE or R/W) is de-asserted first.
Truth Table III — Interrupt Flag(1,2)
Left Port
Right Port
R/WL
CEL
OEL
A0L-A12L
INTL
R/WR
CER
OER
A0R-A12R
INTR
Function
L
L
X
1FFF
X
X
X
X
X
L(3)
Set Right INTR Flag
X
X
X
X
X
X
L
L
1FFF
H(4)
Reset Right INTR Flag
X
(3)
L
L
X
1FFE
X
Set Left INTL Flag
(2)
X
X
X
X
X
Reset Left INTL Flag
X
X
X
L
X
L
1FFE
L
H
4088 tbl 16
NOTES:
1. Assumes BUSYL = BUSYR = VIH.
2. If BUSYL = VIL, then no change.
3. If BUSYR = VIL, then no change.
4. INTR and INTL must be initialized at power-up.
6.42
14
IDT7035S/L
High-Speed 8K x 18 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Truth Table IV — Address BUSY
Arbitration
Inputs
Outputs
CEL
CER
AOL-A12L
AOR-A12R
BUSYL(1)
BUSYR(1)
Function
X
X
NO MATCH
H
H
Normal
H
X
MATCH
H
H
Normal
X
H
MATCH
H
H
Normal
L
L
MATCH
(2)
(2)
Write Inhibit(3)
4088 tbl 17
NOTES:
1. Pins BUSYL and BUSYR are both outputs when the part is configured as a master. BUSY are inputs when configured as a slave. BUSYx outputs on the IDT7035
are push pull, not open drain outputs. On slaves the BUSY asserted internally inhibits write.
2. "L" if the inputs to the opposite port were stable prior to the address and enable inputs of this port. "H" if the inputs to the opposite port became stable after the address
and enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR = LOW will result. BUSYL and BUSYR outputs cannot be LOW simultaneously.
3. Writes to the left port are internally ignored when BUSYL outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored
when BUSYR outputs are driving LOW regardless of actual logic level on the pin.
Truth Table V — Example of Semaphore Procurement Sequence(1,2,3)
Functions
D0 - D17 Left
D0 - D17 Right
Status
No Action
1
1
Semaphore free
Left Port Writes "0" to Semaphore
0
1
Left port has semaphore token
Right Port Writes "0" to Semaphore
0
1
No change. Right side has no write access to semaphore
Left Port Writes "1" to Semaphore
1
0
Right port obtains semaphore token
Left Port Writes "0" to Semaphore
1
0
No change. Left port has no write access to semaphore
Right Port Writes "1" to Semaphore
0
1
Left port obtains semaphore token
Left Port Writes "1" to Semaphore
1
1
Semaphore free
Right Port Writes "0" to Semaphore
1
0
Right port has semaphore token
Right Port Writes "1" to Semaphore
1
1
Semaphore free
Left Port Writes "0" to Semaphore
0
1
Left port has semaphore token
Left Port Writes "1" to Semaphore
1
1
Semaphore free
NOTES:
1. This table denotes a sequence of events for only one of the eight semaphores on the IDT7035.
2. There are eight semaphore flags written to via I/O0 and read from all I/0's. These eight semaphores are addressed by A0 - A2.
3. CE = VIH, SEM = VIL to access the semaphores. Refer to the Semaphore Read/Write Control Truth Table.
Functional Description
The IDT7035 provides two ports with separate control, address and
I/O pins that permit independent access for reads or writes to any location
in memory. The IDT7035 has an automatic power down feature controlled
by CE. The CE controls on-chip power down circuitry that permits the
respective port to go into a standby mode when not selected (CE HIGH).
When a port is enabled, access to the entire memory array is permitted.
Interrupts
If the user chooses the interrupt function, a memory location (mail box
or message center) is assigned to each port. The left port interrupt flag
4088 tbl 18
(INTL) is asserted when the right port writes to memory location 1FFE
(HEX), where a write is defined as the CER = R/WR = VIL per Truth Table
III. The left port clears the interrupt by an address location 1FFE access
when CEL = OEL = VIL, R/WL is a "don't care". Likewise, the right port
interrupt flag (INTR) is asserted when the left port writes to memory location
1FFF (HEX) and to clear the interrupt flag (INTR), the right port must access
the memory location 1FFF, The message (18 bits) at 1FFE or 1FFF is
user-defined, since it is an addressable SRAM location. If the interrupt
function is not used, address locations 1FFE and 1FFF are not used as
mail boxes, but as part of the random access memory. Refer to Truth Table
III for the interrupt operation.
15
6.42
IDT7035S/L
High-Speed 8K x 18 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Busy Logic provides a hardware indication that both ports of the RAM
have accessed the same location at the same time. It also allows one of the
two accesses to proceed and signals the other side that the RAM is “busy”.
The BUSY pin can then be used to stall the access until the operation on
the other side is completed. If a write operation has been attempted from
the side that receives a BUSY indication, the write signal is gated internally
to prevent the write from proceeding.
The use of BUSY logic is not required or desirable for all applications.
In some cases it may be useful to logically OR the BUSY outputs together
and use any BUSY indication as an interrupt source to flag the event of
an illegal or illogical operation. If the write inhibit function of BUSY logic is
not desirable, the BUSY logic can be disabled by placing the part in slave
mode with the M/S pin. Once in slave mode the BUSY pin operates solely
as a write inhibit input pin. Normal operation can be programmed by tying
the BUSY pins HIGH. If desired, unintended write operations can be
prevented to a port by tying the BUSY pin for that port LOW.
The BUSY outputs on the IDT7035 RAM in master mode, are pushpull type outputs and do not require pull up resistors to operate. If these
RAMs are being expanded in depth, then the BUSY indication for the
resulting array requires the use of an external AND gate.
Width Expansion with BUSY Logic
Master/Slave Arrays
When expanding an IDT7035 RAM array in width while using BUSY
logic, one master part is used to decide which side of the RAM array will
receive a BUSY indication, and to output that indication. Any number of
slaves to be addressed in the same address range as the master, use
the BUSY signal as a write inhibit signal. Thus on the IDT7035 RAM the
BUSY pin is an output if the part is used as a master (M/S = VIH), and the
BUSY pin is an input if the part used as a slave (M/S = VIL) as shown in
Figure 3.
If two or more master parts were used when expanding in width, a split
decision could result with one master indicating BUSY on one side of the
array and another master indicating BUSY on one other side of the array.
This would inhibit the write operations from one port for part of a word and
inhibit the write operations from the other port for the other part of the word.
The BUSY arbitration, on a master, is based on the chip enable and
address signals only. It ignores whether an access is a read or write. In
a master/slave array, both address and chip enable must be valid long
enough for a BUSY flag to be output from the master before the actual write
pulse can be initiated with either the R/W signal or the byte enables. Failure
to observe this timing can result in a glitched internal write inhibit signal and
corrupted data in the slave.
Semaphores
The IDT7035 is an extremely fast Dual-Port 8K x 18 CMOS Static RAM
with an additional 8 address locations dedicated to binary semaphore flags.
These flags allow either processor on the left or right side of the Dual-Port
RAM to claim a privilege over the other processor for functions defined by
the system designer’s software. As an example, the semaphore can be
used by one processor to inhibit the other from accessing a portion of the
Dual-Port RAM or any other shared resource.
The Dual-Port RAM features a fast access time, and both ports are
completely independent of each other. This means that the activity on the
BUSYL
CE
MASTER
Dual Port
RAM
BUSYR
BUSYL
CE
SLAVE
Dual Port
RAM
BUSYR
BUSYL
CE
MASTER
Dual Port
RAM
BUSYR
BUSYL
CE
SLAVE
Dual Port
RAM
BUSYR
BUSYL
DECODER
Busy Logic
BUSYR
.
4088 drw 17
Figure 3. Busy and chip enable routing for both width and depth
expansion with IDT7035 RAMs.
left port in no way slows the access time of the right port. Both ports are
identical in function to standard CMOS Static RAM and can be read from,
or written to, at the same time with the only possible conflict arising from the
simultaneous writing of, or a simultaneous READ/WRITE of, a nonsemaphore location. Semaphores are protected against such ambiguous
situations and may be used by the system program to avoid any conflicts
in the non-semaphore portion of the Dual-Port RAM. These devices have
an automatic power-down feature controlled by CE, the Dual-Port RAM
enable, and SEM, the semaphore enable. The CE and SEM pins control
on-chip power down circuitry that permits the respective port to go into
standby mode when not selected. This is the condition which is shown in
Truth Table I where CE and SEM = VIH.
Systems which can best use the IDT7035 contain multiple processors
or controllers and are typically very high-speed systems which are
software controlled or software intensive. These systems can benefit
from a performance increase offered by the IDT7035's hardware
semaphores, which provide a lockout mechanism without requiring
complex programming.
Software handshaking between processors offers the maximum in
system flexibility by permitting shared resources to be allocated in varying
configurations. The IDT7035 does not use its semaphore flags to control
any resources through hardware, thus allowing the system designer total
flexibility in system architecture.
An advantage of using semaphores rather than the more common
methods of hardware arbitration is that wait states are never incurred in
either processor. This can prove to be a major advantage in very highspeed systems.
How the Semaphore Flags Work
The semaphore logic is a set of eight latches which are independent
of the Dual-Port RAM. These latches can be used to pass a flag, or token,
from one port to the other to indicate that a shared resource is in use. The
semaphores provide a hardware assist for a use assignment method
called “Token Passing Allocation.” In this method, the state of a semaphore
latch is used as a token indicating that shared resource is in use. If the left
processor wants to use this resource, it requests the token by setting the
latch. This processor then verifies its success in setting the latch by reading
it. If it was successful, it proceeds to assume control over the shared
resource. If it was not successful in setting the latch, it determines that the
right side processor has set the latch first, has the token and is using the
6.42
16
IDT7035S/L
High-Speed 8K x 18 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
shared resource. The left processor can then either repeatedly request
that semaphore’s status or remove its request for that semaphore to
perform another task and occasionally attempt again to gain control of the
token via the set and test sequence. Once the right side has relinquished
the token, the left side should succeed in gaining control.
The semaphore flags are active LOW. A token is requested by writing
a zero into a semaphore latch and is released when the same side writes
a one to that latch.
The eight semaphore flags reside within the IDT7035 in a separate
memory space from the Dual-Port RAM. This address space is accessed
by placing a LOW input on the SEM pin (which acts as a chip select for the
semaphore flags) and using the other control pins (Address, OE, and
R/W) as they would be used in accessing a standard Static RAM. Each
of the flags has a unique address which can be accessed by either side
through address pins A0 – A2. When accessing the semaphores, none
of the other address pins has any effect.
When writing to a semaphore, only data pin D0 is used. If a low level
is written into an unused semaphore location, that flag will be set to a zero
on that side and a one on the other side (see Truth Table V). That
semaphore can now only be modified by the side showing the zero. When
a one is written into the same location from the same side, the flag will be
set to a one for both sides (unless a semaphore request from the other side
is pending) and then can be written to by both sides. The fact that the side
which is able to write a zero into a semaphore subsequently locks out writes
from the other side is what makes semaphore flags useful in interprocessor
communications. (A thorough discussion on the use of this feature follows
shortly.) A zero written into the same location from the other side will be
stored in the semaphore request latch for that side until the semaphore is
freed by the first side.
When a semaphore flag is read, its value is spread into all data bits so
that a flag that is a one reads as a one in all data bits and a flag containing
a zero reads as all zeros. The read value is latched into one side’s output
register when that side's semaphore select (SEM) and output enable (OE)
signals go active. This serves to disallow the semaphore from changing
state in the middle of a read cycle due to a write cycle from the other side.
Because of this latch, a repeated read of a semaphore in a test loop must
cause either signal (SEM or OE) to go inactive or the output will never
change.
A sequence WRITE/READ must be used by the semaphore in order
to guarantee that no system level contention will occur. A processor
requests access to shared resources by attempting to write a zero into a
semaphore location. If the semaphore is already in use, the semaphore
request latch will contain a zero, yet the semaphore flag will appear as one,
a fact which the processor will verify by the subsequent read (see Truth
Table V). As an example, assume a processor writes a zero to the left port
at a free semaphore location. On a subsequent read, the processor will
verify that it has written successfully to that location and will assume control
over the resource in question. Meanwhile, if a processor on the right side
attempts to write a zero to the same semaphore flag it will fail, as will be
verified by the fact that a one will be read from that semaphore on the right
side during subsequent read. Had a sequence of READ/WRITE been
used instead, system contention problems could have occurred during the
gap between the read and write cycles.
It is important to note that a failed semaphore request must be followed
by either repeated reads or by writing a one into the same location. The
reason for this is easily understood by looking at the simple logic diagram
of the semaphore flag in Figure 4. Two semaphore request latches feed
into a semaphore flag. Whichever latch is first to present a zero to the
semaphore flag will force its side of the semaphore flag LOW and the other
side HIGH. This condition will continue until a one is written to the same
semaphore request latch. Should the other side’s semaphore request latch
have been written to a zero in the meantime, the semaphore flag will flip
over to the other side as soon as a one is written into the first side’s request
latch. The second side’s flag will now stay LOW until its semaphore request
latch is written to a one. From this it is easy to understand that, if a semaphore
is requested and the processor which requested it no longer needs the
resource, the entire system can hang up until a one is written into that
semaphore request latch.
The critical case of semaphore timing is when both sides request a
single token by attempting to write a zero into it at the same time. The
semaphore logic is specially designed to resolve this problem. If simultaneous requests are made, the logic guarantees that only one side receives
the token. If one side is earlier than the other in making the request, the first
side to make the request will receive the token. If both requests arrive at
the same time, the assignment will be arbitrarily made to one port or the
other.
One caution that should be noted when using semaphores is that
semaphores alone do not guarantee that access to a resource is secure.
As with any powerful programming technique, if semaphores are misused
or misinterpreted, a software error can easily happen.
Initialization of the semaphores is not automatic and must be handled
via the initialization program at power-up. Since any semaphore request
flag which contains a zero must be reset to a one, all semaphores on both
sides should have a one written into them at initialization from both sides
to assure that they will be free when needed.
Using Semaphores—Some Examples
Perhaps the simplest application of semaphores is their application as
resource markers for the IDT7035’s Dual-Port RAM. Say the 8K x 18 RAM
was to be divided into two 4K x 18 blocks which were to be dedicated at
any one time to servicing either the left or right port. Semaphore 0 could
be used to indicate the side which would control the lower section of
memory, and Semaphore 1 could be defined as the indicator for the upper
section of memory.
To take a resource, in this example the lower 4K of Dual-Port RAM,
the processor on the left port could write and then read a zero in to
Semaphore 0. If this task was successfully completed (a zero was read
back rather than a one), the left processor would assume control
of the lower 4K. Meanwhile the right processor was attempting to gain
control of the resource after the left processor, it would read back a one
in response to the zero it had attempted to write into Semaphore 0. At this
point, the software could choose to try and gain control of the second 4K
section by writing, then reading a zero into Semaphore 1. If it succeeded
in gaining control, it would lock out the left side.
Once the left side was finished with its task, it would write a one to
Semaphore 0 and may then try to gain access to Semaphore 1. If
Semaphore 1 was still occupied by the right side, the left side could undo
its semaphore request and perform other tasks until it was able to write, then
read a zero into Semaphore 1. If the right processor performs a similar task
with Semaphore 0, this protocol would allow the two processors to swap
4K blocks of Dual-Port RAM with each other.
17
6.42
IDT7035S/L
High-Speed 8K x 18 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
The blocks do not have to be any particular size and can even be
variable, depending upon the complexity of the software using the
semaphore flags. All eight semaphores could be used to divide the DualPort RAM or other shared resources into eight parts. Semaphores can
even be assigned different meanings on different sides rather than being
given a common meaning as was shown in the example above.
Semaphores are a useful form of arbitration in systems like disk
interfaces where the CPU must be locked out of a section of memory during
a transfer and the I/O device cannot tolerate any wait states. With the use
of semaphores, once the two devices has determined which memory area
was “off-limits” to the CPU, both the CPU and the I/O devices could access
their assigned portions of memory continuously without any wait states.
Semaphores are also useful in applications where no memory “WAIT”
state is available on one or both sides. Once a semaphore handshake has
been performed, both processors can access their assigned RAM
segments at full speed.
Another application is in the area of complex data structures. In this
case, block arbitration is very important. For this application one processor
may be responsible for building and updating a data structure. The other
processor then reads and interprets that data structure. If the interpreting
processor reads an incomplete data structure, a major error condition may
exist. Therefore, some sort of arbitration must be used between the two
different processors. The building processor arbitrates for the block, locks
it and then is able to go in and update the data structure. When the update
is completed, the data structure block is released. This allows the
interpreting processor to come back and read the complete data structure,
thereby guaranteeing a consistent data structure.
L PORT
R PORT
SEMAPHORE
REQUEST FLIP FLOP
D0
D
SEMAPHORE
REQUEST FLIP FLOP
Q
Q
D
WRITE
D0
WRITE
SEMAPHORE
READ
SEMAPHORE
READ
4088 drw 18
Figure 4. IDT7035 Semaphore Logic
6.42
18
,
IDT7035S/L
High-Speed 8K x 18 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Ordering Information
IDT XXXXX
Device
Type
A
999
A
A
Power
Speed
Package
Process/
Temperature
Range
Blank
I(1)
Commercial (0°C to +70°C)
Industrial (-40°C to + 85°C)
PF
100-pin TQFP (PN100-1)
15
20
Commercial Only
Commercial Only
S
L
Standard Power
Low Power
7035
144K (8K x 18) Dual-Port RAM
Speed in nanoseconds
4088 drw 19
NOTE:
1. Industrial temperature range is available.
For specific speeds, packages and powers contact your sales office.
Datasheet Document History
1/18/99:
5/19/99:
6/4/99:
9/1/99:
Initiated datasheet document history
Converted to new format
Cosmetic typographical corrections
Added additional notes to pin configurations
Page 9 Fixed typographical error
Changed drawing format
Page 1 Corrected DSC number
Removed Preliminary
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www.idt.com
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19
6.42
for Tech Support:
831-754-4613
[email protected]
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