ON MC10192P Quad bus driver Datasheet

MC10192
Quad Bus Driver
The MC10192 contains four line drivers with complementary
outputs. Each driver has a Data (D) input and shares an Enable (E)
input with another driver. The two driver outputs are the uncommitted
collectors of a pair of NPN transistors operating as a current switch.
Each driver accepts 10K MECL input signals and provides a nominal
signal swing of 800 mV across a 50 Ω load at each output collector.
Outputs can drive higher values of load resistance, provided that the
combination of IR drop and load return voltage VLR does not cause an
output collector to go more negative than –2.4 V with respect to VCC.
To avoid output transistor breakdown, the load return voltage should
not be more positive than +5.5 V with respect to VCC. When the E
input is high, both output transistors of a driver are nonconducting.
When not used, the E inputs, as well as the D inputs, may be left open.
• Open Collector Outputs Drive Terminated Lines or
Transformers
• 50 kW Input Pulldown Resistors on All Inputs (Unused
Inputs May Be Left Open)
• Power Dissipation = 575 mW typ/pkg (No Load)
• Propagation Delay = 3.5 ns typ (E — Output)
3.0 ns typ (D — Output)
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MARKING
DIAGRAMS
16
CDIP–16
L SUFFIX
CASE 620
MC10192L
AWLYYWW
1
16
PDIP–16
P SUFFIX
CASE 648
MC10192P
AWLYYWW
1
1
PLCC–20
FN SUFFIX
CASE 775
10192
AWLYYWW
LOGIC DIAGRAM
E1 7
3
Z1
D1 5
4
Z1
1
Z2
D2 6
2
Z2
D3 10
15 Z3
A
WL
YY
WW
DIP PIN ASSIGNMENT
14 Z3
D4 11
13 Z4
E2 9
12 Z4
VCC = PIN 16
VEE = PIN 8
TRUTH TABLE
Output
Inputs
E
D
Z
Z
H
X
H
H
L
H
H
L
L
L
L
H
January, 2002 – Rev. 7
Z2
1
16
VCC
Z2
2
15
Z3
Z1
3
14
Z3
Z1
4
13
Z4
D1
5
12
Z4
D2
6
11
D4
E1
7
10
D3
VEE
8
9
E2
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion Tables
on page 18 of the ON Semiconductor MECL Data Book
(DL122/D).
ORDERING INFORMATION
Note: Unused outputs must be terminated
to VCC for proper operation.
 Semiconductor Components Industries, LLC, 2002
= Assembly Location
= Wafer Lot
= Year
= Work Week
Device
1
Package
Shipping
MC10192L
CDIP–16
25 Units / Rail
MC10192P
PDIP–16
25 Units / Rail
MC10192FN
PLCC–20
46 Units / Rail
Publication Order Number:
MC10192/D
MC10192
ELECTRICAL CHARACTERISTICS
Test Limits
Characteristic
Symbol
Pin
Under
Test
Max
Unit
IE
8
154
140
154
mAdc
IinH
5
350
220
220
µAdc
Power Supply Drain Current
Input Current
–30°C
Min
+25°C
Max
0.5
Min
+85°C
Max
Min
0.5
µAdc
IinL
5
Output Current High
Logic 1
IOH
2
0.3
Output Current Low
Logic 0
IOL
2
Threshold Current High
Logic 1
IOHC
2
Threshold Current Low
Logic 0
IOLC
2
13.5
14.0
14.0
mAdc
Output Sink Current Low
Logic 0
IOS
2
13.3
13.9
13.3
mAdc
2.0
13.5
18.0
14.0
2.0
VLR
Output Voltage Low (Note 2.)
VOLS
–2.4
2.0
1.5
(50Ω Load)
Propagation Delay
E to Output
D to Output
tPHL
tPLH
Rise/Fall Time
(20 to 80%)
tTLH
tTHL
18.0
14.0
19.0
mAdc
2.0
mAdc
2.0
Load Return Voltage Absolute Max
Rating (Note 1.)
Switching Times
mAdc
5.5
5.5
5.5
V
V
ns
6.0
4.5
3.3
1. The 5.5V value is a maximum rating, do not exceed. A 270Ω resistor will prevent output transistor breakdown.
2. Limitations of load resistor and load return voltage combinations. Refer to page 1 description.
ELECTRICAL CHARACTERISTICS (continued)
TEST VOLTAGE VALUES (Volts)
Characteristic
Power Supply Drain Current
Input Current
@ Test Temperature
VIHmax
VILmin
VIHAmin
VILAmax
VEE
–30°C
–0.890
–1.890
–1.205
–1.500
–5.2
+25°C
–0.810
–1.850
–1.105
–1.475
–5.2
+85°C
–0.700
–1.825
–1.035
–1.440
–5.2
Symbol
Pin
Under
Test
IE
8
IinH
5
IinL
5
Output Current High
Logic 1
IOH
2
Output Current Low
Logic 0
IOL
2
Threshold Current High
Logic 1
IOHC
2
Threshold Current Low
Logic 0
IOLC
Output Sink Current Low
Logic 0
IOS
TEST VOLTAGE APPLIED TO PINS LISTED BELOW
VIHmax
(VCC)
Gnd
8
16
8
16
5
8
16
5,6,10,11
8
16
8
16
8
16
8
16
8
16
VIHAmin
VILAmax
5
5,6,10,11
5,7,9,10,11
5,10,11
2
VEE
VILmin
7,9
5,6,10,11
6
6
Load Return Voltage Absolute Max
Rating (Note 1.)
VLR
8
16
Output Voltage Low (Note 2.)
VOLS
8
16
Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been
established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained.
Outputs are terminated through a 50–ohm resistor to –2.0 volts. Test procedures are shown for only one gate. The other gates are tested in the
same manner.
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2
MC10192
PACKAGE DIMENSIONS
PLCC–20
FN SUFFIX
PLASTIC PLCC PACKAGE
CASE 775–02
ISSUE C
0.007 (0.180)
B
Y BRK
–N–
M
T L-M
0.007 (0.180)
U
M
N
S
T L-M
S
G1
0.010 (0.250)
S
N
S
D
–L–
–M–
Z
W
20
D
1
X
V
S
T L-M
S
N
S
VIEW D–D
A
0.007 (0.180)
M
T L-M
S
N
S
R
0.007 (0.180)
M
T L-M
S
N
S
Z
0.007 (0.180)
H
M
T L-M
S
N
S
K1
K
C
E
F
0.004 (0.100)
G
J
–T–
VIEW S
G1
0.010 (0.250) S T L-M
S
N
S
0.007 (0.180)
M
T L-M
S
VIEW S
SEATING
PLANE
NOTES:
1. DATUMS -L-, -M-, AND -N- DETERMINED
WHERE TOP OF LEAD SHOULDER EXITS PLASTIC
BODY AT MOLD PARTING LINE.
2. DIMENSION G1, TRUE POSITION TO BE
MEASURED AT DATUM -T-, SEATING PLANE.
3. DIMENSIONS R AND U DO NOT INCLUDE MOLD
FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.250)
PER SIDE.
4. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
5. CONTROLLING DIMENSION: INCH.
6. THE PACKAGE TOP MAY BE SMALLER THAN THE
PACKAGE BOTTOM BY UP TO 0.012 (0.300).
DIMENSIONS R AND U ARE DETERMINED AT THE
OUTERMOST EXTREMES OF THE PLASTIC BODY
EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS,
GATE BURRS AND INTERLEAD FLASH, BUT
INCLUDING ANY MISMATCH BETWEEN THE TOP
AND BOTTOM OF THE PLASTIC BODY.
7. DIMENSION H DOES NOT INCLUDE DAMBAR
PROTRUSION OR INTRUSION. THE DAMBAR
PROTRUSION(S) SHALL NOT CAUSE THE H
DIMENSION TO BE GREATER THAN 0.037 (0.940).
THE DAMBAR INTRUSION(S) SHALL NOT CAUSE
THE H DIMENSION TO BE SMALLER THAN 0.025
(0.635).
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3
DIM
A
B
C
E
F
G
H
J
K
R
U
V
W
X
Y
Z
G1
K1
INCHES
MIN
MAX
0.385
0.395
0.385
0.395
0.165
0.180
0.090
0.110
0.013
0.019
0.050 BSC
0.026
0.032
0.020
--0.025
--0.350
0.356
0.350
0.356
0.042
0.048
0.042
0.048
0.042
0.056
--0.020
2
10 0.310
0.330
0.040
---
MILLIMETERS
MIN
MAX
9.78
10.03
9.78
10.03
4.20
4.57
2.29
2.79
0.33
0.48
1.27 BSC
0.66
0.81
0.51
--0.64
--8.89
9.04
8.89
9.04
1.07
1.21
1.07
1.21
1.07
1.42
--0.50
2
10 7.88
8.38
1.02
---
N
S
MC10192
–A–
16
9
1
8
–B–
CDIP–16
L SUFFIX
CERAMIC DIP PACKAGE
CASE 620–10
ISSUE T
C
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION F MAY NARROW TO 0.76 (0.030)
WHERE THE LEAD ENTERS THE CERAMIC
BODY.
L
DIM
A
B
C
D
E
F
G
H
K
L
M
N
–T–
K
N
SEATING
PLANE
M
E
F
J
G
D
16 PL
0.25 (0.010)
16 PL
0.25 (0.010)
M
T A
T B
M
S
PDIP–16
P SUFFIX
PLASTIC DIP PACKAGE
CASE 648–08
ISSUE R
–A–
16
9
1
8
B
F
C
L
S
–T–
SEATING
PLANE
K
H
G
D
M
J
16 PL
0.25 (0.010)
M
S
T A
M
INCHES
MIN
MAX
0.750
0.785
0.240
0.295
--0.200
0.015
0.020
0.050 BSC
0.055
0.065
0.100 BSC
0.008
0.015
0.125
0.170
0.300 BSC
0
15 0.020
0.040
MILLIMETERS
MIN
MAX
19.05
19.93
6.10
7.49
--5.08
0.39
0.50
1.27 BSC
1.40
1.65
2.54 BSC
0.21
0.38
3.18
4.31
7.62 BSC
0
15 0.51
1.01
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
DIM
A
B
C
D
F
G
H
J
K
L
M
S
INCHES
MIN
MAX
0.740
0.770
0.250
0.270
0.145
0.175
0.015
0.021
0.040
0.70
0.100 BSC
0.050 BSC
0.008
0.015
0.110
0.130
0.295
0.305
0
10 0.020
0.040
MILLIMETERS
MIN
MAX
18.80
19.55
6.35
6.85
3.69
4.44
0.39
0.53
1.02
1.77
2.54 BSC
1.27 BSC
0.21
0.38
2.80
3.30
7.50
7.74
0
10 0.51
1.01
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are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes
without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular
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including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
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MC10192/D
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