8/16-bit Atmel XMEGA C3 Microcontroller ATxmega384C3 Features z High-performance, low-power Atmel® AVR® XMEGA® 8/16-bit Microcontroller z Nonvolatile program and data memories 384KBytes of in-system self-programmable flash 8KBytes boot section 4KBytes EEPROM 32KBytes internal SRAM Peripheral features z Two -channel DMA controller z Four-channel event system z Five 16-bit timer/counters z Four timer/counters with four output compare or input capture channels z One timer/counter with two output compare or input capture channels z High resolution extension on two timer/counters z Advanced waveform extension (AWeX) on one timer/counter z One USB device interface z USB 2.0 full speed (12Mbps) and low speed (1.5Mbps) device compliant z 32 Endpoints with full configuration flexibility z Three USARTs with IrDA support for one USART z Two two-wire interfaces with dual address match (I2C and SMBus compatible) z Two serial peripheral interfaces (SPIs) z AES crypto engine z CRC-16 (CRC-CCITT) and CRC-32 (IEEE®802.3) generator z 16-bit real time counter (RTC) with separate oscillator z One sixteen-channel, 12-bit, 300ksps Analog to Digital Converter z Two Analog Comparators with window compare function, and current sources z External interrupts on all general purpose I/O pins z Programmable watchdog timer with separate on-chip ultra low power oscillator z QTouch® library support z Capacitive touch buttons, sliders and wheels Special microcontroller features z Power-on reset and programmable brown-out detection z Internal and external clock options with PLL and prescaler z Programmable multilevel interrupt controller z Five sleep modes z Programming and debug interface z PDI (program and debug interface) I/O and packages z 50 programmable I/O pins z 64-lead TQFP z 64-pad QFN Operating voltage z 1.6 – 3.6V Operating frequency z 0 – 12MHz from 1.6V z 0 – 32MHz from 2.7V z z z z z z z z z 8361C–AVR–4/12 1. Ordering Information Flash (bytes) EEPROM (bytes) SRAM (bytes) 384K + 8K 4K 32K 384K + 8K 4K 32K ATxmega384C3-MH 384K + 8K 4K 32K ATxmega384C3-MHR(4) 384K + 8K 4K 32K Ordering code ATxmega384C3-AU ATxmega384C3-AUR (4) Speed (MHz) 1. 2. 3. 4. Package (1)(2)(3) Temp. 64A 32 Notes: Power supply 1.6 - 3.6V -40°C - 85°C 64Z3 This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green. For packaging information, see “Packaging information” on page 63. Tape and Reel. Package type 64A 64-lead, 14 x 14mm body size, 1.0mm body thickness, 0.8mm lead pitch, thin profile plastic quad flat package (TQFP) 64Z3 64-pad, 9 x 9 x 1.0mm body, lead pitch 0.50mm, 7.65mm exposed pad, quad flat no-lead package (QFN) Typical Applications Industrial control Climate control Low power battery applications ® Factory automation RF and ZigBee Building control USB connectivity Power tools HVAC Board control Sensor control Utility metering White goods Optical Medical applications XMEGA C3 [DATASHEET] 8361C–AVR–4/12 2 2. Pinout/Block Diagram Figure 2-1. Block diagram and pinout. PR1 PR0 RESET/PDI PDI PF7 PF6 VCC GND PF5 PF4 PF3 58 57 56 55 54 53 52 51 50 49 PA2 PA1 PA0 AVCC GND 63 62 61 60 External clock /Crystal pins General Purpose I /O 64 Digital function Analog function /Oscillators 59 Programming, debug, test Power Ground Port R 1 PA4 2 PA5 3 PA6 4 5 PA7 XOSC DATA BUS OSC/CLK Control Internal oscillators Watchdog oscillator Power Supervision Sleep Controller Real Time Counter Watchdog Timer Reset Controller Event System Controller Crypto / CRC OCD Prog/Debug Interface AREF Port A PA3 ADC 48 PF2 47 PF1 46 PF0 45 VCC 44 GND 43 PE7 42 PE6 41 PE5 40 PE4 39 PE3 38 PE2 37 PE1 36 PE0 35 VCC 34 GND 33 PD7 AC0:1 Notes: 1. 2. 18 19 20 21 22 23 24 25 26 27 28 29 PC2 PC3 PC4 PC5 PC6 PC7 GND VDD PD0 PD1 PD2 PD3 Port E 17 Port D PC1 Port C USART0 Port F 32 16 PD6 PC0 TC0 15 31 VDD PD5 14 TOSC GND EVENT ROUTING NETWORK 30 13 DATA BUS PD4 PB7 SRAM TWI 12 EEPROM USART0 PB6 FLASH TC0 11 USB PB5 SPI 10 BUS matrix CPU USART0 PB4 Internal references TC0 9 AREF TWI PB3 DMA Controller SPI 8 PB2 Interrupt Controller USART0 7 TC0:1 PB1 IRCOM 6 Port B PB0 For full details on pinout and alternate pin functions refer to “Pinout and Pin Functions” on page 51. The large center pad underneath the QFN/MLF package should be soldered to ground on the board to ensure good mechanical stability. XMEGA C3 [DATASHEET] 8361C–AVR–4/12 3 3. Overview The Atmel AVR XMEGA is a family of low power, high performance, and peripheral rich 8/16-bit microcontrollers based on the AVR enhanced RISC architecture. By executing instructions in a single clock cycle, the AVR XMEGA devices achieve CPU throughput approaching one million instructions per second (MIPS) per megahertz, allowing the system designer to optimize power consumption versus processing speed. The AVR CPU combines a rich instruction set with 32 general purpose working registers. All 32 registers are directly connected to the arithmetic logic unit (ALU), allowing two independent registers to be accessed in a single instruction, executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs many times faster than conventional single-accumulator or CISC based microcontrollers. The XMEGA C3 devices provide the following features: in-system programmable flash with read-while-write capabilities; internal EEPROM and SRAM; two-channel DMA controller, four-channel event system and programmable multilevel interrupt controller, 50 general purpose I/O lines, 16-bit real-time counter (RTC); five, 16-bit timer/counters with compare and PWM channels; three USARTs; two two-wire serial interfaces (TWIs); one full speed USB 2.0 interface; two serial peripheral interfaces (SPIs); AES cryptographic engine; one sixteen-channel, 12-bit ADC with programmable gain; two analog comparators (ACs) with window mode; programmable watchdog timer with separate internal oscillator; accurate internal oscillators with PLL and prescaler; and programmable brown-out detection. The program and debug interface (PDI), a fast, two-pin interface for programming and debugging, is available. The ATx devices have five software selectable power saving modes. The idle mode stops the CPU while allowing the SRAM, DMA controller, event system, interrupt controller, and all peripherals to continue functioning. The power-down mode saves the SRAM and register contents, but stops the oscillators, disabling all other functions until the next TWI, USB resume, or pin-change interrupt, or reset. In power-save mode, the asynchronous real-time counter continues to run, allowing the application to maintain a timer base while the rest of the device is sleeping. In standby mode, the external crystal oscillator keeps running while the rest of the device is sleeping. This allows very fast startup from the external crystal, combined with low power consumption. In extended standby mode, both the main oscillator and the asynchronous timer continue to run. To further reduce power consumption, the peripheral clock to each individual peripheral can optionally be stopped in active mode and idle sleep mode. Atmel offers a free QTouch library for embedding capacitive touch buttons, sliders and wheels functionality into AVR microcontrollers. The devices are manufactured using Atmel high-density, nonvolatile memory technology. The program flash memory can be reprogrammed in-system through the PDI. A boot loader running in the device can use any interface to download the application program to the flash memory. The boot loader software in the boot flash section will continue to run while the application flash section is updated, providing true read-while-write operation. By combining an 8/16-bit RISC CPU with in-system, self-programmable flash, the AVR XMEGA is a powerful microcontroller family that provides a highly flexible and cost effective solution for many embedded applications. All Atmel AVR XMEGA devices are supported with a full suite of program and system development tools, including: C compilers, macro assemblers, program debugger/simulators, programmers, and evaluation kits. XMEGA C3 [DATASHEET] 8361C–AVR–4/12 4 3.1 Block Diagram Figure 3-1. XMEGA C3 block diagram. PR[0..1] Programming, debug, Power Ground Digital function Analog function /Oscillators XTAL1 External clock /Crystal pins General Purpose I /O XTAL2 Oscillator Circuits/ Clock Generation Real Time Counter PORT R (2) Watchdog Oscillator DATA BUS Watchdog Timer ACA Event System Controller PA[0..7] Oscillator Control PORT A (8) DMA Controller ADCA VCC Power Supervision POR/BOD & RESET SRAM Sleep Controller GND RESET/ PDI_CLK AREFA Prog/Debug Controller BUS Matrix VCC/10 PDI PDI_DATA Int. Refs. Tempref AES OCD AREFB PORT B (8) Flash EEPROM TCF0 PORT F (8) NVM Controller PF[0..7] DATA BUS TWIE TCE0 USARTE0 USB SPID TCD0 USARTD0 SPIC TWIC TCC0:1 USARTC0 EVENT ROUTING NETWORK IRCOM PB[0..7] Interrupt Controller CPU CRC To Clock Generator PORT C (8) PORT D (8) PORT E (8) TOSC1 TOSC2 PC[0..7] PD[0..7] PE[0..7] XMEGA C3 [DATASHEET] 8361C–AVR–4/12 5 4. Resources A comprehensive set of development tools, application notes and datasheets are available for download on http://www.atmel.com/avr. 4.1 Recommended reading z Atmel AVR XMEGA C manual z XMEGA application notes This device data sheet only contains part specific information with a short description of each peripheral and module. The XMEGA C manual describes the modules and peripherals in depth. The XMEGA application notes contain example code and show applied use of the modules and peripherals. All documentation are available from www.atmel.com/avr. XMEGA C3 [DATASHEET] 8361C–AVR–4/12 6 5. Capacitive touch sensing The Atmel QTouch library provides a simple to use solution to realize touch sensitive interfaces on most Atmel AVR microcontrollers. The patented charge-transfer signal acquisition offers robust sensing and includes fully debounced reporting of touch keys and includes Adjacent Key Suppression® (AKS®) technology for unambiguous detection of key events. The QTouch library includes support for the QTouch and QMatrix acquisition methods. Touch sensing can be added to any application by linking the appropriate Atmel QTouch library for the AVR microcontroller. This is done by using a simple set of APIs to define the touch channels and sensors, and then calling the touch sensing API’s to retrieve the channel information and determine the touch sensor states. The QTouch library is FREE and downloadable from the Atmel website at the following location: www.atmel.com/qtouchlibrary. For implementation details and other information, refer to the QTouch library user guide also available for download from the Atmel website. XMEGA C3 [DATASHEET] 8361C–AVR–4/12 7 6. AVR CPU 6.1 Features • 8/16-bit, high-performance Atmel AVR RISC CPU • • • • • • • 6.2 – 142 instructions – Hardware multiplier 32x8-bit registers directly connected to the ALU Stack in RAM Stack pointer accessible in I/O memory space Direct addressing of up to 16MB of program memory and 16MB of data memory True 16/24-bit access to 16/24-bit I/O registers Efficient support for 8-, 16-, and 32-bit arithmetic Configuration change protection of system-critical features Overview All Atmel AVR XMEGA devices use the 8/16-bit AVR CPU. The main function of the CPU is to execute the code and perform all calculations. The CPU is able to access memories, perform calculations, control peripherals, and execute the program in the flash memory. Interrupt handling is described in a separate section, refer to “Interrupts and Programmable Multilevel Interrupt Controller” on page 26. 6.3 Architectural Overview In order to maximize performance and parallelism, the AVR CPU uses a Harvard architecture with separate memories and buses for program and data. Instructions in the program memory are executed with single-level pipelining. While one instruction is being executed, the next instruction is pre-fetched from the program memory. This enables instructions to be executed on every clock cycle. For details of all AVR instructions, refer to http://www.atmel.com/avr. Figure 6-1. Block diagram of the AVR CPU architecture. The arithmetic logic unit (ALU) supports arithmetic and logic operations between registers or between a constant and a register. Single-register operations can also be executed in the ALU. After an arithmetic operation, the status register is updated to reflect information about the result of the operation. XMEGA C3 [DATASHEET] 8361C–AVR–4/12 8 The ALU is directly connected to the fast-access register file. The 32 x 8-bit general purpose working registers all have single clock cycle access time allowing single-cycle arithmetic logic unit (ALU) operation between registers or between a register and an immediate. Six of the 32 registers can be used as three 16-bit address pointers for program and data space addressing, enabling efficient address calculations. The memory spaces are linear. The data memory space and the program memory space are two different memory spaces. The data memory space is divided into I/O registers, SRAM, and external RAM. In addition, the EEPROM can be memory mapped in the data memory. All I/O status and control registers reside in the lowest 4KB addresses of the data memory. This is referred to as the I/O memory space. The lowest 64 addresses can be accessed directly, or as the data space locations from 0x00 to 0x3F. The rest is the extended I/O memory space, ranging from 0x0040 to 0x0FFF. I/O registers here must be accessed as data space locations using load (LD/LDS/LDD) and store (ST/STS/STD) instructions. The SRAM holds data. Code execution from SRAM is not supported. It can easily be accessed through the five different addressing modes supported in the AVR architecture. The first SRAM address is 0x2000. Data addresses 0x1000 to 0x1FFF are reserved for memory mapping of EEPROM. The program memory is divided in two sections, the application program section and the boot program section. Both sections have dedicated lock bits for write and read/write protection. The SPM instruction that is used for selfprogramming of the application flash memory must reside in the boot program section. The application section contains an application table section with separate lock bits for write and read/write protection. The application table section can be used for safe storing of nonvolatile data in the program memory. 6.4 ALU - Arithmetic Logic Unit The arithmetic logic unit (ALU) supports arithmetic and logic operations between registers or between a constant and a register. Single-register operations can also be executed. The ALU operates in direct connection with all 32 general purpose registers. In a single clock cycle, arithmetic operations between general purpose registers or between a register and an immediate are executed and the result is stored in the register file. After an arithmetic or logic operation, the status register is updated to reflect information about the result of the operation. ALU operations are divided into three main categories – arithmetic, logical, and bit functions. Both 8- and 16-bit arithmetic is supported, and the instruction set allows for efficient implementation of 32-bit aritmetic. The hardware multiplier supports signed and unsigned multiplication and fractional format. 6.4.1 Hardware Multiplier The multiplier is capable of multiplying two 8-bit numbers into a 16-bit result. The hardware multiplier supports different variations of signed and unsigned integer and fractional numbers: z Multiplication of unsigned integers z Multiplication of signed integers z Multiplication of a signed integer with an unsigned integer z Multiplication of unsigned fractional numbers z Multiplication of signed fractional numbers z Multiplication of a signed fractional number with an unsigned one A multiplication takes two CPU clock cycles. 6.5 Program Flow After reset, the CPU starts to execute instructions from the lowest address in the flash programmemory ‘0.’ The program counter (PC) addresses the next instruction to be fetched. Program flow is provided by conditional and unconditional jump and call instructions capable of addressing the whole address space directly. Most AVR instructions use a 16-bit word format, while a limited number use a 32-bit format. XMEGA C3 [DATASHEET] 8361C–AVR–4/12 9 During interrupts and subroutine calls, the return address PC is stored on the stack. The stack is allocated in the general data SRAM, and consequently the stack size is only limited by the total SRAM size and the usage of the SRAM. After reset, the stack pointer (SP) points to the highest address in the internal SRAM. The SP is read/write accessible in the I/O memory space, enabling easy implementation of multiple stacks or stack areas. The data SRAM can easily be accessed through the five different addressing modes supported in the AVR CPU. 6.6 Status Register The status register (SREG) contains information about the result of the most recently executed arithmetic or logic instruction. This information can be used for altering program flow in order to perform conditional operations. Note that the status register is updated after all ALU operations, as specified in the instruction set reference. This will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code. The status register is not automatically stored when entering an interrupt routine nor restored when returning from an interrupt. This must be handled by software. The status register is accessible in the I/O memory space. 6.7 Stack and Stack Pointer The stack is used for storing return addresses after interrupts and subroutine calls. It can also be used for storing temporary data. The stack pointer (SP) register always points to the top of the stack. It is implemented as two 8-bit registers that are accessible in the I/O memory space. Data are pushed and popped from the stack using the PUSH and POP instructions. The stack grows from a higher memory location to a lower memory location. This implies that pushing data onto the stack decreases the SP, and popping data off the stack increases the SP. The SP is automatically loaded after reset, and the initial value is the highest address of the internal SRAM. If the SP is changed, it must be set to point above address 0x2000, and it must be defined before any subroutine calls are executed or before interrupts are enabled. During interrupts or subroutine calls, the return address is automatically pushed on the stack. The return address can be two or three bytes, depending on program memory size of the device. For devices with 128KB or less of program memory, the return address is two bytes, and hence the stack pointer is decremented/incremented by two. For devices with more than 128KB of program memory, the return address is three bytes, and hence the SP is decremented/incremented by three. The return address is popped off the stack when returning from interrupts using the RETI instruction, and from subroutine calls using the RET instruction. The SP is decremented by one when data are pushed on the stack with the PUSH instruction, and incremented by one when data is popped off the stack using the POP instruction. To prevent corruption when updating the stack pointer from software, a write to SPL will automatically disable interrupts for up to four instructions or until the next I/O memory write. After reset the stack pointer is initialized to the highest address of the SRAM. See Figure 7-2 on page 14. 6.8 Register File The register file consists of 32 x 8-bit general purpose working registers with single clock cycle access time. The register file supports the following input/output schemes: z One 8-bit output operand and one 8-bit result input z Two 8-bit output operands and one 8-bit result input z Two 8-bit output operands and one 16-bit result input z One 16-bit output operand and one 16-bit result input Six of the 32 registers can be used as three 16-bit address register pointers for data space addressing, enabling efficient address calculations. One of these address pointers can also be used as an address pointer for lookup tables in flash program memory. XMEGA C3 [DATASHEET] 8361C–AVR–4/12 10 7. Memories 7.1 Features • Flash program memory – One linear address space – In-system programmable – Self-programming and boot loader support – Application section for application code – Application table section for application code or data storage – Boot section for application code or boot loader code – Separate read/write protection lock bits for all sections – Built in fast CRC check of a selectable flash program memory section • Data memory – One linear address space – Single-cycle access from CPU – SRAM – EEPROM Byte and page accessible Optional memory mapping for direct load and store – I/O memory Configuration and status registers for all peripherals and modules 4 bit-accessible general purpose registers for global variables or flags – Bus arbitration Deterministic priority handling between CPU, DMA controller, and other bus masters – Separate buses for SRAM, EEPROM and I/O memory Simultaneous bus access for CPU and DMA controller • Production signature row memory for factory programmed data – ID for each microcontroller device type – Serial number for each device – Calibration bytes for factory calibrated peripherals • User signature row – One flash page in size – Can be read and written from software – Content is kept after chip erase 7.2 Overview The Atmel AVR architecture has two main memory spaces, the program memory and the data memory. Executable code can reside only in the program memory, while data can be stored in the program memory and the data memory. The data memory includes the internal SRAM, and EEPROM for nonvolatile data storage. All memory spaces are linear and require no memory bank switching. Nonvolatile memory (NVM) spaces can be locked for further write and read/write operations. This prevents unrestricted access to the application software. A separate memory section contains the fuse bytes. These are used for configuring important system functions, and can only be written by an external programmer. The available memory size configurations are shown in “Ordering Information” on page 2. In addition, each device has a Flash memory signature row for calibration data, device identification, serial number etc. XMEGA C3 [DATASHEET] 8361C–AVR–4/12 11 7.3 Flash Program Memory The Atmel AVR XMEGA devices contain on-chip, in-system reprogrammable flash memory for program storage. The flash memory can be accessed for read and write from an external programmer through the PDI or from application software running in the device. All AVR CPU instructions are 16 or 32 bits wide, and each flash location is 16 bits wide. The flash memory is organized in two main sections, the application section and the boot loader section. The sizes of the different sections are fixed, but device-dependent. These two sections have separate lock bits, and can have different levels of protection. The store program memory (SPM) instruction, which is used to write to the flash from the application software, will only operate when executed from the boot loader section. The application section contains an application table section with separate lock settings. This enables safe storage of nonvolatile data in the program memory. Figure 7-1. Flash program memory (Hexadecimal address). Word address ATxmega384C3 0 Application section (384K) ... 2EFFF 2F000 2FFFF 30000 30FFF 7.3.1 Application table section (8K) Boot section (8K) Application Section The Application section is the section of the flash that is used for storing the executable application code. The protection level for the application section can be selected by the boot lock bits for this section. The application section can not store any boot loader code since the SPM instruction cannot be executed from the application section. 7.3.2 Application Table Section The application table section is a part of the application section of the flash memory that can be used for storing data. The size is identical to the boot loader section. The protection level for the application table section can be selected by the boot lock bits for this section. The possibilities for different protection levels on the application section and the application table section enable safe parameter storage in the program memory. If this section is not used for data, application code can reside here. 7.3.3 Boot Loader Section While the application section is used for storing the application code, the boot loader software must be located in the boot loader section because the SPM instruction can only initiate programming when executing from this section. The SPM instruction can access the entire flash, including the boot loader section itself. The protection level for the boot loader section can be selected by the boot loader lock bits. If this section is not used for boot loader software, application code can be stored here. XMEGA C3 [DATASHEET] 8361C–AVR–4/12 12 7.3.4 Production Signature Row The production signature row is a separate memory section for factory programmed data. It contains calibration data for functions such as oscillators and analog modules. Some of the calibration values will be automatically loaded to the corresponding module or peripheral unit during reset. Other values must be loaded from the signature row and written to the corresponding peripheral registers from software. For details on calibration conditions, refer to “Electrical Characteristics” on page 65. The production signature row also contains an ID that identifies each microcontroller device type and a serial number for each manufactured device. The serial number consists of the production lot number, wafer number, and wafer coordinates for the device. The device ID for the available devices is shown in Table 7-1. The production signature row cannot be written or erased, but it can be read from application software and external programmers. Table 7-1. Device ID bytes. Device ATxmega384C3 7.3.5 Device ID bytes Byte 2 Byte 1 Byte 0 45 98 1E User Signature Row The user signature row is a separate memory section that is fully accessible (read and write) from application software and external programmers. It is one flash page in size, and is meant for static user parameter storage, such as calibration data, custom serial number, identification numbers, random number seeds, etc. This section is not erased by chip erase commands that erase the flash, and requires a dedicated erase command. This ensures parameter storage during multiple program/erase operations and on-chip debug sessions. 7.4 Fuses and Lock bits The fuses are used to configure important system functions, and can only be written from an external programmer. The application software can read the fuses. The fuses are used to configure reset sources such as brownout detector and watchdog, and startup configuration. The lock bits are used to set protection levels for the different flash sections (that is, if read and/or write access should be blocked). Lock bits can be written by external programmers and application software, but only to stricter protection levels. Chip erase is the only way to erase the lock bits. To ensure that flash contents are protected even during chip erase, the lock bits are erased after the rest of the flash memory has been erased. An unprogrammed fuse or lock bit will have the value one, while a programmed fuse or lock bit will have the value zero. Both fuses and lock bits are reprogrammable like the flash program memory. 7.5 Data Memory The data memory contains the I/O memory, internal SRAM, optionally memory mapped EEPROM, and external memory if available. The data memory is organized as one continuous memory section, see Figure 7-2 on page 14. To simplify development, I/O Memory, EEPROM and SRAM will always have the same start addresses for all Atmel AVR XMEGA devices. XMEGA C3 [DATASHEET] 8361C–AVR–4/12 13 Figure 7-2. Data memory map (hexadecimal address). Byte address 0 FFF ATxmega384C3 I/O registers (4K) 1000 EEPROM (4K) 1FFF 2000 9FFF 7.6 Internal SRAM (32K) EEPROM All devices have EEPROM for nonvolatile data storage. It is either addressable in a separate data space (default) or memory mapped and accessed in normal data space. The EEPROM supports both byte and page access. Memory mapped EEPROM allows highly efficient EEPROM reading and EEPROM buffer loading. When doing this, EEPROM is accessible using load and store instructions. Memory mapped EEPROM will always start at hexadecimal address 0x1000. 7.7 I/O Memory The status and configuration registers for peripherals and modules, including the CPU, are addressable through I/O memory locations. All I/O locations can be accessed by the load (LD/LDS/LDD) and store (ST/STS/STD) instructions, which are used to transfer data between the 32 registers in the register file and the I/O memory. The IN and OUT instructions can address I/O memory locations in the range of 0x00 to 0x3F directly. In the address range 0x00 - 0x1F, single-cycle instructions for manipulation and checking of individual bits are available. The I/O memory address for all peripherals and modules is shown in the “Peripheral Module Address Map” on page 56. 7.7.1 General Purpose I/O Registers The lowest 16 I/O memory addresses are reserved as general purpose I/O registers. These registers can be used for storing global variables and flags, as they are directly bit-accessible using the SBI, CBI, SBIS, and SBIC instructions. 7.8 Data Memory and Bus Arbitration Since the data memory is organized as four separate sets of memories, the different bus masters (CPU, DMA controller read and DMA controller write, etc.) can access different memory sections at the same time. 7.9 Memory Timing Read and write access to the I/O memory takes one CPU clock cycle. A write to SRAM takes one cycle, and a read from SRAM takes two cycles. For burst read (DMA), new data are available every cycle. EEPROM page load (write) takes one cycle, and three cycles are required for read. For burst read, new data are available every second cycle. Refer to the instruction summary for more details on instructions and instruction timing. 7.10 Device ID and Revision Each device has a three-byte device ID. This ID identifies Atmel as the manufacturer of the device and the device type. A separate register contains the revision number of the device. XMEGA C3 [DATASHEET] 8361C–AVR–4/12 14 7.11 I/O Memory Protection Some features in the device are regarded as critical for safety in some applications. Due to this, it is possible to lock the I/O register related to the clock system, the event system, and the advanced waveform extensions. As long as the lock is enabled, all related I/O registers are locked and they can not be written from the application software. The lock registers themselves are protected by the configuration change protection mechanism. 7.12 Flash and EEPROM Page Size The flash program memory and EEPROM data memory are organized in pages. The pages are word accessible for the flash and byte accessible for the EEPROM. Table 7-2 on page 15 shows the Flash Program Memory organization and Program Counter (PC) size. Flash write and erase operations are performed on one page at a time, while reading the Flash is done one byte at a time. For Flash access the Z-pointer (Z[m:n]) is used for addressing. The most significant bits in the address (FPAGE) give the page number and the least significant address bits (FWORD) give the word in the page. Table 7-2. Devices Number of words and pages in the flash. PC size bits ATxmega384C3 18 Flash size Page size bytes words 384K + 8K FWORD FPAGE Application Size 256 Z[8:1] Z[19:9] 384K No of pages 768 Boot Size No of pages 8K 16 Table 7-3 shows EEPROM memory organization. EEEPROM write and erase operations can be performed one page or one byte at a time, while reading the EEPROM is done one byte at a time. For EEPROM access the NVM address register (ADDR[m:n]) is used for addressing. The most significant bits in the address (E2PAGE) give the page number and the least significant address bits (E2BYTE) give the byte in the page. Table 7-3. Devices ATxmega384C3 Number of bytes and pages in the EEPROM. EEPROM Page size Size bytes 4K 32 E2BYTE E2PAGE No of pages ADDR[4:0] ADDR[11:5] 128 XMEGA C3 [DATASHEET] 8361C–AVR–4/12 15 8. DMAC – Direct Memory Access Controller 8.1 Features • Allows high speed data transfers with minimal CPU intervention • • • • • • • 8.2 – from data memory to data memory – from data memory to peripheral – from peripheral to data memory – from peripheral to peripheral Two DMA channels with separate – transfer triggers – interrupt vectors – addressing modes Programmable channel priority From 1 byte to 16MB of data in a single transaction – Up to 64KB block transfers with repeat – 1, 2, 4, or 8 byte burst transfers Multiple addressing modes – Static – Incremental – Decremental Optional reload of source and destination addresses at the end of each – Burst – Block – Transaction Optional interrupt on end of transaction Optional connection to CRC generator for CRC on DMA data Overview The two-channel direct memory access (DMA) controller can transfer data between memories and peripherals, and thus offload these tasks from the CPU. It enables high data transfer rates with minimum CPU intervention, and frees up CPU time. The four DMA channels enable up to four independent and parallel transfers. The DMA controller can move data between SRAM and peripherals, between SRAM locations and directly between peripheral registers. With access to all peripherals, the DMA controller can handle automatic transfer of data to/from communication modules. The DMA controller can also read from memory mapped EEPROM. Data transfers are done in continuous bursts of 1, 2, 4, or 8 bytes. They build block transfers of configurable size from 1 byte to 64KB. A repeat counter can be used to repeat each block transfer for single transactions up to 16MB. Source and destination addressing can be static, incremental or decremental. Automatic reload of source and/or destination addresses can be done after each burst or block transfer, or when a transaction is complete. Application software, peripherals, and events can trigger DMA transfers. The two DMA channels have individual configuration and control settings. This include source, destination, transfer triggers, and transaction sizes. They have individual interrupt settings. Interrupt requests can be generated when a transaction is complete or when the DMA controller detects an error on a DMA channel. To allow for continuous transfers, two channels can be interlinked so that the second takes over the transfer when the first is finished, and vice versa. XMEGA C3 [DATASHEET] 8361C–AVR–4/12 16 9. Event System 9.1 Features • System for direct peripheral-to-peripheral communication and signaling • Peripherals can directly send, receive, and react to peripheral events • • • • 9.2 – CPU and DMA controller independent operation – 100% predictable signal timing – Short and guaranteed response time Four event channels for up to four different and parallel signal routing configurations Events can be sent and/or used by most peripherals, clock system, and software Additional functions include – Quadrature decoders – Digital filtering of I/O pin state Works in active mode and idle sleep mode Overview The event system enables direct peripheral-to-peripheral communication and signaling. It allows a change in one peripheral’s state to automatically trigger actions in other peripherals. It is designed to provide a predictable system for short and predictable response times between peripherals. It allows for autonomous peripheral control and interaction without the use of interrupts, CPU, or DMA controller resources, and is thus a powerful tool for reducing the complexity, size and execution time of application code. It also allows for synchronized timing of actions in several peripheral modules. A change in a peripheral’s state is referred to as an event, and usually corresponds to the peripheral’s interrupt conditions. Events can be directly passed to other peripherals using a dedicated routing network called the event routing network. How events are routed and used by the peripherals is configured in software. Figure on page 17 shows a basic diagram of all connected peripherals. The event system can directly connect together analog to digital converter, analog comparators, I/O port pins, the real-time counter, timer/counters, IR communication module (IRCOM), and USB interface. It can also be used to trigger DMA transactions (DMA controller). Events can also be generated from software and the peripheral clock. Figure 9-1. Event system overview and connected peripherals. CPU / Software DMA Controller Event Routing Network clkPER Prescaler Real Time Counter ADC Event System Controller Timer / Counters AC USB Port pins IRCOM The event routing network consists of four software-configurable multiplexers that control how events are routed and used. These are called event channels, and allow for up to four parallel event routing configurations. The maximum routing latency is two peripheral clock cycles. The event system works in both active mode and idle sleep mode. XMEGA C3 [DATASHEET] 8361C–AVR–4/12 17 10. System Clock and Clock options 10.1 Features • Fast start-up time • Safe run-time clock switching • Internal oscillators: • • • • • • 10.2 – 32MHz run-time calibrated and tuneable oscillator – 2MHz run-time calibrated oscillator – 32.768kHz calibrated oscillator – 32kHz ultra low power (ULP) oscillator with 1kHz output External clock options – 0.4MHz - 16MHz crystal oscillator – 32.768kHz crystal oscillator – External clock PLL with 20MHz - 128MHz output frequency – Internal and external clock options and 1x to 31x multiplication – Lock detector Clock prescalers with 1x to 2048x division Fast peripheral clocks running at two and four times the CPU clock Automatic run-time calibration of internal oscillators External oscillator and PLL lock failure detection with optional non-maskable interrupt Overview Atmel AVR XMEGA C3 devices have a flexible clock system supporting a large number of clock sources. It incorporates both accurate internal oscillators and external crystal oscillator and resonator support. A high-frequency phase locked loop (PLL) and clock prescalers can be used to generate a wide range of clock frequencies. A calibration feature (DFLL) is available, and can be used for automatic run-time calibration of the internal oscillators to remove frequency drift over voltage and temperature. An oscillator failure monitor can be enabled to issue a non-maskable interrupt and switch to the internal oscillator if the external oscillator or PLL fails. When a reset occurs, all clock sources except the 32kHz ultra low power oscillator are disabled. After reset, the device will always start up running from the 2MHz internal oscillator. During normal operation, the system clock source and prescalers can be changed from software at any time. Figure 10-1 on page 19 presents the principal clock system. Not all of the clocks need to be active at a given time. The clocks for the CPU and peripherals can be stopped using sleep modes and power reduction registers, as described in “Power Management and Sleep Modes” on page 21. XMEGA C3 [DATASHEET] 8361C–AVR–4/12 18 Figure 10-1. The clock system, clock sources and clock distribution. Real Time Counter Peripherals RAM AVR CPU Non-Volatile Memory clkPER clkPER2 clkCPU clkPER4 USB clkUSB System Clock Prescalers Brown-out Detector Prescaler Watchdog Timer clkSYS clkRTC System Clock Multiplexer (SCLKSEL) RTCSRC USBSRC DIV32 DIV32 DIV32 PLL PLLSRC DIV4 XOSCSEL 32kHz Int. ULP 32.768kHz Int. OSC 32.768kHz TOSC 32MHz Int. Osc 2MHz Int. Osc XTAL2 XTAL1 TOSC2 TOSC1 10.3 0.4 – 16MHz XTAL Clock Sources The clock sources are divided in two main groups: internal oscillators and external clock sources. Most of the clock sources can be directly enabled and disabled from software, while others are automatically enabled or disabled, depending on peripheral settings. After reset, the device starts up running from the 2MHz internal oscillator. The other clock sources, DFLLs and PLL, are turned off by default. The internal oscillators do not require any external components to run. For details on characteristics and accuracy of the internal oscillators, refer to the device datasheet. 10.3.1 32kHz Ultra Low Power Internal Oscillator This oscillator provides an approximate 32kHz clock. The 32kHz ultra low power (ULP) internal oscillator is a very low power clock source, and it is not designed for high accuracy. The oscillator employs a built-in prescaler that provides a XMEGA C3 [DATASHEET] 8361C–AVR–4/12 19 1kHz output. The oscillator is automatically enabled/disabled when it is used as clock source for any part of the device. This oscillator can be selected as the clock source for the RTC. 10.3.2 32.768kHz Calibrated Internal Oscillator This oscillator provides an approximate 32.768kHz clock. It is calibrated during production to provide a default frequency close to its nominal frequency. The calibration register can also be written from software for run-time calibration of the oscillator frequency. The oscillator employs a built-in prescaler, which provides both a 32.768kHz output and a 1.024kHz output. 10.3.3 32.768kHz Crystal Oscillator A 32.768kHz crystal oscillator can be connected between the TOSC1 and TOSC2 pins and enables a dedicated low frequency oscillator input circuit. A low power mode with reduced voltage swing on TOSC2 is available. This oscillator can be used as a clock source for the system clock and RTC, and as the DFLL reference clock. 10.3.4 0.4 - 16MHz Crystal Oscillator This oscillator can operate in four different modes optimized for different frequency ranges, all within 0.4 - 16MHz. 10.3.5 2MHz Run-time Calibrated Internal Oscillator The 2MHz run-time calibrated internal oscillator is the default system clock source after reset. It is calibrated during production to provide a default frequency close to its nominal frequency. A DFLL can be enabled for automatic run-time calibration of the oscillator to compensate for temperature and voltage drift and optimize the oscillator accuracy. 10.3.6 32MHz Run-time Calibrated Internal Oscillator The 32MHz run-time calibrated internal oscillator is a high-frequency oscillator. It is calibrated during production to provide a default frequency close to its nominal frequency. A digital frequency looked loop (DFLL) can be enabled for automatic run-time calibration of the oscillator to compensate for temperature and voltage drift and optimize the oscillator accuracy. This oscillator can also be adjusted and calibrated to any frequency between 30MHz and 55MHz. The production signature row contains 48MHz calibration values intended used when the oscillator is used a full-speed USB clock source. 10.3.7 External Clock Sources The XTAL1 and XTAL2 pins can be used to drive an external oscillator, either a quartz crystal or a ceramic resonator. XTAL1 can be used as input for an external clock signal. The TOSC1 and TOSC2 pins is dedicated to driving a 32.768kHz crystal oscillator. 10.3.8 PLL with 1x-31x Multiplication Factor The built-in phase locked loop (PLL) can be used to generate a high-frequency system clock. The PLL has a userselectable multiplication factor of from 1 to 31. In combination with the prescalers, this gives a wide range of output frequencies from all clock sources. XMEGA C3 [DATASHEET] 8361C–AVR–4/12 20 11. Power Management and Sleep Modes 11.1 Features • Power management for adjusting power consumption and functions • Five sleep modes – Idle – Power down – Power save – Standby – Extended standby • Power reduction register to disable clock and turn off unused peripherals in active and idle modes 11.2 Overview Various sleep modes and clock gating are provided in order to tailor power consumption to application requirements. This enables the Atmel AVR XMEGA microcontroller to stop unused modules to save power. All sleep modes are available and can be entered from active mode. In active mode, the CPU is executing application code. When the device enters sleep mode, program execution is stopped and interrupts or a reset is used to wake the device again. The application code decides which sleep mode to enter and when. Interrupts from enabled peripherals and all enabled reset sources can restore the microcontroller from sleep to active mode. In addition, power reduction registers provide a method to stop the clock to individual peripherals from software. When this is done, the current state of the peripheral is frozen, and there is no power consumption from that peripheral. This reduces the power consumption in active mode and idle sleep modes and enables much more fine-tuned power management than sleep modes alone. 11.3 Sleep Modes Sleep modes are used to shut down modules and clock domains in the microcontroller in order to save power. XMEGA microcontrollers have five different sleep modes tuned to match the typical functional stages during application execution. A dedicated sleep instruction (SLEEP) is available to enter sleep mode. Interrupts are used to wake the device from sleep, and the available interrupt wake-up sources are dependent on the configured sleep mode. When an enabled interrupt occurs, the device will wake up and execute the interrupt service routine before continuing normal program execution from the first instruction after the SLEEP instruction. If other, higher priority interrupts are pending when the wake-up occurs, their interrupt service routines will be executed according to their priority before the interrupt service routine for the wake-up interrupt is executed. After wake-up, the CPU is halted for four cycles before execution starts. The content of the register file, SRAM and registers are kept during sleep. If a reset occurs during sleep, the device will reset, start up, and execute from the reset vector. 11.3.1 Idle Mode In idle mode the CPU and nonvolatile memory are stopped (note that any ongoing programming will be completed), but all peripherals, including the interrupt controller, event system and DMA controller are kept running. Any enabled interrupt will wake the device. 11.3.2 Power-down Mode In power-down mode, all clocks, including the real-time counter clock source, are stopped. This allows operation only of asynchronous modules that do not require a running clock. The only interrupts that can wake up the MCU are the twowire interface address match interrupt, asynchronous port interrupts, and the USB resume interrupt. XMEGA C3 [DATASHEET] 8361C–AVR–4/12 21 11.3.3 Power-save Mode Power-save mode is identical to power down, with one exception. If the real-time counter (RTC) is enabled, it will keep running during sleep, and the device can also wake up from either an RTC overflow or compare match interrupt. 11.3.4 Standby Mode Standby mode is identical to power down, with the exception that the enabled system clock sources are kept running while the CPU, peripheral, and RTC clocks are stopped. This reduces the wake-up time. 11.3.5 Extended Standby Mode Extended standby mode is identical to power-save mode, with the exception that the enabled system clock sources are kept running while the CPU and peripheral clocks are stopped. This reduces the wake-up time. XMEGA C3 [DATASHEET] 8361C–AVR–4/12 22 12. System Control and Reset 12.1 Features • Reset the microcontroller and set it to initial state when a reset source goes active • Multiple reset sources that cover different situations – Power-on reset – External reset – Watchdog reset – Brownout reset – PDI reset – Software reset • Asynchronous operation – No running system clock in the device is required for reset • Reset status register for reading the reset source from the application code 12.2 Overview The reset system issues a microcontroller reset and sets the device to its initial state. This is for situations where operation should not start or continue, such as when the microcontroller operates below its power supply rating. If a reset source goes active, the device enters and is kept in reset until all reset sources have released their reset. The I/O pins are immediately tri-stated. The program counter is set to the reset vector location, and all I/O registers are set to their initial values. The SRAM content is kept. However, if the device accesses the SRAM when a reset occurs, the content of the accessed location can not be guaranteed. After reset is released from all reset sources, the default oscillator is started and calibrated before the device starts running from the reset vector address. By default, this is the lowest program memory address, 0, but it is possible to move the reset vector to the lowest address in the boot section. The reset functionality is asynchronous, and so no running system clock is required to reset the device. The software reset feature makes it possible to issue a controlled system reset from the user software. The reset status register has individual status flags for each reset source. It is cleared at power-on reset, and shows which sources have issued a reset since the last power-on. 12.3 Reset Sequence A reset request from any reset source will immediately reset the device and keep it in reset as long as the request is active. When all reset requests are released, the device will go through three stages before the device starts running again: z Reset counter delay z Oscillator startup z Oscillator calibration If another reset requests occurs during this process, the reset sequence will start over again. 12.4 Reset Sources 12.4.1 Power-on Reset A power-on reset (POR) is generated by an on-chip detection circuit. The POR is activated when the VCC rises and reaches the POR threshold voltage (VPOT), and this will start the reset sequence. The POR is also activated to power down the device properly when the VCC falls and drops below the VPOT level. The VPOT level is higher for falling VCC than for rising VCC. Consult the datasheet for POR characteristics data. XMEGA C3 [DATASHEET] 8361C–AVR–4/12 23 12.4.2 Brownout Detection The on-chip brownout detection (BOD) circuit monitors the VCC level during operation by comparing it to a fixed, programmable level that is selected by the BODLEVEL fuses. If disabled, BOD is forced on at the lowest level during chip erase and when the PDI is enabled. 12.4.3 External Reset The external reset circuit is connected to the external RESET pin. The external reset will trigger when the RESET pin is driven below the RESET pin threshold voltage, VRST, for longer than the minimum pulse period, tEXT. The reset will be held as long as the pin is kept low. The RESET pin includes an internal pull-up resistor. 12.4.4 Watchdog Reset The watchdog timer (WDT) is a system function for monitoring correct program operation. If the WDT is not reset from the software within a programmable timeout period, a watchdog reset will be given. The watchdog reset is active for one to two clock cycles of the 2MHz internal oscillator. For more details see “WDT – Watchdog Timer” on page 25. 12.4.5 Software Reset The software reset makes it possible to issue a system reset from software by writing to the software reset bit in the reset control register.The reset will be issued within two CPU clock cycles after writing the bit. It is not possible to execute any instruction from when a software reset is requested until it is issued. 12.4.6 Program and Debug Interface Reset The program and debug interface reset contains a separate reset source that is used to reset the device during external programming and debugging. This reset source is accessible only from external debuggers and programmers. XMEGA C3 [DATASHEET] 8361C–AVR–4/12 24 13. WDT – Watchdog Timer 13.1 Features • • • • • Issues a device reset if the timer is not reset before its timeout period Asynchronous operation from dedicated oscillator 1kHz output of the 32kHz ultra low power oscillator 11 selectable timeout periods, from 8ms to 8s Two operation modes: – Normal mode – Window mode • Configuration lock to prevent unwanted changes 13.2 Overview The watchdog timer (WDT) is a system function for monitoring correct program operation. It makes it possible to recover from error situations such as runaway or deadlocked code. The WDT is a timer, configured to a predefined timeout period, and is constantly running when enabled. If the WDT is not reset within the timeout period, it will issue a microcontroller reset. The WDT is reset by executing the WDR (watchdog timer reset) instruction from the application code. The window mode makes it possible to define a time slot or window inside the total timeout period during which WDT must be reset. If the WDT is reset outside this window, either too early or too late, a system reset will be issued. Compared to the normal mode, this can also catch situations where a code error causes constant WDR execution. The WDT will run in active mode and all sleep modes, if enabled. It is asynchronous, runs from a CPU-independent clock source, and will continue to operate to issue a system reset even if the main clocks fail. The configuration change protection mechanism ensures that the WDT settings cannot be changed by accident. For increased safety, a fuse for locking the WDT settings is also available. XMEGA C3 [DATASHEET] 8361C–AVR–4/12 25 14. Interrupts and Programmable Multilevel Interrupt Controller 14.1 Features • Short and predictable interrupt response time • Separate interrupt configuration and vector address for each interrupt • Programmable multilevel interrupt controller – Interrupt prioritizing according to level and vector address – Three selectable interrupt levels for all interrupts: low, medium and high – Selectable, round-robin priority scheme within low-level interrupts – Non-maskable interrupts for critical functions • Interrupt vectors optionally placed in the application section or the boot loader section 14.2 Overview Interrupts signal a change of state in peripherals, and this can be used to alter program execution. Peripherals can have one or more interrupts, and all are individually enabled and configured. When an interrupt is enabled and configured, it will generate an interrupt request when the interrupt condition is present. The programmable multilevel interrupt controller (PMIC) controls the handling and prioritizing of interrupt requests. When an interrupt request is acknowledged by the PMIC, the program counter is set to point to the interrupt vector, and the interrupt handler can be executed. All peripherals can select between three different priority levels for their interrupts: low, medium, and high. Interrupts are prioritized according to their level and their interrupt vector address. Medium-level interrupts will interrupt low-level interrupt handlers. High-level interrupts will interrupt both medium- and low-level interrupt handlers. Within each level, the interrupt priority is decided from the interrupt vector address, where the lowest interrupt vector address has the highest interrupt priority. Low-level interrupts have an optional round-robin scheduling scheme to ensure that all interrupts are serviced within a certain amount of time. Non-maskable interrupts (NMI) are also supported, and can be used for system critical functions. 14.3 Interrupt vectors The interrupt vector is the sum of the peripheral’s base interrupt address and the offset address for specific interrupts in each peripheral. The base addresses for the Atmel AVR XMEGA C3 devices are shown in Table 14-1. Offset addresses for each interrupt available in the peripheral are described for each peripheral in the XMEGA C manual. For peripherals or modules that have only one interrupt, the interrupt vector is shown in Table 14-1. The program address is the word address. Table 14-1. Reset and interrupt vectors. Program address (base address) Source 0x000 RESET 0x002 OSCF_INT_vect Crystal oscillator failure interrupt vector (NMI) 0x004 PORTC_INT_base Port C interrupt base 0x008 PORTR_INT_base Port R interrupt base 0x00C DMA_INT_base DMA controller interrupt base 0x014 RTC_INT_base Real Time Counter Interrupt base 0x018 TWIC_INT_base Two-Wire Interface on Port C Interrupt base 0x01C TCC0_INT_base Timer/Counter 0 on port C Interrupt base Interrupt description XMEGA C3 [DATASHEET] 8361C–AVR–4/12 26 Program address (base address) Source Interrupt description 0x028 TCC1_INT_base Timer/Counter 1 on port C Interrupt base 0x030 SPIC_INT_vect SPI on port C Interrupt vector 0x032 USARTC0_INT_base USART 0 on port C Interrupt base 0x03E AES_INT_vect AES Interrupt vector 0x040 NVM_INT_base Non-Volatile Memory Interrupt base 0x044 PORTB_INT_base Port B Interrupt base 0x056 PORTE_INT_base Port E INT base 0x05A TWIE_INT_base Two-Wire Interface on Port E Interrupt base 0x05E TCE0_INT_base Timer/Counter 0 on port E Interrupt base 0x074 USARTE0_INT_base USART 0 on port E Interrupt base 0x080 PORTD_INT_base Port D Interrupt base 0x084 PORTA_INT_base Port A Interrupt base 0x088 ACA_INT_base Analog Comparator on Port A Interrupt base 0x08E ADCA_INT_base Analog to Digital Converter on Port A Interrupt base 0x09A TCD0_INT_base Timer/Counter 0 on port D Interrupt base 0x0AE SPID_INT_vector SPI D Interrupt vector 0x0B0 USARTD0_INT_base USART 0 on port D Interrupt base 0x0B6 USARTD1_INT_base USART 1 on port D Interrupt base 0x0D0 PORTF_INT_base Port F Interrupt base 0x0D8 TCF0_INT_base Timer/Counter 0 on port F Interrupt base 0x0FA USB_INT_base USB on port D Interrupt base XMEGA C3 [DATASHEET] 8361C–AVR–4/12 27 15. I/O Ports 15.1 Features • 50 general purpose input and output pins with individual configuration • Output driver with configurable driver and pull settings: • • • • • • • • • • 15.2 – Totem-pole – Wired-AND – Wired-OR – Bus-keeper – Inverted I/O Input with synchronous and/or asynchronous sensing with interrupts and events – Sense both edges – Sense rising edges – Sense falling edges – Sense low level Optional pull-up and pull-down resistor on input and Wired-OR/AND configurations Optional slew rate control Asynchronous pin change sensing that can wake the device from all sleep modes Two port interrupts with pin masking per I/O port Efficient and safe access to port pins – Hardware read-modify-write through dedicated toggle/clear/set registers – Configuration of multiple pins in a single operation – Mapping of port registers into bit-accessible I/O memory space Peripheral clocks output on port pin Real-time counter clock output to port pin Event channels can be output on port pin Remapping of digital peripheral pin functions – Selectable USART, SPI, and timer/counter input/output pin locations Overview One port consists of up to eight port pins: pin 0 to 7. Each port pin can be configured as input or output with configurable driver and pull settings. They also implement synchronous and asynchronous input sensing with interrupts and events for selectable pin change conditions. Asynchronous pin-change sensing means that a pin change can wake the device from all sleep modes, included the modes where no clocks are running. All functions are individual and configurable per pin, but several pins can be configured in a single operation. The pins have hardware read-modify-write (RMW) functionality for safe and correct change of drive value and/or pull resistor configuration. The direction of one port pin can be changed without unintentionally changing the direction of any other pin. The port pin configuration also controls input and output selection of other device functions. It is possible to have both the peripheral clock and the real-time clock output to a port pin, and available for external use. The same applies to events from the event system that can be used to synchronize and control external functions. Other digital peripherals, such as USART, SPI, and timer/counters, can be remapped to selectable pin locations in order to optimize pin-out versus application needs. The notation of the ports are PORTA, PORTB, PORTC, PORTD, PORTE, PORTF and PORTR. 15.3 Output Driver All port pins (Pn) have programmable output configuration. The port pins also have configurable slew rate limitation to reduce electromagnetic emission. XMEGA C3 [DATASHEET] 8361C–AVR–4/12 28 15.3.1 Push-pull Figure 15-1. I/O configuration - Totem-pole. DIRn OUTn Pn INn 15.3.2 Pull-down Figure 15-2. I/O configuration - Totem-pole with pull-down (on input). DIRn OUTn Pn INn 15.3.3 Pull-up Figure 15-3. I/O configuration - Totem-pole with pull-up (on input). DIRn OUTn Pn INn 15.3.4 Bus-keeper The bus-keeper’s weak output produces the same logical level as the last output level. It acts as a pull-up if the last level was ‘1’, and pull-down if the last level was ‘0’. XMEGA C3 [DATASHEET] 8361C–AVR–4/12 29 Figure 15-4. I/O configuration - Totem-pole with bus-keeper. DIRn OUTn Pn INn 15.3.5 Others Figure 15-5. Output configuration - Wired-OR with optional pull-down. OUTn Pn INn Figure 15-6. I/O configuration - Wired-AND with optional pull-up. INn Pn OUTn XMEGA C3 [DATASHEET] 8361C–AVR–4/12 30 15.4 Input sensing Input sensing is synchronous or asynchronous depending on the enabled clock for the ports, and the configuration is shown in Figure 15-7. Figure 15-7. Input sensing system overview. Asynchronous sensing EDGE DETECT Interrupt Control IREQ Synchronous sensing Pn Synchronizer INn D Q D Q INVERTED I/O R EDGE DETECT Event R When a pin is configured with inverted I/O, the pin value is inverted before the input sensing. 15.5 Alternate Port Functions Most port pins have alternate pin functions in addition to being a general purpose I/O pin. When an alternate function is enabled, it might override the normal port pin function or pin value. This happens when other peripherals that require pins are enabled or configured to use pins. If and how a peripheral will override and use pins is described in the section for that peripheral. “Pinout and Pin Functions” on page 51 shows which modules on peripherals that enable alternate functions on a pin, and which alternate functions that are available on a pin. XMEGA C3 [DATASHEET] 8361C–AVR–4/12 31 16. TC0/1 – 16-bit Timer/Counter Type 0 and 1 16.1 Features • Five 16-bit timer/counters • • • • • • • • • • • • • 16.2 – Four timer/counters of type 0 – One timer/counter of type 1 – Split-mode enabling two 8-bit timer/counter from each timer/counter type 0 32-bit timer/counter support by cascading two timer/counters Up to four compare or capture (CC) channels – Four CC channels for timer/counters of type 0 – Two CC channels for timer/counters of type 1 Double buffered timer period setting Double buffered capture or compare channels Waveform generation: – Frequency generation – Single-slope pulse width modulation – Dual-slope pulse width modulation Input capture: – Input capture with noise cancelling – Frequency capture – Pulse width capture – 32-bit input capture Timer overflow and error interrupts/events One compare match or input capture interrupt/event per CC channel Can be used with event system for: – Quadrature decoding – Count and direction control – Capture Can be used with DMA and to trigger DMA transactions High-resolution extension – Increases frequency and waveform resolution by 4x (2-bit) or 8x (3-bit) Advanced waveform extension: – Low- and high-side output with programmable dead-time insertion (DTI) Event controlled fault protection for safe disabling of drivers Overview Atmel AVR XMEGA C3 devices have a set of five flexible 16-bit timer/counters (TC). Their capabilities include accurate program execution timing, frequency and waveform generation, and input capture with time and frequency measurement of digital signals. Two timer/counters can be cascaded to create a 32-bit timer/counter with optional 32-bit capture. A timer/counter consists of a base counter and a set of compare or capture (CC) channels. The base counter can be used to count clock cycles or events. It has direction control and period setting that can be used for timing. The CC channels can be used together with the base counter to do compare match control, frequency generation, and pulse width waveform modulation, as well as various input capture operations. A timer/counter can be configured for either capture or compare functions, but cannot perform both at the same time. A timer/counter can be clocked and timed from the peripheral clock with optional prescaling or from the event system. The event system can also be used for direction control and capture trigger or to synchronize operations. There are two differences between timer/counter type 0 and type 1. Timer/counter 0 has four CC channels, and timer/counter 1 has two CC channels. All information related to CC channels 3 and 4 is valid only for timer/counter 0. XMEGA C3 [DATASHEET] 8361C–AVR–4/12 32 Only Timer/Counter 0 has the split mode feature that split it into two 8-bit Timer/Counters with four compare channels each. Some timer/counters have extensions to enable more specialized waveform and frequency generation. The advanced waveform extension (AWeX) is intended for motor control and other power control applications. It enables low- and highside output with dead-time insertion, as well as fault protection for disabling and shutting down external drivers. It can also generate a synchronized bit pattern across the port pins. The advanced waveform extension can be enabled to provide extra and more advanced features for the Timer/Counter. This are only available for Timer/Counter 0. See “AWeX – Advanced Waveform Extension” on page 35 for more details. The high-resolution (hi-res) extension can be used to increase the waveform output resolution by four or eight times by using an internal clock source running up to four times faster than the peripheral clock. See “Hi-Res – High Resolution Extension” on page 36 for more details. Figure 16-1. Overview of a Timer/Counter and closely related peripherals. Timer/Counter Base Counter Timer Period Counter Prescaler Control Logic clkPER Event System clkPER4 Buffer Capture Control Waveform Generation Dead-Time Insertion Pattern Generation Fault Protection PORT Comparator AWeX Hi-Res Compare/Capture Channel D Compare/Capture Channel C Compare/Capture Channel B Compare/Capture Channel A PORTC has one Timer/Counter 0 and one Timer/Counter1. PORTD, PORTE and PORTF each has one Timer/Counter 0. Notation of these are TCC0 (Time/Counter C0), TCC1, TCD0, TCE0, and TCF0, respectively. XMEGA C3 [DATASHEET] 8361C–AVR–4/12 33 17. TC2 – Timer/Counter Type 2 17.1 Features • Eight eight-bit timer/counters • • • • • 17.2 – Four Low-byte timer/counter – Four High-byte timer/counter Up to eight compare channels in each Timer/Counter 2 – Four compare channels for the low-byte timer/counter – Four compare channels for the high-byte timer/counter Waveform generation – Single slope pulse width modulation Timer underflow interrupts/events One compare match interrupt/event per compare channel for the low-byte timer/counter Can be used with the event system for count control Overview There are four Timer/Counter 2. These are realized when a Timer/Counter 0 is set in split mode. It is then a system of two eight-bit timer/counters, each with four compare channels. This results in eight configurable pulse width modulation (PWM) channels with individually controlled duty cycles, and is intended for applications that require a high number of PWM channels. The two eight-bit timer/counters in this system are referred to as the low-byte timer/counter and high-byte timer/counter, respectively. The difference between them is that only the low-byte timer/counter can be used to generate compare match interrupts and events. The two eight-bit timer/counters have a shared clock source and separate period and compare settings. They can be clocked and timed from the peripheral clock, with optional prescaling, or from the event system. The counters are always counting down. PORTC, PORTD, PORTE and PORTF each has one Timer/Counter 2. Notation of these are TCC2 (Time/Counter C2), TCD2, TCE2 and TCF2, respectively. XMEGA C3 [DATASHEET] 8361C–AVR–4/12 34 18. AWeX – Advanced Waveform Extension 18.1 Features • Waveform output with complementary output from each compare channel • Four dead-time insertion (DTI) units – 8-bit resolution – Separate high and low side dead-time setting – Double buffered dead time – Optionally halts timer during dead-time insertion • Pattern generation unit creating synchronised bit pattern across the port pins – Double buffered pattern generation – Optional distribution of one compare channel output across the port pins • Event controlled fault protection for instant and predictable fault triggering 18.2 Overview The advanced waveform extension (AWeX) provides extra functions to the timer/counter in waveform generation (WG) modes. It is primarily intended for use with different types of motor control and other power control applications. It enables low- and high side output with dead-time insertion and fault protection for disabling and shutting down external drivers. It can also generate a synchronized bit pattern across the port pins. Each of the waveform generator outputs from the timer/counter 0 are split into a complimentary pair of outputs when any AWeX features are enabled. These output pairs go through a dead-time insertion (DTI) unit that generates the noninverted low side (LS) and inverted high side (HS) of the WG output with dead-time insertion between LS and HS switching. The DTI output will override the normal port value according to the port override setting. The pattern generation unit can be used to generate a synchronized bit pattern on the port it is connected to. In addition, the WG output from compare channel A can be distributed to and override all the port pins. When the pattern generator unit is enabled, the DTI unit is bypassed. The fault protection unit is connected to the event system, enabling any event to trigger a fault condition that will disable the AWeX output. The event system ensures predictable and instant fault reaction, and gives flexibility in the selection of fault triggers. The AWeX is available for TCC0. The notation of this is AWEXC. XMEGA C3 [DATASHEET] 8361C–AVR–4/12 35 19. Hi-Res – High Resolution Extension 19.1 Features • Increases waveform generator resolution up to 8x (three bits) • Supports frequency, single-slope PWM, and dual-slope PWM generation • Supports the AWeX when this is used for the same timer/counter 19.2 Overview The high-resolution (hi-res) extension can be used to increase the resolution of the waveform generation output from a timer/counter by four or eight. It can be used for a timer/counter doing frequency, single-slope PWM, or dual-slope PWM generation. It can also be used with the AWeX if this is used for the same timer/counter. The hi-res extension uses the peripheral 4x clock (ClkPER4). The system clock prescalers must be configured so the peripheral 4x clock frequency is four times higher than the peripheral and CPU clock frequency when the hi-res extension is enabled. There is one hi-res extensions that can be enabled for timer/counters pair on PORTC. The notation of this is HIRESC. XMEGA C3 [DATASHEET] 8361C–AVR–4/12 36 20. RTC – 16-bit Real-Time Counter 20.1 Features • 16-bit resolution • Selectable clock source • • • • • 20.2 – 32.768kHz external crystal – External clock – 32.768kHz internal oscillator – 32kHz internal ULP oscillator Programmable 10-bit clock prescaling One compare register One period register Clear counter on period overflow Optional interrupt/event on overflow and compare match Overview The 16-bit real-time counter (RTC) is a counter that typically runs continuously, including in low-power sleep modes, to keep track of time. It can wake up the device from sleep modes and/or interrupt the device at regular intervals. The reference clock is typically the 1.024kHz output from a high-accuracy crystal of 32.768kHz, and this is the configuration most optimized for low power consumption. The faster 32.768kHz output can be selected if the RTC needs a resolution higher than 1ms. The RTC can also be clocked from an external clock signal, the 32.768kHz internal oscillator or the 32kHz internal ULP oscillator. The RTC includes a 10-bit programmable prescaler that can scale down the reference clock before it reaches the counter. A wide range of resolutions and time-out periods can be configured. With a 32.768kHz clock source, the maximum resolution is 30.5µs, and time-out periods can range up to 2000 seconds. With a resolution of 1s, the maximum timeout period is more than18 hours (65536 seconds). The RTC can give a compare interrupt and/or event when the counter equals the compare register value, and an overflow interrupt and/or event when it equals the period register value. Figure 20-1. Real-time counter overview. External Clock TOSC1 TOSC2 32.768kHz Crystal Osc 32.768kHz Int. Osc DIV32 DIV32 32kHz int ULP (DIV32) PER RTCSRC clkRTC 10-bit prescaler = TOP/ Overflow = ”match”/ Compare CNT COMP XMEGA C3 [DATASHEET] 8361C–AVR–4/12 37 21. USB – Universal Serial Bus Interface 21.1 Features • One USB 2.0 full speed (12Mbps) and low speed (1.5Mbps) device compliant interface • Integrated on-chip USB transceiver, no external components needed • 16 endpoint addresses with full endpoint flexibility for up to 31 endpoints • • • • • • • • • • • • 21.2 – One input endpoint per endpoint address – One output endpoint per endpoint address Endpoint address transfer type selectable to – Control transfers – Interrupt transfers – Bulk transfers – Isochronous transfers Configurable data payload size per endpoint, up to 1023 bytes Endpoint configuration and data buffers located in internal SRAM – Configurable location for endpoint configuration data – Configurable location for each endpoint's data buffer Built-in direct memory access (DMA) to internal SRAM for: – Endpoint configurations – Reading and writing endpoint data Ping-pong operation for higher throughput and double buffered operation – Input and output endpoint data buffers used in a single direction – CPU/DMA controller can update data buffer during transfer Multipacket transfer for reduced interrupt load and software intervention – Data payload exceeding maximum packet size is transferred in one continuous transfer – No interrupts or software interaction on packet transaction level Transaction complete FIFO for workflow management when using multiple endpoints – Tracks all completed transactions in a first-come, first-served work queue Clock selection independent of system clock source and selection Minimum 1.5MHz CPU clock required for low speed USB operation Minimum 12MHz CPU clock required for full speed operation Connection to event system On chip debug possibilities during USB transactions Overview The USB module is a USB 2.0 full speed (12Mbps) and low speed (1.5Mbps) device compliant interface. The USB supports 16 endpoint addresses. All endpoint addresses have one input and one output endpoint, for a total of 31 configurable endpoints and one control endpoint. Each endpoint address is fully configurable and can be configured for any of the four transfer types; control, interrupt, bulk, or isochronous. The data payload size is also selectable, and it supports data payloads up to 1023 bytes. No dedicated memory is allocated for or included in the USB module. Internal SRAM is used to keep the configuration for each endpoint address and the data buffer for each endpoint. The memory locations used for endpoint configurations and data buffers are fully configurable. The amount of memory allocated is fully dynamic, according to the number of endpoints in use and the configuration of these. The USB module has built-in direct memory access (DMA), and will read/write data from/to the SRAM when a USB transaction takes place. To maximize throughput, an endpoint address can be configured for ping-pong operation. When done, the input and output endpoints are both used in the same direction. The CPU or DMA controller can then read/write one data buffer while the USB module writes/reads the others, and vice versa. This gives double buffered communication. XMEGA C3 [DATASHEET] 8361C–AVR–4/12 38 Multipacket transfer enables a data payload exceeding the maximum packet size of an endpoint to be transferred as multiple packets without software intervention. This reduces the CPU intervention and the interrupts needed for USB transfers. For low-power operation, the USB module can put the microcontroller into any sleep mode when the USB bus is idle and a suspend condition is given. Upon bus resumes, the USB module can wake up the microcontroller from any sleep mode. PORTD has one USB. Notation of this is USB. XMEGA C3 [DATASHEET] 8361C–AVR–4/12 39 22. TWI – Two-Wire Interface 22.1 Features • Two Identical two-wire interface peripherals • Bidirectional, two-wire communication interface • • • • • • • • • 22.2 – Phillips I2C compatible – System Management Bus (SMBus) compatible Bus master and slave operation supported – Slave operation – Single bus master operation – Bus master in multi-master bus environment – Multi-master arbitration Flexible slave address match functions – 7-bit and general call address recognition in hardware – 10-bit addressing supported – Address mask register for dual address match or address range masking – Optional software address recognition for unlimited number of addresses Slave can operate in all sleep modes, including power-down Slave address match can wake device from all sleep modes 100kHz and 400kHz bus frequency support Slew-rate limited output drivers Input filter for bus noise and spike suppression Support arbitration between start/repeated start and data bit (SMBus) Slave arbitration allows support for address resolve protocol (ARP) (SMBus) Overview The two-wire interface (TWI) is a bidirectional, two-wire communication interface. It is I2C and System Management Bus (SMBus) compatible. The only external hardware needed to implement the bus is one pull-up resistor on each bus line. A device connected to the bus must act as a master or a slave. The master initiates a data transaction by addressing a slave on the bus and telling whether it wants to transmit or receive data. One bus can have many slaves and one or several masters that can take control of the bus. An arbitration process handles priority if more than one master tries to transmit data at the same time. Mechanisms for resolving bus contention are inherent in the protocol. The TWI module supports master and slave functionality. The master and slave functionality are separated from each other, and can be enabled and configured separately. The master module supports multi-master bus operation and arbitration. It contains the baud rate generator. Both 100kHz and 400kHz bus frequency is supported. Quick command and smart mode can be enabled to auto-trigger operations and reduce software complexity. The slave module implements 7-bit address match and general address call recognition in hardware. 10-bit addressing is also supported. A dedicated address mask register can act as a second address match register or as a register for address range masking. The slave continues to operate in all sleep modes, including power-down mode. This enables the slave to wake up the device from all sleep modes on TWI address match. It is possible to disable the address matching to let this be handled in software instead. The TWI module will detect START and STOP conditions, bus collisions, and bus errors. Arbitration lost, errors, collision, and clock hold on the bus are also detected and indicated in separate status flags available in both master and slave modes. It is possible to disable the TWI drivers in the device, and enable a four-wire digital interface for connecting to an external TWI bus driver. This can be used for applications where the device operates from a different VCC voltage than used by the TWI bus. PORTC and PORTE each has one TWI. Notation of these peripherals are TWIC and TWIE. XMEGA C3 [DATASHEET] 8361C–AVR–4/12 40 23. SPI – Serial Peripheral Interface 23.1 Features • • • • • • • • • 23.2 Two Identical SPI peripherals Full-duplex, three-wire synchronous data transfer Master or slave operation Lsb first or msb first data transfer Eight programmable bit rates Interrupt flag at the end of transmission Write collision flag to indicate data collision Wake up from idle sleep mode Double speed master mode Overview The Serial Peripheral Interface (SPI) is a high-speed synchronous data transfer interface using three or four pins. It allows fast communication between an Atmel AVR XMEGA device and peripheral devices or between several microcontrollers. The SPI supports full-duplex communication. A device connected to the bus must act as a master or slave. The master initiates and controls all data transactions. PORTC and PORTD each has one SPI. Notation of these peripherals are SPIC and SPID, respectively. XMEGA C3 [DATASHEET] 8361C–AVR–4/12 41 24. USART 24.1 Features • Three identical USART peripherals • Full-duplex operation • Asynchronous or synchronous operation • • • • • • • 24.2 – Synchronous clock rates up to 1/2 of the device clock frequency – Asynchronous clock rates up to 1/8 of the device clock frequency Supports serial frames with 5, 6, 7, 8, or 9 data bits and 1 or 2 stop bits Fractional baud rate generator – Can generate desired baud rate from any system clock frequency – No need for external oscillator with certain frequencies Built-in error detection and correction schemes – Odd or even parity generation and parity check – Data overrun and framing error detection – Noise filtering includes false start bit detection and digital low-pass filter Separate interrupts for – Transmit complete – Transmit data register empty – Receive complete Multiprocessor communication mode – Addressing scheme to address a specific devices on a multidevice bus – Enable unaddressed devices to automatically ignore all frames Master SPI mode – Double buffered operation – Operation up to 1/2 of the peripheral clock frequency IRCOM module for IrDA compliant pulse modulation/demodulation Overview The universal synchronous and asynchronous serial receiver and transmitter (USART) is a fast and flexible serial communication module. The USART supports full-duplex communication and asynchronous and synchronous operation. The USART can be configured to operate in SPI master mode and used for SPI communication. Communication is frame based, and the frame format can be customized to support a wide range of standards. The USART is buffered in both directions, enabling continued data transmission without any delay between frames. Separate interrupts for receive and transmit complete enable fully interrupt driven communication. Frame error and buffer overflow are detected in hardware and indicated with separate status flags. Even or odd parity generation and parity check can also be enabled. The clock generator includes a fractional baud rate generator that is able to generate a wide range of USART baud rates from any system clock frequencies. This removes the need to use an external crystal oscillator with a specific frequency to achieve a required baud rate. It also supports external clock input in synchronous slave operation. When the USART is set in master SPI mode, all USART-specific logic is disabled, leaving the transmit and receive buffers, shift registers, and baud rate generator enabled. Pin control and interrupt generation are identical in both modes. The registers are used in both modes, but their functionality differs for some control settings. An IRCOM module can be enabled for one USART to support IrDA 1.4 physical compliant pulse modulation and demodulation for baud rates up to 115.2kbps. PORTC, PORTD, and PORTE each has one USART. Notation of these peripherals are USARTC0, USARTD0 and USARTE0, respectively. XMEGA C3 [DATASHEET] 8361C–AVR–4/12 42 25. IRCOM – IR Communication Module 25.1 Features • Pulse modulation/demodulation for infrared communication • IrDA compatible for baud rates up to 115.2Kbps • Selectable pulse modulation scheme – 3/16 of the baud rate period – Fixed pulse period, 8-bit programmable – Pulse modulation disabled • Built-in filtering • Can be connected to and used by any USART 25.2 Overview Atmel AVR XMEGA devices contain an infrared communication module (IRCOM) that is IrDA compatible for baud rates up to 115.2Kbps. It can be connected to any USART to enable infrared pulse encoding/decoding for that USART. XMEGA C3 [DATASHEET] 8361C–AVR–4/12 43 26. AES Crypto Engine 26.1 Features • Advanced Encryption Standard (AES) crypto module • DES Instruction – Encryption and decryption – DES supported – Encryption/decryption in 16 CPU clock cycles per 8-byte block • AES crypto module – Encryption and decryption – Supports 128-bit keys – Supports XOR data load mode to the state memory – Encryption/decryption in 375 clock cycles per 16-byte block 26.2 Overview The Advanced Encryption Standard (AES) is a commonly used standards for cryptography. It is supported through an AES peripheral module, and the communication interfaces and the CPU can use these for fast, encrypted communication and secure data storage. The AES crypto module encrypts and decrypts 128-bit data blocks with the use of a 128-bit key. The key and data must be loaded into the key and state memory in the module before encryption/decryption is started. It takes 375 peripheral clock cycles before the encryption/decryption is done. The encrypted/encrypted data can then be read out, and an optional interrupt can be generated. The AES crypto module also has DMA support with transfer triggers when encryption/decryption is done and optional auto-start of encryption/decryption when the state memory is fully loaded. XMEGA C3 [DATASHEET] 8361C–AVR–4/12 44 27. CRC – Cyclic Redundancy Check Generator 27.1 Features • Cyclic redundancy check (CRC) generation and checking for – Communication data – Program or data in flash memory – Data in SRAM and I/O memory space • Integrated with flash memory, DMA controller and CPU – Continuous CRC on data going through a DMA channel – Automatic CRC of the complete or a selectable range of the flash memory – CPU can load data to the CRC generator through the I/O interface • CRC polynomial software selectable to – CRC-16 (CRC-CCITT) – CRC-32 (IEEE 802.3) • Zero remainder detection 27.2 Overview A cyclic redundancy check (CRC) is an error detection technique test algorithm used to find accidental errors in data, and it is commonly used to determine the correctness of a data transmission, and data present in the data and program memories. A CRC takes a data stream or a block of data as input and generates a 16- or 32-bit output that can be appended to the data and used as a checksum. When the same data are later received or read, the device or application repeats the calculation. If the new CRC result does not match the one calculated earlier, the block contains a data error. The application will then detect this and may take a corrective action, such as requesting the data to be sent again or simply not using the incorrect data. Typically, an n-bit CRC applied to a data block of arbitrary length will detect any single error burst not longer than n bits (any single alteration that spans no more than n bits of the data), and will detect the fraction 1-2-n of all longer error bursts. The CRC module in Atmel AVR XMEGA devices supports two commonly used CRC polynomials; CRC-16 (CRCCCITT) and CRC-32 (IEEE 802.3). z z CRC-16: Polynomial: x16+x12+x5+1 Hex value: 0x1021 CRC-32: Polynomial: x32+x26+x23+x22+x16+x12+x11+x10+x8+x7+x5+x4+x2+x+1 Hex value: 0x04C11DB7 XMEGA C3 [DATASHEET] 8361C–AVR–4/12 45 28. ADC – 12-bit Analog to Digital Converter 28.1 Features • One Analog to Digital Converter (ADC) • 12-bit resolution • Up to 300 thousand samples per second • • • • • • • • • 28.2 – Down to 2.3µs conversion time with 8-bit resolution – Down to 3.35µs conversion time with 12-bit resolution Differential and single-ended input – 16 single-ended inputs – 16x4 differential inputs without gain – 8x4 differential input with gain Built-in differential gain stage – 1/2x, 1x, 2x, 4x, 8x, 16x, 32x, and 64x gain options Single, continuous and scan conversion options Three internal inputs – Internal temperature sensor – VCC voltage divided by 10 – 1.1V bandgap voltage Internal and external reference options Compare function for accurate monitoring of user defined thresholds Optional event triggered conversion for accurate timing Optional DMA transfer of conversion results Optional interrupt/event on compare result Overview The ADC converts analog signals to digital values. The ADC has 12-bit resolution and is capable of converting up to 300 thousand samples per second (ksps). The input selection is flexible, and both single-ended and differential measurements can be done. For differential measurements, an optional gain stage is available to increase the dynamic range. In addition, several internal signal inputs are available. The ADC can provide both signed and unsigned results. The ADC measurements can either be started by application software or an incoming event from another peripheral in the device. The ADC measurements can be started with predictable timing, and without software intervention. It is possible to use DMA to move ADC results directly to memory or peripherals when conversions are done. Both internal and external reference voltages can be used. An integrated temperature sensor is available for use with the ADC. The VCC/10 and the bandgap voltage can also be measured by the ADC. The ADC has a compare function for accurate monitoring of user defined thresholds with minimum software intervention required. XMEGA C3 [DATASHEET] 8361C–AVR–4/12 46 Figure 28-1. ADC overview. ADC0 • • • ADC15 Compare Register ADC Internal signals ADC0 • • • ADC7 < > VINP Threshold (Int Req) CH0 Result VINN Internal 1.00V Internal VCC/1.6V Internal VCC/2 AREFA AREFB Reference Voltage The ADC may be configured for 8- or 12-bit result, reducing the minimum conversion time (propagation delay) from 3.35µs for 12-bit to 2.3µs for 8-bit result. ADC conversion results are provided left- or right adjusted with optional ‘1’ or ‘0’ padding. This eases calculation when the result is represented as a signed integer (signed 16-bit number). PORTA has one ADC. Notation of this peripheral is ADCA. XMEGA C3 [DATASHEET] 8361C–AVR–4/12 47 29. AC – Analog Comparator 29.1 Features • Two Analog Comparators (AC) • Selectable hysteresis • • • • • 29.2 – No – Small – Large Analog comparator output available on pin Flexible input selection – All pins on the port – Bandgap reference voltage – A 64-level programmable voltage scaler of the internal VCC voltage Interrupt and event generation on: – Rising edge – Falling edge – Toggle Window function interrupt and event generation on: – Signal above window – Signal inside window – Signal below window Constant current source with configurable output pin selection Overview The analog comparator (AC) compares the voltage levels on two inputs and gives a digital output based on this comparison. The analog comparator may be configured to generate interrupt requests and/or events upon several different combinations of input change. The analog comparator hysteresis can be adjusted in order to achieve the optimal operation for each application. The input selection includes analog port pins, several internal signals, and a 64-level programmable voltage scaler. The analog comparator output state can also be output on a pin for use by external devices. A constant current source can be enabled and output on a selectable pin. This can be used to replace, for example, external resistors used to charge capacitors in capacitive touch sensing applications. The analog comparators are always grouped in pairs on each port. These are called analog comparator 0 (AC0) and analog comparator 1 (AC1). They have identical behavior, but separate control registers. Used as pair, they can be set in window mode to compare a signal to a voltage range instead of a voltage level. PORTA has one AC pair. Notation is ACA . XMEGA C3 [DATASHEET] 8361C–AVR–4/12 48 Figure 29-1. Analog comparator overview. Pin Input + AC0OUT AC0 Pin Input Hysteresis Enable Voltage Scaler ACnCTRL ACnMUXCTRL Bandgap Interrupt Mode WINCTRL Enable Interrupt Sensititivity Control & Window Function Interrupts Events Hysteresis + Pin Input AC1OUT AC1 Pin Input The window function is realized by connecting the external inputs of the two analog comparators in a pair as shown in Figure 29-2. Figure 29-2. Analog comparator window function. + AC0 Upper limit of window Interrupt sensitivity control Input signal Interrupts Events + AC1 Lower limit of window - XMEGA C3 [DATASHEET] 8361C–AVR–4/12 49 30. Programming and Debugging 30.1 Features • Programming – External programming through PDI interface Minimal protocol overhead for fast operation Built-in error detection and handling for reliable operation – Boot loader support for programming through any communication interface • Debugging – Nonintrusive, real-time, on-chip debug system – No software or hardware resources required from device except pin connection – Program flow control Go, Stop, Reset, Step Into, Step Over, Step Out, Run-to-Cursor – Unlimited number of user program breakpoints – Unlimited number of user data breakpoints, break on: Data location read, write, or both read and write Data location content equal or not equal to a value Data location content is greater or smaller than a value Data location content is within or outside a range – No limitation on device clock frequency • Program and Debug Interface (PDI) – Two-pin interface for external programming and debugging – Uses the Reset pin and a dedicated pin – No I/O pins required during programming or debugging 30.2 Overview The Program and Debug Interface (PDI) is an Atmel proprietary interface for external programming and on-chip debugging of a device. The PDI supports fast programming of nonvolatile memory (NVM) spaces; flash, EEPOM, fuses, lock bits, and the user signature row. Debug is supported through an on-chip debug system that offers nonintrusive, real-time debug. It does not require any software or hardware resources except for the device pin connection. Using the Atmel tool chain, it offers complete program flow control and support for an unlimited number of program and complex data breakpoints. Application debug can be done from a C or other high-level language source code level, as well as from an assembler and disassembler level. Programming and debugging can be done through the PDI physical layer. This is a two-pin interface that uses the Reset pin for the clock input (PDI_CLK) and one other dedicated pin for data input and output (PDI_DATA). Any external programmer or on-chip debugger/emulator can be directly connected to this interface. XMEGA C3 [DATASHEET] 8361C–AVR–4/12 50 31. Pinout and Pin Functions The device pinout is shown in “Pinout/Block Diagram” on page 3. In addition to general purpose I/O functionality, each pin can have several alternate functions. This will depend on which peripheral is enabled and connected to the actual pin. Only one of the pin functions can be used at time. 31.1 Alternate Pin Function Description The tables below show the notation for all pin functions available and describe its function. 31.1.1 Operation/Power Supply VCC Digital supply voltage AVCC Analog supply voltage GND Ground 31.1.2 Port Interrupt functions SYNC Port pin with full synchronous and limited asynchronous interrupt function ASYNC Port pin with full synchronous and full asynchronous interrupt function 31.1.3 Analog functions ACn Analog Comparator input pin n ACnOUT Analog Comparator n Output ADCn Analog to Digital Converter input pin n AREF Analog Reference input pin 31.1.4 Timer/Counter and AWEX functions OCnxLS Output Compare Channel x Low Side for Timer/Counter n OCnxHS Output Compare Channel x High Side for Timer/Counter n XMEGA C3 [DATASHEET] 8361C–AVR–4/12 51 31.1.5 Communication functions SCL Serial Clock for TWI SDA Serial Data for TWI SCLIN Serial Clock In for TWI when external driver interface is enabled SCLOUT Serial Clock Out for TWI when external driver interface is enabled SDAIN Serial Data In for TWI when external driver interface is enabled SDAOUT Serial Data Out for TWI when external driver interface is enabled XCKn Transfer Clock for USART n RXDn Receiver Data for USART n TXDn Transmitter Data for USART n SS Slave Select for SPI MOSI Master Out Slave In for SPI MISO Master In Slave Out for SPI SCK Serial Clock for SPI D- Data- for USB D+ Data+ for USB 31.1.6 Oscillators, Clock and Event TOSCn Timer Oscillator pin n XTALn Input/Output for Oscillator pin n CLKOUT Peripheral Clock Output EVOUT Event Channel Output RTCOUT RTC Clock Source Output 31.1.7 Debug/System functions RESET Reset pin PDI_CLK Program and Debug Interface Clock pin PDI_DATA Program and Debug Interface Data pin XMEGA C3 [DATASHEET] 8361C–AVR–4/12 52 31.2 Alternate Pin Functions The tables below show the primary/default function for each pin on a port in the first column, the pin number in the second column, and then all alternate pin functions in the remaining columns. The head row shows what peripheral that enable and use the alternate pin functions. For better flexibility, some alternate functions also have selectable pin locations for their functions, this is noted under the first table where this apply. Table 31-1. Port A - Alternate functions. ADCA POS/ PORT A PIN # INTERRUPT GAIN POS ADCA NEG ADCA GAINNEG ACA POS ACA NEG GND 60 AVCC 61 PA0 62 SYNC ADC0 ADC0 AC0 AC0 PA1 63 SYNC ADC1 ADC1 AC1 AC1 PA2 64 SYNC/ASYN C ADC2 ADC2 AC2 PA3 1 SYNC ADC3 ADC3 AC3 PA4 2 SYNC ADC4 ADC4 AC4 PA5 3 SYNC ADC5 ADC5 AC5 PA6 4 SYNC ADC6 ADC6 AC6 PA7 5 SYNC ADC7 ADC7 ACA OUT REFA AREFA AC3 AC5 AC1OUT AC7 AC0OUT Table 31-2. Port B - Alternate functions. PORT B PIN # INTERRUPT ADCA POS REFB PB0 6 SYNC ADC8 AREFB PB1 6 SYNC ADC9 PB2 8 SYNC/ASYN C ADC10 PB3 9 SYNC ADC11 PB4 10 SYNC ADC12 PB5 11 SYNC ADC13 PB6 12 SYNC ADC14 PB7 13 SYNC ADC15 GND 14 VCC 15 XMEGA C3 [DATASHEET] 8361C–AVR–4/12 53 Table 31-3. Port C - Alternate functions. PIN # INTERRUPT TCC0(1)(2) AWEXC PC0 16 SYNC OC0A OC0ALS PC1 17 SYNC OC0B OC0AHS XCK0 PC2 18 SYNC/ASYN C OC0C OC0BLS RXD0 PC3 19 SYNC OC0D OC0BHS TXD0 PC4 20 SYNC OC0CLS OC1A SS PC5 21 SYNC OC0CHS OC1B MOSI PC6 22 SYNC OC0DLS MISO RTCOUT PC7 23 SYNC OC0DHS SCK clkPER GND 24 VCC 25 PORT C Notes: 1. 2. 3. 4. 5. 6. TCC1 USARTC0(3) SPIC(4) TWIC CLOCKOUT (5) EVENTOUT(6) SDA SCL EVOUT Pin mapping of all TC0 can optionally be moved to high nibble of port. If TC0 is configured as TC2 all eight pins can be used for PWM output. Pin mapping of all USART0 can optionally be moved to high nibble of port. Pins MOSI and SCK for all SPI can optionally be swapped. CLKOUT can optionally be moved between port C, D and E and between pin 4 and 7. EVOUT can optionally be moved between port C, D and E and between pin 4 and 7 Table 31-4. Port D - Alternate functions. PORT D PIN # INTERRUPT TCD0 USARTD0 SPID USB PD0 26 SYNC OC0A PD1 27 SYNC OC0B XCK0 PD2 28 SYNC/ASYN C OC0C RXD0 PD3 29 SYNC OC0D TXD0 PD4 30 SYNC SS PD5 31 SYNC MOSI PD6 32 SYNC MISO D- PD7 33 SYNC SCK D+ GND 34 VCC 35 CLOCKOUT EVENTOUT ClkPER EVOUT XMEGA C3 [DATASHEET] 8361C–AVR–4/12 54 Table 31-5. Port E - Alternate functions. PORT E PIN # INTERRUPT TCE0 USARTE0 TOSC PE0 36 SYNC OC0A PE1 37 SYNC OC0B XCK0 PE2 38 SYNC/ASYNC OC0C RXD0 PE3 39 SYNC OC0D TXD0 PE4 40 SYNC PE5 41 SYNC PE6 42 SYNC TOSC2 PE7 43 SYNC TOSC1 GND 44 VCC 45 TWIE CLOCKOUT EVENTOUT ClkPER EVOUT SDA SCL Table 31-6. Port F - Alternate functions. PORT F PIN # INTERRUPT TCF0 PF0 46 SYNC OC0A PF1 47 SYNC OC0B PF2 48 SYNC/ASYNC OC0C PF3 49 SYNC OC0D PF4 50 SYNC PF5 51 SYNC PF6 54 SYNC PF7 55 SYNC GND 52 VCC 53 Table 31-7. Port R - Alternate functions PORT R PIN # INTERRUPT PDI XTAL PDI 56 PDI_DATA RESET 57 PDI_CLOCK PRO 58 SYNC XTAL2 PR1 59 SYNC XTAL1 XMEGA C3 [DATASHEET] 8361C–AVR–4/12 55 32. Peripheral Module Address Map The address maps show the base address for each peripheral and module in Atmel AVR XMEGA C3. For complete register description and summary for each peripheral module, refer to the XMEGA C manual. Table 32-1. Peripheral module address map. Base address Name Description 0x0000 GPIO General Purpose IO Registers 0x0010 VPORT0 Virtual Port 0 0x0014 VPORT1 Virtual Port 1 0x0018 VPORT2 Virtual Port 2 0x001C VPORT3 Virtual Port 2 0x0030 CPU CPU 0x0040 CLK Clock Control 0x0048 SLEEP Sleep Controller 0x0050 OSC Oscillator Control 0x0060 DFLLRC32M DFLL for the 32 MHz Internal RC Oscillator 0x0068 DFLLRC2M DFLL for the 2 MHz RC Oscillator 0x0070 PR Power Reduction 0x0078 RST Reset Controller 0x0080 WDT Watch-Dog Timer 0x0090 MCU MCU Control 0x00A0 PMIC Programmable MUltilevel Interrupt Controller 0x00B0 PORTCFG 0x0180 EVSYS 0x00C0 AES AES Module 0x00D0 CRC CRC Module 0x0100 DMA DMA Controller 0x01C0 NVM Non Volatile Memory (NVM) Controller 0x0200 ADCA Analog to Digital Converter on port A 0x0380 ACA Analog Comparator pair on port A 0x0400 RTC Real Time Counter 0x0480 TWIC Two Wire Interface on port C 0x04C0 USB Universal Serial Bus Interface 0x04A0 TWIE Two Wire Interface on port E 0x0600 PORTA Port Configuration Event System Port A XMEGA C3 [DATASHEET] 8361C–AVR–4/12 56 Base address Name Description 0x0620 PORTB Port B 0x0640 PORTC Port C 0x0660 PORTD Port D 0x0680 PORTE Port E 0x06A0 PORTF Port F 0x07E0 PORTR Port R 0x0800 TCC0 Timer/Counter 0 on port C 0x0840 TCC1 Timer/Counter 1 on port C 0x0880 AWEXC Advanced Waveform Extension on port C 0x0890 HIRESC High Resolution Extension on port C 0x08A0 USARTC0 0x08C0 SPIC 0x08F8 IRCOM 0x0900 TCD0 0x09A0 USARTD0 0x09C0 SPID Serial Peripheral Interface on port D 0x0A00 TCE0 Timer/Counter 0 on port E 0x0A80 AWEXE 0x0AA0 USARTE0 0x0AC0 SPIE Serial Peripheral Interface on port E 0x0B00 TCF0 Timer/Counter 0 on port F USART 0 on port C Serial Peripheral Interface on port C Infrared Communication Module Timer/Counter 0 on port D USART 0 on port D Advanced Waveform Extensionon port E USART 0 on port E XMEGA C3 [DATASHEET] 8361C–AVR–4/12 57 33. Instruction Set Summary Mnemonics Operands Description Operation Flags #Clocks Arithmetic and Logic Instructions ADD Rd, Rr Add without Carry Rd ← Rd + Rr Z,C,N,V,S,H 1 ADC Rd, Rr Add with Carry Rd ← Rd + Rr + C Z,C,N,V,S,H 1 ADIW Rd, K Add Immediate to Word Rd ← Rd + 1:Rd + K Z,C,N,V,S 2 SUB Rd, Rr Subtract without Carry Rd ← Rd - Rr Z,C,N,V,S,H 1 SUBI Rd, K Subtract Immediate Rd ← Rd - K Z,C,N,V,S,H 1 SBC Rd, Rr Subtract with Carry Rd ← Rd - Rr - C Z,C,N,V,S,H 1 SBCI Rd, K Subtract Immediate with Carry Rd ← Rd - K - C Z,C,N,V,S,H 1 SBIW Rd, K Subtract Immediate from Word Rd + 1:Rd ← Rd + 1:Rd - K Z,C,N,V,S 2 AND Rd, Rr Logical AND Rd ← Rd • Rr Z,N,V,S 1 ANDI Rd, K Logical AND with Immediate Rd ← Rd • K Z,N,V,S 1 OR Rd, Rr Logical OR Rd ← Rd v Rr Z,N,V,S 1 ORI Rd, K Logical OR with Immediate Rd ← Rd v K Z,N,V,S 1 EOR Rd, Rr Exclusive OR Rd ← Rd ⊕ Rr Z,N,V,S 1 COM Rd One’s Complement Rd ← $FF - Rd Z,C,N,V,S 1 NEG Rd Two’s Complement Rd ← $00 - Rd Z,C,N,V,S,H 1 SBR Rd,K Set Bit(s) in Register Rd ← Rd v K Z,N,V,S 1 CBR Rd,K Clear Bit(s) in Register Rd ← Rd • ($FFh - K) Z,N,V,S 1 INC Rd Increment Rd ← Rd + 1 Z,N,V,S 1 DEC Rd Decrement Rd ← Rd - 1 Z,N,V,S 1 TST Rd Test for Zero or Minus Rd ← Rd • Rd Z,N,V,S 1 CLR Rd Clear Register Rd ← Rd ⊕ Rd Z,N,V,S 1 SER Rd Set Register Rd ← $FF None 1 MUL Rd,Rr Multiply Unsigned R1:R0 ← Rd x Rr (UU) Z,C 2 MULS Rd,Rr Multiply Signed R1:R0 ← Rd x Rr (SS) Z,C 2 MULSU Rd,Rr Multiply Signed with Unsigned R1:R0 ← Rd x Rr (SU) Z,C 2 FMUL Rd,Rr Fractional Multiply Unsigned R1:R0 ← Rd x Rr<<1 (UU) Z,C 2 FMULS Rd,Rr Fractional Multiply Signed R1:R0 ← Rd x Rr<<1 (SS) Z,C 2 FMULSU Rd,Rr Fractional Multiply Signed with Unsigned R1:R0 ← Rd x Rr<<1 (SU) Z,C 2 DES K Data Encryption if (H = 0) then R15:R0 else if (H = 1) then R15:R0 ← ← Encrypt(R15:R0, K) Decrypt(R15:R0, K) PC ← PC + k + 1 None 2 1/2 Branch instructions RJMP k Relative Jump IJMP Indirect Jump to (Z) PC(15:0) PC(21:16) ← ← Z, 0 None 2 EIJMP Extended Indirect Jump to (Z) PC(15:0) PC(21:16) ← ← Z, EIND None 2 JMP k Jump PC ← k None 3 RCALL k Relative Call Subroutine PC ← PC + k + 1 None 2 / 3(1) XMEGA C3 [DATASHEET] 8361C–AVR–4/12 58 Mnemonics Operands Description Operation Flags #Clocks ICALL Indirect Call to (Z) PC(15:0) PC(21:16) ← ← Z, 0 None 2 / 3(1) EICALL Extended Indirect Call to (Z) PC(15:0) PC(21:16) ← ← Z, EIND None 3(1) call Subroutine PC ← k None 3 / 4(1) RET Subroutine Return PC ← STACK None 4 / 5(1) RETI Interrupt Return PC ← STACK I 4 / 5(1) if (Rd = Rr) PC ← PC + 2 or 3 None 1/2/3 CALL k CPSE Rd,Rr Compare, Skip if Equal CP Rd,Rr Compare CPC Rd,Rr Compare with Carry CPI Rd,K Compare with Immediate SBRC Rr, b Skip if Bit in Register Cleared if (Rr(b) = 0) PC ← PC + 2 or 3 None 1/2/3 SBRS Rr, b Skip if Bit in Register Set if (Rr(b) = 1) PC ← PC + 2 or 3 None 1/2/3 SBIC A, b Skip if Bit in I/O Register Cleared if (I/O(A,b) = 0) PC ← PC + 2 or 3 None 2/3/4 SBIS A, b Skip if Bit in I/O Register Set If (I/O(A,b) =1) PC ← PC + 2 or 3 None 2/3/4 BRBS s, k Branch if Status Flag Set if (SREG(s) = 1) then PC ← PC + k + 1 None 1/2 BRBC s, k Branch if Status Flag Cleared if (SREG(s) = 0) then PC ← PC + k + 1 None 1/2 BREQ k Branch if Equal if (Z = 1) then PC ← PC + k + 1 None 1/2 BRNE k Branch if Not Equal if (Z = 0) then PC ← PC + k + 1 None 1/2 BRCS k Branch if Carry Set if (C = 1) then PC ← PC + k + 1 None 1/2 BRCC k Branch if Carry Cleared if (C = 0) then PC ← PC + k + 1 None 1/2 BRSH k Branch if Same or Higher if (C = 0) then PC ← PC + k + 1 None 1/2 BRLO k Branch if Lower if (C = 1) then PC ← PC + k + 1 None 1/2 BRMI k Branch if Minus if (N = 1) then PC ← PC + k + 1 None 1/2 BRPL k Branch if Plus if (N = 0) then PC ← PC + k + 1 None 1/2 BRGE k Branch if Greater or Equal, Signed if (N ⊕ V= 0) then PC ← PC + k + 1 None 1/2 BRLT k Branch if Less Than, Signed if (N ⊕ V= 1) then PC ← PC + k + 1 None 1/2 BRHS k Branch if Half Carry Flag Set if (H = 1) then PC ← PC + k + 1 None 1/2 BRHC k Branch if Half Carry Flag Cleared if (H = 0) then PC ← PC + k + 1 None 1/2 BRTS k Branch if T Flag Set if (T = 1) then PC ← PC + k + 1 None 1/2 BRTC k Branch if T Flag Cleared if (T = 0) then PC ← PC + k + 1 None 1/2 BRVS k Branch if Overflow Flag is Set if (V = 1) then PC ← PC + k + 1 None 1/2 BRVC k Branch if Overflow Flag is Cleared if (V = 0) then PC ← PC + k + 1 None 1/2 BRIE k Branch if Interrupt Enabled if (I = 1) then PC ← PC + k + 1 None 1/2 BRID k Branch if Interrupt Disabled if (I = 0) then PC ← PC + k + 1 None 1/2 Rd ← Rr None 1 Rd+1:Rd ← Rr+1:Rr None 1 Rd ← K None 1 Rd - Rr Z,C,N,V,S,H 1 Rd - Rr - C Z,C,N,V,S,H 1 Rd - K Z,C,N,V,S,H 1 Data transfer instructions MOV Rd, Rr Copy Register MOVW Rd, Rr Copy Register Pair LDI Rd, K Load Immediate XMEGA C3 [DATASHEET] 8361C–AVR–4/12 59 Mnemonics Operands Description Flags #Clocks LDS Rd, k Load Direct from data space Rd ← (k) None 2(1)(2) LD Rd, X Load Indirect Rd ← (X) None 1(1)(2) LD Rd, X+ Load Indirect and Post-Increment Rd X ← ← (X) X+1 None 1(1)(2) LD Rd, -X Load Indirect and Pre-Decrement X ← X - 1, Rd ← (X) ← ← X-1 (X) None 2(1)(2) LD Rd, Y Load Indirect Rd ← (Y) ← (Y) None 1(1)(2) LD Rd, Y+ Load Indirect and Post-Increment Rd Y ← ← (Y) Y+1 None 1(1)(2) LD Rd, -Y Load Indirect and Pre-Decrement Y Rd ← ← Y-1 (Y) None 2(1)(2) LDD Rd, Y+q Load Indirect with Displacement Rd ← (Y + q) None 2(1)(2) LD Rd, Z Load Indirect Rd ← (Z) None 1(1)(2) LD Rd, Z+ Load Indirect and Post-Increment Rd Z ← ← (Z), Z+1 None 1(1)(2) LD Rd, -Z Load Indirect and Pre-Decrement Z Rd ← ← Z - 1, (Z) None 2(1)(2) LDD Rd, Z+q Load Indirect with Displacement Rd ← (Z + q) None 2(1)(2) STS k, Rr Store Direct to Data Space (k) ← Rd None 2(1) ST X, Rr Store Indirect (X) ← Rr None 1(1) ST X+, Rr Store Indirect and Post-Increment (X) X ← ← Rr, X+1 None 1(1) ST -X, Rr Store Indirect and Pre-Decrement X (X) ← ← X - 1, Rr None 2(1) ST Y, Rr Store Indirect (Y) ← Rr None 1(1) ST Y+, Rr Store Indirect and Post-Increment (Y) Y ← ← Rr, Y+1 None 1(1) ST -Y, Rr Store Indirect and Pre-Decrement Y (Y) ← ← Y - 1, Rr None 2(1) STD Y+q, Rr Store Indirect with Displacement (Y + q) ← Rr None 2(1) ST Z, Rr Store Indirect (Z) ← Rr None 1(1) ST Z+, Rr Store Indirect and Post-Increment (Z) Z ← ← Rr Z+1 None 1(1) ST -Z, Rr Store Indirect and Pre-Decrement Z ← Z-1 None 2(1) STD Z+q,Rr Store Indirect with Displacement (Z + q) ← Rr None 2(1) Load Program Memory R0 ← (Z) None 3 LPM Operation LPM Rd, Z Load Program Memory Rd ← (Z) None 3 LPM Rd, Z+ Load Program Memory and Post-Increment Rd Z ← ← (Z), Z+1 None 3 Extended Load Program Memory R0 ← (RAMPZ:Z) None 3 ELPM ELPM Rd, Z Extended Load Program Memory Rd ← (RAMPZ:Z) None 3 ELPM Rd, Z+ Extended Load Program Memory and PostIncrement Rd Z ← ← (RAMPZ:Z), Z+1 None 3 Store Program Memory (RAMPZ:Z) ← R1:R0 None - Store Program Memory and Post-Increment by 2 (RAMPZ:Z) Z ← ← R1:R0, Z+2 None - SPM SPM Z+ XMEGA C3 [DATASHEET] 8361C–AVR–4/12 60 Mnemonics Operands Description IN Rd, A In From I/O Location OUT A, Rr Out To I/O Location PUSH Rr Push Register on Stack POP Rd XCH Operation Flags #Clocks Rd ← I/O(A) None 1 I/O(A) ← Rr None 1 STACK ← Rr None 1(1) Pop Register from Stack Rd ← STACK None 2(1) Z, Rd Exchange RAM location Temp Rd (Z) ← ← ← Rd, (Z), Temp None 2 LAS Z, Rd Load and Set RAM location Temp Rd (Z) ← ← ← Rd, (Z), Temp v (Z) None 2 LAC Z, Rd Load and Clear RAM location Temp Rd (Z) ← ← ← Rd, (Z), ($FFh – Rd) z (Z) None 2 LAT Z, Rd Load and Toggle RAM location Temp Rd (Z) ← ← ← Rd, (Z), Temp ⊕ (Z) None 2 Rd(n+1) Rd(0) C ← ← ← Rd(n), 0, Rd(7) Z,C,N,V,H 1 Rd(n) Rd(7) C ← ← ← Rd(n+1), 0, Rd(0) Z,C,N,V 1 Rd(0) Rd(n+1) C ← ← ← C, Rd(n), Rd(7) Z,C,N,V,H 1 Bit and bit-test instructions LSL Rd Logical Shift Left LSR Rd Logical Shift Right ROL Rd Rotate Left Through Carry ROR Rd Rotate Right Through Carry Rd(7) Rd(n) C ← ← ← C, Rd(n+1), Rd(0) Z,C,N,V 1 ASR Rd Arithmetic Shift Right Rd(n) ← Rd(n+1), n=0..6 Z,C,N,V 1 SWAP Rd Swap Nibbles Rd(3..0) ↔ Rd(7..4) None 1 BSET s Flag Set SREG(s) ← 1 SREG(s) 1 BCLR s Flag Clear SREG(s) ← 0 SREG(s) 1 SBI A, b Set Bit in I/O Register I/O(A, b) ← 1 None 1 CBI A, b Clear Bit in I/O Register I/O(A, b) ← 0 None 1 BST Rr, b Bit Store from Register to T T ← Rr(b) T 1 BLD Rd, b Bit load from T to Register Rd(b) ← T None 1 SEC Set Carry C ← 1 C 1 CLC Clear Carry C ← 0 C 1 SEN Set Negative Flag N ← 1 N 1 CLN Clear Negative Flag N ← 0 N 1 SEZ Set Zero Flag Z ← 1 Z 1 CLZ Clear Zero Flag Z ← 0 Z 1 SEI Global Interrupt Enable I ← 1 I 1 CLI Global Interrupt Disable I ← 0 I 1 SES Set Signed Test Flag S ← 1 S 1 CLS Clear Signed Test Flag S ← 0 S 1 XMEGA C3 [DATASHEET] 8361C–AVR–4/12 61 Mnemonics Operands Description Operation Flags #Clocks SEV Set Two’s Complement Overflow V ← 1 V 1 CLV Clear Two’s Complement Overflow V ← 0 V 1 SET Set T in SREG T ← 1 T 1 CLT Clear T in SREG T ← 0 T 1 SEH Set Half Carry Flag in SREG H ← 1 H 1 CLH Clear Half Carry Flag in SREG H ← 0 H 1 None 1 None 1 MCU control instructions BREAK Break NOP No Operation SLEEP Sleep (see specific descr. for Sleep) None 1 WDR Watchdog Reset (see specific descr. for WDR) None 1 Notes: 1. 2. (See specific descr. for BREAK) Cycle times for data memory accesses assume internal memory accesses, and are not valid for accesses via the external RAM interface. One extra cycle must be added when accessing internal SRAM. XMEGA C3 [DATASHEET] 8361C–AVR–4/12 62 34. Packaging information 34.1 64A PIN 1 B e PIN 1 IDENTIFIER E1 E D1 D C 0°~7° A1 A2 A L COMMON DIMENSIONS (Unit of Measure = mm) Notes: 1.This package conforms to JEDEC reference MS-026, Variation AEB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.10mm maximum. SYMBOL MIN NOM MAX A – – 1.20 A1 0.05 – 0.15 A2 0.95 1.00 1.05 D 15.75 16.00 16.25 D1 13.90 14.00 14.10 E 15.75 16.00 16.25 E1 13.90 14.00 14.10 B 0.30 – 0.45 C 0.09 – 0.20 L 0.45 – 0.75 e NOTE Note 2 Note 2 0.80 TYP 2010-10-20 R 2325 Orchard Parkway San Jose, CA 95131 TITLE 64A, 64-lead, 14 x 14mm Body Size, 1.0mm Body Thickness, 0.8mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP) DRAWING NO. REV. 64A C XMEGA C3 [DATASHEET] 8361C–AVR–4/12 63 34.2 64Z3 XMEGA C3 [DATASHEET] 8361C–AVR–4/12 64 35. Electrical Characteristics All typical values are measured at T = 25°C unless other temperature condition is given. All minimum and maximum values are valid across operating temperature and voltage unless other conditions are given. 35.1 Absolute Maximum Ratings Stresses beyond those listed in Table 35-1 under may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 35-1. Absolute maximum ratings. Symbol 35.2 Parameter Condition Min. Typ. -0.3 Max. Units 4 V VCC Power supply voltage IVCC Current into a VCC pin 200 IGND Current out of a Gnd pin 200 VPIN Pin voltage with respect to Gnd and VCC -0.5 VCC+0.5 V IPIN I/O pin sink/source current -25 25 mA TA Storage temperature -65 150 Tj Junction temperature 150 mA °C General Operating Ratings The device must operate within the ratings listed in Table 35-2 in order for all other electrical characteristics and typical characteristics of the device to be valid. Table 35-2. General operating conditions. Symbol Parameter Condition Min. Typ. Max. VCC Power supply voltage 1.60 3.6 AVCC Analog supply voltage 1.60 3.6 TA Temperature range -40 85 Tj Junction temperature -40 105 Units V °C Table 35-3. Operating voltage and frequency. Symbol ClkCPU Parameter CPU clock frequency Condition Min. Typ. Max. VCC = 1.6V 0 12 VCC = 1.8V 0 12 VCC = 2.7V 0 32 VCC = 3.6V 0 32 Units MHz XMEGA C3 [DATASHEET] 8361C–AVR–4/12 65 The maximum CPU clock frequency depends on VCC. As shown in Figure 35-1 the Frequency vs. VCC curve is linear between 1.8V < VCC < 2.7V. Figure 35-1. Maximum Frequency vs. VCC. MHz 32 Safe Operating Area 12 1.6 1.8 2.7 3.6 V XMEGA C3 [DATASHEET] 8361C–AVR–4/12 66 35.3 Current consumption Table 35-4. Current consumption for Active mode and sleep modes. Symbol Parameter Condition 32kHz, Ext. Clk Active power consumption(1) 1MHz, Ext. Clk 2MHz, Ext. Clk 32MHz, Ext. Clk 32kHz, Ext. Clk Idle power consumption(1) 1MHz, Ext. Clk 2MHz, Ext. Clk ICC 32MHz, Ext. Clk T = 25°C T = 85°C Power-down power consumption WDT and sampled BOD enabled, T = 25°C WDT and sampled BOD enabled, T = 85°C Power-save power consumption(2) Reset power consumption Notes: 1. 2. Min. Typ. Max. VCC = 1.8V 150 VCC = 3.0V 320 VCC = 1.8V 410 VCC = 3.0V 830 VCC = 1.8V 660 800 1.3 1.8 10 15 VCC = 3.0V µA VCC = 1.8V 4 VCC = 3.0V 5 VCC = 1.8V 50 VCC = 3.0V 100 VCC = 1.8V 100 350 200 600 3.3 7 0.2 1.0 3.5 6.0 1.5 2.0 6 10 VCC = 3.0V VCC = 3.0V mA µA mA VCC = 3.0V RTC from ULP clock, WDT and sampled BOD enabled, T = 25°C VCC = 1.8V 1.4 VCC = 3.0V 1.5 RTC from 1.024kHz low power 32.768kHz TOSC, T = 25°C VCC = 1.8V 0.7 2 VCC = 3.0V 0.8 2 RTC from low power 32.768kHz TOSC, T = 25°C VCC = 1.8V 0.9 3 VCC = 3.0V 1.1 3 VCC = 3.0V 300 Current through RESET pin substracted Units µA All Power Reduction Registers set. Maximum limits are based on characterization, and not tested in production. XMEGA C3 [DATASHEET] 8361C–AVR–4/12 67 Table 35-5. Current consumption for modules and peripherals. Symbol Parameter Condition(1) Min. ULP oscillator 32MHz int. oscillator PLL ICC Units 27 85 DFLL enabled with 32.768kHz int. osc. as reference 115 240 DFLL enabled with 32.768kHz int. osc. as reference 430 20x multiplication factor, 32MHz int. osc. DIV4 as reference 300 Watchdog timer BOD Max. 0.93 32.768kHz int. oscillator 2MHz int. oscillator Typ. µA 1 Continuous mode 140 Sampled mode, includes ULP oscillator 1.3 Internal 1.0V reference 220 Temperature sensor 215 1.12 16ksps VREF = Ext ref ADC 75ksps VREF = Ext ref 1. 1.01 CURRLIMIT = MEDIUM 0.9 CURRLIMIT = HIGH 0.8 CURRLIMIT = LOW 1.7 mA 300ksps VREF = Ext ref 3.1 DMA 615KBps between I/O registers and SRAM 115 USART Rx and Tx enabled, 9600 BAUD 9.5 Flash memory and EEPROM programming Note: CURRLIMIT = LOW 4 µA mA All parameters measured as the difference in current consumption between module enabled and disabled. All data at VCC = 3.0V, ClkSYS = 1MHz external clock without prescaling, T = 25°C unless other conditions are given. XMEGA C3 [DATASHEET] 8361C–AVR–4/12 68 35.4 Wake-up time from sleep modes Table 35-6. Device wake-up time from sleep modes with various system clock sources. Symbol Parameter Wake-up time from idle, standby, and extended standby mode twakeup Wake-up time from power-save and power-down mode Note: 1. Condition Min. Typ. (1) External 2MHz clock 2.0 32.768kHz internal oscillator 130 2MHz internal oscillator 2.0 32MHz internal oscillator 0.2 External 2MHz clock 4.5 32.768kHz internal oscillator 320 2MHz internal oscillator 9.0 32MHz internal oscillator 5.0 Max. Units µs The wake-up time is the time from the wake-up request is given until the peripheral clock is available on pin, see Figure 35-2. All peripherals and modules start execution from the first clock cycle, expect the CPU that is halted for four clock cycles before program execution starts. Figure 35-2. Wake-up time definition. Wakeup time Wakeup request Clock output XMEGA C3 [DATASHEET] 8361C–AVR–4/12 69 35.5 I/O Pin Characteristics The I/O pins complies with the JEDEC LVTTL and LVCMOS specification and the high- and low level input and output voltage limits reflect or exceed this specification. Table 35-7. I/O pin characteristics. Symbol (1) IOH / IOL (2) Parameter Max. Units -15 15 mA VCC = 2.4 - 3.6V 0.7*Vcc VCC+0.5 VCC = 1.6 - 2.4V 0.8*VCC VCC+0.5 VCC = 2.4- 3.6V -0.5 0.3*VCC VCC = 1.6 - 2.4V -0.5 0.2*VCC I/O pin source/sink current VIH High level input voltage VIL Low level input voltage VOH High level output voltage VOL Low level output voltage IIN Input leakage current I/O pin RP Notes: Condition 2. Typ. VCC = 3.3V IOH = -4mA 2.6 2.9 VCC = 3.0V IOH = -3mA 2.1 2.6 VCC = 1.8V IOH = -1mA 1.4 1.6 VCC = 3.3V IOL = 8mA 0.4 0.76 VCC = 3.0V IOL = 5mA 0.3 0.64 VCC = 1.8V IOL = 3mA 0.2 0.46 <0.01 1 T = 25°C Pull/buss keeper resistor 1. Min. V 25 µA kΩ The sum of all IOH for PORTA and PORTB must not exceed 100mA. The sum of all IOH for PORTC, PORTD, PORTE must for each port not exceed 200mA. The sum of all IOH for pins PF[0-5] on PORTF must not exceed 200mA. The sum of all IOL for pins PF[6-7] on PORTF, PORTR and PDI must not exceed 100mA. The sum of all IOL for PORTA and PORTB must not exceed 100mA. The sum of all IOL for PORTC, PORTD, PORTE must for each port not exceed 200mA. The sum of all IOL for pins PF[0-5] on PORTFmust not exceed 200mA. The sum of all IOL for pins PF[6-7] on PORTF, PORTR and PDI must not exceed 100mA. XMEGA C3 [DATASHEET] 8361C–AVR–4/12 70 35.6 ADC characteristics Table 35-8. Power supply, reference and input range. Symbol Parameter AVCC Analog supply voltage VREF Reference voltage Condition Min. Typ. Max. VCC- 0.3 VCC+ 0.3 1 AVCC- 0.6 Units V Rin Input resistance Switched 4.5 kΩ Cin Input capacitance Switched 5 pF RAREF Reference input resistance (leakage only) CAREF Reference input capacitance Static load Vin Input range ΔV Conversion range Differential mode, Vinp - Vinn Conversion range Single ended unsigned mode, Vinp >10 MΩ 7 pF 0 VREF -VREF VREF -ΔV VREF-ΔV Fixed offset voltage 200 V lsb Table 35-9. Clock and timing. Symbol ClkADC fClkADC fADC Parameter ADC clock frequency Condition Typ. Max. Maximum is 1/4 of peripheral clock frequency 100 1800 Measuring internal signals 100 125 16 300 Current limitation (CURRLIMIT) off 16 300 CURRLIMIT = LOW 16 250 CURRLIMIT = MEDIUM 16 150 CURRLIMIT = HIGH 16 50 Sample rate Sample rate Min. Sampling time Configureable in steps of 1/2 ClkADC cycles up to 32 ClkADC cycles 0.28 320 Conversion time (latency) (RES+1)/2 + GAIN RES (Resolution) = 8 or 12, GAIN=0 to 3 5.5 10 Start-up time ADC clock cycles 12 24 ADC settling time After changing reference or input mode 7 7 XMEGA C3 [DATASHEET] 8361C–AVR–4/12 Units kHz ksps µs ClkADC cycles 71 Table 35-10. Accuracy characteristics. Symbol RES Condition(2) Parameter Resolution 12-bit resolution Differential mode INL(1) Integral non-linearity Single ended unsigned mode Differential mode DNL(1) Differential non-linearity Single ended unsigned mode Offset error Gain error Differential mode Differential mode Min. Typ. Max. Differential 8 12 12 Single ended signed 7 11 11 Single ended unsigned 8 12 12 16ksps, VREF = 3V 0.5 1 16ksps, all VREF 0.8 2 300ksps, VREF = 3V 0.6 1 300ksps, all VREF 1 2 16ksps, VREF = 3.0V 0.5 1 16ksps, all VREF 1.3 2 16ksps, VREF = 3V 0.3 1 16ksps, all VREF 0.5 1 300ksps, VREF = 3V 0.35 1 300ksps, all VREF 0.5 1 16ksps, VREF = 3.0V 0.6 1 16ksps, all VREF 0.6 1 300ksps, VREF=3V -7 mV Temperature drift, VREF=3V 0.01 mV/K Operating voltage drift 0.16 mV/V External reference -5 AVCC/1.6 -5 AVCC/2.0 -6 Bandgap ±10 Temperature drift Single ended unsigned mode 1. 2. mV 2 mV/V -8 AVCC/1.6 -8 AVCC/2.0 -8 Bandgap ±10 mV 0.03 mV/K 2 mV/V Operating voltage drift Notes: lsb mV/K External reference Temperature drift Bits 0.02 Operating voltage drift Gain error Units Maximum numbers are based on characterisation and not tested in production, and valid for 5% to 95% input voltage range. Unless otherwise noted all linearity, offset and gain error numbers are valid under the condition that external VREF is used. XMEGA C3 [DATASHEET] 8361C–AVR–4/12 72 Table 35-11. Gain stage characteristics. Symbol Parameter Condition Min. Typ. Max. Units Rin Input resistance Switched in normal mode 4.0 kΩ Csample Input capacitance Switched in normal mode 4.4 pF Signal range Gain stage output Propagation delay ADC conversion rate 1/2 Clock rate Same as ADC 100 1 0.5x gain, normal mode -1 1x gain, normal mode -1 8x gain, normal mode -1 64x gain, normal mode 5 0.5x gain, normal mode 10 Offset error, 1x gain, normal mode 5 input referred 8x gain, normal mode -20 64x gain, normal mode -126 Gain error 35.7 0 AVCC- 0.6 V 3 ClkADC cycles 1800 kHz % mV Analog Comparator Characteristics Table 35-12. Analog Comparator characteristics. Symbol Parameter Condition Min. Typ. Voff Input offset voltage 10 Ilk Input leakage current <10 Input voltage range -0.1 AC startup time Hysteresis, none Vcc=1.6V - 3.6V 0 Vhys2 Hysteresis, small Vcc=1.6V - 3.6V 15 Vhys3 Hysteresis, large Vcc=1.6V - 3.6V 30 tdelay Propagation delay VCC = 3.0V, T= 85°C 20 VCC = 3.0V, T= 85°C 17 Integral non-linearity (INL) 0.3 Current source accuracy after calibration current source calibration range 50 nA AVCC V µs mV 90 0.5 5 4 Units mV 50 Vhys1 64-level voltage scaler Max. ns lsb % 6 XMEGA C3 [DATASHEET] 8361C–AVR–4/12 µA 73 35.8 Bandgap and Internal 1.0V Reference Characteristics Table 35-13. Bandgap and Internal 1.0V reference characteristics. Symbol Parameter Startup time Condition Min. As reference for ADC 35.9 Max. 1 ClkPER + 2.5µs As input voltage to ADC and AC 1.1 Internal 1.00V reference T= 85°C, after calibration Variation over voltage and temperature Calibrated at T= 85°C 0.99 1 Units µs 1.5 Bandgap voltage INT1V Typ. 1.01 2 V % Brownout Detection Characteristics Table 35-14. Brownout detection characteristics(1). Symbol Parameter Condition BOD level 0 falling VCC VBOT tBOD Note: Typ. Max. 1.60 1.62 1.72 BOD level 1 falling VCC 1.8 BOD level 2 falling VCC 2.0 BOD level 3 falling VCC 2.2 BOD level 4 falling VCC 2.4 BOD level 5 falling VCC 2.6 BOD level 6 falling VCC 2.8 BOD level 7 falling VCC 3.0 Detection time VHYST Min. Continuous mode µs 1000 Hysteresis 1. V 0.4 Sampled mode Units 1.0 % BOD is calibrated at 85°C within BOD level 0 values, and BOD level 0 is the default level. 35.10 External Reset Characteristics Table 35-15. External reset characteristics. Symbol tEXT VRST RRST Parameter Condition Minimum reset pulse width Reset threshold voltage Reset pin pull-up resistor Min. Typ. 1000 90 Max. Units ns VCC = 2.7 - 3.6V 0.45*VCC VCC = 1.6 - 2.7V 0.45*VCC 25 V kΩ XMEGA C3 [DATASHEET] 8361C–AVR–4/12 74 35.11 Power-on Reset Characteristics Table 35-16. Power-on reset characteristics. Symbol Parameter VPOT- (1) POR threshold voltage falling VCC VPOT+ Note: Condition Min. Typ. VCC falls faster than 1V/ms 0.4 1.0 VCC falls at 1V/ms or slower 0.8 1.3 POR threshold voltage rising VCC 1. Max. Units V 1.3 1.59 Typ. Max. VPOT- values are only valid when BOD is disabled. When BOD is enabled VPOT- = VPOT+. 35.12 Flash and EEPROM Memory Characteristics Table 35-17. Endurance and data retention. Symbol Parameter Condition Write/Erase cycles Flash Data retention Write/Erase cycles EEPROM Data retention Min. 25°C 10K 85°C 10K 25°C 100 55°C 25 25°C 100K 85°C 100K 25°C 100 55°C 25 Units Cycle Year Cycle Year Table 35-18. Programming time. Symbol Parameter Chip erase(2) Flash EEPROM Notes: 1. 2. Condition 384KB Flash, EEPROM Min. Typ.(1) Max. Units 130 Page erase 4 Page write 4 Atomic page erase and write 8 Page erase 4 Page write 4 Atomic page erase and write 8 ms Programming is timed from the 2MHz internal oscillator. EEPROM is not erased if the EESAVE fuse is programmed. XMEGA C3 [DATASHEET] 8361C–AVR–4/12 75 35.13 Clock and Oscillator Characteristics 35.13.1 Calibrated 32.768kHz Internal Oscillator characteristics Table 35-19. 32.768kHz internal oscillator characteristics. Symbol Parameter Condition Min. Frequency Factory calibration accuracy Typ. Max. 32.768 T = 85°C, VCC = 3.0V User calibration accuracy Units kHz -0.5 0.5 -0.5 0.5 % 35.13.2 Calibrated 2MHz RC Internal Oscillator characteristics Table 35-20. 2MHz internal oscillator characteristics. Symbol Parameter Frequency range Condition Min. DFLL can tune to this frequency over voltage and temperature 1.8 Factory calibrated frequency Factory calibration accuracy Typ. Max. 2.2 Units MHz 2.0 T = 85°C, VCC= 3.0V User calibration accuracy -1.5 1.5 -0.2 0.2 % Units DFLL calibration stepsize 0.23 35.13.3 Calibrated and tunable 32MHz internal oscillator characteristics Table 35-21. 32MHz internal oscillator characteristics. Symbol Parameter Frequency range Condition Min. Typ. Max. DFLL can tune to this frequency over voltage and temperature 30 32 35 Factory calibrated frequency Factory calibration accuracy MHz 32 T = 85°C, VCC= 3.0V User calibration accuracy -1.5 1.5 -0.2 0.2 % Max. Units DFLL calibration step size 0.24 35.13.4 32kHz Internal ULP Oscillator characteristics Table 35-22. 32kHz internal ULP oscillator characteristics. Symbol Parameter Condition Min. Factory calibrated frequency Factory calibration accuracy Accuracy Typ. 32 T = 85°C, VCC= 3.0V kHz -12 12 -30 30 XMEGA C3 [DATASHEET] 8361C–AVR–4/12 % 76 35.13.5 Internal Phase Locked Loop (PLL) characteristics Table 35-23. Internal PLL characteristics. Symbol fIN Input frequency Output frequency (1) fOUT Note: Parameter 1. Condition Min. Typ. Output frequency must be within fOUT 0.4 64 VCC= 1.6 - 1.8V 20 48 VCC= 2.7 - 3.6V 20 128 Start-up time 25 Re-lock time 25 Max. Units MHz µs The maximum output frequency vs. supply voltage is linear between 1.8V and 2.7V, and can never be higher than four times the maximum CPU frequency. 35.13.6 External clock characteristics Figure 35-3. External clock drive waveform . tCH tCH tCR tCF VIH1 VIL1 tCL tCK Table 35-24. External clock(1). Symbol Parameter Clock frequency(2) 1/tCK tCK Clock period tCH/CL Clock high/low time VIL/IH Low/high level input voltage ΔtCK Reduction in period time from one clock cycle to the next Notes: 1. 2. Condition Min. Typ. Max. VCC = 1.6 - 1.8V 0 90 VCC = 2.7 - 3.6V 0 142 VCC = 1.6 - 1.8V 11 VCC = 2.7 - 3.6V 7.0 VCC = 1.6 - 1.8V 4.5 VCC = 2.7 - 3.6V 2.4 Units MHz ns See Table 35-7 on page 70 V 10 % System Clock Prescalers must be set so that maximum CPU clock frequency for device is not exceeded. The maximum frequency vs. supply voltage is linear between 1.8V and 2.7V, and the same applies for all other parameters with supply voltage conditions. XMEGA C3 [DATASHEET] 8361C–AVR–4/12 77 35.13.7 External 16MHz crystal oscillator and XOSC characteristics Table 35-25. External 16MHz crystal oscillator and XOSC characteristics. . Symbol Parameter Cycle to cycle jitter Condition XOSCPWR=0 Min. FRQRANGE=0 0 FRQRANGE=1, 2, or 3 0 XOSCPWR=1 Long term jitter XOSCPWR=0 XOSCPWR=0 FRQRANGE=0 0 FRQRANGE=1, 2, or 3 0 XOSCPWR=0 XOSCPWR=1 Units ns 0 FRQRANGE=0 0.03 FRQRANGE=1 0.03 FRQRANGE=2 or 3 0.03 XOSCPWR=1 Duty cycle Max. 0 XOSCPWR=1 Frequency error Typ. 0.003 FRQRANGE=0 50 FRQRANGE=1 50 FRQRANGE=2 or 3 50 % 50 XMEGA C3 [DATASHEET] 8361C–AVR–4/12 78 Symbol Parameter Condition 1MHz crystal, CL=20pF 67k 2MHz crystal, CL=20pF 67k 2MHz crystal 82k 8MHz crystal 1500 9MHz crystal 1500 8MHz crystal 2700 9MHz crystal 2700 12MHz crystal 1000 9MHz crystal 3600 12MHz crystal 1300 16MHz crystal 590 9MHz crystal 390 12MHz crystal 50 16MHz crystal 10 9MHz crystal 1500 12MHz crystal 650 16MHz crystal 270 XOSCPWR=1, FRQRANGE=2, CL=20pF 12MHz crystal 1000 16MHz crystal 440 XOSCPWR=1, FRQRANGE=3, CL=20pF 12MHz crystal 1300 16MHz crystal 590 XOSCPWR=0, FRQRANGE=0 0.4MHz resonator, CL=100pF 1.0 XOSCPWR=0, FRQRANGE=1 2MHz crystal, CL=20pF 2.6 XOSCPWR=0, FRQRANGE=2 8MHz crystal, CL=20pF 0.8 XOSCPWR=0, FRQRANGE=3 12MHz crystal, CL=20pF 1.0 XOSCPWR=1, FRQRANGE=3 16MHz crystal, CL=20pF 1.4 XOSCPWR=0, FRQRANGE=2, CL=20pF XOSCPWR=0, FRQRANGE=3, CL=20pF XOSCPWR=1, FRQRANGE=0, CL=20pF XOSCPWR=1, FRQRANGE=1, CL=20pF Start-up time Max. 44k XOSCPWR=0, FRQRANGE=1, CL=20pF Negative impedance Typ. 0.4MHz resonator, CL=100pF XOSCPWR=0, FRQRANGE=0 RQ Min. Units Ω ms XMEGA C3 [DATASHEET] 8361C–AVR–4/12 79 Symbol Parameter Condition Min. Typ. CXTAL1 Parasitic capacitance XTAL1 pin 5.9 CXTAL2 Parasitic capacitance XTAL2 pin 8.3 CLOAD Parasitic capacitance load 3.5 Max. Units pF 35.13.8 External 32.768kHz crystal oscillator and TOSC characteristics Table 35-26. External 32.768kHz crystal oscillator and TOSC characteristics. Symbol ESR/R1 Parameter Condition Recommended crystal equivalent series resistance (ESR) Typ. 60 Crystal load capacitance 9.0pF 35 Crystal load capacitance 12pF 28 Parasitic capacitance TOSC1 pin 3.5 CTOSC2 Parasitic capacitance TOSC2 pin 3.5 1. Max. Crystal load capacitance 6.5pF CTOSC1 Recommended safety factor Note: Min. capacitance load matched to crystal specification Units kΩ pF 3 See Figure 35-4 for definition. Figure 35-4. TOSC input capacitance. CL1 TOSC1 CL2 Device internal External TOSC2 32.768kHz crystal The parasitic capacitance between the TOSC pins is CL1 + CL2 in series as seen from the crystal when oscillating without external capacitors. XMEGA C3 [DATASHEET] 8361C–AVR–4/12 80 35.14 SPI Characteristics Figure 35-5. SPI timing requirements in master mode. SS tMOS tSCKR tSCKF SCK (CPOL = 0) tSCKW SCK (CPOL = 1) tSCKW tMIS MISO (Data Input) tMIH tSCK MSB LSB tMOH MOSI (Data Output) tMOH MSB LSB Figure 35-6. SPI timing requirements in slave mode. SS tSSS tSCKR tSCKF tSSH SCK (CPOL = 0) tSSCKW SCK (CPOL = 1) tSSCKW tSIS MOSI (Data Input) tSIH MSB tSOSSS MISO (Data Output) tSSCK LSB tSOS MSB tSOSSH LSB XMEGA C3 [DATASHEET] 8361C–AVR–4/12 81 Table 35-27. SPI timing characteristics and requirements. Symbol Parameter Condition Min. Typ. Max. tSCK SCK period Master (See Table 20-3 in XMEGA C Manual) tSCKW SCK high/low width Master 0.5*SCK tSCKR SCK rise time Master 2.7 tSCKF SCK fall time Master 2.7 tMIS MISO setup to SCK Master 10 tMIH MISO hold after SCK Master 10 tMOS MOSI setup SCK Master 0.5*SCK tMOH MOSI hold after SCK Master 1 tSSCK Slave SCK Period Slave 4*t ClkPER tSSCKW SCK high/low width Slave 2*t ClkPER tSSCKR SCK rise time Slave 1600 tSSCKF SCK fall time Slave 1600 tSIS MOSI setup to SCK Slave 3 tSIH MOSI hold after SCK Slave t ClkPER tSSS SS setup to SCK Slave 21 tSSH SS hold after SCK Slave 20 tSOS MISO setup SCK Slave 8 tSOH MISO hold after SCK Slave 13 tSOSS MISO setup after SS low Slave 11 tSOSH MISO hold after SS high Slave 8 Units ns XMEGA C3 [DATASHEET] 8361C–AVR–4/12 82 35.15 Two-Wire Interface Characteristics Table 35-28 describes the requirements for devices connected to the Two-Wire Interface Bus. The Atmel AVR XMEGA Two-Wire Interface meets or exceeds these requirements under the noted conditions. Timing symbols refer to Figure 357. Figure 35-7. Two-wire interface bus timing. tof tHIGH tLOW tr SCL tSU;STA tHD;DAT tSU;STO tSU;DAT tHD;STA SDA tBUF Table 35-28. Two-wire interface characteristics. Symbol Parameter Condition Min. Typ. Max. VIH Input high voltage 0.7VCC VCC+0.5 VIL Input low voltage 0.5 0.3VCC Vhys Hysteresis of Schmitt trigger inputs VOL Output low voltage tr Rise time for both SDA and SCL tof Output fall time from VIHmin to VILmax tSP Spikes suppressed by input filter II Input current for each I/O Pin CI Capacitance for each I/O Pin fSCL SCL clock frequency 0.05VCC (1) 3mA, sink current 10pF < Cb < 400pF (2) 0.1VCC < VI < 0.9VCC fPER (3)>max(10fSCL, 250kHz) fSCL ≤ 100kHz RP tHD;STA tLOW tHIGH tSU;STA Value of pull-up resistor Hold time (repeated) START condition Low period of SCL clock High period of SCL clock Set-up time for a repeated START condition Units V 0 0.4 20+0.1Cb (1)(2) 300 20+0.1Cb (1)(2) 250 0 50 -10 10 µA 10 pF 400 kHz 0 fSCL > 100kHz V CC – 0.4V ---------------------------3mA fSCL ≤ 100kHz 4.0 fSCL > 100kHz 0.6 fSCL ≤ 100kHz 4.7 fSCL > 100kHz 1.3 fSCL ≤ 100kHz 4.0 fSCL > 100kHz 0.6 fSCL ≤ 100kHz 4.7 fSCL > 100kHz 0.6 100ns --------------Cb 300ns --------------Cb ns Ω µs XMEGA C3 [DATASHEET] 8361C–AVR–4/12 83 Symbol Parameter tHD;DAT Data hold time tSU;DAT Data setup time tSU;STO Setup time for STOP condition Bus free time between a STOP and START condition tBUF Notes: 1. 2. 3. Condition Min. Typ. Max. fSCL ≤ 100kHz 0 3.45 fSCL > 100kHz 0 0.9 fSCL ≤ 100kHz 250 fSCL > 100kHz 100 fSCL ≤ 100kHz 4.0 fSCL > 100kHz 0.6 fSCL ≤ 100kHz 4.7 fSCL > 100kHz 1.3 Units µs Required only for fSCL > 100kHz. Cb = Capacitance of one bus line in pF. fPER = Peripheral clock frequency. XMEGA C3 [DATASHEET] 8361C–AVR–4/12 84 36. Typical Characteristics 36.1 Current consumption 36.1.1 Active mode supply current Figure 36-1. Active supply current vs. frequency. fSYS = 0 - 1MHz external clock, T = 25°C. ICC [µA] 1200 1100 3.6V 1000 3.3V 900 3.0V 800 2.7V 700 600 2.2V 500 1.8V 400 300 200 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency [MHz] Figure 36-2. Active supply current vs. frequency. fSYS = 1 - 32MHz external clock, T = 25°C. 14 3.6V 12 3.3V ICC [mA] 10 3.0V 2.7V 8 6 2.2V 4 1.8V 2 0 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 Frequency[MHz] XMEGA C3 [DATASHEET] 8361C–AVR–4/12 85 Figure 36-3. Active mode supply current vs. VCC. fSYS = 32.768kHz internal oscillator. 500 -40°C 450 400 25°C ICC [µA] 350 85°C 300 250 200 150 100 50 0 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] Figure 36-4. Active mode supply current vs. VCC. fSYS = 1MHz external clock. 1300 1200 -40°C 1100 25°C 85°C Icc [µA] 1000 900 800 700 600 500 400 300 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] XMEGA C3 [DATASHEET] 8361C–AVR–4/12 86 Figure 36-5. Active mode supply current vs. VCC. fSYS = 2MHz internal oscillator. 650 85°C 600 25°C 550 -40°C ICC [µA] 500 450 400 350 300 250 200 150 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] Figure 36-6. Active mode supply current vs. VCC. fSYS = 32MHz internal oscillator prescaled to 8MHz. 6.5 6.0 -40°C 5.5 25°C 85°C ICC [mA] 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] XMEGA C3 [DATASHEET] 8361C–AVR–4/12 87 Figure 36-7. Active mode supply current vs. VCC. fSYS = 32MHz internal oscillator. 10 85°C 25°C 9 -40°C ICC [mA] 8 7 6 5 4 3 2 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] 36.1.2 Idle mode supply current Figure 36-8. Idle mode supply current vs. frequency. fSYS = 0 - 1MHz external clock, T = 25°C. 140 ICC [µA] 3.6V 120 3.3V 100 3.0V 2.7V 80 2.2V 60 1.8V 40 20 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency [MHz] XMEGA C3 [DATASHEET] 8361C–AVR–4/12 88 Figure 36-9. Idle mode supply current vs. frequency. fSYS = 1 - 32MHz external clock, T = 25°C. 4.5 3.6V 4.0 3.3V 3.5 ICC [mA] 3.0V 3.0 2.7V 2.5 2.0 1.5 2.2V 1.0 1.8V 0.5 0 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 Frequency [MHz] Figure 36-10.Idle mode supply current vs. VCC. fSYS = 32.768kHz internal oscillator. 37 85°C 36 Icc [µA] 35 34 -40°C 33 32 25°C 31 30 29 28 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] XMEGA C3 [DATASHEET] 8361C–AVR–4/12 89 Figure 36-11.Idle mode supply current vs. VCC. fSYS = 1MHz external clock. 150 85°C 25°C -40°C 140 130 ICC [µA] 120 110 100 90 80 70 60 50 40 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] Figure 36-12.Idle mode supply current vs. VCC. fSYS = 2MHz internal oscillator. 400 -40°C 25°C 85°C 375 350 ICC [µA] 325 300 275 250 225 200 175 150 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] XMEGA C3 [DATASHEET] 8361C–AVR–4/12 90 Figure 36-13.Idle mode supply current vs. VCC. fSYS = 32MHz internal oscillator prescaled to 8MHz. 1900 -40°C 25°C 85°C 1700 ICC [µA] 1500 1300 1100 900 700 500 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] Figure 36-14.Idle mode current vs. VCC. fSYS = 32MHz internal oscillator. ICC [µA] 5250 5000 -40°C 4750 25°C 4500 85°C 4250 4000 3750 3500 3250 3000 2750 2500 2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 3.6 VCC [V] XMEGA C3 [DATASHEET] 8361C–AVR–4/12 91 36.1.3 Power-down mode supply current Figure 36-15.Power-down mode supply current vs. VCC. All functions disabled. 4.5 85°C 4 3.5 ICC [µA] 3 2.5 2 1.5 1 0.5 25°C -40°C 0 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] Figure 36-16.Power-down mode supply current vs. VCC. Watchdog and sampled BOD enabled. 7 85°C 6 Icc [µA] 5 4 3 2 25°C -40°C 1 0 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] XMEGA C3 [DATASHEET] 8361C–AVR–4/12 92 Figure 36-17.Power-down mode supply current vs. Temperature. Watchdog and sampled BOD enabled and running from internal ULP oscillator. 7 6 3.0V 2.7V 2.2V 1.8V Icc [µA] 5 4 3 2 1 0 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 Temperature [°C] 36.2 I/O Pin Characteristics 36.2.1 Pull-up Figure 36-18.I/O pin pull-up resistor current vs. input voltage. VCC = 1.8V. 80 70 IPIN [µA] 60 50 40 30 20 -40°C 25°C 85°C 10 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 VPIN [V] XMEGA C3 [DATASHEET] 8361C–AVR–4/12 93 Figure 36-19.I/O pin pull-up resistor current vs. input voltage. VCC = 3.0V. 120 108 96 IPIN [µA] 84 72 60 48 36 24 -40°C 25°C 85°C 12 0 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3 VPIN [V] Figure 36-20.I/O pin pull-up resistor current vs. input voltage. VCC = 3.3V. 140 126 112 IPIN [µA] 98 84 70 56 42 -40°C 25°C 85°C 28 14 0 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3 3.3 VPIN [V] XMEGA C3 [DATASHEET] 8361C–AVR–4/12 94 36.2.2 Output Voltage vs. Sink/Source Current Figure 36-21.I/O pin output voltage vs. source current. VCC = 1.8V. 2 1.8 1.6 VPIN [V] 1.4 1.2 1 0.8 -40°C 25°C 0.6 85°C 0.4 0.2 0 -5 -4.5 -4 -3.5 -3 -2.5 -2 -1.5 -1 -0.5 0 I PIN [mA] Figure 36-22.I/O pin output voltage vs. source current. VCC = 3.0V. 3.5 3 VPIN [V] 2.5 2 1.5 -40°C 25°C 1 85°C 0.5 0 -16 -14 -12 -10 -8 -6 -4 -2 0 IPIN [mA] XMEGA C3 [DATASHEET] 8361C–AVR–4/12 95 Figure 36-23.I/O pin output voltage vs. source current. VCC = 3.3V. 3.5 3 VPIN[V] 2.5 2 1.5 -40°C 25°C 1 85°C 0.5 0 -20 -18 -16 -14 -12 -10 -8 -6 -4 -2 0 IPIN [mA] Figure 36-24.I/O pin output voltage vs. sink current. VCC = 1.8V. 1 85°C 0.9 0.8 25°C VPIN [V] 0.7 -40°C 0.6 0.5 0.4 0.3 0.2 0.1 0 0 1 2 3 4 5 6 7 8 9 IPIN [mA] XMEGA C3 [DATASHEET] 8361C–AVR–4/12 96 Figure 36-25.I/O pin output voltage vs. sink current. VCC = 3.0V. 1 85°C VPIN [V] 0.9 0.8 25°C 0.7 -40°C 0.6 0.5 0.4 0.3 0.2 0.1 0 0 2 4 6 8 10 12 14 16 IPIN [mA] Figure 36-26.I/O pin output voltage vs. sink current. VCC = 3.3V. 1 25°C 85°C 0.9 -40°C 0.8 VPIN [V] 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0 2 4 6 8 10 12 14 16 18 20 IPIN [mA] XMEGA C3 [DATASHEET] 8361C–AVR–4/12 97 36.2.3 Thresholds and Hysteresis Figure 36-27.I/O pin input threshold voltage vs. VCC. VIH I/O pin read as “1”. 1.8 85°C 25°C -40°C 1.7 Vthreshold [V] 1.6 1.5 1.4 1.3 1.2 1.1 1 0.9 0.8 0.7 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] Figure 36-28.I/O pin input threshold voltage vs. VCC. VIL I/O pin read as “0”. 1.6 85°C 25°C -40°C 1.5 Vthreshold [V] 1.4 1.3 1.2 1.1 1 0.9 0.8 0.7 0.6 0.5 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] XMEGA C3 [DATASHEET] 8361C–AVR–4/12 98 Figure 36-29.I/O pin input hysteresis vs. VCC. 0.42 0.39 Vthreshold [V] 0.36 0.33 0.3 0.27 0.24 -40°C 25°C 85°C 0.21 0.18 0.15 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 2.4 2.6 2.8 3.6 VCC [V] ADC Characteristics Figure 36-30.INL error vs. external VREF. T = 25°C, VCC = 3.6V, external reference. 1.6 1.4 1.2 INL[LSB] 36.3 Single-ended unsigned mode 1.0 0.8 0.6 Differential mode 0.4 Single-ended signed mode 0.2 0.0 1.0 1.2 1.4 1.6 1.8 2.0 2.2 3.0 VREF [V] XMEGA C3 [DATASHEET] 8361C–AVR–4/12 99 Figure 36-31.INL error vs. sample rate. T = 25°C, VCC = 3.6V, VREF = 3.0V external. 0.70 0.65 Single-ended unsigned mode INL[LSB] 0.60 0.55 Differential mode 0.50 0.45 0.40 0.35 Single-ended signed mode 0.30 0.25 50 100 150 200 250 300 ADC sample rate [ksps] Figure 36-32.INL error vs. input code. 1.25 1.00 0.75 INL[LSB] 0.50 0.25 0.00 -0.25 -0.50 -0.75 -1.00 -1.25 0 512 1024 1536 2048 2560 3072 3584 4096 ADC input code XMEGA C3 [DATASHEET] 8361C–AVR–4/12 100 Figure 36-33.DNL error vs. external VREF. T = 25°C, VCC = 3.6V, external reference. 0.70 0.65 0.60 Single-ended unsigned mode DNL [LSB] 0.55 0.50 0.45 0.40 Differential mode 0.35 Single-ended signed mode 0.30 0.25 0.20 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 VREF [V] Figure 36-34.DNL error vs. sample rate. T = 25°C, VCC = 3.6V, VREF = 3.0V external. 0.60 0.55 Single-ended unsigned mode DNL [LSB] 0.50 0.45 0.40 Differential mode 0.35 0.30 Single-ended signed mode 0.25 0.20 50 100 150 200 250 300 ADC sample rate [ksps] XMEGA C3 [DATASHEET] 8361C–AVR–4/12 101 Figure 36-35.DNL error vs. input code. 1 DNL [LSB] 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 0 512 1024 1536 2048 2560 3072 3584 4096 ADC input code Figure 36-36.Gain error vs. VREF. T = 25°C, VCC = 3.6V, ADC sample rate = 300ksps. -5 Gain error [mV] -6 -7 Differential mode -8 -9 Single-ended signed mode -10 -11 -12 Single-ended unsigned mode -13 -14 -15 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 VREF [V] XMEGA C3 [DATASHEET] 8361C–AVR–4/12 102 Figure 36-37.Gain error vs. VCC. T = 25°C, VREF = external 1.0V, ADC sample rate = 300ksps. -2 Gain error [mV] -3 -4 Differential mode -5 Single-ended signed mode -6 Single-ended unsigned mode -7 -8 -9 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] Figure 36-38.Offset error vs. VREF. T = 25°C, VCC = 3.6V, ADC sample rate = 300ksps. 9.4 9.2 Offset error [mV] 9.0 8.8 Differential mode 8.6 8.4 8.2 8.0 7.8 7.6 7.4 7.2 7.0 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 VREF [V] XMEGA C3 [DATASHEET] 8361C–AVR–4/12 103 Figure 36-39.Gain error vs. temperature. VCC = 3.0V, VREF = external 2.0V. -3 Gain error [mV] -4 -5 Single-ended signed mode -6 -7 Differential mode -8 -9 -10 Single-ended unsigned mode -11 -12 -13 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 Temperature [°C] Figure 36-40.Offset error vs. VCC. T = 25°C, VREF = external 1.0V, ADC sample rate = 300ksps. 8.00 Offset error [mV] 7.00 6.00 5.00 Differential mode 4.00 3.00 2.00 1.00 0.00 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] XMEGA C3 [DATASHEET] 8361C–AVR–4/12 104 Analog Comparator Characteristics Figure 36-41.Analog comparator hysteresis vs. VCC. Small hysteresis. 19 18 85°C VHYST [mV] 17 16 25°C 15 14 -40°C 13 12 11 10 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] Figure 36-42.Analog comparator hysteresis vs. VCC. Large hysteresis. 36 34 85°C 32 VHYST [mV] 36.4 30 25°C 28 -40°C 26 24 22 20 18 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] XMEGA C3 [DATASHEET] 8361C–AVR–4/12 105 Figure 36-43.Analog comparator current source vs. calibration value. VCC = 3.0V. 8 7 I [µA] 6 5 3.6V 4 3.0V 3 2.4V 2.0V 1.6V 2 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CALIBA[3..0] Figure 36-44.Voltage scaler INL vs. SCALEFAC. T = 25°C, VCC = 3.0V. 0.44 25°C 0.41 INL [LSB] 0.38 0.35 0.32 0.29 0.26 0.23 0.2 0 5 10 15 20 25 30 35 40 45 50 55 60 65 SCALEFAC XMEGA C3 [DATASHEET] 8361C–AVR–4/12 106 36.5 Internal 1.0V reference Characteristics Figure 36-45.ADC Internal 1.0V reference vs. temperature. 1.035 Bandgap Voltage [V] 1.03 1.025 1.02 1.015 1.01 1.005 1.6V 2.4V 3.6V 1 0.995 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 Temperature [°C] BOD Characteristics Figure 36-46.BOD thresholds vs. temperature. BOD level = 1.6V. 1.78 1.74 1.7 VBOT [V] 36.6 1.66 1.62 1.58 1.54 1.5 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 Temperature [°C] XMEGA C3 [DATASHEET] 8361C–AVR–4/12 107 Figure 36-47.BOD thresholds vs. temperature. BOD level = 3.0V. 3.3 3.25 VBOT [V] 3.2 3.15 3.1 3.05 3 2.95 2.9 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 Temperature [°C] External Reset Characteristics Figure 36-48.Minimum Reset pin pulse width vs. VCC. 135 130 125 120 tRST [ns] 36.7 115 110 105 100 85°C 95 90 25°C -40°C 85 80 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] XMEGA C3 [DATASHEET] 8361C–AVR–4/12 108 Figure 36-49.Reset pin pull-up resistor current vs. reset pin voltage. VCC = 1.8V. 80 70 IRESET [µA] 60 50 40 30 20 -40°C 25°C 85°C 10 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 VRESET [V] Figure 36-50.Reset pin pull-up resistor current vs. reset pin voltage. VCC = 3.0V. 130 117 104 IRESET[µA] 91 78 65 52 39 26 -40°C 25°C 85°C 13 0 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3 VRESET [V] XMEGA C3 [DATASHEET] 8361C–AVR–4/12 109 Figure 36-51.Reset pin pull-up resistor current vs. reset pin voltage. VCC = 3.3V. 140 126 112 IRESET [µA] 98 84 70 56 42 28 -40°C 25°C 85°C 14 0 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3 3.3 VRESET [V] Figure 36-52.Reset pin input threshold voltage vs. VCC. VIH - Reset pin read as “1”. 1.8 85°C 25°C -40°C VTHRESHOLD [V] 1.6 1.4 1.2 1 0.8 0.6 0.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] XMEGA C3 [DATASHEET] 8361C–AVR–4/12 110 36.8 Oscillator Characteristics 36.8.1 Ultra Low-Power internal oscillator Figure 36-53.Ultra Low-Power internal oscillator frequency vs. temperature. 35.5 Frequency [kHz] 35.0 34.5 34.0 33.0 33.0 3.6V 3.0V 2.7V 1.8V 32.5 32.0 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 Temperature [°C] 36.8.2 32.768kHz Internal Oscillator Frequency [kHz] Figure 36-54.32.768kHz internal oscillator frequency vs. temperature. 32.84 1.8V 32.81 2.2V 2.7V 3.0V 3.6V 3.3V 32.78 32.75 32.72 32.69 32.66 32.63 32.60 32.57 32.54 32.51 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 Temperature [°C] XMEGA C3 [DATASHEET] 8361C–AVR–4/12 111 Figure 36-55.32.768kHz internal oscillator frequency vs. calibration value. VCC = 3.0V, T = 25°C. 53 3.0 V Frequency [kHz] 50 47 44 41 38 35 32 29 26 23 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 RC32KCAL[7..0] 36.8.3 2MHz Internal Oscillator Figure 36-56.2MHz internal oscillator frequency vs. temperature. DFLL disabled. 2.20 2.18 Frequency [MHz] 2.16 2.14 2.12 2.10 2.08 2.06 3.3 V 3.0 V 2.7 V 2.2 V 1.8 V 2.04 2.02 2.00 1.98 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 Temperature [°C] XMEGA C3 [DATASHEET] 8361C–AVR–4/12 112 Figure 36-57.2MHz internal oscillator frequency vs. temperature. DFLL enabled, from the 32.768kHz internal oscillator . Frequency [MHz] 2.01 2.008 3.3V 2.006 3.0V 2.004 2.7V 2.2V 2.002 1.8V 2.000 1.998 1.996 1.994 1.992 1.99 1.988 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 Temperature [°C] Figure 36-58.2MHz internal oscillator frequency vs. CALA calibration value. VCC = 3V. 2.6 -40°C Frequency [MHz] 2.5 2.4 25°C 2.3 85°C 2.2 2.1 2.0 1.9 1.8 1.7 0 8 16 24 32 40 48 56 64 72 80 88 96 104 112 120 128 CALA XMEGA C3 [DATASHEET] 8361C–AVR–4/12 113 36.8.4 32MHz Internal Oscillator Figure 36-59.32MHz internal oscillator frequency vs. temperature. DFLL disabled. 37 36.5 Frequency [MHz] 36 35.5 35 34.5 34 33.5 3.3V 3.0V 2.7V 2.2V 1.8V 33 32.5 32 31.5 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 Temperature [°C] Figure 36-60.32MHz internal oscillator frequency vs. temperature. DFLL enabled, from the 32.768kHz internal oscillator. 32.09 1.8V 2.2V Frequency [MHz] 32.06 32.03 2.7V 3.0V 3.3V 32.00 31.97 31.94 31.91 31.88 31.85 31.82 31.79 31.76 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 Temperature [°C] XMEGA C3 [DATASHEET] 8361C–AVR–4/12 114 Figure 36-61.32MHz internal oscillator CALA calibration step size. VCC = 3.0V. 0.39 0.36 Step size:[%] 0.33 0.30 -40°C 0.27 0.24 0.21 25°C 0.18 85°C 0.15 0 8 16 24 32 40 48 56 64 72 80 88 96 104 112 120 128 CALA Figure 36-62.32MHz internal oscillator frequency vs. CALB calibration value. VCC = 3.0V. 80 -40°C 25°C 85°C 74 Frequency [MHz] 68 62 56 50 44 38 32 26 20 0 7 14 21 28 35 42 49 56 63 DFLLRC2MCALB XMEGA C3 [DATASHEET] 8361C–AVR–4/12 115 36.8.5 32MHz internal oscillator calibrated to 48MHz Figure 36-63.48MHz internal oscillator frequency vs. temperature. DFLL disabled. 55 Frequency [MHz] 54 53 52 51 50 3.3V 3.0V 2.7V 2.2V 1.8V 49 48 47 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 Temperature [°C] Figure 36-64.48MHz internal oscillator frequency vs. temperature. DFLL enabled, from the 32.768kHz internal oscillator. Frequency [MHz] 48.2 1.8V 2.2V 48.1 2.7V 3.0V 3.3V 48 47.9 47.8 47.7 47.6 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 Temperature [°C] XMEGA C3 [DATASHEET] 8361C–AVR–4/12 116 Two-Wire Interface characteristics Figure 36-65.SDA hold time vs. temperature. 500 450 3 Hold time [ns] 400 350 2 300 250 200 150 100 1 50 0 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 Temperature [°C] Figure 36-66.SDA hold time vs. supply voltage. 500 450 3 400 Hold time [ns] 36.9 350 2 300 250 200 150 100 1 50 0 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 VCC [V] XMEGA C3 [DATASHEET] 8361C–AVR–4/12 117 36.10 PDI characteristics fMAX [MHz] Figure 36-67.Maximum PDI frequency vs. VCC. 36 -40°C 31 25°C 85°C 26 21 16 11 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 VCC [V] XMEGA C3 [DATASHEET] 8361C–AVR–4/12 118 37. Errata 37.1 ATxmega384C3 37.1.1 Rev. B No known errata. XMEGA C3 [DATASHEET] 8361C–AVR–4/12 119 38. Datasheet Revision History Please note that the referring page numbers in this section are referred to this document. The referring revision in this section are referring to the document revision. 38.1 8361C – 04/12 1. 38.2 38.3 Updated four plots in typical characteristics: Figures 36-1 and Figure 36-2 on page 85; and Figures 36-8 and Figure 36-3 on page 86. 8361B – 03/12 1. Editing update. 2. Atmel new datasheet template used. 8361A – 02/12 1. Initial revision. XMEGA C3 [DATASHEET] 8361C–AVR–4/12 120 Table of Contents Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2. Pinout/Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3.1 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4. Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4.1 Recommended reading. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 5. Capacitive touch sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 6. AVR CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 ALU - Arithmetic Logic Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Program Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Stack and Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Register File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 7. Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11 7.12 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fuses and Lock bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Memory and Bus Arbitration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Memory Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Device ID and Revision. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Memory Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash and EEPROM Page Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 11 12 13 13 14 14 14 14 14 15 15 8. DMAC – Direct Memory Access Controller . . . . . . . . . . . . . . . . . . . 16 8.1 8.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 9. Event System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 9.1 9.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 10. System Clock and Clock options . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 10.1 10.2 10.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Clock Sources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 XMEGA C3 [DATASHEET] 8361C–AVR–4/12 i 11. Power Management and Sleep Modes . . . . . . . . . . . . . . . . . . . . . . 21 11.1 11.2 11.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Sleep Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 12. System Control and Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 12.1 12.2 12.3 12.4 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 23 23 23 13. WDT – Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 13.1 13.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 14. Interrupts and Programmable Multilevel Interrupt Controller . . . . . . 26 14.1 14.2 14.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Interrupt vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 15. I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 15.1 15.2 15.3 15.4 15.5 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input sensing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Alternate Port Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 28 28 31 31 16. TC0/1 – 16-bit Timer/Counter Type 0 and 1 . . . . . . . . . . . . . . . . . . 32 16.1 16.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 17. TC2 – Timer/Counter Type 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 17.1 17.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 18. AWeX – Advanced Waveform Extension . . . . . . . . . . . . . . . . . . . . . 35 18.1 18.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 19. Hi-Res – High Resolution Extension . . . . . . . . . . . . . . . . . . . . . . . . 36 19.1 19.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 20. RTC – 16-bit Real-Time Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 20.1 20.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 21. USB – Universal Serial Bus Interface . . . . . . . . . . . . . . . . . . . . . . . 38 21.1 21.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 22. TWI – Two-Wire Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 22.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 XMEGA C3 [DATASHEET] 8361C–AVR–4/12 ii 22.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 23. SPI – Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 23.1 23.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 24. USART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 24.1 24.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 25. IRCOM – IR Communication Module . . . . . . . . . . . . . . . . . . . . . . . . 43 25.1 25.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 26. AES Crypto Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 26.1 26.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 27. CRC – Cyclic Redundancy Check Generator . . . . . . . . . . . . . . . . . 45 27.1 27.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 28. ADC – 12-bit Analog to Digital Converter . . . . . . . . . . . . . . . . . . . . 46 28.1 28.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 29. AC – Analog Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 29.1 29.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 30. Programming and Debugging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 30.1 30.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 31. Pinout and Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 31.1 31.2 Alternate Pin Function Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Alternate Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 32. Peripheral Module Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 33. Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 34. Packaging information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 34.1 34.2 64A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 64Z3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 35. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 35.1 35.2 35.3 35.4 35.5 35.6 35.7 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General Operating Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Current consumption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wake-up time from sleep modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Pin Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Analog Comparator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XMEGA C3 [DATASHEET] 8361C–AVR–4/12 65 65 67 69 70 71 73 iii 35.8 35.9 35.10 35.11 35.12 35.13 35.14 35.15 Bandgap and Internal 1.0V Reference Characteristics. . . . . . . . . . . . . . . . . . Brownout Detection Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Reset Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power-on Reset Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash and EEPROM Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . Clock and Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Two-Wire Interface Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 74 74 75 75 76 81 83 36. Typical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 36.1 36.2 36.3 36.4 36.5 36.6 36.7 36.8 36.9 36.10 Current consumption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 I/O Pin Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Analog Comparator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Internal 1.0V reference Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 BOD Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 External Reset Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Two-Wire Interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 PDI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 37. Errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 37.1 ATxmega384C3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 38. Datasheet Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 38.1 38.2 38.3 8361C – 04/12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 8361B – 03/12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 8361A – 02/12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i XMEGA C3 [DATASHEET] 8361C–AVR–4/12 iv XMEGA C3 [DATASHEET] 8361C–AVR–4/12 v Atmel Corporation 2325 Orchard Parkway Atmel Asia Limited Unit 01-5 & 16, 19F Atmel Munich GmbH Business Campus Atmel Japan G.K. 16F Shin-Osaki Kangyo Bldg San Jose, CA 95131 BEA Tower, Millennium City 5 Parkring 4 1-6-4 Osaki, Shinagawa-ku USA 418 Kwun Tong Roa D-85748 Garching b. Munich Tokyo 141-0032 Tel: (+1) (408) 441-0311 Kwun Tong, Kowloon GERMANY JAPAN Fax: (+1) (408) 487-2600 HONG KONG Tel: (+49) 89-31970-0 Tel: (+81) (3) 6417-0300 www.atmel.com Tel: (+852) 2245-6100 Fax: (+49) 89-3194621 Fax: (+81) (3) 6417-0370 Fax: (+852) 2722-1369 © 2012 Atmel Corporation. All rights reserved. / Rev.: 8361C–AVR–4/12 Atmel®, Atmel logos and combinations thereof, and others are registered trademarks or trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. 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