TI MSP430X44X Mixed signal microcontroller Datasheet

 SLAS344C – JANUARY 2002 – REVISED MARCH2003
D Low Supply-Voltage Range, 1.8 V to 3.6 V
D Ultralow-Power Consumption:
D
D
D
D
D
D
D
D
D
D
– Active Mode: 280 µA at 1 MHz, 2.2 V
– Standby Mode: 1.1 µA
– Off Mode (RAM Retention): 0.1 µA
Five Power Saving Modes
Wake-Up From Standby Mode in 6 µs
16-Bit RISC Architecture,
125-ns Instruction Cycle Time
12-Bit A/D Converter With Internal
Reference, Sample-and-Hold and Autoscan
Feature
16-Bit Timer_B With Three† or Seven‡
Capture/Compare-With-Shadow Registers
16-Bit Timer_A With Three
Capture/Compare Registers
On-Chip Comparator
Serial Communication Interface (USART),
Select Asynchronous UART or
Synchronous SPI by Software:
– Two USARTs (USART0, USART1) —
MSP430x44x Devices
– One USART (USART0) —
MSP430x43x Devices
Brownout Detector
Supply Voltage Supervisor/Monitor With
Programmable Level Detection
D Serial Onboard Programming,
D
D
D
No External Programming Voltage Needed
Programmable Code Protection by Security
Fuse
Integrated LCD Driver for Up to
160 Segments
Family Members Include:
– MSP430F435:
16KB+256B Flash Memory,
512B RAM
– MSP430F436:
24KB+256B Flash Memory,
1KB RAM
– MSP430F437:
32KB+256B Flash Memory,
1KB RAM
– MSP430F447:
32KB+256B Flash Memory,
1KB RAM
– MSP430F448:
48KB+256B Flash Memory,
2KB RAM
– MSP430F449:
60KB+256B Flash Memory,
2KB RAM
For Complete Module Descriptions, See
The MSP430x4xx Family User’s Guide,
Literature Number SLAU056
† ’F435, ’F436, and ’F437 devices
‡ ’F447, ’F448, and ’F449 devices
description
The Texas Instruments MSP430 family of ultralow power microcontrollers consist of several devices featuring
different sets of peripherals targeted for various applications. The architecture, combined with five low power
modes is optimized to achieve extended battery life in portable measurement applications. The device features
a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that attribute to maximum code efficiency.
The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less than 6µs.
The MSP430x43x and the MSP430x44x series are microcontroller configurations with two built-in 16-bit timers,
a fast 12-bit A/D converter, one or two universal serial synchronous/asynchronous communication interfaces
(USART), 48 I/O pins, and a liquid crystal driver (LCD) with up to 160 segments.
Typical applications include sensor systems that capture analog signals, convert them to digital values, and
process and transmit the data to a host system, or process this data and displays it on a LCD panel. The timers
make the configurations ideal for industrial control applications such as ripple counters, digital motor control,
EE-meters, hand-held meters, etc. The hardware multiplier enhances the performance and offers a broad code
and hardware-compatible family solution.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  2002 – 2003, Texas Instruments Incorporated
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AVAILABLE OPTIONS
PACKAGED DEVICES
TA
PLASTIC 80-PIN QFP
(PN)
–40°C to 85°C
PLASTIC 100-PIN QFP
(PZ)
MSP430F435IPN
MSP430F436IPN
MSP430F437IPN
MSP430F435IPZ
MSP430F436IPZ
MSP430F437IPZ
MSP430F447IPZ
MSP430F448IPZ
MSP430F449IPZ
AVCC
DVSS1
AVSS
P6.2/A2
P6.1/A1
P6.0/A0
RST/NMI
TCK
TMS
TDI
TDO/TDI
XT2IN
XT2OUT
P1.0/TA0
P1.1/TA0/MCLK
P1.2/TA1
P1.3/TBOUTH/SVSOUT
PN PACKAGE
(TOP VIEW)
P1.4/TBCLK/SMCLK
P1.5/TACLK/ACLK
P1.6/CA0
pin designation, MSP430x435IPN, MSP430x436IPN, MSP430x437IPN
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
1
60
2
59
3
58
4
57
5
56
6
55
7
54
8
53
9
10
11
MSP430F435IPN
MSP430F436IPN
MSP430F437IPN
52
51
50
12
49
13
48
14
47
15
46
16
45
17
44
18
43
19
42
20
41
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
P4.0/S9
S10
S11
S12
S13
S14
S15
S16
S17
P2.7/ADC12CLK/S18
P2.6/CAOUT/S19
S20
S21
S22
S23
P3.7/S24
P3.6/S25
P3.5/S26
P3.4/S27
P3.3/UCLK0/S28
DVCC1
P6.3/A3
P6.4/A4
P6.5/A5
P6.6/A6
P6.7/A7/SVSin
VREF+
XIN
XOUT/TCLK
VeREF+
VREF–/VeREF–
P5.1/S0
P5.0/S1
P4.7/S2
P4.6/S3
P4.5/S4
P4.4/S5
P4.3/S6
P4.2/S7
P4.1/S8
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P1.7CA1
P2.0/TA2
P2.1/TB0
P2.2/TB1
P2.3/TB2
P2.4/UTXD0
P2.5/URXD0
DVSS2
DVCC2
P5.7/R33
P5.6/R23
P5.5/R13
R03
P5.4/COM3
P5.3/COM2
P5.2/COM1
COM0
P3.0/STE0/S31
P3.1/SIMO0/S30
P3.2/SOMI0/S29
SLAS344C – JANUARY 2002 – REVISED MARCH2003
pin designation, MSP430x435IPZ, MSP430x436IPZ, MSP430x437IPZ
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
AVCC
DVSS1
AVSS
P6.2/A2
P6.1/A1
P6.0/A0
RST/NMI
TCK
TMS
TDI
TDO/TDI
XT2IN
XT2OUT
P1.0/TA0
P1.1/TA0/MCLK
P1.2/TA1
P1.3/TBOUTH/SVSOUT
P1.4/TBCLK/SMCLK
P1.5/TACLK/ACLK
P1.6/CA0
P1.7/CA1
P2.0/TA2
P2.1/TB0
P2.2/TB1
P2.3/TB2
PZ PACKAGE
(TOP VIEW)
MSP430F435IPZ
MSP430F436IPZ
MSP430F437IPZ
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
P2.4/UTXD0
P2.5/URXD0
P2.6/CAOUT
P2.7/ADC12CLK
P3.0/STE0
P3.1/SIMO0
P3.2/SOMI0
P3.3/UCLK0
P3.4
P3.5
P3.6
P3.7
P4.0
P4.1
DVSS2
DVCC2
P5.7/R33
P5.6/R23
P5.5/R13
R03
P5.4/COM3
P5.3/COM2
P5.2/COM1
COM0
P4.2/S39
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
S14
S15
S16
S17
S18
S19
S20
S21
S22
S23
S24
S25
S26
S27
S28
S29
S30
S31
S32
S33
P4.7/S34
P4.6/S35
P4.5/S36
P4.4/S37
P4.3/S38
DVCC1
P6.3/A3
P6.4/A4
P6.5/A5
P6.6/A6
P6.7/A7/SVSin
VREF+
XIN
XOUT/TCLK
VeREF+
VREF–/VeREF–
P5.1/S0
P5.0/S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
S11
S12
S13
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pin designation, MSP430x447IPZ, MSP430x448IPZ, MSP430x449IPZ
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
AVCC
DVSS1
AVSS
P6.2/A2
P6.1/A1
P6.0/A0
RST/NMI
TCK
TMS
TDI
TDO/TDI
XT2IN
XT2OUT
P1.0/TA0
P1.1/TA0/MCLK
P1.2/TA1
P1.3/TBOUTH/SVSOUT
P1.4/TBCLK/SMCLK
P1.5/TACLK/ACLK
P1.6/CA0
P1.7/CA1
P2.0/TA2
P2.1/TB0
P2.2/TB1
P2.3/TB2
PZ PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
MSP430F447IPZ
MSP430F448IPZ
MSP430F449IPZ
S14
S15
S16
S17
S18
S19
S20
S21
S22
S23
S24
S25
S26
S27
S28
S29
S30
S31
S32
S33
P4.7/S34
P4.6/S35
P4.5/UCLK1/S36
P4.4/SOMI1/S37
4.3/SIMO1/S38
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
DVCC1
P6.3/A3
P6.4/A4
P6.5/A5
P6.6/A6
P6.7/A7/SVSin
VREF+
XIN
XOUT/TCLK
VeREF+
VREF–/VeREF–
P5.1/S0
P5.0/S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
S11
S12
S13
4
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75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
P2.4/UTXD0
P2.5/URXD0
P2.6/CAOUT
P2.7/ADC12CLK
P3.0/STE0
P3.1/SIMO0
P3.2/SOMI0
P3.3/UCLK0
P3.4/TB3
P3.5/TB4
P3.6/TB5
P3.7/TB6
P4.0/UTXD1
P4.1/URXD1
DVSS2
DVCC2
P5.7/R33
P5.6/R23
P5.5/R13
R03
P5.4/COM3
P5.3/COM2
P5.2/COM1
COM0
P4.2/STE1/S39
SLAS344C – JANUARY 2002 – REVISED MARCH2003
MSP430x43x functional block diagrams
XIN
XOUT/TCLK
Oscillator
XT2IN
FLL+
DVCC
DVSS
AVCC
AVSS RST/NMI
ACLK
16 kB Flash
512 B RAM
12 Bit ADC
SMCLK
24 kB Flash
1 kB RAM
8 Channels
32 kB Flash
1 kB RAM
<10 µs Conv.
XT2OUT
P5
P6
I/O Port 5/6
P3
P4
I/O Port 3/4
16 I/Os
P1
P2
I/O Port 1/2
USART0
16 I/Os, With
UART or
SPI
Function
Interrupt
Capability
MCLK
Test
MAB,
4 Bit
MAB, 16 Bit
JTAG
CPU
MCB
Emulation
Module
Incl. 16 Reg.
Bus
Conv
MDB, 16 Bit
MDB, 8 Bit
4
TMS
Watchdog
Timer
TCK
TDI
15 / 16 Bit
TDO/TDI
Timer_B3
3 CC–Reg
Shadow
Reg.
Timer_A3
POR
SVS
Brownout
3 CC-Reg.
Comparator
A
Basic
Timer1
1 Interrupt
Vector
LCD
160
Segments
1,2,3,4 MUX
fLCD
MSP430x44x functional block diagrams
XIN
XOUT/TCLK
Oscillator
XT2IN
FLL+
DVCC
DVSS
AVCC
AVSS RST/NMI
ACLK
32 kB Flash
1 kB RAM
12 Bit ADC
SMCLK
48 kB Flash
2 kB RAM
8 Channels
60 kB Flash
2 kB RAM
<10 µs Conv.
XT2OUT
P5
P6
I/O Port 5/6
P3
P4
I/O Port 3/4
16 I/Os
P1
P2
I/O Port 1/2
USART0
USART1
16 I/Os, With
UART or
SPI
Function
Interrupt
Capability
MCLK
Test
MAB,
4 Bit
MAB, 16 Bit
JTAG
CPU
MCB
Emulation
Module
Incl. 16 Reg.
Bus
Conv
MDB, 16 Bit
MDB, 8 Bit
4
TMS
Multiply
TCK
MPY, MPYS
MAC,MACS
8×8 Bit
8×16 Bit
16×8 Bit
16×16 Bit
TDI
TDO/TDI
Watchdog
Timer
15 / 16 Bit
Timer_B7
7 CC-Reg.
Shadow
Reg.
Timer_A3
3 CC-Reg.
POR
SVS
Brownout
Comparator
A
Basic
Timer1
1 Interrupt
Vector
LCD
160
Segments
1,2,3,4 MUX
fLCD
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MSP430x43x Terminal Functions
TERMINAL
PN
NAME
NO.
PZ
I/O
NAME
NO.
DESCRIPTION
I/O
DVCC1
1
2
I/O
DVCC1
P6.3/A3
1
P6.3/A3
2
I/O
General-purpose digital I/O, analog input a3—12-bit ADC
P6.4/A4
3
I/O
P6.4/A4
3
I/O
General-purpose digital I/O, analog input a4—12-bit ADC
P6.5/A5
4
I/O
P6.5/A5
4
I/O
General-purpose digital I/O, analog input a5—12-bit ADC
P6.6/A6
5
I/O
P6.6/A6
5
I/O
General-purpose digital I/O, analog input a6—12-bit ADC
P6.7/A7/SVSin
6
I/O
P6.7/A7/SVSin
6
I/O
General-purpose digital I/O, analog input a7—12-bit ADC, analog input
to brownout, supply voltage supervisor
VREF+
7
O
VREF+
7
O
Output of positive terminal of the reference voltage in the ADC
XIN
8
I
XIN
8
I
Input port for crystal oscillator XT1. Standard or watch crystals can be
connected.
XOUT/TCLK
9
I/O
XOUT/TCLK
9
I/O
VeREF+
10
I
VeREF+
10
I
Input for an external reference voltage to the ADC
VREF–/VeREF–
11
I
VREF–/VeREF–
11
I
Negative terminal for the ADC’s reference voltage for both sources, the
internal reference voltage, or an external applied reference voltage.
P5.1/S0
12
I/O
P5.1/S0
12
I/O
General-purpose I/O / LCD segment output 0
P5.0/S1
13
I/O
P5.0/S1
13
I/O
General-purpose I/O / LCD segment output 1
P4.7/S2
14
I/O
S2
14
O
General-purpose I/O / LCD segment output 2
P4.6/S3
15
I/O
S3
15
O
General-purpose I/O / LCD segment output 3
P4.5/S4
16
I/O
S4
16
O
General-purpose I/O / LCD segment output 4
P4.4/S5
17
I/O
S5
17
O
General-purpose I/O / LCD segment output 5
P4.3/S6
18
I/O
S6
18
O
General-purpose I/O / LCD segment output 6
P4.2/S7
19
I/O
S7
19
O
General-purpose I/O / LCD segment output 7
P4.1/S8
20
I/O
S8
20
O
General-purpose I/O / LCD segment output 8
P4.0/S9
21
I/O
S9
21
O
General-purpose I/O / LCD segment output 9
S10
22
O
S10
22
O
LCD segment output 10
S11
23
O
S11
23
O
LCD segment output 11
S12
24
O
S12
24
O
LCD segment output 12
S13
25
O
S13
25
O
LCD segment output 13
S14
26
O
S14
26
O
LCD segment output 14
S15
27
O
S15
27
O
LCD segment output 15
S16
28
O
S16
28
O
LCD segment output 16
S17
29
O
S17
29
O
LCD segment output 17
P2.7/ADC12CLK/
S18
30
I/O
S18
30
O
General-purpose digital I/O / conversion clock—12-bit ADC
LCD segment output 18
P2.6/CAOUT/S19
31
I/O
S19
31
O
General-purpose digital I/O / Comparator_A output / LCD segment
output 19
S20
32
O
S20
32
O
LCD segment output 20
S21
33
O
S21
33
O
LCD segment output 21
S22
34
O
S22
34
O
LCD segment output 22
S23
35
O
S23
35
O
LCD segment output 23
P3.7/S24
36
I/O
S24
36
O
General-purpose digital I/O / LCD segment output 24
P3.6/S25
37
I/O
S25
37
O
General-purpose digital I/O / LCD segment output 25
P3.5/S26
38
I/O
S26
38
O
General-purpose digital I/O / LCD segment output 26
P3.4/S27
39
I/O
S27
39
O
General-purpose digital I/O / LCD segment output 27
6
Digital supply voltage, positive terminal. Supplies all digital parts
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SLAS344C – JANUARY 2002 – REVISED MARCH2003
MSP430x43x Terminal Functions (Continued)
TERMINAL
PN
PZ
I/O
NAME
NO.
DESCRIPTION
I/O
NAME
NO.
P3.3/UCLK0/S28
40
I/O
S28
40
O
General-purpose digital I/O / ext. clock i/p—USART0/UART or SPI
mode, clock o/p—USART0/SPI mode / LCD segment output 28
P3.2/SOMI0/S29
41
I/O
S29
41
O
General-purpose digital I/O / slave out/master in of USART0/SPI mode
/ LCD segment output 29
P3.1/SIMO0/S30
42
I/O
S30
42
O
General-purpose digital I/O / slave out/master out of USART0/SPI
mode / LCD segment output 30
P3.0/STE0/S31
43
I/O
S31
43
O
General-purpose digital I/O / slave transmit enable-USART0/SPI
mode / LCD segment output 31
S32
44
O
LCD segment output 32
S33
45
O
LCD segment output 33
P4.7/S34
46
I/O
General-purpose digital I/O / LCD segment output 34
P4.6/S35
47
I/O
General-purpose digital I/O / LCD segment output 35
P4.5/S36
48
I/O
General-purpose digital I/O / LCD segment output 36
P4.4/S37
49
I/O
General-purpose digital I/O / LCD segment output 37
P4.3/S38
50
I/O
General-purpose digital I/O / LCD segment output 38
P4.2/S39
51
I/O
General-purpose digital I/O / LCD segment output 39
COM0
44
O
COM0
52
O
COM0–3 are used for LCD backplanes.
P5.2/COM1
45
I/O
P5.2/COM1
53
I/O
General-purpose digital I/O / common output, COM0–3 are used for
LCD backplanes.
P5.3/COM2
46
I/O
P5.3/COM2
54
I/O
General-purpose digital I/O / common output, COM0–3 are used for
LCD backplanes.
P5.4/COM3
47
I/O
P5.4/COM3
55
I/O
General-purpose digital I/O / common output, COM0–3 are used for
LCD backplanes.
R03
48
I
R03
56
I
P5.5/R13
49
I/O
P5.5/R13
57
I/O
General-purpose digital I/O / input port of third most positive analog
LCD level (V4 or V3)
P5.6/R23
50
I/O
P5.6/R23
58
I/O
General-purpose digital I/O / input port of second most positive analog
LCD level (V2)
P5.7/R33
51
I/O
P5.7/R33
59
I/O
General-purpose digital I/O / output port of most positive analog LCD
level (V1)
DVCC2
52
53
DVCC2
DVSS2
60
DVSS2
P4.1
62
I/O
General-purpose digital I/O
P4.0
63
I/O
General-purpose digital I/O
P3.7
64
I/O
General-purpose digital I/O
P3.6
65
I/O
General-purpose digital I/O
P3.5
66
I/O
General-purpose digital I/O
P3.4
67
I/O
General-purpose digital I/O
P3.3/UCLK0
68
I/O
General-purpose digital I/O / external clock input—USART0/UART or
SPI mode, clock output—USART0/SPI mode
P3.2/SOMI0
69
I/O
General-purpose digital I/O / slave out/master in of USART0/SPI mode
P3.1/SIMO0
70
I/O
General-purpose digital I/O / slave in/master out of USART0/SPI mode
P3.0/STE0
71
I/O
General-purpose digital I/O / slave transmit enable USART0/SPI mode
P2.7/ADC12CLK
72
I/O
General-purpose digital I/O / conversion clock—12-bit ADC
P2.6/CAOUT
73
I/O
General-purpose digital I/O / Comparator_A output
P2.5/URXD0
74
I/O
General-purpose digital I/O / receive data in—USART0/UART mode
P2.5/URXD0
54
I/O
Input port of fourth positive (lowest) analog LCD level (V5)
61
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MSP430x43x Terminal Functions (Continued)
TERMINAL
PN
NAME
NO.
PZ
I/O
NAME
NO.
DESCRIPTION
I/O
P2.4/UTXD0
55
I/O
P2.4/UTXD0
75
I/O
General-purpose digital I/O / transmit data out—USART0/UART mode
P2.3/TB2
56
I/O
P2.3/TB2
76
I/O
General-purpose digital I/O / Timer_B3 CCR2.
Capture: CCI2A/CCI2B input, compare: Out2 output
P2.2/TB1
57
I/O
P2.2/TB1
77
I/O
General-purpose digital I/O / Timer_B3 CCR1.
Capture: CCI1A/CCI1B input, compare: Out1 output
P2.1/TB0
58
I/O
P2.1/TB0
78
I/O
General-purpose digital I/O / Timer_B3 CCR0.
Capture: CCI0A/CCI0B input, compare: Out0 output
P2.0/TA2
59
I/O
P2.0/TA2
79
I/O
General-purpose digital I/O / Timer_A
Capture: CCI2A input, compare: Out2 output
P1.7/CA1
60
I/O
P1.7/CA1
80
I/O
General-purpose digital I/O / Comparator_A input
P1.6/CA0
61
I/O
P1.6/CA0
81
I/O
General-purpose digital I/O / Comparator_A input
82
I/O
General-purpose digital I/O / Timer_A, clock signal TACLK input /
ACLK output (divided by 1, 2, 4, or 8)
P1.5/TACLK/
ACLK
62
I/O
P1.5/TACLK/
ACLK
P1.4/TBCLK/
SMCLK
63
I/O
P1.4/TBCLK/
SMCLK
83
I/O
General-purpose digital I/O / input clock TBCLK—Timer_B3 / submain
system clock SMCLK output
P1.3/TBOUTH/
SVSOUT
64
I/O
P1.3/TBOUTH/
SVSOUT
84
I/O
General-purpose digital I/O / switch all PWM digital output ports to high
impedance—Timer_B3 TB0 to TB2 / SVS: output of SVS comparator
P1.2/TA1
65
I/O
P1.2/TA1
85
I/O
General-purpose digital I/O / Timer_A, Capture: CCI1A, compare:
Out1 output
P1.1/TA0/MCLK
66
I/O
P1.1/TA0/MCLK
86
I/O
General-purpose digital I/O / Timer_A. Capture: CCI0B / MCLK output.
Note: TA0 is only an input on this pin.
P1.0/TA0
67
I/O
P1.0/TA0
87
I/O
General-purpose digital I/O / Timer_A. Capture: CCI0A input,
compare: Out0 output
XT2OUT
68
O
XT2OUT
88
O
Output terminal of crystal oscillator XT2
XT2IN
69
I
XT2IN
89
I
Input port for crystal oscillator XT2. Only standard crystals can be
connected.
TDO/TDI
70
I/O
TDO/TDI
90
I/O
Test data output port. TDO/TDI data output or programming data input
terminal
TDI
71
I
TDI
91
I
Test data input. TDI is used as a data input port. The device protection
fuse is connected to TDI.
TMS
72
I
TMS
92
I
Test mode select. TMS is used as an input port for device programming
and test.
TCK
73
I
TCK
93
I
Test clock. TCK is the clock input port for device programming and test.
RST/NMI
74
I
RST/NMI
94
I
General-purpose digital I/O / reset input or nonmaskable interrupt input
port
P6.0/A0
75
I/O
P6.0/A0
95
I/O
General-purpose digital I/O / analog input a0 – 12-bit ADC
P6.1/A1
76
I/O
P6.1/A1
96
I/O
General-purpose digital I/O / analog input a1 – 12-bit ADC
P6.2/A2
77
I/O
P6.2/A2
97
I/O
General-purpose digital I/O / analog input a2 – 12-bit ADC
AVSS
78
AVSS
98
Negative terminal that supplies SVS, brownout, oscillator, FLL+,
comparator_A, port 1, and LCD resistive divider circuitry.
DVSS1
79
DVSS1
99
Digital supply voltage, negative terminal. Supplies all digital parts,
except those which are supplied via AVCC/AVSS.
AVCC
80
AVCC
100
Positive terminal that supplies SVS, brownout, oscillator, FLL+,
comparator_A, port 1, and LCD resistive divider circuitry; must not
power up prior to DVCC1/DVCC2.
8
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MSP430x44x Terminal Functions
TERMINAL
PN
NAME
I/O
DESCRIPTION
NO.
DVCC1
1
P6.3/A3
2
I/O
Digital supply voltage, positive terminal. Supplies all digital parts
General-purpose digital I/O, analog input a3—12-bit ADC
P6.4/A4
3
I/O
General-purpose digital I/O, analog input a4—12-bit ADC
P6.5/A5
4
I/O
General-purpose digital I/O, analog input a5—12-bit ADC
P6.6/A6
5
I/O
General-purpose digital I/O, analog input a6—12-bit ADC
P6.7/A7/SVSin
6
I/O
General-purpose digital I/O, analog input a7—12-bit ADC, analog input to brownout, supply voltage
supervisor
VREF+
XIN
7
O
Output of positive terminal of the reference voltage in the ADC
8
I
Input port for crystal oscillator XT1. Standard or watch crystals can be connected.
XOUT/TCLK
9
I/O
VeREF+
10
I
Input for an external reference voltage to the ADC
VREF–/VeREF–
11
I
Negative terminal for the ADC’s reference voltage for both sources, the internal reference voltage, or an
external applied reference voltage
P5.1/S0
12
O
General-purpose digital I/O, LCD segment output 0
P5.0/S1
13
O
General-purpose digital I/O, LCD segment output 1
S2
14
O
LCD segment output 2
S3
15
O
LCD segment output 3
S4
16
O
LCD segment output 4
S5
17
O
LCD segment output 5
S6
18
O
LCD segment output 6
S7
19
O
LCD segment output 7
S8
20
O
LCD segment output 8
S9
21
O
LCD segment output 9
S10
22
O
LCD segment output 10
S11
23
O
LCD segment output 11
S12
24
O
LCD segment output 12
S13
25
O
LCD segment output 13
S14
26
O
LCD segment output 14
S15
27
O
LCD segment output 15
S16
28
O
LCD segment output 16
S17
29
O
LCD segment output 17
S18
30
O
LCD segment output 18
S19
31
O
LCD segment output 19
S20
32
O
LCD segment output 20
S21
33
O
LCD segment output 21
S22
34
O
LCD segment output 22
S23
35
O
LCD segment output 23
S24
36
O
LCD segment output 24
S25
37
O
LCD segment output 25
S26
38
O
LCD segment output 26
S27
39
O
LCD segment output 27
S28
40
O
LCD segment output 28
Output terminal of crystal oscillator XT1 or test clock input
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MSP430x44x Terminal Functions (Continued)
TERMINAL
PN
NAME
I/O
DESCRIPTION
NO.
S29
41
O
LCD segment output 29
S30
42
O
LCD segment output 30
S31
43
O
LCD segment output 31
S32
44
O
LCD segment output 32
S33
45
O
LCD segment output 33
P4.7/S34
46
I/O
General-purpose digital I/O / LCD segment output 34
P4.6/S35
47
I/O
General-purpose digital I/O / LCD segment output 35
P4.5/UCLK1/S36
48
I/O
General-purpose digital I/O / external clock input—USART1/UART or SPI mode, clock
output—USART1/SPI MODE / LCD segment output 36
P4.4/SOMI1/S37
49
I/O
General-purpose digital I/O / slave out/master in of USART1/SPI mode / LCD segment output 37
P4.3/SIMO1/S38
50
I/O
General-purpose digital I/O / slave in/master out of USART1/SPI mode / LCD segment output 38
P4.2/STE1/S39
51
I/O
General-purpose digital I/O / slave transmit enable—USART1/SPI mode / LCD segment output 39
COM0
52
O
COM0–3 are used for LCD backplanes.
P5.2/COM1
53
I/O
General-purpose digital I/O / common output, COM0–3 are used for LCD backplanes.
P5.3/COM2
54
I/O
General-purpose digital I/O / common output, COM0–3 are used for LCD backplanes.
P5.4/COM3
55
I/O
General-purpose digital I/O / common output, COM0–3 are used for LCD backplanes.
R03
56
I
P5.5/R13
57
I/O
General-purpose digital I/O / Input port of third most positive analog LCD level (V4 or V3)
P5.6/R23
58
I/O
General-purpose digital I/O / Input port of second most positive analog LCD level (V2)
P5.7/R33
59
I/O
General-purpose digital I/O / Output port of most positive analog LCD level (V1)
DVCC2
60
DVSS2
61
P4.1/URXD1
62
I/O
General-purpose digital I/O / receive data in—USART1/UART mode
P4.0/UTXD1
63
I/O
General-purpose digital I/O / transmit data out—USART1/UART mode
P3.7/TB6
64
I/O
General-purpose digital I/O / Timer_B7 CCR6 / Capture: CCI6A/CCI6B input, compare: Out6 output
P3.6/TB5
65
I/O
General-purpose digital I/O / Timer_B7 CCR5 / Capture: CCI5A/CCI5B input, compare: Out5 output
P3.5/TB4
66
I/O
General-purpose digital I/O / Timer_B7 CCR4 / Capture: CCI4A/CCI4B input, compare: Out4 output
P3.4/TB3
67
I/O
General-purpose digital I/O / Timer_B7 CCR3 / Capture: CCI3A/CCI3B input, compare: Out3 output
P3.3/UCLK0
68
I/O
General-purpose digital I/O / external clock input—USART0/UART or SPI mode, clock
output—USART0/SPI mode
P3.2/SOMI0
69
I/O
General-purpose digital I/O / slave out/master in of USART0/SPI mode
P3.1/SIMO0
70
I/O
General-purpose digital I/O / slave in/master out of USART0/SPI mode
P3.0/STE0
71
I/O
General-purpose digital I/O / slave transmit enable—USART0/SPI mode
P2.7/ADC12CLK
72
I/O
General-purpose digital I/O / conversion clock—12-bit ADC
P2.6/CAOUT
73
I/O
General-purpose digital I/O / Comparator_A output
P2.5/URXD0
74
I/O
General-purpose digital I/O / receive data in—USART0/UART mode
P2.4/UTXD0
75
I/O
General-purpose digital I/O / transmit data out—USART0/UART mode
P2.3/TB2
76
I/O
General-purpose digital I/O / Timer_B7 CCR2. Capture: CCI2A/CCI2B input, compare: Out2 output
P2.2/TB1
77
I/O
General-purpose digital I/O / Timer_B7 CCR1. Capture: CCI1A/CCI1B input, compare: Out1 output
P2.1/TB0
78
I/O
General-purpose digital I/O / Timer_B7 CCR0. Capture: CCI0A/CCI0B input, compare: Out0 output
P2.0/TA2
79
I/O
General-purpose digital I/O / Timer_A Capture: CCI2A input, compare: Out2 output
P1.7/CA1
80
I/O
General-purpose digital I/O / Comparator_A input
10
Input port of fourth positive (lowest) analog LCD level (V5)
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MSP430x44x Terminal Functions (Continued)
TERMINAL
PN
NAME
I/O
DESCRIPTION
NO.
P1.6/CA0
81
I/O
General-purpose digital I/O / Comparator_A input
P1.5/TACLK/
ACLK
82
I/O
General-purpose digital I/O / Timer_A, clock signal TACLK input / ACLK output (divided by 1, 2, 4, or 8)
P1.4/TBCLK/
SMCLK
83
I/O
General-purpose digital I/O / input clock TBCLK—Timer_B7 / submain system clock SMCLK output
P1.3/TBOutH/
SVSOut
84
I/O
General-purpose digital I/O / switch all PWM digital output ports to high impedance—Timer_B7 TB0 to TB6
/ SVS: output of SVS comparator
P1.2/TA1
85
I/O
General-purpose digital I/O / Timer_A, Capture: CCI1A, compare: Out1 output
P1.1/TA0/MCLK
86
I/O
General-purpose digital I/O / Timer_A. Capture: CCI0B / MCLK output.
Note: TA0 is only an input on this pin.
P1.0/TA0
87
I/O
General-purpose digital I/O / Timer_A. Capture: CCI0A input, compare: Out0 output
XT2OUT
88
O
Output terminal of crystal oscillator XT2
XT2IN
89
I
Input port for crystal oscillator XT2. Only standard crystals can be connected.
TDO/TDI
90
I/O
TDI
91
I
Test data input. TDI is used as a data input port. The device protection fuse is connected to TDI.
TMS
92
I
Test mode select. TMS is used as an input port for device programming and test.
TCK
93
I
Test clock. TCK is the clock input port for device programming and test.
RST/NMI
94
I
Reset input or nonmaskable interrupt input port
P6.0/A0
95
I/O
General-purpose digital I/O, analog input a0—12-bit ADC
P6.1/A1
96
I/O
General-purpose digital I/O, analog input a1—12-bit ADC
P6.2/A2
97
I/O
General-purpose digital I/O, analog input a2—12-bit ADC
AVSS
98
DVSS1
99
AVCC
100
Test data output port. TDO/TDI data output or programming data input terminal
Negative terminal that supplies SVS, brownout, oscillator, FLL+, comparator_A, port 1, and LCD resistive
divider circuitry.
Digital supply voltage, negative terminal. Supplies all digital parts, except those which are supplied via
AVCC/AVSS.
Positive terminal that supplies SVS, brownout, oscillator, FLL+, comparator_A, port 1, and LCD resistive
divider circuitry; must not power up prior to DVCC1/DVCC2.
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SLAS344C – JANUARY 2002 – REVISED MARCH2003
short-form description
CPU
The MSP430 CPU has a 16-bit RISC architecture
that is highly transparent to the application. All
operations, other than program-flow instructions,
are performed as register operations in conjunction with seven addressing modes for source
operand and four addressing modes for destination operand.
Program Counter
PC/R0
Stack Pointer
SP/R1
SR/CG1/R2
Status Register
Constant Generator
The CPU is integrated with 16 registers that
provide reduced instruction execution time. The
register-to-register operation execution time is
one cycle of the CPU clock.
Four of the registers, R0 to R3, are dedicated as
program counter, stack pointer, status register,
and constant generator respectively. The remaining registers are general-purpose registers.
Peripherals are connected to the CPU using data,
address, and control buses, and can be handled
with all instructions.
instruction set
The instruction set consists of 51 instructions with
three formats and seven address modes. Each
instruction can operate on word and byte data.
Table 1 shows examples of the three types of
instruction formats; the address modes are listed
in Table 2.
CG2/R3
General-Purpose Register
R4
General-Purpose Register
R5
General-Purpose Register
R6
General-Purpose Register
R7
General-Purpose Register
R8
General-Purpose Register
R9
General-Purpose Register
R10
General-Purpose Register
R11
General-Purpose Register
R12
General-Purpose Register
R13
General-Purpose Register
R14
General-Purpose Register
R15
Table 1. Instruction Word Formats
Dual operands, source-destination
e.g. ADD R4,R5
R4 + R5 –––> R5
Single operands, destination only
e.g. CALL
PC ––>(TOS), R8––> PC
Relative jump, un/conditional
e.g. JNE
R8
Jump-on-equal bit = 0
Table 2. Address Mode Descriptions
ADDRESS MODE
S D
Register
n n
MOV Rs,Rd
MOV R10,R11
Indexed
n n
MOV X(Rn),Y(Rm)
MOV 2(R5),6(R6)
Symbolic (PC relative)
n n
MOV EDE,TONI
M(EDE) ––> M(TONI)
n n
MOV and MEM,and
TCDAT
M(MEM) ––> M(TCDAT)
Absolute
EXAMPLE
OPERATION
R10
––> R11
M(2+R5)––> M(6+R6)
Indirect
n
MOV @Rn,Y(Rm)
MOV @R10,Tab(R6)
M(R10) ––> M(Tab+R6)
Indirect
autoincrement
n
MOV @Rn+,Rm
MOV @R10+,R11
M(R10) ––> R11
R10 + 2––> R10
Immediate
n
MOV #X,TONI
MOV #45,TONI
NOTE: S = source
12
SYNTAX
D = destination
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#45
––> M(TONI)
SLAS344C – JANUARY 2002 – REVISED MARCH2003
operating modes
The MSP430 has one active mode and five software selectable low-power modes of operation. An interrupt
event can wake up the device from any of the five low-power modes, service the request and restore back to
the low-power mode on return from the interrupt program.
The following six operating modes can be configured by software:
D Active mode AM;
–
All clocks are active
D Low-power mode 0 (LPM0);
–
CPU is disabled
ACLK and SMCLK remain active. MCLK is disabled
FLL+ Loop control remains active
D Low-power mode 1 (LPM1);
–
CPU is disabled
FLL+ Loop control is disabled
ACLK and SMCLK remain active. MCLK is disabled
D Low-power mode 2 (LPM2);
–
CPU is disabled
MCLK and FLL+ loop control and DCOCLK are disabled
DCO’s dc-generator remains enabled
ACLK remains active
D Low-power mode 3 (LPM3);
–
CPU is disabled
MCLK, FLL+ loop control, and DCOCLK are disabled
DCO’s dc-generator is disabled
ACLK remains active
D Low-power mode 4 (LPM4);
–
CPU is disabled
ACLK is disabled
MCLK, FLL+ loop control, and DCOCLK are disabled
DCO’s dc-generator is disabled
Crystal oscillator is stopped
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SLAS344C – JANUARY 2002 – REVISED MARCH2003
interrupt vector addresses
The interrupt vectors and the power-up starting address are located in the address range 0FFFFh – 0FFE0h.
The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.
Table 3. Interrupt Sources, Flags, and Vectors of 4xx Configurations
INTERRUPT SOURCE
INTERRUPT FLAG
SYSTEM INTERRUPT
WORD
ADDRESS
PRIORITY
Power-Up
External Reset
Watchdog
Flash Memory
WDTIFG
KEYV
(see Note 1)
Reset
0FFFEh
15, highest
NMI
Oscillator Fault
Flash Memory Access Violation
Timer_B7†
NMIIFG (see Notes 1 and 3)
OFIFG (see Notes 1 and 3)
ACCVIFG (see Notes 1 and 3)
(Non)maskable
(Non)maskable
(Non)maskable
0FFFCh
14
TBCCR0 CCIFG (see Note 2)
Maskable
0FFFAh
13
Timer_B7†
TBCCR1 to TBCCR6 CCIFGs
TBIFG (see Notes 1 and 2)
Maskable
0FFF8h
12
Comparator_A
CAIFG
Maskable
0FFF6h
11
Watchdog Timer
WDTIFG
Maskable
0FFF4h
10
USART0 Receive
URXIFG0
Maskable
0FFF2h
9
USART0 Transmit
UTXIFG0
Maskable
0FFF0h
8
ADC12
ADC12IFG (see Notes 1 and 2)
Maskable
0FFEEh
7
Timer_A3
TACCR0 CCIFG (see Note 2)
Maskable
0FFECh
6
Timer_A3
TACCR1 and TACCR2 CCIFGs,
TAIFG (see Notes 1 and 2)
Maskable
0FFEAh
5
I/O Port P1 (Eight Flags)
P1IFG.0 (see Notes 1 and 2)
To
P1IFG.7 (see Notes 1 and 2)
Maskable
0FFE8h
4
URXIFG1
Maskable
0FFE6h
3
UTXIFG1
Maskable
0FFE4h
2
P2IFG.0 (see Notes 1 and 2)
To
P2IFG.7 (see Notes 1 and 2)
Maskable
0FFE2h
1
USART1 Receive‡
USART1 Transmit‡
I/O Port P2 (Eight Flags)
Basic Timer1
BTIFG
Maskable
0FFE0h
0, lowest
† ’43x uses Timer_B3 with TBCCR0, 1 and 2 CCIFG flags, and TBIFG. ’44x uses Timer_B7 with TBCCR0 CCIFG, TBCCR1 to TBCCR6 CCIFGs,
and TBIFG
‡ USART1 is implemented in ’44x only.
NOTES: 1. Multiple source flags
2. Interrupt flags are located in the module.
3. (Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable can not disable
it.
14
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special function registers
Most interrupt and module-enable bits are collected in the lowest address space. Special-function register bits
not allocated to a functional purpose are not physically present in the device. This arrangement provides simple
software access.
interrupt enable 1 and 2
7
Address
0h
6
UTXIE0
rw–0
URXIE0
rw–0
5
4
ACCVIE
NMIIE
rw–0
3
2
1
OFIE
rw–0
rw–0
0
WDTIE
rw–0
WDTIE:
Watchdog-timer interrupt enable. Inactive if watchdog mode is selected. Active if watchdog
timer is configured in interval timer mode.
OFIE:
Oscillator-fault-interrupt enable
NMIIE:
Nonmaskable-interrupt enable
ACCVIE:
Flash access violation interrupt enable
URXIE0:
USART0, UART, and SPI receive-interrupt enable
UTXIE0:
USART0, UART, and SPI transmit-interrupt enable
7
Address
6
BTIE
01h
rw–0
5
4
UTXIE1
URXIE1
rw–0
3
2
1
0
rw–0
URXIE1:
USART1, UART, and SPI receive-interrupt enable (MSP430F44x devices only)
UTXIE1:
USART1, UART, and SPI transmit-interrupt enable (MSP430F44x devices only)
BTIE:
Basic timer interrupt enable
interrupt flag register 1 and 2
7
Address
02h
6
UTXIFG0
rw–1
5
URXIFG0
4
3
2
1
NMIIFG
rw–0
OFIFG
rw–0
rw–1
0
WDTIFG
rw–0
WDTIFG:
Set on watchdog timer overflow (in watchdog mode) or security key violation. Reset on VCC
power up or a reset condition at the RST/NMI pin in reset mode.
OFIFG:
Flag set on oscillator fault
NMIIFG:
Set via RST/NMI pin
URXIFG0:
USART0, UART, and SPI receive flag
UTXIFG0:
USART0, UART, and SPI transmit flag
7
Address
03h
6
BTIFG
rw
5
4
UTXIFG1
URXIFG1
rw–1
3
2
1
0
rw–0
URXIFG1:
USART1, UART, and SPI receive flag (MSP430F44x devices only)
UTXIFG1:
USART1, UART, and SPI transmit flag (MSP430F44x devices only)
BTIFG:
Basic timer flag
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SLAS344C – JANUARY 2002 – REVISED MARCH2003
module enable registers 1 and 2
7
UTXE0
Address
04h
rw–0
6
URXE0
USPIE0
5
4
3
1
0
2
1
0
rw–0
URXE0:
USART0, UART mode receive enable
UTXE0:
USART0, UART mode transmit enable
USPIE0:
USART0, SPI mode transmit and receive enable
Address
2
7
6
05h
5
UTXE1
rw–0
4
URXE1
USPIE1
3
rw–0
URXE1:
USART1, UART mode receive enable (MSP430F44x devices only)
UTXE1:
USART1, UART mode transmit enable (MSP430F44x devices only)
USPIE1:
USART1, SPI mode transmit and receive enable (MSP430F44x devices only)
Bit Can Be Read and Written
Bit Can Be Read and Written. It Is Reset by PUC.
SFR Bit Not Present in Device
Legend: rw:
rw–0:
memory organization
MSP430F435
MSP430F436
MSP430F437
MSP430F447
MSP430F448
MSP430F449
Memory
Main: interrupt vector
Main: code memory
Size
Flash
Flash
16KB
0FFFFh – 0FFE0h
0FFFFh – 0C000h
24KB
0FFFFh – 0FFE0h
0FFFFh – 0A000h
32KB
0FFFFh – 0FFE0h
0FFFFh – 08000h
48KB
0FFFFh – 0FFE0h
0FFFFh – 04000h
60KB
0FFFFh – 0FFE0h
0FFFFh – 01100h
Information memory
Size
Flash
256 Byte
010FFh – 01000h
256 Byte
010FFh – 01000h
256 Byte
010FFh – 01000h
256 Byte
010FFh – 01000h
256 Byte
010FFh – 01000h
Boot memory
Size
ROM
1KB
0FFFh – 0C00h
1KB
0FFFh – 0C00h
1KB
0FFFh – 0C00h
1KB
0FFFh – 0C00h
1KB
0FFFh – 0C00h
Size
512 Byte
03FFh – 0200h
1KB
05FFh – 0200h
1KB
05FFh – 0200h
2KB
09FFh – 0200h
2KB
09FFh – 0200h
16-bit
8-bit
8-bit SFR
01FFh – 0100h
0FFh – 010h
0Fh – 00h
01FFh – 0100h
0FFh – 010h
0Fh – 00h
01FFh – 0100h
0FFh – 010h
0Fh – 00h
01FFh – 0100h
0FFh – 010h
0Fh – 00h
01FFh – 0100h
0FFh – 010h
0Fh – 00h
RAM
Peripherals
bootstrap loader (BSL)
The MSP430 bootstrap loader (BSL) enables users to program the flash memory or RAM using a UART serial
interface. Access to the MSP430 memory via the BSL is protected by user-defined password. For complete
description of the features of the BSL and its implementation, see the Application report Features of the MSP430
Bootstrap Loader, Literature Number SLAA089.
16
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SLAS344C – JANUARY 2002 – REVISED MARCH2003
flash memory
The flash memory can be programmed via the JTAG port, the bootstrap loader, or in-system by the CPU. The
CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory include:
D Flash memory has n segments of main memory and two segments of information memory (A and B) of 128
bytes each. Each segment in main memory is 512 bytes in size.
D Segments 0 to n may be erased in one step, or each segment may be individually erased.
D Segments A and B can be erased individually, or as a group with segments 0–n.
Segments A and B are also called information memory.
D New devices may have some bytes programmed in the information memory (needed for test during
manufacturing). The user should perform an erase of the information memory prior to the first use.
16KB
24KB
32KB
48KB
60KB
0FFFFh
0FFFFh
0FFFFh
0FFFFh
0FFFFh
0FE00h
0FDFFh
0FE00h
0FDFFh
0FE00h
0FDFFh
0FE00h
0FDFFh
0FE00h
0FDFFh
Segment 1
0FC00h
0FBFFh
0FC00h
0FBFFh
0FC00h
0FBFFh
0FC00h
0FBFFh
0FC00h
0FBFFh
Segment 2
0FA00h
0F9FFh
0FA00h
0F9FFh
0FA00h
0F9FFh
0FA00h
0F9FFh
0FA00h
0F9FFh
0C400h
0C3FFh
0A400h
0A3FFh
08400h
083FFh
04400h
043FFh
01400h
013FFh
0C200h
0C1FFh
0A200h
0A1FFh
08200h
081FFh
04200h
041FFh
01200h
011FFh
0C000h
010FFh
0A000h
010FFh
08000h
010FFh
04000h
010FFh
01100h
010FFh
01080h
0107Fh
01080h
0107Fh
01080h
0107Fh
01080h
0107Fh
01080h
0107Fh
01000h
01000h
01000h
01000h
01000h
Segment 0
w/ Interrupt Vectors
Main
Memory
Segment n-1
Segment n
Segment A
Information
Memory
Segment B
peripherals
Peripherals are connected to the CPU through data, address, and control busses and can be handled using
all instructions.
digital I/O
There are six 8-bit I/O ports implemented—ports P1 through P6:
D
D
D
D
All individual I/O bits are independently programmable.
Any combination of input, output, and interrupt conditions is possible.
Edge-selectable interrupt input capability for all the eight bits of ports P1 and P2.
Read/write access to port-control registers is supported by all instructions.
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SLAS344C – JANUARY 2002 – REVISED MARCH2003
oscillator and system clock
The clock system in the MSP430x43x and MSP43x44x family of devices is supported by the FLL+ module that
includes support for a 32768-Hz watch crystal oscillator, an internal digitally-controlled oscillator (DCO) and a
high frequency crystal oscillator. The FLL+ clock module is designed to meet the requirements of both low
system cost and low-power consumption. The FLL+ features a digital frequency locked loop (FLL) hardware
which in conjunction with a digital modulator stabilizes the DCO frequency to a programmable multiple of the
watch crystal frequency. The internal DCO provides a fast turn-on clock source and stabilizes in less than 6 µs.
The FLL+ module provides the following clock signals:
D
D
D
D
Auxiliary clock (ACLK), sourced from a 32768-Hz watch crystal or a high frequency crystal.
Main clock (MCLK), the system clock used by the CPU.
Sub-Main clock (SMCLK), the sub-system clock used by the peripheral modules.
ACLK/n, the buffered output of ACLK, ACLK/2, ACLK/4, or ACLK/8.
brownout, supply voltage supervisor
The brownout circuit is implemented to provide the proper internal reset signal to the device during power on
and power off. The supply voltage supervisor (SVS) circuitry detects if the supply voltage drops below a user
selectable level and supports both supply voltage supervision (the device is automatically reset) and supply
voltage monitoring (SVM, the device is not automatically reset).
The CPU begins code execution after the brownout circuit releases the device reset. However, VCC may not
have ramped to VCC(min) at that time. The user must insure the default FLL+ settings are not changed until VCC
reaches VCC(min). If desired, the SVS circuit can be used to determine when VCC reaches VCC(min).
multiplication (MSP430x44x Only)
The multiplication operation is supported by a dedicated peripheral module. The module performs 16 16,
16 8, 8 16, and 8 8 bit operations. The module is capable of supporting signed and unsigned multiplication
as well as signed and unsigned multiply and accumulate operations. The result of an operation can be accessed
immediately after the operands have been loaded into the peripheral registers. No additional clock cycles are
required.
Basic Timer1
The Basic Timer1 has two independent 8-bit timers which can be cascaded to form a 16-bit timer/counter. Both
timers can be read and written by software. The Basic Timer1 can be used to generate periodic interrupts and
clock for the LCD module.
LCD drive
The LCD driver generates the segment and common signals required to drive an LCD display. The LCD
controller has dedicated data memory to hold segment drive information. Common and segment signals are
generated as defined by the mode. Static, 2-MUX, 3-MUX, and 4-MUX LCDs are supported by this peripheral.
18
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Table 4. MSP430x43xIPN Terminal Function, Selected by Bits 5/6/7 in LCD Mode Control Register LCDM
TERMINAL
NAME
NO
I/O
BITS 5/6/7 IN LCD MODE CONTROL REGISTER LCDM
000X XXXX
001X XXXX
010X XXX
011X XXXX
100X XXXX
12
I/O
P5.1
S0
P5.0/S1
13
I/O
P5.0
S1
P4.7/S2
14
I/O
P4.7
S2
P4.6/S3
15
I/O
P4.6
S3
P4.5/S4
16
I/O
P4.5
S4
P4.4/S5
17
I/O
P4.4
S5
P4.3/S6
18
I/O
P4.3
S6
P4.2/S7
19
I/O
P4.2
S7
P4.1/S8
20
I/O
P4.1
S8
P4.0/S9
21
I/O
P4.0
S10–S17
22–29
O
30
I/O
P2.7/ADC10CLK
P2.7/ADC10CLK
P2.6/CAOUT
P2.6/CAOUT
P2.7/ADC10CLK/S18
P2.6/CAOUT/S19
101X XXXX
110X XXX
111X XXXX
S9
S10–S17
S18
31
I/O
S20–S23
32–35
O
S19
P3.7/S24
36
I/O
P3.7
P3.7
P3.7
P3.7
S24
P3.6/S25
37
I/O
P3.6
P3.6
P3.6
P3.6
S25
P3.5/S26
38
I/O
P3.5
P3.5
P3.5
P3.5
S26
P3.4/S27
39
I/O
P3.4
P3.4
P3.4
P3.4
P3.3/UCLK0/S28
40
I/O
P3.3/UCLK0
P3.3/UCLK0
P3.3/UCLK0
P3.3/UCLK0
P3.3/UCLK0
S28
P3.2/SOMI0/S29
41
I/O
P3.2/SOMI0
P3.2/SOMI0
P3.2/SOMI0
P3.2/SOMI0
P3.2/SOMI0
S29
P3.1/SIMO0/S30
42
I/O
P3.1/SIMO0
P3.1/SIMO0
P3.1/SIMO0
P3.1/SIMO0
P3.1/SIMO0
S30
P3.0/STE0/S31
43
I/O
P3.0/STE0
P3.0/STE0
P3.0/STE0
P3.0/STE0
P3.0/STE0
S31
S20–S23
S27
,
, , 19
SLAS344B – JANUARY 2002 – REVISED OCTOBER 2002
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
P5.1/S0
NAME
I/O
NO
000X XXXX
001X XXXX
010X XXX
011X XXXX
100X XXXX
101X XXXX
110X XXXX
111X XXXX
P5.1/S0
12
I/O
P5.1
S0
P5.0/S1
13
I/O
P5.0
S1
S2–S33
14–45
O
P4.7/S34
46
I/O
P4.7
P4.7
P4.7
P4.7
P4.7
P4.7
P4.6/S35
47
I/O
P4.6
P4.6
P4.6
P4.6
P4.6
P4.6
P4.5/S36
48
I/O
P4.5
P4.5
P4.5
P4.5
P4.5
P4.5
P4.5
S36
P4.4/S36
48
I/O
P4.4
P4.4
P4.4
P4.4
P4.4
P4.4
P4.4
S37
P4.3/S36
48
I/O
P4.3
P4.3
P4.3
P4.3
P4.3
P4.3
P4.3
S38
P4.2/S36
48
I/O
P4.2
P4.2
P4.2
P4.2
P4.2
P4.2
P4.2
S39
S2–S33
S34
S35
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Table 6. MSP430x44xIPZ Terminal Functions, Selected by Bits 5/6/7 in LCD Mode Control Register LCDM
BITS 5/6/7 IN LCD MODE CONTROL REGISTER LCDM
TERMINAL
NAME
P5.1/S0
I/O
NO
000X XXXX
001X XXXX
010X XXX
011X XXXX
100X XXXX
101X XXXX
110X XXXX
111X XXXX
12
I/O
P5.1
S0
P5.0/S1
13
I/O
P5.0
S2–S33
14–45
O
P4.7/S34
46
I/O
P4.6/S35
47
I/O
P4.6
P4.6
P4.6
P4.6
P4.6
P4.6
P4.5/UCLK1/S36
48
I/O
P4.5/UCLK1
P4.5UCLK1
P4.5/UCLK1
P4.5/UCLK1
P4.5/UCLK1
P4.5/UCLK1
P4.5/UCLK1
S36
P4.4/SOMI1/S37
49
I/O
P4.4/SOMI1
P4.4/SOMI1
P4.4/SOMI1
P4.4/SOMI1
P4.4/SOMI1
P4.4/SOMI1
P4.4/SOMI1
S37
P4.3/SIMO1/S38
50
I/O
P4.3/SIMO1
P4.3/SIMO1
P4.3/SIMO1
P4.3/SIMO1
P4.3/SIMO1
P4.3/SIMO1
P4.3/SIMO1
S38
P4.2/STE1/S39
51
I/O
P4.2/STE1
P4.2/STE1
P4.2/STE1
P4.2/STE1
P4.2/STE1
P4.2/STE1
P4.2/STE1
S39
S1
S2–S33
P4.7
P4.7
P4.7
P4.7
P4.7
P4.7
S34
S35
,
, , BITS 5/6/7 IN LCD MODE CONTROL REGISTER LCDM
TERMINAL
SLAS344B – JANUARY 2002 – REVISED OCTOBER 2002
20
Table 5. MSP430x43xIPZ Terminal Functions, Selected by Bits 5/6/7 in LCD Mode Control Register LCDM
SLAS344B – JANUARY 2002 – REVISED OCTOBER 2002
watchdog timer
The primary function of the watchdog timer (WDT) module is to perform a controlled system restart after a
software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog
function is not needed in an application, the module can be configured as an interval timer and can generate
interrupts at selected time intervals.
USART0
The MSP430x43x and the MSP430x44x have one hardware universal synchronous/asynchronous receive
transmit (USART0) peripheral module that is used for serial data communication. The USART supports
synchronous SPI (3 or 4 pin) and asynchronous UART communication protocols, using double-buffered
transmit and receive channels.
USART1 (MSP430x44x Only)
The MSP430x44x has a second hardware universal synchronous/asynchronous receive transmit (USART1)
peripheral module that is used for serial data communication. The USART supports synchronous SPI (3 or 4
pin) and asynchronous UART communication protocols, using double-buffered transmit and receive channels.
Operation of USART1 is identical to USART0.
timer_A3
Timer_A3 is a 16-bit timer/counter with three capture/compare registers. Timer_A3 can support multiple
capture/compares, PWM outputs, and interval timing. Timer_A3 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
timer_B7 (MSP430x44x Only)
Timer_B7 is a 16-bit timer/counter with seven capture/compare registers. Timer_B7 can support multiple
capture/compares, PWM outputs, and interval timing. Timer_B7 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
timer_B3 (MSP430x43x Only)
Timer_B3 is a 16-bit timer/counter with three capture/compare registers. Timer_B3 can support multiple
capture/compares, PWM outputs, and interval timing. Timer_B3 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
comparator_A
The primary function of the comparator_A module is to support precision slope analog–to–digital conversions,
battery–voltage supervision, and monitoring of external analog signals.
ADC12
The ADC12 module supports fast, 12-bit analog-to-digital conversions. The module implements a 12-bit SAR
core, sample select control, reference generator and a 16 word conversion-and-control buffer. The
conversion-and-control buffer allows up to 16 independent ADC samples to be converted and stored without
any CPU intervention.
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SLAS344B – JANUARY 2002 – REVISED OCTOBER 2002
peripheral file map
PERIPHERALS WITH WORD ACCESS
Watchdog
Watchdog timer control
WDTCTL
0120h
Timer_B7
_
Timer_B3
(see Note 6)
Capture/compare register 6
TBCCR6
019Eh
Capture/compare register 5
TBCCR5
019Ch
Capture/compare register 4
TBCCR4
019Ah
Capture/compare register 3
TBCCR3
0198h
Capture/compare register 2
TBCCR2
0196h
Capture/compare register 1
TBCCR1
0194h
Capture/compare register 0
TBCCR0
0192h
Timer_B register
TBR
0190h
Capture/compare control 6
TBCCTL6
018Eh
Capture/compare control 5
TBCCTL5
018Ch
Capture/compare control 4
TBCCTL4
018Ah
Capture/compare control 3
TBCCTL3
0188h
Capture/compare control 2
TBCCTL2
0186h
Capture/compare control 1
TBCCTL1
0184h
Capture/compare control 0
TBCCTL0
0182h
Timer_B control
TBCTL
0180h
Timer_B interrupt vector
TBIV
011Eh
Timer_A3
_
Reserved
017Eh
Reserved
017Ch
Reserved
017Ah
Reserved
0178h
Capture/compare register 2
TACCR2
0176h
Capture/compare register 1
TACCR1
0174h
Capture/compare register 0
TACCR0
0172h
Timer_A register
TAR
0170h
Reserved
016Eh
Reserved
016Ch
Reserved
016Ah
Reserved
Multiply
py
(MSP430x44x only)
0168h
Capture/compare control 2
TACCTL2
0166h
Capture/compare control 1
TACCTL1
0164h
Capture/compare control 0
TACCTL0
0162h
Timer_A control
TACTL
0160h
Timer_A interrupt vector
TAIV
012Eh
Sum extend
SUMEXT
013Eh
Result high word
RESHI
013Ch
Result low word
RESLO
013Ah
Second operand
OP2
0138h
Multiply signed + accumulate/operand1
MACS
0136h
Multiply + accumulate/operand1
MAC
0134h
Multiply signed/operand1
MPYS
0132h
Multiply unsigned/operand1
MPY
0130h
NOTE 4: Timer_B7 in the MSP430x44x family has seven CCRs; Timer_B3 in the MSP430x43x family has three CCRs.
22
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SLAS344B – JANUARY 2002 – REVISED OCTOBER 2002
peripheral file map (continued)
PERIPHERALS WITH WORD ACCESS (CONTINUED)
Flash
ADC12
Flash control 3
FCTL3
012Ch
Flash control 2
FCTL2
012Ah
Flash control 1
FCTL1
0128h
Conversion memory 15
ADC12MEM15
015Eh
Conversion memory 14
ADC12MEM14
015Ch
Conversion memory 13
ADC12MEM13
015Ah
Conversion memory 12
ADC12MEM12
0158h
Conversion memory 11
ADC12MEM11
0156h
Conversion memory 10
ADC12MEM10
0154h
Conversion memory 9
ADC12MEM9
0152h
Conversion memory 8
ADC12MEM8
0150h
Conversion memory 7
ADC12MEM7
014Eh
Conversion memory 6
ADC12MEM6
014Ch
Conversion memory 5
ADC12MEM5
014Ah
Conversion memory 4
ADC12MEM4
0148h
Conversion memory 3
ADC12MEM3
0146h
Conversion memory 2
ADC12MEM2
0144h
Conversion memory 1
ADC12MEM1
0142h
Conversion memory 0
ADC12MEM0
0140h
Interrupt-vector-word register
ADC12IV
01A8h
Inerrupt-enable register
ADC12IE
01A6h
Inerrupt-flag register
ADC12IFG
01A4h
Control register 1
ADC12CTL1
01A2h
Control register 0
ADC12CTL0
01A0h
ADC memory-control register15
ADC12MCTL15
08Fh
ADC memory-control register14
ADC12MCTL14
08Eh
ADC memory-control register13
ADC12MCTL13
08Dh
ADC memory-control register12
ADC12MCTL12
08Ch
ADC memory-control register11
ADC12MCTL11
08Bh
ADC memory-control register10
ADC12MCTL10
08Ah
ADC memory-control register9
ADC12MCTL9
089h
ADC memory-control register8
ADC12MCTL8
088h
ADC memory-control register7
ADC12MCTL7
087h
ADC memory-control register6
ADC12MCTL6
086h
ADC memory-control register5
ADC12MCTL5
085h
ADC memory-control register4
ADC12MCTL4
084h
ADC memory-control register3
ADC12MCTL3
083h
ADC memory-control register2
ADC12MCTL2
082h
ADC memory-control register1
ADC12MCTL1
081h
ADC memory-control register0
ADC12MCTL0
080h
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23
SLAS344B – JANUARY 2002 – REVISED OCTOBER 2002
peripheral file map (continued)
PERIPHERALS WITH BYTE ACCESS
LCD
LCD memory 20
:
LCD memory 16
LCD memory 15
:
LCD memory 1
LCD control and mode
LCDM20
:
LCDM16
LCDM15
:
LCDM1
LCDCTL
0A4h
:
0A0h
09Fh
:
091h
090h
USART1
(Only in ‘x44x)
Transmit buffer
U1TXBUF
07Fh
Receive buffer
U1RXBUF
07Eh
Baud rate
U1BR1
07Dh
Baud rate
U1BR0
07Ch
Modulation control
U1MCTL
07Bh
Receive control
U1RCTL
07Ah
Transmit control
U1TCTL
079h
USART control
U1CTL
078h
Transmit buffer
U0TXBUF
077h
Receive buffer
U0RXBUF
076h
Baud rate
U0BR1
075h
Baud rate
U0BR0
074h
Modulation control
U0MCTL
073h
Receive control
U0RCTL
072h
Transmit control
U0TCTL
071h
USART control
U0CTL
070h
Comparator_A port disable
CAPD
05Bh
Comparator_A control2
CACTL2
05Ah
Comparator_A control1
CACTL1
059h
BrownOUT, SVS
SVS control register (Reset by brownout signal)
SVSCTL
056h
FLL+ Clock
FLL+ Control1
FLL_CTL1
054h
FLL+ Control0
FLL_CTL0
053h
System clock frequency control
SCFQCTL
052h
System clock frequency integrator
SCFI1
051h
System clock frequency integrator
SCFI0
050h
Basic Timer1
BT counter2
BT counter1
BT control
BTCNT2
BTCNT1
BTCTL
047h
046h
040h
Port P6
Port P6 selection
P6SEL
037h
Port P6 direction
P6DIR
036h
Port P6 output
P6OUT
035h
Port P6 input
P6IN
034h
Port P5 selection
P5SEL
033h
Port P5 direction
P5DIR
032h
Port P5 output
P5OUT
031h
Port P5 input
P5IN
030h
USART0
Comparator_A
p
_
Port P5
24
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SLAS344B – JANUARY 2002 – REVISED OCTOBER 2002
peripheral file map (continued)
PERIPHERALS WITH BYTE ACCESS
Port P4
Port P3
Port P2
Port P1
Special
functions
p
Port P4 selection
P4SEL
01Fh
Port P4 direction
P4DIR
01Eh
Port P4 output
P4OUT
01Dh
Port P4 input
P4IN
01Ch
Port P3 selection
P3SEL
01Bh
Port P3 direction
P3DIR
01Ah
Port P3 output
P3OUT
019h
Port P3 input
P3IN
018h
Port P2 selection
P2SEL
02Eh
Port P2 interrupt enable
P2IE
02Dh
Port P2 interrupt-edge select
P2IES
02Ch
Port P2 interrupt flag
P2IFG
02Bh
Port P2 direction
P2DIR
02Ah
Port P2 output
P2OUT
029h
Port P2 input
P2IN
028h
Port P1 selection
P1SEL
026h
Port P1 interrupt enable
P1IE
025h
Port P1 interrupt-edge select
P1IES
024h
Port P1 interrupt flag
P1IFG
023h
Port P1 direction
P1DIR
022h
Port P1 output
P1OUT
021h
Port P1 input
P1IN
020h
SFR module enable2
ME2
005h
SFR module enable1
ME1
004h
SFR interrupt flag2
IFG2
003h
SFR interrupt flag1
IFG1
002h
SFR interrupt enable2
IE2
001h
SFR interrupt enable1
IE1
000h
absolute maximum ratings over operating free-air temperature (unless otherwise noted)†
Voltage applied at VCC to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 4.1 V
Voltage applied to any pin (referenced to VSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to VCC + 0.3 V
Diode current at any device terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±2 mA
Storage temperature, Tstg: (unprogrammed device) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 150°C
(programmed device) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 85°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE: All voltages referenced to VSS.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
25
SLAS344B – JANUARY 2002 – REVISED OCTOBER 2002
recommended operating conditions
MIN
NOM
MAX
UNITS
Supply voltage during program execution,
VCC (AVCC = DVCC1 = DVCC2 = VCC)
MSP430F43x,
MSP430F44x
1.8
3.6
V
Supply voltage during flash memory programming, VCC
(AVCC = DVCC1 = DVCC2 = VCC)
MSP430F43x,
MSP430F44x
2.7
3.6
V
Supply voltage during program execution, SVS enabled (see
Note 1),
VCC (AVCC = DVCC1 = DVCC2 = VCC)
MSP430F43x,
MSP430F44x
2
3.6
V
0
0
V
–40
85
°C
Supply voltage, VSS (AVSS = DVSS1 = DVSS2 = VSS)
MSP430x43x
MSP430x44x
Operating free-air temperature range, TA
LFXT1 crystal frequency, f(LFXT1)
(see Note 2)
LF selected,
XTS_FLL=0
Watch crystal
XT1 selected,
XTS_FLL=1
Ceramic resonator
XT1 selected,
XTS_FLL=1
Crystal
Ceramic resonator
XT2 crystal
cr stal frequency,
freq enc f(XT2)
Crystal
32.768
kHz
450
8000
kHz
1000
8000
kHz
450
8000
1000
8000
DC
4.15
DC
8
257
476
kHz
3
ms
kH
kHz
Processor frequency
freq enc (signal MCLK)
MCLK), f(System)
VCC = 1.8 V
VCC = 3.6 V
Flash-timing-generator frequency, f(FTG)
MSP430F43x,
MSP430F44x
Cumulative program time, t(CPT) (see Note 3)
VCC = 2.7 V/3.6 V
MSP430F43x
MSP430F44x
Mass erase time, t(MEras) (See the flash memory, timing
generator, control register FCTL2 section and Note 4)
VCC = 2.7 V/3.6 V
Low-level input voltage (TCK, TMS, TDI, RST/NMI), VIL
(excluding Xin, Xout)
VCC = 2.2 V/3 V
VSS
VSS + 0.6
V
High-level input voltage (TCK, TMS, TDI, RST/NMI), VIH
(excluding Xin, Xout)
VCC = 2.2 V/3 V
0.8 × VCC
VCC
V
VCC = 2.2 V/3 V
VSS
0.8 × VCC
0.2 × VCC
V
Input levels at Xin and Xout
VIL(Xin, Xout)
VIH(Xin, Xout)
200
MH
MHz
ms
VCC
NOTES: 1. The minimum operating supply voltage is defined according to the trip point where POR is going active by decreasing the supply
voltage. POR is going inactive when the supply voltage is raised above the minimum supply voltage plus the hysteresis of the SVS
circuitry.
2. In LF mode, the LFXT1 oscillator requires a watch crystal. In XT1 mode, LFXT1 accepts a ceramic resonator or a crystal.
3. The cumulative program time must not be exceeded during a block-write operation. This parameter is only relevant if segment write
option is used.
4. The mass erase duration generated by the flash timing generator is at least 11.1 ms. The cumulative mass erase time needed is
200 ms. This can be achieved by repeating the mass erase operation until the cumulative mass erase time is met (a minimum of
19 cycles may be required).
26
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SLAS344B – JANUARY 2002 – REVISED OCTOBER 2002
typical characteristics
f (MHz)
8 MHz
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
Supply voltage range,
’F43x/’F44x, during
program execution
4.15 MHz
1.8
2.7
3
Supply Voltage – V
Supply voltage range, ’F43x/’F44x,
during flash memory programming
3.6
Figure 1. Frequency vs Supply Voltage, MSP430F43x or MSP430F44x
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
supply current into AVCC + DVCC excluding external current
PARAMETER
TEST CONDITIONS
Active mode, (see Note 1)
f(MCLK) = f(SMCLK) = 1 MHz,
f(ACLK) = 32,768 Hz
XTS=0, SELM=(0,1)
F43x,
F44x
40°C to 85°C
TA = –40°C
I(LPM0)
Low ower mode, (LPM0)
Low-power
(see Note 1)
F43x,
F44x
TA = –40°C
40°C to 85°C
I(LPM2)
Low-power mode, (LPM2),
f(MCLK) = f (SMCLK) = 0 MHz,
MHz
f(ACLK) = 32,768 Hz, SCG0 = 0 (see Note 2)
I(AM)
TA = –40°C
40°C to 85°C
TA = –40°C
TA = 25°C
I(LPM3)
Low ower mode, (LPM3)
Low-power
f((MCLK)) = f((SMCLK)) = 0 MHz,
f(ACLK) = 32,768
32 768 Hz,
Hz SCG0 = 1 (see Note 3)
TA = 60°C
TA = 85°C
TA = –40°C
TA = 25°C
TA = 60°C
TA = 85°C
TA = –40°C
TA = 25°C
I(LPM4)
Low-power mode, (LPM4)
f(MCLK) = 0 MHz
MHz, f(SMCLK) = 0 MHz
MHz,
f(ACLK) = 0 Hz, SCG0 = 1 (see Note 2)
TA = 60°C
TA = 85°C
TA = –40°C
TA = 25°C
TA = 60°C
TA = 85°C
MIN
NOM
MAX
VCC = 2.2 V
280
350
VCC = 3 V
420
560
VCC = 2.2 V
VCC = 3 V
32
45
55
70
VCC = 2.2 V
11
14
VCC = 3 V
17
22
UNIT
A
µA
VCC = 2.2
22V
VCC = 3 V
22V
VCC = 2.2
VCC = 3 V
1
1.5
1.1
1.5
2
3
3.5
6
1.8
2.2
1.6
1.9
2.5
3.5
4.2
7.5
0.1
0.5
0.1
0.5
0.7
1.1
1.7
3
0.1
0.5
0.1
0.5
0.8
1.2
1.9
3.5
µA
A
µA
A
µA
A
µA
A
A
µA
µA
A
NOTES: 1. Timer_B is clocked by f(DCOCLK) = 1 MHz. All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
2. All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
3. All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current. The current consumption in LPM3 is measured with
active Basic Timer1 and LCD (ACLK selected). The current consumption of the Comparator_A and the SVS module are specified
in the respective sections. The LPM3 currents are characterized with a KDS Daishinku DT–38 (6 pF) crystal and OSCCAP=1.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
27
SLAS344B – JANUARY 2002 – REVISED OCTOBER 2002
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
Current consumption of active mode versus system frequency, F-version:
I(AM) = I(AM) [1 MHz] × f(System) [MHz]
Current consumption of active mode versus supply voltage, F-version:
I(AM) = I(AM) [3 V] + 175 µA/V × (VCC – 3 V)
SCHMITT-trigger inputs – ports P1, P2, P3, P4, P5, and P6; RST/NMI; JTAG: TCK, TMS, TDI, TDO
PARAMETER
TEST CONDITIONS
VIT+
Positi e going input
Positive-going
inp t threshold voltage
oltage
VIT–
Negati e going inp
Negative-going
inputt threshold voltage
oltage
Vhys
h
Input voltage hysteresis (VIT
IT+ – VIT
IT–)
MIN
TYP
MAX
VCC = 2.2 V
VCC = 3 V
VCC = 2.2 V
1.1
1.5
1.5
1.9
0.4
0.9
VCC = 3 V
VCC = 2.2 V
0.9
1.3
0.3
1.1
VCC = 3 V
0.5
1
UNIT
V
V
V
outputs – ports P1, P2, P3, P4, P5, and P6
PARAMETER
VOH
VOL
High level output voltage
High-level
Low level output voltage
Low-level
TEST CONDITIONS
MIN
IOH(max) = –1.5 mA,
IOH(max) = –6 mA,
VCC = 2.2 V,
VCC = 2.2 V,
See Note 1
IOH(max) = –1.5 mA,
IOH(max) = –6 mA,
VCC = 3 V,
VCC = 3 V,
See Note 1
IOL(max) = 1.5 mA,
IOL(max) = 6 mA,
VCC = 2.2 V,
VCC = 2.2 V,
See Note 1
IOL(max) = 1.5 mA,
IOL(max) = 6 mA,
VCC = 3 V,
VCC = 3 V,
See Note 1
See Note 2
See Note 2
See Note 2
See Note 2
TYP
MAX
VCC–0.25
VCC–0.6
VCC
VCC
VCC–0.25
VCC–0.6
VCC
VCC
VSS
VSS
VSS+0.25
VSS+0.6
VSS
VSS
VSS+0.25
VSS+0.6
UNIT
V
V
NOTES: 1. The maximum total current, IOH(max) and IOL(max), for all outputs combined, should not exceed ±12 mA to satisfy the maximum
specified voltage drop.
2. The maximum total current, IOH(max) and IOL(max), for all outputs combined, should not exceed ±48 mA to satisfy the maximum
specified voltage drop.
28
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SLAS344B – JANUARY 2002 – REVISED OCTOBER 2002
typical characteristics
TYPICAL LOW-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
TYPICAL LOW-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
25
TA = 25°C
VCC = 2.2 V
P2.7
14
12
I OL – Typical Low-level Output Current – mA
I OL – Typical Low-level Output Current – mA
16
TA = 85°C
10
8
6
4
2
0
0.0
0.5
1.0
1.5
2.0
VCC = 3 V
P2.7
TA = 85°C
15
10
5
0
0.0
2.5
TA = 25°C
20
0.5
VOL – Low-Level Output Voltage – V
1.0
Figure 2
I OL – Typical High-level Output Current – mA
I OL – Typical High-level Output Current – mA
–6
–8
TA = 85°C
–12
TA = 25°C
0.5
3.0
3.5
0
VCC = 2.2 V
P2.7
–4
–14
0.0
2.5
TYPICAL HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
0
–10
2.0
Figure 3
TYPICAL HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
–2
1.5
VOL – Low-Level Output Voltage – V
1.0
1.5
2.0
2.5
VOH – High-Level Output Voltage – V
VCC = 3 V
P2.7
–5
–10
–15
–20
TA = 85°C
–25
–30
0.0
TA = 25°C
0.5
1.0
1.5
2.0
2.5
3.0
3.5
VOH – High-Level Output Voltage – V
Figure 5
Figure 4
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
29
SLAS344B – JANUARY 2002 – REVISED OCTOBER 2002
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
output frequency
PARAMETER
f(Px.y)
(1 ≤ x ≤ 6,
6 0 ≤ y ≤ 7)
CL = 20 pF,
F,
IL = ±1.5 mA
f(ACLK)
f(MCLK)
P1.1/TA0/MCLK,
P1
1/TA0/MCLK P1.5/TACLK/
P1 5/TACLK/
ACLK P1.4/TBCLK/SMCLK
P1 4/TBCLK/SMCLK
CL = 20 pF
F
TEST CONDITIONS
MIN
TYP
MAX
VCC = 2.2 V
VCC = 3 V
DC
5
DC
7.5
f(System)
UNIT
MH
MHz
MHz
f(SMCLK)
f(ACLK) = f(LFXT1) = f(XT1)
f(ACLK) = f(LFXT1) = f(LF)
P1.5/TACLK/ACLK,
CL = 20 pF
F
VCC = 2.2 V / 3 V
t(Xdc)
Duty cycle of output frequency
40%
f(ACLK) = f(LFXT1)
f(MCLK) = f(XT1)
P1.1/TA0/MCLK,
CL = 20 pF,
VCC = 2.2 V / 3 V
70%
50%
f(MCLK) = f(DCOCLK)
40%
60%
50%–
15 ns
50%
50%+
15 ns
40%
60%
50%–
15 ns
50%
50%+
15 ns
f(SMCLK) = f(XT2)
P1.4/TBCLK/SMCLK,
CL = 20 pF,
VCC = 2.2 V / 3 V
60%
30%
f(SMCLK) = f(DCOCLK)
inputs Px.x, TAx, TBx
PARAMETER
t(int)
External interrupt timing
g
TEST CONDITIONS
VCC
2.2 V/3 V
P t P1,
P1 P2:
P2 P1.x
P1 to
t P2.x,
P2 external
t
l trigger
ti
i
l
Port
signal
for the interrupt flag, (see Note 1)
TA0,
TA1, TA2 (see Note 2)
TA0 TA1
t(cap)
f(TAext)
f(TBext)
Timer_A,
_ , Timer_B
_ capture
timing
Timer_A, Timer_B clock
frequency externally applied
to pin
MIN
2.2 V
62
3V
50
2.2 V/3 V
1.5
2.2 V
62
3V
50
TB0, TB1, TB2, TB3, TB4, TB5, TB6
(see Note 3)
TACLK TBCLK
TACLK,
TBCLK, INCLK: t(H) = t(L)
TYP
MAX
1.5
UNIT
cycle
ns
cycle
ns
2.2 V
8
3V
10
MHz
f(TAint)
2.2 V
8
Timer_A, Timer_B clock
SMCLK or ACLK signal selected
MHz
f(BTAint) frequency
3V
10
NOTES: 1. The external signal sets the interrupt flag every time the minimum t(int) cycle and time parameters are met. It may be set even with
trigger signals shorter than t(int). Both the cycle and timing specifications must be met to ensure the flag is set. t(int) is measured in
MCLK cycles.
2. The external capture signal triggers the capture event every time the minimum t(cap) cycle and time parameters are met. A capture
may be triggered with capture signals even shorter than t(cap). Both the cycle and timing specifications must be met to ensure a
correct capture of the 16-bit timer value and to ensure the flag is set.
3. Seven capture/compare registers in ’x44x and three capture/compare registers in ’x43x.
wake-up LPM3
PARAMETER
TEST CONDITIONS
f = 1 MHz
td(LPM3)
Delay time
f = 2 MHz
POST OFFICE BOX 655303
TYP
MAX
UNIT
6
VCC = 2.2 V/3 V
f = 3 MHz
30
MIN
• DALLAS, TEXAS 75265
6
6
µs
SLAS344B – JANUARY 2002 – REVISED OCTOBER 2002
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
leakage current (see Notes 1 and 2)
PARAMETER
Ilkg(P1.x)
Ilkg(P6.x)
Leakage
current
TEST CONDITIONS
Port P1
Port 1: V(P1.x)
Port P6
Port 6: V(P6.x)
MIN
TYP
MAX
±50
VCC = 2
2.2
2 V/3 V
±50
UNIT
nA
NOTES: 1. The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted.
2. The port pin must be selected as input and there must be no optional pullup or pulldown resistor.
RAM
PARAMETER
TEST CONDITIONS
VRAMh
MIN
CPU halted (see Note 1)
TYP
MAX
1.6
UNIT
V
NOTE 1: This parameter defines the minimum supply voltage when the data in program memory RAM remain unchanged. No program execution
should take place during this supply voltage condition.
LCD
PARAMETER
V(33)
V(23)
V(13)
V(33) – V(03)
2.5
Voltage at P5.5/R13
R03 = VSS
Input leakage
g
P5.5/R13 = VCC/3
P5.6/R23 = 2 × VCC/3
Segment line
voltage
g
I(Sxx)
3 µA,
µA
(S ) = –3
2.5
No load at all
segment and
common lines
lines,
VCC = 3 V
VCC = 3 V
V(Sxx3)
POST OFFICE BOX 655303
TYP
MAX
UNIT
VCC + 0.2
[V(33)–V(03)] × 2/3 + V(03)
[V(33)–V(03)] × 1/3 + V(03)
VCC = 3 V
Voltage at R33 to R03
I(R23)
V(Sxx0)
V(Sxx1)
V(Sxx2)
MIN
Voltage at P5.6/R23
Analog voltage
oltage
I(R03)
I(R13)
TEST CONDITIONS
Voltage at P5.7/R33
V
VCC + 0.2
±20
±20
nA
±20
V(03)
V(13)
V(03) – 0.1
V(13) – 0.1
V(23)
V(33)
V(23) – 0.1
V(33) + 0.1
• DALLAS, TEXAS 75265
V
31
SLAS344B – JANUARY 2002 – REVISED OCTOBER 2002
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
Comparator_A (see Note 1)
PARAMETER
TEST CONDITIONS
I(CC)
CAON 1 CARSEL
CAON=1,
CARSEL=0,
0 CAREF
CAREF=0
0
I(Refladder/RefDiode)
CAON=1, CARSEL=0, CAREF=1/2/3,
No load at P2.3/CA0/TA1
P2 3/CA0/TA1 and
P2.4/CA1/TA2
V(Ref025)
Voltage @ 0.25 V
MAX
VCC = 2.2 V
VCC = 3 V
25
40
45
60
VCC = 2.2 V
30
50
VCC = 3 V
45
71
UNIT
µA
A
µA
A
PCA0=1, CARSEL=1, CAREF=1,
No load at P2.3/CA0 and P2.4/CA1
VCC = 2.2 V / 3 V
0.23
0.24
0.25
node
PCA0=1, CARSEL=1, CAREF=2,
No load at P2.3/CA0 and P2.4/CA1
VCC = 2.2V / 3 V
0.47
0.48
0.5
PCA0=1, CARSEL=1, CAREF=3,
No load at P2.3/CA0
P2 3/CA0 and P2.4/CA1;
P2 4/CA1;
TA = 85°C
VCC = 2.2 V
390
480
540
VCC = 3 V
400
490
550
Common-mode input
voltage range
CAON=1
VCC = 2.2 V / 3 V
0
VCC–1
Offset voltage
See Note 2
VCC = 2.2 V / 3 V
–30
30
mV
Input hysteresis
CAON = 1
VCC = 2.2 V / 3 V
VCC = 2.2 V
0
0.7
1.4
mV
160
210
300
80
150
240
1.4
1.9
3.4
0.9
1.5
2.6
130
210
300
80
150
240
1.4
1.9
3.4
CC
V
V(Ref050)
V
CC
CC
V(RefVT)
Vp–VS
Vhys
TYP
node
CC
Voltage @ 0.5 V
VIC
MIN
TA = 25
25°C,
C,
Overdrive 10 mV, without filter: CAF = 0
t(response LH)
TA = 25
25°C
C
Overdrive 10 mV, with filter: CAF = 1
TA = 25
25°C
C
Overdrive 10 mV, without filter: CAF = 0
t(response HL)
25°C,
TA = 25
C,
Overdrive 10 mV, with filter: CAF = 1
mV
VCC = 3 V
VCC = 2.2 V
VCC = 3 V
VCC = 2.2 V
VCC = 3 V
VCC = 2.2 V
V
ns
µss
ns
µss
VCC = 3 V
0.9
1.5
2.6
NOTES: 1. The leakage current for the Comparator_A terminals is identical to Ilkg(Px.x) specification.
2. The input offset voltage can be cancelled by using the CAEX bit to invert the Comparator_A inputs on successive measurements.
The two successive measurements are then summed together.
32
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SLAS344B – JANUARY 2002 – REVISED OCTOBER 2002
typical characteristics
REFERENCE VOLTAGE
vs
FREE-AIR TEMPERATURE
REFERENCE VOLTAGE
vs
FREE-AIR TEMPERATURE
650
650
VCC = 3 V
VCC = 2.2 V
VREF – Reference Voltage – V
VREF – Reference Voltage – V
600
Typical
550
500
450
400
–45
–25
–5
15
35
55
75
600
Typical
550
500
450
400
–45
95
TA – Free-Air Temperature – °C
–25
–5
15
35
55
75
95
TA – Free-Air Temperature – °C
Figure 6. V(RefVT) vs Temperature
Figure 7. V(RefVT) vs Temperature
0 V VCC
0
1
CAF
CAON
Low-Pass Filter
V+
V–
+
_
0
0
1
1
To Internal
Modules
CAOUT
Set CAIFG
Flag
τ ≈ 2 µs
Figure 8. Block Diagram of Comparator_A Module
VCAOUT
Overdrive
V–
400 mV
V+
t(response)
Figure 9. Overdrive Definition
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33
SLAS344B – JANUARY 2002 – REVISED OCTOBER 2002
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
POR/brownout reset (BOR) (see Note 1)
PARAMETER
TEST CONDITIONS
td(BOR)
VCC(start)
MIN
dVCC/dt ≤ 3 V/s (see Figure 10)
V(B_IT–)
Vhys(B_IT–)
Note 2))
MAX
UNIT
2000
µs
0.7 × V(B_IT–)
dVCC/dt ≤ 3 V/s (see Figure 10 through Figure 12)
dVCC/dt ≤ 3 V/s (see Figure 10)
Brownout (see
(
TYP
70
130
V
1.71
V
180
mV
Pulse length needed at RST/NMI pin to accepted reset internally,
t(reset)
2
µs
VCC = 2.2 V/3 V
NOTES: 1. The current consumption of the brownout module is already included in the ICC current consumption data. The voltage level V(B_IT–)
+ Vhys(B_IT–) is ≤ 1.8V.
2. During power up, the CPU begins code execution following a period of td(BOR) after VCC = V(B,IT–) + Vhys(B,IT–). The default FLL+
settings must not be changed until VCC ≥ VCC(min). See the MSP430x4xx Family User’s Guide (SLAU056) for more information on
the brownout/SVS circuit.
typical characteristics
VCC
Vhys(B_IT–)
V(B_IT–)
VCC(start)
1
0
t d(BOR)
Figure 10. POR/Brownout Reset (BOR) vs Supply Voltage
VCC
3V
2
VCC(min)– V
VCC = 3 V
Typical Conditions
1.5
1
VCC(min)
0.5
0
0.001
1
1000
1 ns
tpw – Pulse Width – µs
34
t pw
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1 ns
tpw – Pulse Width – µs
SLAS344B – JANUARY 2002 – REVISED OCTOBER 2002
Figure 11. VCC(min) Level With a Square Voltage Drop to Generate a POR/Brownout Signal
typical characteristics
VCC
VCC(min)– V
2
1.5
t pw
3V
VCC = 3 V
Typical Conditions
1
VCC(min)
0.5
0
0.001
tf = tr
1
1000
tf
tr
tpw – Pulse Width – µs
tpw – Pulse Width – µs
Figure 12. VCC(min) Level With a Triangle Voltage Drop to Generate a POR/Brownout Signal
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
SVS (supply voltage supervisor/monitor)
PARAMETER
TEST CONDITIONS
MIN
t(SVSR)
dVCC/dt > 30 V/ms (see Figure 13)
dVCC/dt ≤ 30 V/ms
5
td(SVSon)
tsettle
SVSon, switch from VLD=0 to VLD ≠ 0, VCC = 3 V
VLD ≠ 0‡
20
V(SVSstart)
VLD ≠ 0, VCC/dt ≤ 3 V/s (see Figure 13)
1.55
VLD = 1
VCC/dt ≤ 3 V/s (see Figure 13)
VLD = 2 .. 14
Vhys(B_IT–)
hys(B IT–)
VCC/dt ≤ 3 V/s (see Figure 13), external voltage applied
on A7
VCC/dt ≤ 3 V/s (see Figure 13)
V(SVS
IT )
(SVS_IT–)
VCC/dt ≤ 3 V/s (see Figure 13), external voltage applied
on A7
VLD = 15
70
120
V(SVS_IT–)
x 0.004
MAX
UNIT
150
µs
2000
µs
150
µs
12
µs
1.7
V
155
mV
V(SVS_IT–)
x 0.008
4.4
10.4
VLD = 1
1.8
1.9
2.05
VLD = 2
1.94
2.1
2.25
VLD = 3
2.05
2.2
2.37
VLD = 4
2.14
2.3
2.48
VLD = 5
2.24
2.4
2.6
VLD = 6
2.33
2.5
2.71
VLD = 7
2.46
2.65
2.86
VLD = 8
2.58
2.8
3
VLD = 9
2.69
2.9
3.13
VLD = 10
2.83
3.05
3.29
VLD = 11
2.94
3.2
VLD = 12
3.11
3.35
3.42
3.61†
VLD = 13
3.24
VLD = 14
3.43
3.5
3.7†
3.76†
3.99†
VLD = 15
1.1
1.2
1.3
10
15
ICC(SVS)
VLD ≠ 0, VCC = 2.2 V/3 V
(see Note 1)
† The recommended operating voltage range is limited to 3.6 V.
POST OFFICE BOX 655303
NOM
• DALLAS, TEXAS 75265
mV
V
µA
35
SLAS344B – JANUARY 2002 – REVISED OCTOBER 2002
‡ tsettle is the settling time that the comparator o/p needs to have a stable level after VLD is switched VLD ≠ 0 to a different VLD value somewhere
between 2 and 15. The overdrive is assumed to be > 50 mV.
NOTE 1: The current consumption of the SVS module is not included in the ICC current consumption data.
Software Sets VLD>0:
SVS is Active
VCC
V(SVS_IT–)
V(SVSstart)
Vhys(SVS_IT–)
Vhys(B_IT–)
V(B_IT–)
VCC(start)
Brownout
BrownOut
Region
Brownout
Region
1
0
SVSOut
1
td(BOR)
SVS Circuit is Active From VLD > to VCC < V(B_IT–)
0
td(SVSon)
Set POR
1
td(SVSR)
undefined
0
Figure 13. SVS Reset (SVSR) vs Supply Voltage
36
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
t d(BOR)
SLAS344B – JANUARY 2002 – REVISED OCTOBER 2002
VCC
3V
t pw
2
Rectangular Drop
VCC(min)– V
1.5
Triangular Drop
1
1 ns
1 ns
0.5
VCC
t pw
3V
0
1
10
100
1000
tpw – Pulse Width – µs
VCC(min)
tf = tr
tf
tr
t – Pulse Width – µs
Figure 14. VCC(min) With a Square Voltage Drop and a Triangle Voltage Drop to Generate an SVS Signal
POST OFFICE BOX 655303
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37
SLAS344B – JANUARY 2002 – REVISED OCTOBER 2002
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
DCO
PARAMETER
f(DCOCLK)
TEST CONDITIONS
N(DCO)=01E0h, FN_8=FN_4=FN_3=FN_2=0, D = 2, DCOPLUS= 0
f(DCO2)
FN 8 FN 4 FN 3 FN 2 0 , DCO+
FN_8=FN_4=FN_3=FN_2=0
DCO = 1
f(DCO27)
FN 8 FN 4 FN 3 FN 2 0 DCO+
FN_8=FN_4=FN_3=FN_2=0,
DCO = 1,
1 (see Note 1)
FN_8=FN_4=FN_3=0, FN_2=1
FN_2=1; DCO+ = 1
f(DCO2)
f(DCO27)
FN 8 FN 4 FN 3 0 FN
FN_8=FN_4=FN_3=0,
FN_2=1;
2 1 DCO
DCO+ = 1
1, (see Note 1)
f(DCO2)
FN 8 FN 4 0 FN
3 1
FN 2 x DCO+
DCO = 1
FN_8=FN_4=0,
FN_3=
1, FN_2=x;
f(DCO27)
FN 8 FN 4 0 FN
FN_8=FN_4=0,
FN_3=
3 1
1, FN
FN_2=x;,
2
DCO
DCO+ = 1
1, (see Note 1)
f(DCO2)
FN 8 0 FN_4=
FN_8=0,
FN 4 1,
1 FN_3=
FN 3 FN_2=x;
FN 2
DCO+
DCO = 1
f(DCO27)
FN 8 0 FN
FN_8=0,
FN_4=1,
4 1 FN
FN_3=
3 FN
FN_2=x;
2
DCO
DCO+ = 1
1, (see Note 1)
f(DCO2)
FN 8 1 FN
FN_8=1,
FN_4=FN_3=FN_2=x;
4 FN 3 FN 2
DCO
DCO+ = 1
f(DCO27)
FN 8 1 FN 4 FN 3 FN 2 x DCO = 1,
1 (see Note 1)
FN_8=1,FN_4=FN_3=FN_2=x,DCO+
S
f(NDCO)+1 = f(NDCO)
Dt
MIN
TYP
0.3
0.65
1.25
VCC = 3 V
VCC = 2.2 V
0.3
0.7
1.3
2.5
5.6
10.5
VCC = 3 V
VCC = 2.2 V
2.7
6.1
11.3
0.7
1.3
2.3
VCC = 3 V
VCC = 2.2 V
0.8
1.5
2.5
5.7
10.8
18
VCC = 3 V
VCC = 2.2 V
6.5
12.1
20
1.2
2
3
VCC = 3 V
VCC = 2.2 V
1.3
2.2
3.5
9
15.5
25
VCC = 3 V
VCC = 2.2 V
10.3
17.9
28.5
1.8
2.8
4.2
VCC = 3 V
VCC = 2.2 V
2.1
3.4
5.2
13.5
21.5
33
16
26.6
41
VCC = 2.2 V/3 V
VCC = 2.2 V
VCC = 3 V
VCC = 2.2 V
4.2
6.2
4.2
6.3
9.2
21
32
46
VCC = 3 V
2 < TAP ≤ 20
30
46
70
1.06
MH
MHz
MH
MHz
MH
MHz
MH
MHz
MHz
MH
MHz
MH
MHz
MH
MHz
MH
MHz
MHz
1.13
1.1
VCC = 2.2 V
VCC = 3 V
UNIT
MHz
2.8
Drift with VCC variation, N(DCO) = 01E0h,
FN_8=FN_4=FN_3=FN_2=0 D = 2, DCO+ = 0 (see Note 2)
DV
1
VCC = 3 V
VCC = 2.2 V
TAP > 20
Tem erature drift, N(DCO) = 01E0h, FN_8=FN_4=FN_3=FN_2=0
Temperature
D = 2, DCO+ = 0, (see Note 2)
MAX
1.17
–0.2
–0.3
–0.4
–0.2
–0.3
–0.4
0
5
15
%/_C
%/V
NOTES: 1. Do not exceed the maximum system frequency.
2. This parameter not production tested.
f
f
f
(DCO)
f
(DCO3V)
(DCO)
(DCO20 C)
1.0
1.0
0
1.8
2.4
3.0
3.6
VCC – V
–40
–20
0
20
40
60
Figure 15. DCO Frequency vs Supply Voltage VCC and vs Ambient Temperature
38
POST OFFICE BOX 655303
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85
TA – °C
SLAS344B – JANUARY 2002 – REVISED OCTOBER 2002
f(DCO)
Legend
Tolerance at Tap 27
DCO Frequency
Adjusted by Bits
29 to 2 5 in SCFI1 {N (DCO)}
Tolerance at Tap 2
Overlapping DCO Ranges:
uninterrupted frequency range
FN_2=0
FN_3=0
FN_4=0
FN_8=0
FN_2=1
FN_3=0
FN_4=0
FN_8=0
FN_2=x
FN_3=1
FN_4=0
FN_8=0
FN_2=x
FN_3=x
FN_4=1
FN_8=0
FN_2=x
FN_3=x
FN_4=x
FN_8=1
Figure 16. Five Overlapping DCO Ranges Controlled by FN_x Bits
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
crystal oscillator, LFXT1 oscillator (see Notes 1 and 2)
PARAMETER
C(XIN)
C(XOUT)
Integrated input
inp t capacitance
Integrated output
o tp t capacitance
TEST CONDITIONS
MIN
TYP
OSCCAP = 0, VCC = 2.2 V / 3 V
0
OSCCAP = 1, VCC = 2.2 V / 3 V
10
OSCCAP = 2, VCC = 2.2 V / 3 V
14
OSCCAP = 3, VCC = 2.2 V / 3 V
18
OSCCAP = 0, VCC = 2.2 V / 3 V
0
OSCCAP = 1, VCC = 2.2 V / 3 V
10
OSCCAP = 2, VCC = 2.2 V / 3 V
14
MAX
UNIT
pF
pF
OSCCAP = 3, VCC = 2.2 V / 3 V
18
NOTES: 1. The parasitic capacitance from the package and board may be estimated to be 2 pF. The effective load capacitor for the crystal is
(X(CIN) x X(COUT)) / (X(CIN) + X(COUT)). This is independent of XST_FLL.
2. To improve EMI on the low-power LFXT1 oscillator, particularly in the LF mode (32 kHz), the following guidelines should be observed.
– Keep as short of a trace as possible between the F43x/44x and the crystal.
– Design a good ground plane around the oscillator pins.
– Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
– Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
– Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins.
– If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins.
– Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other
documentation. This signal is no longer required for the serial programming adapter.
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39
SLAS344B – JANUARY 2002 – REVISED OCTOBER 2002
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
crystal oscillator, XT2 oscillator (see Note 1)
PARAMETER
XCIN
XCOUT
XINL
XINH
Integrated input capacitance
TEST CONDITIONS
Integrated output capacitance
VCC = 2.2 V/3 V
VCC = 2.2 V/3 V
Input levels at XIN
XIN, XOUT
VCC = 2.2
2 2 V/3 V
MIN
NOM
VSS
0.8 × VCC
MAX
UNIT
2
pF
2
pF
0.2 × VCC
V
VCC
V
NOTE 1: The oscillator needs capacitors at both terminals, with values specified by the crystal manufacturer.
USART0, USART1 (see Note 1)
PARAMETER
t(τ)
( )
USART0/1: deglitch time
TEST CONDITIONS
VCC = 2.2 V
VCC = 3 V
MIN
NOM
MAX
200
430
800
150
280
500
UNIT
ns
NOTE 1: The signal applied to the USART0/1 receive signal/terminal (URXD0/1) should meet the timing requirements of t(t) to ensure that the
URXS flip-flop is set. The URXS flip-flop is set with negative pulses meeting the minimum-timing condition of t(t). The operating
conditions to set the flag must be met independently from this timing constraint. The deglitch circuitry is active only on negative
transitions on the URXD0/1 line.
40
POST OFFICE BOX 655303
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SLAS344B – JANUARY 2002 – REVISED OCTOBER 2002
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
12-bit ADC, power supply and input range conditions (see Note 1)
PARAMETER
AVCC
Analog supply
voltage
TEST CONDITIONS
AVCC and DVCC are connected together
AVSS and DVSS are connected together
V(AVSS) = V(DVSS) = 0 V
0 mA ≤ I(Load) ≤ 0.5 mA
VCC(min)
CC( i )
0.5 mA ≤ I(Load) ≤ 1.5 mA
VO(REF+)
O(REF )
IL(VREF+)
L(VREF )
IL(VREF+)†
Positive built-in
reference voltage
output
REF2_5 V = 1 for 2.5-V
built-in reference
REF2
5 V = 0 for 1
5V
REF2_5
1.5-V
built-in reference
I(VREF+) ≤ I(VREF+_max)
Load current out of
VREF+ terminal
Load-current
regulation VREF+
terminal
I((VREF+)) = 500 µA ±100 µA
Analog input voltage ~0.75
0 75 V;
REF2_5 V = 0
I(VREF+) = 500 µA ± 100 µA
Analog input voltage ~1.25 V;
REF2_5 V = 1
VCC = 3 V
MIN
NOM
MAX
2.2
3.6
VREF+
VREF+ +
150 mV
VREF+
VREF+ +
350 mV
2.4
2.5
UNIT
V
2.6
V
VCC = 2.2 V/3 V
1.44
VCC = 2.2 V
VCC = 3 V
0.01
1.5
1.56
–0.5
–1
mA
VCC = 2.2 V
±2
VCC = 3 V
±2
VCC = 3 V
±2
LSB
20
ns
LSB
IL(VREF+)‡
Load current
regulation VREF+
terminal
I(VREF+) =100 µA → 900 µA,
VCC = 3 V, ax ~0.5 x VREF+
C(VREF+)
(VREF ) = 5 µF
Error of conversion result
≤ 1 LSB
Vref(VREF+)
Positive external
reference voltage
input
VeREF+ > VREF–/VeREF– (see Note 2)
1.4
V(AVCC)
V
Vref(VREF– /VeREF–)
Negative external
reference voltage
input
VeREF+ > VREF–/VeREF– (see Note 3)
0
1.2
V
† Not production tested, limits characterized
‡ Not production tested, limits verified by design
NOTES: 1. The leakage current is defined in the leakage current table with P6.x/Ax parameter.
2. The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced
accuracy requirements.
3. The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with reduced
accuracy requirements.
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12-bit ADC, power supply and input range conditions (continued)
PARAMETER
(VeREF+ –
VREF–/VeREF–)
Differential external
reference voltage
input
VI(P6.x/Ax)
Analog input voltage
range (see Note 2)
TEST CONDITIONS
VeREF+ > VREF–/VeREF– (see Note 1)
All P6.0/A0 to P6.7/A7/SVSin terminals. Analog
inputs selected in ADC12MCTLx register and
P6Sel.x=1
0 ≤ x ≤ 7; V(AVSS) ≤ VI(P6.x/Ax) ≤ V(AVCC)
f(ADC12CLK) = 5 MHz
VCC = 2.2 V
ADC12ON = 1, REFON = 0
SHT0=0, SHT1=0,
VCC = 3 V
ADC12DIV=0
Operating supply
current into AVCC
terminal
(see Note 3)
Operating supply
current into AVCC
terminal
(see Note 4)
IDD(ADC12)
IDD(REF+)
MIN
f(ADC12CLK) = 5 MHz
ADC12ON = 0,
REFON = 1, 2_5V = 1
NOM
MAX
UNIT
1.4
V(AVCC)
V
0
V(AVCC)
V
0.65
1.3
0.8
1.6
VCC = 3 V
0.5
0.8
VCC = 2.2 V
0.5
0.8
VCC = 3 V
0.5
0.8
mA
mA
f((ADC12CLK)) = 5 MHz
ADC12ON = 0,
0
REFON = 1, 2_5V = 0
O erating su
Operating
supply
ly
current (see Note 4)
NOTES: 1. The accuracy limits minimum external differential reference voltage. Lower differential reference voltage levels may be applied with
reduced accuracy requirements.
2. The analog input voltage range must be within the selected reference voltage range VR+ to VR– for valid conversion results
3. The internal reference supply current is not included in current consumption parameter IDD(ADC12).
4. The internal reference current is supplied via terminal AVCC. Consumption is independent of the ADC12ON control bit, unless a
conversion is active. The REFON bit enables to settle the built-in reference before starting an A/D conversion.
12-bit ADC, built-in reference (see Note 1)
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX
UNIT
IDD(VeREF+)
Static input current
(see Note 2)
0 V ≤ VeREF+ ≤ V(AVCC)
VCC = 2.2 V/3 V
±1
µA
IDD(VREF–/VeREF–)
Static input current
(see Note 2)
0 V ≤ VeREF– ≤ V(AVCC)
VCC = 2.2 V/3 V
±1
µA
C(VREF+)
Capacitance at pin
VREF+ (see Note 3)
REFON = 1,
0 mA ≤ I(VREF+) ≤ I(VREF_max)
VCC = 2.2 V/3 V
Ci‡
Input capacitance
(see Note 4)
Only one terminal can be selected
at one time, P6.x/Ax
VCC = 2.2 V
Zi‡
Input MUX ON
resistance (see Note 4)
0 V ≤ V(Ax) ≤ V(AVCC)
T(REF+)†
Temperature coefficient
of built-in reference
I(VREF+) is a constant in the range
of 0 mA ≤ I(VREF+) ≤ 1 mA
5
µF
10
40
pF
VCC = 3 V
2000
Ω
VCC = 2.2 V/3 V
±100 ppm/°C
† Not production tested, limits characterized
‡ Not production tested, limits verified by design
NOTES: 1. The voltage source on VeREF+ and VREF–/VeREF– needs to have low-dynamic impedance for 12-bit accuracy to allow the charge
to settle for this accuracy (See Figure 9 and Figure 10).
2. The external reference is used during conversion to charge and discharge the capacitance array. The dynamic impedance should
follow the recommendations on analog-source impedance to allow the charge to settle for 12-bit accuracy.
3. The internal buffer operational amplifier and the accuracy specifications require an external capacitor.
4. The input capacitance is also the dynamic load for an external reference during conversion. The dynamic impedance of the reference
supply should follow the recommendations on analog-source impedance to allow the charge to settle for 12-bit accuracy. All INL
and DNL tests uses two capacitors between pins VREF+ and AVSS and VREF–/VeREF– and AVSS: 10-µF tantalum and
100-nF ceramic.
42
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SLAS344B – JANUARY 2002 – REVISED OCTOBER 2002
timing requirements
12-bit ADC, timing parameters
PARAMETER
Settle time of internal
reference voltage (see
Figure 17 and Note 1)
ts(REF_ON)†
TEST CONDITIONS
MIN
I(VREF+) = 0.5 mA, C(VREF+) = 10 µF,
VREF+ = 1.5 V, V(AVCC) = 2.2 V
Error of conversion result ≤ ±2 LSB
2.2V/3V
f(ADC12OSC)
ADC12DIV=0 [f(ADC12CLK) =
f(ADC12OSC)]
VCC = 2.2 V/3
V
tc
AVCC(min)≤ V(AVCC)≤AVCC(max),
VCC = 2.2 V/3
C(VREF+) ≥ 5 µF, internal oscillator,
V
fOSC = 3.7 MHz to 6.3 MHz
AVCC(min) ≤ V(AVCC) ≤ AVCC(max),
External fADC12CLK from ACLK or MCLK or SMCLK:
ADC12SSEL ≠ 0
ts(ADC12ON)‡
t(Sample)
(S
l )‡
Settle time of the ADC
Sampling time
MAX
17
f(ADC12CLK)
Con ersion time
Conversion
NOM
AVCC(min) ≤ V(AVCC) ≤ AVCC(max) (see Note 2)
V(AVCC_min) < V(AVCC) <
VCC = 3 V
V(AVCC_max)
Ri(source) = 400 Ω, Zi = 1000 Ω,
Ci = 30 pF
τ = [Ri(source) x+ Zi] x Ci,
VCC = 2.2 V
(see Note 3)
5
UNIT
ms
MHz
37
3.7
63
6.3
MHz
2.06
3.51
µs
13×ADC12DIV×
1/fADC12CLK
µs
100
ns
1220
ns
1400
† Not production tested, limits characterized
‡ Not production tested, limits verified by design
NOTES: 1. The condition is that the error in a conversion started after ts(REF_ON) is less than ±0.5 LSB. The settling time depends on the external
capacitive load.
2. The condition is that the error in a conversion started after ts(ADC12ON) is less than ±0.5 LSB. The reference and input signal are
already settled.
3. Ten Tau (τ) are needed to get an error of less than ±0.5 LSB. t(Sample) = 10 x (Ri + Zi) x Ci + 800 ns
C(VREF+)
100 µF
t(REF_ON) ~ 0.66 x C(VREF+) [ms] With C(VREF+) in µF
10 µF
1 µF
0
1 ms
10 ms
100 ms
t(REF_ON)
Figure 17. Typical Settling Time of Internal Reference t(REF_ON) vs External Capacitor on VREF+
POST OFFICE BOX 655303
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43
SLAS344B – JANUARY 2002 – REVISED OCTOBER 2002
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
12-bit ADC, linearity parameters, VCC = 2.2 V/3 V
PARAMETER
TEST CONDITIONS
MIN
NOM
1.4 V ≤ (VeREF+ – VREF–/VeREF–) min ≤ 1.6 V
E(I)
Integral linearity
linearit error
ED
Differential linearity error
(VeREF+ – VREF–/VeREF–)min ≤ (VeREF+ – VREF–/VeREF–),
C(VREF+) = 10 µF (tantalum) and 100 nF (ceramic)
EO
Offset error
(VeREF+ – VREF–/VeREF–)min ≤ (VeREF+ – VREF–/VeREF–),
internal impedance of source Ri < 100 Ω,
C(VREF+) = 10 µF (tantalum) and 100 nF (ceramic)
EG
Gain error
E(T)
Total unadjusted error
MAX
±2
±1.7
LSB
±1
LSB
±2
±4
LSB
(VeREF+ – VREF–/VeREF–)min ≤ (VeREF+ – VREF–/VeREF–),
C(VREF+) = 10 µF (tantalum) and 100 nF (ceramic)
±1.1
±2
LSB
(VeREF+ – VREF–/VeREF–)min ≤ (VeREF+ – VREF–/VeREF–),
C(VREF+) = 10 µF (tantalum) and 100 nF (ceramic)
±2
±5
LSB
1.6 V < (VeREF+ – VREF–/VeREF–) min ≤ [V(AVCC)]
From
Power
Supply
DVCC1/DVCC2
+
–
10 µ F
DVSS1/DVSS2
100 nF
AVCC
+
–
10 µ F
Apply External Reference (VeREF+)
or Use Internal Reference (VREF+)
AVSS
10 µ F
MSP430F44x
VREF+ or VeREF+
100 nF
VREF–/VeREF–
+
–
10 µ F
MSP430F43x
100 nF
+
–
Apply
External
Reference
100 nF
Figure 18. Supply Voltage and Reference Voltage Design VREF–/VeREF– External Supply
44
UNIT
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SLAS344B – JANUARY 2002 – REVISED OCTOBER 2002
From
Power
Supply
DVCC1/DVCC2
+
–
10 µ F
DVSS1/DVSS2
100 nF
AVCC
+
–
10 µ F
Apply External Reference (VeREF+)
or Use Internal Reference (VREF+)
AVSS
MSP430F44x
100 nF
VREF+ or VeREF+
+
–
10 µ F
MSP430F43x
100 nF
Reference Is Internally
Switched to AVSS
VREF–/VeREF–
Figure 19. Supply Voltage and Reference Voltage Design VREF–/VeREF– = AVSS, Internally Connected
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
12-bit ADC, temperature sensor and built-in Vmid
PARAMETER
ICC(SENSOR)
Operating supply current
into AVCC terminal
(see Note 1)
TEST CONDITIONS
V(REFON) = 0, INCH = 0Ah,
ADC12ON = NA, TA = 25_C
MIN
NOM
MAX
VCC = 2.2 V
40
120
VCC = 3 V
60
160
UNIT
µA
A
V(SENSOR)†
ADC12ON = 1, INCH = 0Ah,
TA = 0°C
2 V/3 V
VCC = 2
2.2
986
986±5%
mV
TC(SENSOR)†
ADC12ON = 1
1, INCH = 0Ah
2 V/3 V
VCC = 2
2.2
3 55
3.55
3
55±3%
3.55±3%
mV/°C
ts(SENSOR)†
Sample time required if
channel 10 is selected
(see Note 2)
ADC12ON = 1, INCH = 0Ah,
Error of conversion result ≤ 1 LSB
VCC = 2
2.2
2 V/3 V
V(MID)
AVCC divider
di ider at channel 11
ADC12ON = 1, INCH = 0Bh,
V(MID) is ~0.5 x V(AVCC)
VCC = 2.2 V
VCC = 3 V
t(ON_VMID)
(ON VMID)
On-time
On
time if channel 11 is
selected (see Note 3)
ADC12ON = 1, INCH = 0Bh,
Error of conversion result ≤ 1 LSB
2 V/3 V
VCC = 2
2.2
µss
30
1.1
1.1±0.04
1.5
1.5±0.04
NA
V
ns
† Not production tested, limits characterized
‡ Not production tested, limits verified by design
NOTES: 1. The sensor current ISENSOR is consumed if (ADC12ON = 1 and V(REFON) = 1), or (ADC12ON=1 AND INCH=0Ah and sample signal
is high). Therefore, it includes the constant current through the sensor and the reference.
2. The typical equivalent impedance of the sensor is 51 kΩ. The sample time needed is the sensor-on time t(SENSOR_ON)
3. The on-time t(ON_VMID) is identical to sampling time t(Sample); no additional on time is needed.
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SLAS344B – JANUARY 2002 – REVISED OCTOBER 2002
JTAG, program memory and fuse
PARAMETER
f(TCK)
JTAG/Testt
JTAG/T
(see Note 4)
JTAG/fuse
(see Note 2)
I(FB)
I(DD-PGM)
I(DD-Erase)
t(retention)
( t ti )
NOTES: 1.
2.
3.
4.
46
MIN
TCK freq
frequency
enc
VCC = 2.2 V
VCC = 3 V
Pull-up resistors on TMS, TCK, TDI (see Note 1)
VCC = 2.2 V/3 V
Supply voltage during fuse blow condition,
TA = 25°C
VCC(FB)
V(FB)
TEST CONDITIONS
NOM
DC
5
DC
10
25
60
Fuse-blow voltage, F versions (see Note 3)
F versions only
F-versions
Current from DVCC when erase is active
Write/erase cycles
104
Data retention TJ = 25°C
100
MH
MHz
kΩ
7
100
VCC = 2.7 V/3.6 V
VCC = 2.7 V/3.6 V
UNIT
V
6
Supply current on TDI with fuse blown
Current from DVCC when programming is active
90
2.5
Time to blow the fuse
F-versions
F
versions only
(see Note 4)
MAX
mA
1
ms
3
5
mA
3
5
10
5
mA
cycles
years
TMS, TDI, and TCK pull-up resistors are implemented in all F versions.
Once the fuse is blown, no further access to the MSP430 JTAG/test feature is possible. The JTAG block is switched to bypass mode.
The supply voltage to blow the fuse is applied to the TDI pin.
f(TCK) may be restricted to meet the timing requirements of the module selected. Duration of the program/erase cycle is determined
by f(FTG) applied to the flash timing controller. It can be calculated as follows:
t(word write) = 35
1/f(FTG)
t(block write, byte 0) = 30
1/f(FTG)
t(block write, byte 1 – 63) = 20
1/f(FTG)
t(block write, sequence end) = 6 1/f (FTG)
t(mass erase) = 5297
1/f(FTG)
t(segment erase) = 4819
1/f(FTG)
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SLAS344B – JANUARY 2002 – REVISED OCTOBER 2002
input/output schematic
Port P1, P1.0 to P1.5, input/output with Schmitt-trigger
Pad Logic
CAPD.x
P1SEL.x
0: Input
1: Output
0
P1DIR.x
Direction Control
From Module
P1OUT.x
1
0
P1.x
1
Module X OUT
Bus
Keeper
P1.0/TA0
P1.1/TA0/MCLK
P1.2/TA1
P1.3/TBOutH/SVSOut
P1.4/TBCLK/SMCLK
P1.5/TACLK/ACLK
P1IN.x
EN
D
Module X IN
P1IE.x
P1IRQ.x
P1IFG.x
Q
EN
Set
Interrupt
Edge
Select
P1IES.x
Note: 0 < x< 5
Note: Port function is active if CAPD.x = 0
Direction
PnOUT.x
Control
From Module
P1SEL.x
Module X
OUT
PnSel.x
PnDIR.x
P1Sel.0
P1DIR.0
P1DIR.0
P1OUT.0
Out0 sig.
P1Sel.1
P1DIR.1
P1DIR.1
P1OUT.1
MCLK
P1Sel.2
P1DIR.2
P1DIR.2
P1OUT.2
Out1 sig.
P1Sel.3
P1DIR.3
P1DIR.3
P1OUT.3
SVSOut
†
†
PnIN.x
Module X IN
P1IN.0
CCI0A
P1IN.1
CCI0B
†
†
†
PnIE.x
PnIFG.x
PnIES.x
P1IE.0
P1IFG.0
P1IES.0
P1IE.1
P1IFG.1
P1IES.1
P1IE.2
P1IFG.2
P1IES.2
P1IN.2
CCI1A
P1IN.3
TBOutH
‡
P1IE.3
P1IFG.3
P1IES.3
‡
TBCLK
P1IE.4
P1IFG.4
P1IES.4
P1IE.5
P1IFG.5
P1IES.5
P1Sel.4
P1DIR.4
P1DIR.4
P1OUT.4
SMCLK
P1IN.4
P1Sel.5
P1DIR.5
P1DIR.5
P1OUT.5
ACLK
P1IN.5
TACLK
†
† Timer_A
‡ Timer_B
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
47
SLAS344B – JANUARY 2002 – REVISED OCTOBER 2002
input/output schematic (continued)
Port P1, P1.6, P1.7, input/output with Schmitt-trigger
Pad Logic
Note: Port function is active if CAPD.6 = 0
CAPD.6
P1SEL.6
0: Input
1: Output
0
P1DIR.6
P1.6/
CA0
1
P1DIR.6
0
P1OUT.6
1
DVSS
Bus
Keeper
P1IN.6
EN
unused
D
P1IE.7
P1IRQ.07
EN
Interrupt
Edge
Select
Q
P1IFG.7
Set
P1IES.x
P1SEL.x
Comparator_A
P2CA
AVcc
CAREF
CAEX
CA0
CAF
CCI1B
+
to Timer_Ax
–
CA1
2
CAREF
Reference Block
Pad Logic
CAPD.7
Note: Port function is active if CAPD.7 = 0
P1SEL.7
0: input
1: output
0
P1DIR.7
P1.7/
CA1
1
P1DIR.7
0
P1OUT.7
1
DVSS
Bus
keeper
P1IN.7
EN
unused
D
P1IE.7
P1IRQ.07
EN
Q
P1IFG.7
Set
Interrupt
Edge
Select
P1IES.7
48
P1SEL.7
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SLAS344B – JANUARY 2002 – REVISED OCTOBER 2002
input/output schematic (continued)
port P2, P2.0, P2.4 to P2.5, input/output with Schmitt-trigger
Pad Logic
DVSS
DVSS
P2SEL.x
0: Input
1: Output
0
P2DIR.x
Direction Control
From Module
1
0
1
P2OUT.x
Module X OUT
Bus
Keeper
P2.0/TA2
P2.4/UTXD0
P2IN.x
P2.5/URXD0
EN
Module X IN
D
P2IE.x
P2IRQ.x
P2IFG.x
EN
Interrupt
Edge
Select
Q
Set
P2IES.x
Note:
P2SEL.x
x {0,4,5}
PnSel.x
PnDIR.x
Dir. Control
from module
PnOUT.x
Module X
OUT
PnIN.x
Module X IN
PnIE.x
PnIFG.x
P2Sel.0
P2DIR.0
P2DIR.0
P2OUT.0
Out2 sig. †
P2IN.0
CCI2A †
P2IE.0
P2IFG.0
P2IES.0
P2IN.4
unused
P2IE.4
P2IFG.4
P2IES.4
P2IN.5
URXD0 ‡
P2IE.5
P2IFG.5
P2IES.5
P2Sel.4
P2DIR.4
DVCC
P2OUT.4
UTXD0
P2Sel.5
P2DIR.5
DVSS
P2OUT.5
DVSS
‡
PnIES.x
†Timer_A
‡USART0
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
49
SLAS344B – JANUARY 2002 – REVISED OCTOBER 2002
input/output schematic (continued)
port P2, P2.1 to P2.3, input/output with Schmitt-trigger
Pad Logic
DVSS
DVSS
Module IN of pin
P1.3/TBOutH/SVSOut
P1DIR.3
P1SEL.3
P2SEL.x
0: Input
1: Output
0
P2DIR.x
Direction Control
From Module
P2OUT.x
1
0
1
Module X OUT
Bus
Keeper
P2.1/TB0
P2.2/TB1
P2IN.x
P2.3/TB2
EN
D
Module X IN
P2IE.x
P2IRQ.x
Q
P2IFG.x
EN
Interrupt
Edge
Select
Set
P2IES.x
Note:
P2SEL.x
1<x <3
PnSel.x
PnDIR.x
Dir. Control
from module
PnOUT.x
Module X
OUT
PnIN.x
P2Sel.1
P2DIR.1
P2DIR.1
P2OUT.1
Out0 sig. †
P2IN.1
Module X IN
PnIE.x
PnIFG.x
CCI0A †
CCI0B
P2IE.1
P2IFG.1
P2IES.1
P2IE.2
P2IFG.2
P2IES.2
P2IE.3
P2IFG.3
P2IES.3
P2Sel.2
P2DIR.2
P2DIR.2
P2OUT.2
Out1 sig. †
P2IN.2
CCI1A †
CCI1B
P2Sel.3
P2DIR.3
P2DIR.3
P2OUT.3
Out2 sig. †
P2IN.3
CCI2A †
CCI2B
†Timer_B
50
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
PnIES.x
SLAS344B – JANUARY 2002 – REVISED OCTOBER 2002
input/output schematic (continued)
port P2, P2.6 to P2.7, input/output with Schmitt-trigger
0: Port active
1: Segment xx function active
Pad Logic
Port/LCD‡
Segment xx‡
P2SEL.x
0: Input
1: Output
0
P2DIR.x
Direction Control
From Module
1
0
P2OUT.x
1
Module X OUT
Bus
Keeper
P2.6/CAOUT/S19‡
P2.7/ADC12CLK/S18‡
P2IN.x
‡Segment function
only available with
MSP430x43xIPN
EN
D
Module X IN
P2IE.x
P2IRQ.x
P2IFG.x
EN
Q
Set
Interrupt
Edge
Select
P2IES.x
Note:
P2SEL.x
6<x <7
PnSel.x
PnDIR.x
Dir. Control
from module
PnOUT.x
Module X
OUT
PnIN.x
Module X IN
PnIE.x
PnIFG.x
PnIES.x
‡
Port/LCD
P2Sel.6
P2DIR.6
P2DIR.6
P2OUT.6
CAOUT †
P2IN.6
unused
P2IE.6
P2IFG.6
P2IES.6
0: LCDM<40h ‡
P2Sel.7
P2DIR.7
P2DIR.7
P2OUT.7
ADC12CLK§
P2IN.7
unused
P2IE.7
P2IFG.7
P2IES.7
0: LCDM<40h
‡
† Comparator_A
‡Port/LCD signal is 1 only with MSP430xIPN and LCDM ≥40h.
§ ADC12
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
51
SLAS344B – JANUARY 2002 – REVISED OCTOBER 2002
input/output schematic (continued)
port P3, P3.0 to P3.3, input/output with Schmitt-trigger
MSP430x43xIPN (80-Pin) Only
0: Port active
1: Segment xx function active
LCDM.5
LCDM.6
LCDM.7
Pad Logic
Segment xx
x43xIPZ and x44xIPZ have not segment
Function on Port P3: Both lines are low.
P3SEL.x
0: Input
1: Output
0
P3DIR.x
Direction Control
From Module
1
0
1
P3OUT.x
Module X OUT
Bus
Keeper
P3.0/STEO/S31†
P3.1/SIMO0/S30†
P3.2/SOMI0/S29†
P3.3/UCLK0/S28†
P3IN.x
EN
Module X IN
Note:
D
0<x<3
Direction
PnOUT.x
Control
From Module
Module X
OUT
PnIN.x
Module X IN
DVSS
P3IN.0
STE0(in)
DCM_SIMO0 P3OUT.1
SIMO0(out)
P3IN.1
SIMO0(in)
P3DIR.2
DCM_SOMI0 P3OUT.2
SOMIO(out)
P3IN.2
SOMI0(in)
P3DIR.3
DCM_UCLK0 P3OUT.3
UCLK0(out)
P3IN.3
UCLK0(in)
PnSel.x
PnDIR.x
P3Sel.0
P3DIR.0
P3Sel.1
P3DIR.1
P3Sel.2
P3Sel.3
DVSS
P3OUT.0
† S24 to S31 shared with port function only at MSP430x43xIPN (80-pin QFP)
Direction Control for SIMO0 and UCLK0
SYNC
MM
52
DCM_SIMO0
DCM_UCLK0
Direction Control for SOMI0
SYNC
MM
STC
STC
STE
STE
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
DCM_SOMI0
SLAS344B – JANUARY 2002 – REVISED OCTOBER 2002
port P3, P3.4 to P3.7, input/output with Schmitt-trigger
LCDM.7† or DVSS‡
0: Port active
1: Segment xx function active
Pad Logic
Segmentxx† or DVSS‡
TBoutHiZ# or DVSS§
P3SEL.x
0: Input
1: Output
0
P3DIR.x
Direction Control
From Module
P3OUT.x
1
0
1
Module XOUT
Bus
Keeper
’x43xIPN
’x43xIPZ
80-Pin
100-Pin
’x44x
P3IN.x
P3.4/S27
P3.5/S26
P3.6/S25
P3.7/S24
EN
Module X IN
Note:
D
P3.4
P3.5
P3.6
P3.7
P3.4/TB3
P3.5/TB4
P3.6/TB5
P3.7/TB6
4<x <7
Module IN of pin
P1.3/TBOutH/SVSOut
P1DIR.3
P1SEL.3
P3DIR.x
P3SEL.x
TBoutHiZ
PnSel.x
PnDIR.x
Dir. Control
from module
PnOUT.x
P3Sel.4
P3DIR.4
P3DIR.4
P3OUT.4
P3Sel.5
P3DIR.5
P3DIR.5
P3OUT.5
P3Sel.6
P3DIR.6
P3DIR.6
P3OUT.6
P3Sel.7
P3DIR.7
P3DIR.7
P3OUT.7
Module X
OUT
DVSS
OUT3
DVSS
OUT4
DVSS
OUT5
DVSS
OUT6
§
#
§
#
§
#
§
#
PnIN.x
P3IN.4
P3IN.5
P3IN.6
P3IN.7
Module X IN
unused §
CCI3A/B#
unused §
CCI4A/B#
unused §
CCI5A/B#
unused §
CCI6A/B#
† MSP430x43xIPN
‡ MSP430x43xIPZ, MSP430x44xIPZ
§ MSP430x43x
# MSP430x44x
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
53
SLAS344B – JANUARY 2002 – REVISED OCTOBER 2002
input/output schematic (continued)
port P4, P4.0 to P4.7, input/output with Schmitt-trigger
0: Port active
1: Segment xx function active
Pad Logic
Port/LCD§
Segment xx
P4SEL.x
0: Input
1: Output
0
P4DIR.x
Direction Control
From Module
1
0
1
P4OUT.x
Module X OUT
Bus
Keeper
x43xIPN
80-Pin
QFP:
x43xIPZ
100-Pin
QFP:
P4.7/S2
P4.6/S3
P4.5/S4
P4.3/S6
P4.4/S5
P4.2/S7
P4.1/S8
P4.0/S9
P4.7/S34
P4.6/S35
P4.5/S36
P4.3/S37
P4.4/S38
P4.2/S39
P4.0
P4.1
x44x
P4IN.x
EN
Module X IN
Note:
D
0<x<7
PnSel.x
PnDIR.x
Direction
Control
From Module
PnOUT.x
P4Sel.0
P4DIR.0
P4DIR.0†
DVCC‡
P4OUT.0
P4Sel.1
P4DIR.1
P4DIR.1†
DVSS‡
P4Sel.2
P4DIR.2
P4Sel.3
P4DIR.3
P4Sel.4
P4DIR.4
P4Sel.5
P4DIR.5
P4Sel.6
P4DIR.4
P4Sel.7
P4DIR.5
Module X
PnIN.x
Module X IN
DVSS†
UTXD1‡
P4IN.0
unused
P4OUT.1
DVSS
P4IN.1
unused†
URXD1‡
P4DIR.2†
DVSS‡
P4OUT.2
DVSS
P4IN.2
unused†
STE1(in)‡
P4DIR3.†
DCM_SIMO1‡
P4OUT.3
DVSS†
SIMO1(out)‡
P4IN.3
unused†
SIMO1(in)‡
P4OUT.4
DVSS†
SOMI1(out)‡
P4IN.4
unused
SOMI1(in)‡
P4OUT.5
DVSS†
UCLK1(out)‡
P4IN.5
unused†
UCLK1(in)‡
P4DIR.6
P4OUT.6
DVSS
P4IN.6
unused
P4DIR.7
P4OUT.7
DVSS
P4IN.7
unused
P4DIR4.†
DCM_SOMI1‡
P4DIR5.†
DCM_UCLK1‡
OUT
† Signal at MSP430x43x
‡ Signal at MSP430x44x
§
DEVICE
54
PORT BITS
PORT FUNCTION
LCD SEG. FUNCTION
x43xIPN 80-pin QFP
P4.0 . . .P4.7
LCDM < 020h
LCDM ≥ 020h
x43xIPZ 100-pin QFP
P4.2 . . .P4.5
LCDM < 0E0h
LCDM ≥ 0E0h
x44xIPZ 100-pin QFP
P4.6 . . .P4.7
LCDM < 0C0h
LCDM ≥ 0C0h
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
P4.7/S34
P4.6/S35
P4.5/UCLK1/S36
P4.4/SMO1/S37
P4.3/SIMO1/S38
P4.2/STE1/S39
P4.1/URXD1
P4.0/UTXD1
SLAS344B – JANUARY 2002 – REVISED OCTOBER 2002
input/output schematic (continued)
Direction Control for SIMO1 and UCLK1
Direction Control for SOMI1
SYNC
SYNC
MM
DCM_SIMO1
DCM_UCLK1
MM
DCM_SOMI1
STC
STC
STE
STE
port P5, P5.0 to P5.1, input/output with Schmitt-trigger
0: Port active
1: Segment function active
Port/LCD
Segment Pad Logic
Segment
Port Pad Logic
P5SEL.x
0
P5DIR.x
Direction Control
From Module
0: Input
1
1: Output
0
P5OUT.x
1
Module X OUT
Bus
Keeper
P5.0/S1
P5.1/S0
P5IN.x
EN
Module X IN
Note:
D
0 <x <1
PnSel.x
PnDIR.x
P5Sel.0
P5DIR.0
P5Sel.1
P5DIR.1
PnOUT.x
Module X
OUT
PnIN.x
Module X IN
Segment
P5DIR.0
P5OUT.0
DVSS
P5IN.0
unused
S1
0: LCDM<20h
P5DIR.1
P5OUT.1
DVSS
P5IN.1
unused
S0
0: LCDM<20h
Dir. Control
from module
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Port/LCD
55
SLAS344B – JANUARY 2002 – REVISED OCTOBER 2002
input/output schematic (continued)
port P5, P5.2 to P5.4, input/output with Schmitt-trigger
0: Port active
1: LCD function active
Port/LCD
LCD signal
Pad Logic
P5SEL.x
0: Input
1: Output
0
P5DIR.x
Direction Control
From Module
1
0
1
P5OUT.x
Module X OUT
Bus
Keeper
P5.2/COM1
P5.3/COM2
P5.4/COM3
P5IN.x
EN
Module X IN
D
Note:
56
2<x <4
PnSel.x
PnDIR.x
Dir. Control
from module
PnOUT.x
Module X
OUT
PnIN.x
Module X IN
P5Sel.2
P5DIR.2
P5DIR.2
P5OUT.2
DVSS
P5IN.2
unused
COM1
P5SEL.2
P5Sel.3
P5DIR.3
P5DIR.3
P5OUT.3
DVSS
P5IN.3
unused
COM2
P5SEL.3
P5Sel.4
P5DIR.4
P5DIR.4
P5OUT.4
DVSS
P5IN.4
unused
COM3
P5SEL.4
POST OFFICE BOX 655303
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LCD signal
Port/LCD
SLAS344B – JANUARY 2002 – REVISED OCTOBER 2002
input/output schematic (continued)
port P5, P5.5 to P5.7, input/output with Schmitt-trigger
0: Port active
1: LCD function active
Port/LCD
LCD signal
Pad Logic
P5SEL.x
0: Input
1: Output
0
P5DIR.x
Direction Control
From Module
1
0
1
P5OUT.x
Module X OUT
Bus
Keeper
P5.5/R13
P5.6/R23
P5.7/R33
P5IN.x
EN
Module X IN
D
Note:
5<x <7
PnSel.x
PnDIR.x
Dir. Control
from module
PnOUT.x
Module X
OUT
PnIN.x
Module X IN
P5Sel.5
P5DIR.5
P5DIR.5
P5OUT.5
DVSS
P5IN.5
unused
R13
P5SEL.5
P5Sel.6
P5DIR.6
P5DIR.6
P5OUT.6
DVSS
P5IN.6
unused
R23
P5SEL.6
P5Sel.7
P5DIR.7
P5DIR.7
P5OUT.7
DVSS
P5IN.7
unused
R33
P5SEL.7
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LCD signal
Port/LCD
57
SLAS344B – JANUARY 2002 – REVISED OCTOBER 2002
input/output schematic (continued)
port P6, P6.0 to P6.6, input/output with Schmitt-trigger
P6SEL.x
0
P6DIR.x
Direction Control
From Module
1
0: Input
1: Output
Pad Logic
P6.0/A0 ..
P6.6/A6
0
P6OUT.x
Module X OUT
1
Bus Keeper
P6IN.x
EN
Module X IN
D
From ADC
To ADC
x: Bit Identifier, 0 to 6 for Port P6
NOTE: Analog signals applied to digital gates can cause current flow from the positive to the negative terminal. The throughput current flows if
the analog signal is in the range of transitions 0→1 or 1←0. The value of the throughput current depends on the driving capability of the
gate. For MSP430, it is approximately 100 µA.
Use P6SEL.x=1 to prevent throughput current. P6SEL.x should be set, even if the signal at the pin is not being used by the ADC12.
PnSel.x
PnDIR.x
Dir. Control
From Module
PnOUT.x
Module X OUT
PnIN.x
Module X IN
P6Sel.0
P6DIR.0
P6DIR.0
P6OUT.0
DVSS
P6IN.0
unused
P6Sel.1
P6DIR.1
P6DIR.1
P6OUT.1
DVSS
P6IN.1
unused
P6Sel.2
P6DIR.2
P6DIR.2
P6OUT.2
DVSS
P6IN.2
unused
P6Sel.3
P6DIR.3
P6DIR.3
P6OUT.3
DVSS
P6IN.3
unused
P6Sel.4
P6DIR.4
P6DIR.4
P6OUT.4
DVSS
P6IN.4
unused
P6Sel.5
P6DIR.5
P6DIR.5
P6OUT.5
DVSS
P6IN.5
unused
P6Sel.6
P6DIR.6
P6DIR.6
P6OUT.6
DVSS
P6IN.6
unused
NOTE: The signal at pins P6.x/Ax is used by the 12-bit ADC module.
58
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SLAS344B – JANUARY 2002 – REVISED OCTOBER 2002
input/output schematic (continued)
port P6, P6.7, input/output with Schmitt-trigger
P6SEL.x
VLP(SVS)=15
0
P6DIR.x
Direction Control
From Module
1
0: Input
1: Output
Pad Logic
P6.7/A7/SVSin
0
P6OUT.x
Module X OUT
1
Bus Keeper
P6IN.x
EN
Module X IN
D
From ADC
To ADC
To Brownout/SVS Module
x: Bit Identifier, 7 for Port P6
NOTE: Analog signals applied to digital gates can cause current flow from the positive to the negative terminal. The throughput current flows if
the analog signal is in the range of transitions 0→1 or 1←0. The value of the throughput current depends on the driving capability of the
gate. For MSP430, it is approximately 100 µA.
Use P6SEL.x=1 to prevent throughput current. P6SEL.x should be set, even if the signal at the pin is not being used by the ADC12.
PnSel.x
PnDIR.x
Dir. Control
From Module
PnOUT.x
Module X OUT
PnIN.x
Module X IN
P6Sel.7
P6DIR.7
P6DIR.7
P6OUT.7
DVSS
P6IN.7
unused
NOTE: The signal at pins P6.x/Ax is used by the 12-bit ADC module.
The signal at pin P6.7/A7/SVSin is also connected to the input multiplexer in the module brownout/supply voltage supervisor.
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59
SLAS344B – JANUARY 2002 – REVISED OCTOBER 2002
input/output schematic (continued)
JTAG pins TMS, TCK, TDI, TDO/TDI, input/output with Schmitt-trigger or output
TDO
Controlled by JTAG
Controlled by JTAG
TDO/TDI
JTAG
Controlled
by JTAG
DVCC
TDI
Burn and Test
Fuse
TDI
Test
and
Emulation
DVCC
TMS
Module
TMS
DVCC
TCK
TCK
RST/NMI
Tau ~ 50 ns
Brownout
TCK
60
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G
D
U
S
G
D
U
S
SLAS344B – JANUARY 2002 – REVISED OCTOBER 2002
JTAG fuse check mode
MSP430 devices that have the fuse on the TDI terminal have a fuse check mode that tests the continuity of the
fuse the first time the JTAG port is accessed after a power-on reset (POR). When activated, a fuse check current
(I(TF)) of 1 mA at 3 V can flow from the TDI pin to ground if the fuse is not burned. Care must be taken to avoid
accidentally activating the fuse check mode and increasing overall system power consumption.
Activation of the fuse check mode occurs with the first negative edge on the TMS pin after power up or if the
TMS is being held low during power up. The second positive edge on the TMS pin deactivates the fuse check
mode. After deactivation, the fuse check mode remains inactive until another POR occurs. After each POR the
fuse check mode has the potential to be activated.
The fuse check current only flows when the fuse check mode is active and the TMS pin is in a low state (see
Figure 20). Therefore, the additional current flow can be prevented by holding the TMS pin high (default
condition). The JTAG pins are terminated internally and therefore do not require external termination.
Time TMS Goes Low After POR
TMS
I(TF)
I(TDI)
Figure 20. Fuse Check Mode Current MSP430x43x, MSP430x44x
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61
SLAS344B – JANUARY 2002 – REVISED OCTOBER 2002
MECHANICAL DATA
PN (S-PQFP-G80)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
0,08 M
41
60
61
40
80
21
0,13 NOM
1
20
Gage Plane
9,50 TYP
12,20
SQ
11,80
14,20
SQ
13,80
0,25
0°–ā7°
0,05 MIN
0,75
0,45
1,45
1,35
Seating Plane
0,08
1,60 MAX
4040135/B 11/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
62
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SLAS344B – JANUARY 2002 – REVISED OCTOBER 2002
MECHANICAL DATA
PZ (S-PQFP-G100)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
75
0,08 M
51
76
50
100
26
1
0,13 NOM
25
12,00 TYP
Gage Plane
14,20
SQ
13,80
16,20
SQ
15,80
0,05 MIN
1,45
1,35
0,25
0°–ā7°
0,75
0,45
Seating Plane
0,08
1,60 MAX
4040149/B 11/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
POST OFFICE BOX 655303
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63
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