IRF IRFB4620PBF High efficiency synchronous rectification in smp Datasheet

PD -96172
IRFB4620PbF
HEXFET® Power MOSFET
Applications
l High Efficiency Synchronous Rectification in SMPS
l Uninterruptible Power Supply
l High Speed Power Switching
l Hard Switched and High Frequency Circuits
D
G
S
VDSS
RDS(on) typ.
max.
ID
200V
60m:
72.5m:
25A
Benefits
l Improved Gate, Avalanche and Dynamic dV/dt
Ruggedness
l Fully Characterized Capacitance and Avalanche
SOA
l Enhanced body diode dV/dt and dI/dt Capability
l Lead-Free
TO-220AB
IRFB4620PbF
G
D
S
Gate
Drain
Source
Absolute Maximum Ratings
Symbol
ID @ TC = 25°C
ID @ TC = 100°C
IDM
PD @TC = 25°C
VGS
Parameter
Max.
Continuous Drain Current, VGS @ 10V
Continuous Drain Current, VGS @ 10V
c
Pulsed Drain Current
Maximum Power Dissipation
Linear Derating Factor
Gate-to-Source Voltage
Peak Diode Recovery
Operating Junction and
Storage Temperature Range
Soldering Temperature, for 10 seconds
(1.6mm from case)
Mounting torque, 6-32 or M3 screw
e
dv/dt
TJ
TSTG
Avalanche Characteristics
EAS (Thermally limited)
IAR
EAR
Single Pulse Avalanche Energy
Avalanche Current
Repetitive Avalanche Energy
c
d
Units
25
18
100
144
0.96
± 20
54
-55 to + 175
A
W
W/°C
V
V/ns
°C
300
x
x
10lb in (1.1N m)
113
See Fig. 14, 15, 22a, 22b,
f
mJ
A
mJ
Thermal Resistance
Symbol
RθJC
RθCS
RθJA
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Parameter
j
Junction-to-Case
Case-to-Sink, Flat, Greased Surface
Junction-to-Ambient (PCB Mount)
ij
Typ.
Max.
Units
–––
0.50
–––
1.045
°C/W
62
1
09/05/08
IRFB4620PbF
Static @ TJ = 25°C (unless otherwise specified)
Symbol
Parameter
V(BR)DSS
∆V(BR)DSS/∆TJ
RDS(on)
VGS(th)
IDSS
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
Drain-to-Source Leakage Current
IGSS
RG(int)
Min. Typ. Max. Units
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
200
–––
–––
3.0
–––
–––
–––
–––
–––
0.23
60
–––
–––
–––
–––
–––
Internal Gate Resistance
–––
2.6
Conditions
–––
V VGS = 0V, ID = 250µA
––– V/°C Reference to 25°C, ID = 5mA
72.5 mΩ VGS = 10V, ID = 15A
5.0
V VDS = VGS, ID = 100µA
VDS = 200V, VGS = 0V
20
µA
250
VDS = 200V, VGS = 0V, TJ = 125°C
100
VGS = 20V
nA
VGS = -20V
-100
c
f
–––
Ω
Dynamic @ TJ = 25°C (unless otherwise specified)
Symbol
gfs
Qg
Qgs
Qgd
Qsync
td(on)
tr
td(off)
tf
Ciss
Coss
Crss
Coss eff. (ER)
Coss eff. (TR)
Parameter
Min. Typ. Max. Units
Forward Transconductance
Total Gate Charge
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Total Gate Charge Sync. (Qg - Qgd)
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
h
Effective Output Capacitance (Energy Related)
Effective Output Capacitance (Time Related)
g
37
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
25
8.2
7.9
17
13.4
22.4
25.4
14.8
1710
125
30
113
317
–––
38
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
Conditions
S
VDS = 50V, ID = 15A
ID = 15A
VDS = 100V
nC
VGS = 10V
ID = 15A, VDS =0V, VGS = 10V
VDD = 130V
ID = 15A
ns
RG = 7.3Ω
VGS = 10V
VGS = 0V
VDS = 50V
pF ƒ = 1.0MHz (See Fig.5)
VGS = 0V, VDS = 0V to 160V (See Fig.11)
VGS = 0V, VDS = 0V to 160V
f
f
h
g
Diode Characteristics
Symbol
IS
Parameter
Continuous Source Current
VSD
trr
(Body Diode)
Pulsed Source Current
(Body Diode)
Diode Forward Voltage
Reverse Recovery Time
Qrr
Reverse Recovery Charge
IRRM
ton
Reverse Recovery Current
Forward Turn-On Time
ISM
c
Notes:
 Repetitive rating; pulse width limited by max. junction
temperature.
‚ Limited by TJmax, starting TJ = 25°C, L = 1.0mH
RG = 25Ω, IAS = 15A, VGS =10V. Part not recommended for use
above this value .
ƒ ISD ≤ 15A, di/dt ≤ 634A/µs, VDD ≤ V(BR)DSS, TJ ≤ 175°C.
„ Pulse width ≤ 400µs; duty cycle ≤ 2%.
2
Min. Typ. Max. Units
–––
–––
25
–––
–––
100
Conditions
MOSFET symbol
A
showing the
integral reverse
D
G
p-n junction diode.
TJ = 25°C, IS = 15A, VGS = 0V
TJ = 25°C
VR = 100V,
TJ = 125°C
IF = 15A
di/dt = 100A/µs
TJ = 25°C
S
f
––– –––
1.3
V
–––
78
–––
ns
–––
99
–––
––– 294 –––
nC
TJ = 125°C
––– 432 –––
–––
7.6
–––
A TJ = 25°C
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
f
Coss eff. (TR) is a fixed capacitance that gives the same charging time
as Coss while VDS is rising from 0 to 80% VDSS .
† Coss eff. (ER) is a fixed capacitance that gives the same energy as
Coss while VDS is rising from 0 to 80% VDSS.
‡ When mounted on 1" square PCB (FR-4 or G-10 Material). For recom
mended footprint and soldering techniques refer to application note #AN-994.
ˆ Rθ is measured at TJ approximately 90°C
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IRFB4620PbF
1000
1000
100
BOTTOM
10
1
5.0V
0.1
≤60µs PULSE WIDTH
Tj = 25°C
100
BOTTOM
10
5.0V
1
≤60µs PULSE WIDTH
Tj = 175°C
0.1
0.01
0.1
1
10
0.1
100
Fig 1. Typical Output Characteristics
10
100
Fig 2. Typical Output Characteristics
1000
3.5
100
RDS(on) , Drain-to-Source On Resistance
(Normalized)
ID, Drain-to-Source Current (A)
1
V DS, Drain-to-Source Voltage (V)
V DS, Drain-to-Source Voltage (V)
TJ = 175°C
T J = 25°C
10
1
VDS = 50V
≤60µs PULSE WIDTH
0.1
ID = 15A
VGS = 10V
3.0
2.5
2.0
1.5
1.0
0.5
2
4
6
8
10
12
14
16
-60 -40 -20 0 20 40 60 80 100120140160180
T J , Junction Temperature (°C)
VGS, Gate-to-Source Voltage (V)
Fig 4. Normalized On-Resistance vs. Temperature
Fig 3. Typical Transfer Characteristics
14.0
100000
VGS, Gate-to-Source Voltage (V)
VGS = 0V,
f = 1 MHZ
C iss = C gs + C gd, C ds SHORTED
C rss = C gd
C oss = C ds + C gd
10000
C, Capacitance (pF)
VGS
15V
12V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
TOP
ID, Drain-to-Source Current (A)
ID, Drain-to-Source Current (A)
TOP
VGS
15V
12V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
Ciss
1000
Coss
100
Crss
ID= 15A
12.0
VDS= 160V
VDS= 100V
VDS= 40V
10.0
8.0
6.0
4.0
2.0
0.0
10
1
10
100
1000
VDS, Drain-to-Source Voltage (V)
Fig 5. Typical Capacitance vs. Drain-to-Source Voltage
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0
5
10
15
20
25
30
35
QG, Total Gate Charge (nC)
Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage
3
IRFB4620PbF
1000
T J = 175°C
ID, Drain-to-Source Current (A)
ISD, Reverse Drain Current (A)
100
T J = 25°C
10
OPERATION IN THIS AREA
LIMITED BY R DS(on)
100
100µsec
1msec
10
10msec
DC
1
Tc = 25°C
Tj = 175°C
Single Pulse
VGS = 0V
0.1
1.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1
1.6
VSD, Source-to-Drain Voltage (V)
ID, Drain Current (A)
25
20
15
10
5
0
75
100
125
150
175
V(BR)DSS , Drain-to-Source Breakdown Voltage (V)
30
50
Fig 9. Maximum Drain Current vs.
Case Temperature
260
Id = 5mA
250
240
230
220
210
200
190
-60 -40 -20 0 20 40 60 80 100120140160180
Fig 10. Drain-to-Source Breakdown Voltage
3.0
EAS , Single Pulse Avalanche Energy (mJ)
500
2.5
2.0
Energy (µJ)
1000
T J , Temperature ( °C )
T C , Case Temperature (°C)
1.5
1.0
0.5
0.0
-50
0
50
100
150
VDS, Drain-to-Source Voltage (V)
Fig 11. Typical COSS Stored Energy
4
100
Fig 8. Maximum Safe Operating Area
Fig 7. Typical Source-Drain Diode
Forward Voltage
25
10
VDS, Drain-to-Source Voltage (V)
200
ID
TOP
2.05A
2.94A
BOTTOM 15A
450
400
350
300
250
200
150
100
50
0
25
50
75
100
125
150
175
Starting T J , Junction Temperature (°C)
Fig 12. Maximum Avalanche Energy vs. DrainCurrent
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IRFB4620PbF
Thermal Response ( Z thJC ) °C/W
10
1
D = 0.50
0.20
0.10
0.05
0.1
τJ
0.02
0.01
0.01
R1
R1
τJ
τ1
R2
R2
τC
τ2
τ1
Ci= τi/Ri
Ci i/Ri
1E-005
0.0001
τi (sec)
0.000311
0.589
0.003759
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
SINGLE PULSE
( THERMAL RESPONSE )
0.001
1E-006
τ
τ2
Ri (°C/W)
0.456
0.001
0.01
0.1
t1 , Rectangular Pulse Duration (sec)
Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case
100
Avalanche Current (A)
Duty Cycle = Single Pulse
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming ∆Tj = 150°C and
Tstart =25°C (Single Pulse)
0.01
10
0.05
0.10
1
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming ∆Τ j = 25°C and
Tstart = 150°C.
0.1
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
tav (sec)
Fig 14. Typical Avalanche Current vs.Pulsewidth
EAR , Avalanche Energy (mJ)
120
Notes on Repetitive Avalanche Curves , Figures 14, 15:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a temperature far in
excess of Tjmax. This is validated for every part type.
2. Safe operation in Avalanche is allowed as long asTjmax is not exceeded.
3. Equation below based on circuit and waveforms shown in Figures 16a, 16b.
4. PD (ave) = Average power dissipation per single avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase
during avalanche).
6. Iav = Allowable avalanche current.
7. ∆T = Allowable rise in junction temperature, not to exceed Tjmax (assumed as
25°C in Figure 14, 15).
tav = Average time in avalanche.
D = Duty cycle in avalanche = tav ·f
ZthJC(D, tav) = Transient thermal resistance, see Figures 13)
TOP
Single Pulse
BOTTOM 1.0% Duty Cycle
ID = 15A
100
80
60
40
20
0
25
50
75
100
125
150
175
Starting T J , Junction Temperature (°C)
PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC
Iav = 2DT/ [1.3·BV·Zth]
EAS (AR) = PD (ave)·tav
Fig 15. Maximum Avalanche Energy vs. Temperature
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5
6.0
90
5.5
80
5.0
70
4.5
IF = 10A
V R = 100V
TJ = 25°C
TJ = 125°C
60
4.0
3.5
IRR (A)
VGS(th), Gate threshold Voltage (V)
IRFB4620PbF
ID = 100µA
ID = 250uA
ID = 1.0mA
ID = 1.0A
3.0
2.5
2.0
50
40
30
20
10
1.5
0
1.0
-75 -50 -25
0
0
25 50 75 100 125 150 175
200
90
1600
TJ = 25°C
TJ = 125°C
1400
50
QRR (A)
IRR (A)
1000
IF = 10A
V R = 100V
1800
TJ = 25°C
TJ = 125°C
60
800
2000
IF = 15A
V R = 100V
70
600
Fig. 17 - Typical Recovery Current vs. dif/dt
Fig 16. Threshold Voltage vs. Temperature
80
400
diF /dt (A/µs)
T J , Temperature ( °C )
1200
40
1000
30
800
20
600
10
400
0
0
200
400
600
800
200
1000
0
200
diF /dt (A/µs)
400
600
800
1000
diF /dt (A/µs)
Fig. 19 - Typical Stored Charge vs. dif/dt
Fig. 18 - Typical Recovery Current vs. dif/dt
2000
IF = 15A
V R = 100V
1800
1600
TJ = 25°C
TJ = 125°C
QRR (A)
1400
1200
1000
800
600
400
200
0
200
400
600
800
1000
diF /dt (A/µs)
6
Fig. 20 - Typical Stored Charge vs. dif/dt
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IRFB4620PbF
Driver Gate Drive
D.U.T
ƒ
-
‚
-
-
„
*
D.U.T. ISD Waveform
Reverse
Recovery
Current
+

RG
•
•
•
•
dv/dt controlled by RG
Driver same type as D.U.T.
I SD controlled by Duty Factor "D"
D.U.T. - Device Under Test
VDD
P.W.
Period
VGS=10V
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
+
D=
Period
P.W.
+
+
-
Body Diode Forward
Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
Re-Applied
Voltage
Body Diode
VDD
Forward Drop
Inductor
Current
Inductor Curent
ISD
Ripple ≤ 5%
* VGS = 5V for Logic Level Devices
Fig 21. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
V(BR)DSS
15V
DRIVER
L
VDS
tp
D.U.T
RG
VGS
20V
+
V
- DD
IAS
A
0.01Ω
tp
I AS
Fig 22a. Unclamped Inductive Test Circuit
RD
VDS
Fig 22b. Unclamped Inductive Waveforms
VDS
90%
VGS
D.U.T.
RG
+
- VDD
V10V
GS
10%
VGS
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
td(on)
Fig 23a. Switching Time Test Circuit
tr
t d(off)
Fig 23b. Switching Time Waveforms
Id
Current Regulator
Same Type as D.U.T.
Vds
Vgs
50KΩ
12V
tf
.2µF
.3µF
D.U.T.
+
V
- DS
Vgs(th)
VGS
3mA
IG
ID
Current Sampling Resistors
Fig 24a. Gate Charge Test Circuit
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Qgs1 Qgs2
Qgd
Qgodr
Fig 24b. Gate Charge Waveform
7
IRFB4620PbF
TO-220AB Package Outline
Dimensions are shown in millimeters (inches)
TO-220AB Part Marking Information
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TO-220AB packages are not recommended for Surface Mount Application.
Note: For the most current drawing please refer to IR website at http://www.irf.com/package/
Data and specifications subject to change without notice.
This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.
8
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 09/2008
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