EL5162, EL5163, EL5262, EL5263, EL5362 ® Data Sheet January 4, 2008 500MHz Low Power Current Feedback Amplifiers with Enable The EL5162, EL5163, EL5262, EL5263, and EL5362 are current feedback amplifiers with a bandwidth of 500MHz. This makes these amplifiers ideal for today’s high speed video and monitor applications. With a supply current of just 1.5mA and the ability to run from a single supply voltage from 5V to 12V, these amplifiers are also ideal for handheld, portable or battery-powered equipment. The EL5162 also incorporates an enable and disable function to reduce the supply current to 100µA typical per amplifier. Allowing the CE pin to float or applying a low logic level will enable the amplifier. The EL5162 is available in 6 Ld SOT-23 and 8 Ld SOIC packages, the EL5163 in 5 Ld SOT-23 and SC-70 packages, the EL5262 in the 10 Ld MSOP package, the EL5263 in 8 Ld MSOP and SO packages, and the EL5362 in 16 Ld SOIC (0.150”) and QSOP packages. All operate over the industrial temperature range of -40°C to +85°C. FN7388.10 Features • 500MHz to 3dB bandwidth • 4000V/µs slew rate • 1.5mA supply current • Single and dual supply operation, from 5V to 12V supply span • Fast enable/disable (EL5162, EL5262 and EL5362 only) • Available in SOT-23 packages • Pb-free available (RoHS compliant) • High speed, 1.4GHz product available (EL5167 and EL5167) • High speed, 4mA, 630MHz product available (EL5164 and EL5165) Applications • Battery-powered equipment • Handheld, portable devices • Video amplifiers • Cable drivers • RGB amplifiers • Test equipment • Instrumentation • Current to voltage converters 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2004, 2005, 2007, 2008. All Rights Reserved. All other trademarks mentioned are the property of their respective owners. EL5162, EL5163, EL5262, EL5263, EL5362 Ordering Information PART NUMBER PART MARKING PACKAGE PKG. DWG. # EL5162IS 5162IS 8 Ld SOIC (150 mil) MDP0027 EL5162IS-T7* 5162IS 8 Ld SOIC (150 mil) MDP0027 EL5162IS-T13* 5162IS 8 Ld SOIC (150 mil) MDP0027 EL5162ISZ (Note) 5162ISZ 8 Ld SOIC (150 mil) (Pb-free) MDP0027 EL5162ISZ-T7* (Note) 5162ISZ 8 Ld SOIC (150 mil) (Pb-free) MDP0027 EL5162ISZ-T13* (Note) 5162ISZ 8 Ld SOIC (150 mil) (Pb-free) MDP0027 EL5162IW-T7* j 6 Ld SOT-23 MDP0038 EL5162IW-T7A* j 6 Ld SOT-23 MDP0038 EL5162IWZ-T7* (Note) BAKA 6 Ld SOT-23 (Pb-free) MDP0038 EL5162IWZ-T7A* (Note) BAKA 6 Ld SOT-23 (Pb-free) MDP0038 EL5163IW-T7* d 5 Ld SOT-23 MDP0038 EL5163IW-T7A* d 5 Ld SOT-23 MDP0038 EL5163IWZ-T7* (Note) BALA 5 Ld SOT-23 (Pb-free) MDP0038 EL5163IWZ-T7A* (Note) BALA 5 Ld SOT-23 (Pb-free) MDP0038 EL5163IC-T7* E 5 Ld SC-70 (1.25mm) P5.049 EL5163IC-T7A* E 5 Ld SC-70 (1.25mm) P5.049 EL5163ICZ-T7* (Note) BDA 5 Ld SC-70 (1.25mm) (Pb-free) P5.049 EL5163ICZ-T7A* (Note) BDA 5 Ld SC-70 (1.25mm) (Pb-free) P5.049 EL5262IY BLAAA 10 Ld MSOP (3.0mm) MDP0043 EL5262IY-T7* BLAAA 10 Ld MSOP (3.0mm) MDP0043 EL5262IY-T13* BLAAA 10 Ld MSOP (3.0mm) MDP0043 EL5262IYZ (Note) BBTAA 10 Ld MSOP (3.0mm) (Pb-free) MDP0043 EL5262IYZ-T7* (Note) BBTAA 10 Ld MSOP (3.0mm) (Pb-free) MDP0043 EL5262IYZ-T13* (Note) BBTAA 10 Ld MSOP (3.0mm) (Pb-free) MDP0043 EL5263IS 5263IS 8 Ld SOIC (150 mil) MDP0027 EL5263IS-T7* 5263IS 8 Ld SOIC (150 mil) MDP0027 EL5263IS-T13* 5263IS 8 Ld SOIC (150 mil) MDP0027 EL5263ISZ (Note) 5263ISZ 8 Ld SOIC (150 mil) (Pb-free) MDP0027 EL5263ISZ-T7* (Note) 5263ISZ 8 Ld SOIC (150 mil) (Pb-free) MDP0027 EL5263ISZ-T13* (Note) 5263ISZ 8 Ld SOIC (150 mil) (Pb-free) MDP0027 EL5263IY BMAAA 8 Ld MSOP (3.0mm) MDP0043 EL5263IY-T7* BMAAA 8 Ld MSOP (3.0mm) MDP0043 EL5263IY-T13* BMAAA 8 Ld MSOP (3.0mm) MDP0043 EL5263IYZ (Note) BBBJA 8 Ld MSOP (3.0mm) (Pb-free) MDP0043 EL5263IYZ-T7* (Note) BBBJA 8 Ld MSOP (3.0mm) (Pb-free) MDP0043 EL5263IYZ-T13* (Note) BBBJA 8 Ld MSOP (3.0mm) (Pb-free) MDP0043 EL5362IS EL5362IS 16 Ld SOIC (150 mil) MDP0027 EL5362IS-T7* EL5362IS 16 Ld SOIC (150 mil) MDP0027 EL5362IS-T13* EL5362IS 16 Ld SOIC (150 mil) MDP0027 2 FN7388.10 January 4, 2008 EL5162, EL5163, EL5262, EL5263, EL5362 Ordering Information PART NUMBER (Continued) PART MARKING PACKAGE PKG. DWG. # EL5362ISZ (Note) EL5362ISZ 16 Ld SOIC (150 mil) (Pb-free) MDP0027 EL5362ISZ-T7* (Note) EL5362ISZ 16 Ld SOIC (150 mil) (Pb-free) MDP0027 EL5362ISZ-T13* (Note) EL5362ISZ 16 Ld SOIC (150 mil) (Pb-free) MDP0027 EL5362IU 5362IU 16 Ld QSOP (150 mil) MDP0040 EL5362IU-T7* 5362IU 16 Ld QSOP (150 mil) MDP0040 EL5362IU-T13* 5362IU 16 Ld QSOP (150 mil) MDP0040 EL5362IUZ (Note) 5362IUZ 16 Ld QSOP (Pb-free) MDP0040 EL5362IUZ-T7* (Note) 5362IUZ 16 Ld QSOP (Pb-free) MDP0040 EL5362IUZ-T13* (Note) 5362IUZ 16 Ld QSOP (Pb-free) MDP0040 *Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3 FN7388.10 January 4, 2008 EL5162, EL5163, EL5262, EL5263, EL5362 Pinouts NC 1 8 CE OUT 1 7 VS+ VS- 2 IN+ 3 6 OUT IN+ 3 VS- 4 5 NC IN- 2 + IN- 2 IN+ 3 VS- 4 CE 5 10 VS+ + + + - 6 VS+ OUT 1 5 CE VS- 2 4 IN- IN+ 3 OUT1 1 9 OUT IN- 2 8 IN- IN+ 3 7 IN+ 6 CE VS- 4 5 VS+ + - EL5263 (8 LD SOIC, MSOP) TOP VIEW EL5262 (10 LD MSOP) TOP VIEW OUT 1 EL5163 (5 LD SOT-23, SC-70) TOP VIEW EL5162 (6 LD SOT-23) TOP VIEW EL5162 (8 LD SOIC) TOP VIEW 8 VS+ 7 OUT2 + + 6 IN5 IN+ 4 IN- EL5362 (16 LD SOIC, QSOP) TOP VIEW INA+ 1 CEA 2 16 INA+ VS- 3 CEB 4 14 VS+ + - INB+ 5 INC+ 8 4 13 OUTB 12 INB- NC 6 CEC 7 15 OUTA 11 NC + - 10 OUTC 9 INC- FN7388.10 January 4, 2008 EL5162, EL5163, EL5262, EL5263, EL5362 Absolute Maximum Ratings (TA = +25°C) Thermal Information Supply Voltage between VS+ and VS- . . . . . . . . . . . . . . . . . . . 13.2V Maximum Continuous Output Current . . . . . . . . . . . . . . . . . . . 50mA Slewrate of VS+ to VS-. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1V/µs Maximum Voltage between IN+ and IN-, disabled . . . . . . . . . . ±1.5V Current into IN+, IN-, CE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±5mA Pin Voltages . . . . . . . . . . . . . . . . . . . . . . . . . VS- -0.5V to VS+ +0.5V Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Ambient Operating Temperature . . . . . . . . . . . . . . . .-40°C to +85°C Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +125°C Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA Electrical Specifications PARAMETER VS+ = +5V, VS- = -5V, RF = 750Ω for AV = 1, RF = 400Ω for AV = 2, RL = 150Ω, TA = +25°C unless otherwise specified. DESCRIPTION CONDITIONS MIN TYP MAX UNIT AC PERFORMANCE BW -3dB Bandwidth BW1 0.1dB Bandwidth SR Slew Rate tS 0.1% Settling Time eN AV = +1, RL = 500Ω, RF = 598Ω 500 MHz AV = +2, RL = 150Ω, RF = 422Ω 233 MHz 30 MHz VO = -2.5V to +2.5V, AV = +2, RL = 100Ω (EL5262, EL5263, EL5362) 2000 2500 4000 V/µs VO = -2.5V to +2.5V, AV = +2, RL = 100Ω (EL5162, EL5163) 2800 4000 6000 V/µs VOUT = -2.5V to +2.5V, AV = +1 25 ns Input Voltage Noise 3 nV/√Hz iN- IN- Input Current Noise 10 pA/√Hz iN+ IN+ Input Current Noise 6.5 pA/√Hz dG Differential Gain Error (Note 1) AV = +2 0.05 % dP Differential Phase Error (Note 1) AV = +2 0.15 ° DC PERFORMANCE VOS Offset Voltage TCVOS Input Offset Voltage Temperature Coefficient ROL Transimpedance -5 Measured from TMIN to TMAX 1.5 +5 mV 6 µV/°C 500 1000 kΩ V INPUT CHARACTERISTICS CMIR Common Mode Input Range Guaranteed by CMRR test ±3 ±3.3 CMRR Common Mode Rejection Ratio VIN = ±3V 50 62 75 dB -ICMR - Input Current Common Mode Rejection -1 0.22 +1 µA/V +IIN + Input Current -8 0.5 +8 µA -IIN - Input Current -10 2 +10 µA RIN Input Resistance 0.8 1.6 3 MΩ CIN Input Capacitance 1 pF OUTPUT CHARACTERISTICS VO IOUT Output Voltage Swing Output Current 5 RL = 150Ω to GND ±3.35 ±3.6 ±3.75 V RL = 1kΩ to GND ±3.75 ±3.9 ±4.15 V RL = 10Ω to GND 60 100 mA FN7388.10 January 4, 2008 EL5162, EL5163, EL5262, EL5263, EL5362 Electrical Specifications PARAMETER VS+ = +5V, VS- = -5V, RF = 750Ω for AV = 1, RF = 400Ω for AV = 2, RL = 150Ω, TA = +25°C unless otherwise specified. (Continued) DESCRIPTION CONDITIONS MIN TYP MAX UNIT SUPPLY ISON Supply Current - Enabled, per Amplifier No load, VIN = 0V 1.3 1.5 2.0 mA ISOFF- Supply Current - Disabled, per Amplifier No load, VIN = 0V -25 -14 0 µA 0 10 +25 µA ISOFF+ PSRR Power Supply Rejection Ratio DC, VS = ±4.75V to ±5.25V 65 76 -IPSR - Input Current Power Supply Rejection DC, VS = ±4.75V to ±5.25V -0.5 0.1 dB +0.5 µA/V ENABLE (EL5162, EL5262, EL5362 ONLY) tEN Enable Time 380 ns tDIS Disable Time 800 ns IIHCE CE Pin Input High Current CE = VS+ 1 5 25 µA IILCE CE Pin Input Low Current CE = (VS+) -5V -1 0 +1 µA VIHCE CE Input High Voltage for Power-down VILCE CE Input Low Voltage for Power-down VS+ - 1 V VS+ - 3 V NOTE: 1. Standard NTSC test, AC signal amplitude = 286mVP-P, f = 3.58MHz 6 FN7388.10 January 4, 2008 EL5162, EL5163, EL5262, EL5263, EL5362 Typical Performance Curves +4 +2 +1 +4 VCC = +5V VEE = -5V RL = 500Ω RF = 598Ω +3 NORMALIZED GAIN (dB) NORMALIZED GAIN (dB) +3 0 -1 -2 -3 -4 +2 VCC = +5V VEE = -5V RF = 375Ω +1 0 -1 -2 -3 -4 -5 -5 -6 100k 1M 10M 100M -6 100k 1G 1M FREQENCY (Hz) +2 +3 +1 +2 0 -1 -2 -3 -4 -5 -6 -7 VCC = +5V VEE = -5V AV = +10 RL = 150Ω RF = 375Ω -8 100k +1 0 -1 -2 -3 -4 -5 -6 1M 10M 100M VCC = +5V VEE = -5V RL = 150Ω RF = 422Ω -7 100k 1G 1M FREQUENCY (Hz) +4 +1 +3 NORMALIZED GAIN (dB) NORMALIZED GAIN (dB) +5 +2 0 -1 -2 -3 -6 -7 100k 100M 1G FIGURE 4. FREQUENCY RESPONSE FOR AV = +2 +3 -5 10M FREQUENCY (Hz) FIGURE 3. FREQUENCY RESPONSE FOR AV = +10 -4 1G FIGURE 2. FREQUENCY RESPONSE FOR AV = +4.6 NORMALIZED GAIN (dB) NORMALIZED GAIN (dB) FIGURE 1. FREQUENCY RESPONSE FOR AV = +1 10M 100M FREQUENCY (Hz) VCC = +5V VEE = -5V RL = 150Ω RF = 422Ω AV = +1 RL = 150Ω RF = 698Ω +2 ±6V +1 0 -1 VCC, VEE = ±5V ±4V -2 ±3V ±2.5V -3 -4 1M 10M 100M 1G FREQUENCY (Hz) FIGURE 5. FREQUENCY RESPONSE FOR AV = +4 7 -5 100k 1M 10M 100M 500M FREQUENCY (Hz) FIGURE 6. FREQUENCY RESPONSE FOR VARIOUS VCC, VEE FN7388.10 January 4, 2008 EL5162, EL5163, EL5262, EL5263, EL5362 Typical Performance Curves (Continued) OUTPUT IMPEDANCE (Ω) 100 VCC = +5V VEE = -5V AV = +2 VCC = +5V VEE = -5V AV = +2 RL = 150Ω 10 1V/DIV INPUT RISE TIME 1.028ns OUTPUT RISE TIME 2.218ns 1 2V/DIV 0.1 10k 100k 1M 10M 100M 4ns/DIV FREQUENCY (Hz) FIGURE 7. CLOSED LOOP OUTPUT IMPEDANCE 1V/DIV INPUT FALL TIME 1.036ns OUTPUT FALL TIME 2.21ns VCC = +5V VEE = -5V AV = +2 RL = 150Ω FIGURE 8. EL5262 OUTPUT RISE TIME CH 1 2V/DIV CH 2 CH1 = 5V CH2 = 200mV M = 100ns 4ns/DIV 100ns/DIV FIGURE 9. EL5262 OUTPUT FALL TIME FIGURE 10. TURN ON TIME 0 VCC = +5V -10 V = -5V EE -20 AV = +2 RL = 150Ω -30 CH1 = 5V CH2 = 200mV M = 100ns PSRR (dB) CH1 -40 -50 -60 -70 -80 CH2 -90 -100 100 100ns/DIV FIGURE 11. TURN OFF TIME 8 1k 10k 100k 1M 10M 100M FREQUENCY (Hz) FIGURE 12. PSRR (VCC) FN7388.10 January 4, 2008 EL5162, EL5163, EL5262, EL5263, EL5362 Typical Performance Curves (Continued) JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 0 1.4 POWER DISSIPATION (W) PSRR (dB) VCC = +5V -10 VEE = -5V -20 AV = +2 RL = 150Ω -30 -40 -50 -60 -70 -80 -90 -100 100 1k 10k 100k 1M 10M 1.2 1.250W SO16 (0.150”) θJA = +80°C/W 1.0 0.8 909mW 0.6 SO8 θJA = +110°C/W 0.4 0.2 0 100M 0 25 FREQUENCY (Hz) 150 FIGURE 14. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 1.4 0.50 0.45 435mW 1.2 POWER DISSIPATION (W) POWER DISSIPATION (W) 125 AMBIENT TEMPERATURE (°C) FIGURE 13. PSRR (VEE) 1.0 893mW 0.8 QSOP16 θJA = +112°C/W 0.6 0.4 0.2 0.40 0.35 SOT23-5/6 θJA = +230°C/W 0.30 0.25 0.20 0.15 0.10 0.05 0 0 0 25 75 85 100 50 125 150 0 25 AMBIENT TEMPERATURE (°C) 125 150 JEDEC JESD51-3 LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 1.0 0.9 870mW 0.9 POWER DISSIPATION (W) 1.0 0.8 MSOP8/10 θJA = +115°C/W 0.6 75 85 100 FIGURE 16. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 0.7 50 AMBIENT TEMPERATURE (°C) FIGURE 15. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE POWER DISSIPATION (W) 75 85 100 50 0.5 0.4 0.3 0.2 909mW 0.8 SO16 (0.15 0”) θJA = +110°C/W 0.7 0.6 625mW 0.5 0.4 SO8 θJA = +160°C/W 0.3 0.2 0.1 0.1 0 0 0 25 75 85 50 100 125 AMBIENT TEMPERATURE (°C) FIGURE 17. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE 9 0 25 50 75 85 100 125 150 AMBIENT TEMPERATURE (°C) FIGURE 18. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE FN7388.10 January 4, 2008 EL5162, EL5163, EL5262, EL5263, EL5362 Typical Performance Curves (Continued) JEDEC JESD51-3 LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD JEDEC JESD51-3 LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 0.45 POWER DISSIPATION (W) POWER DISSIPATION (W) 1.2 1.0 0.8 633mW QSOP16 θJA = +158°C/W 0.6 0.4 0.2 391mW 0.40 0.35 0.30 SOT23-5/6 θJA = +256°C/W 0.25 0.20 0.15 0.10 0.05 0 0 0 25 50 75 85 100 150 125 0 25 AMBIENT TEMPERATURE (°C) 50 75 85 100 125 150 AMBIENT TEMPERATURE (°C) FIGURE 19. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE FIGURE 20. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE JEDEC JESD51-3 LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD POWER DISSIPATION (W) 0.6 486mW 0.5 MSOP8/10 θJA = +206°C/W 0.4 0.3 0.2 0.1 0 0 25 50 75 85 100 125 AMBIENT TEMPERATURE (°C) FIGURE 21. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE 10 FN7388.10 January 4, 2008 EL5162, EL5163, EL5262, EL5263, EL5362 SOT-23 Package Family MDP0038 e1 D SOT-23 PACKAGE FAMILY A MILLIMETERS 6 N SYMBOL 4 E1 2 E 3 0.15 C D 1 2X 2 3 0.20 C 5 2X e 0.20 M C A-B D B b NX 0.15 C A-B 1 3 SOT23-5 SOT23-6 A 1.45 1.45 MAX A1 0.10 0.10 ±0.05 A2 1.14 1.14 ±0.15 b 0.40 0.40 ±0.05 c 0.14 0.14 ±0.06 D 2.90 2.90 Basic E 2.80 2.80 Basic E1 1.60 1.60 Basic e 0.95 0.95 Basic e1 1.90 1.90 Basic L 0.45 0.45 ±0.10 L1 0.60 0.60 Reference N 5 6 Reference D 2X TOLERANCE Rev. F 2/07 NOTES: C A2 2. Plastic interlead protrusions of 0.25mm maximum per side are not included. SEATING PLANE A1 0.10 C 1. Plastic or metal protrusions of 0.25mm maximum per side are not included. 3. This dimension is measured at Datum Plane “H”. 4. Dimensioning and tolerancing per ASME Y14.5M-1994. NX 5. Index area - Pin #1 I.D. will be located within the indicated zone (SOT23-6 only). (L1) 6. SOT23-5 version has no center lead (shown as a dashed line). H A GAUGE PLANE c L 11 0.25 0° +3° -0° FN7388.10 January 4, 2008 EL5162, EL5163, EL5262, EL5263, EL5362 Small Outline Package Family (SO) A D h X 45° (N/2)+1 N A PIN #1 I.D. MARK E1 E c SEE DETAIL “X” 1 (N/2) B L1 0.010 M C A B e H C A2 GAUGE PLANE SEATING PLANE A1 0.004 C 0.010 M C A B L b 0.010 4° ±4° DETAIL X MDP0027 SMALL OUTLINE PACKAGE FAMILY (SO) INCHES SYMBOL SO-14 SO16 (0.300”) (SOL-16) SO20 (SOL-20) SO24 (SOL-24) SO28 (SOL-28) TOLERANCE NOTES A 0.068 0.068 0.068 0.104 0.104 0.104 0.104 MAX - A1 0.006 0.006 0.006 0.007 0.007 0.007 0.007 ±0.003 - A2 0.057 0.057 0.057 0.092 0.092 0.092 0.092 ±0.002 - b 0.017 0.017 0.017 0.017 0.017 0.017 0.017 ±0.003 - c 0.009 0.009 0.009 0.011 0.011 0.011 0.011 ±0.001 - D 0.193 0.341 0.390 0.406 0.504 0.606 0.704 ±0.004 1, 3 E 0.236 0.236 0.236 0.406 0.406 0.406 0.406 ±0.008 - E1 0.154 0.154 0.154 0.295 0.295 0.295 0.295 ±0.004 2, 3 e 0.050 0.050 0.050 0.050 0.050 0.050 0.050 Basic - L 0.025 0.025 0.025 0.030 0.030 0.030 0.030 ±0.009 - L1 0.041 0.041 0.041 0.056 0.056 0.056 0.056 Basic - h 0.013 0.013 0.013 0.020 0.020 0.020 0.020 Reference - 16 20 24 28 Reference - N SO-8 SO16 (0.150”) 8 14 16 Rev. M 2/07 NOTES: 1. Plastic or metal protrusions of 0.006” maximum per side are not included. 2. Plastic interlead protrusions of 0.010” maximum per side are not included. 3. Dimensions “D” and “E1” are measured at Datum Plane “H”. 4. Dimensioning and tolerancing per ASME Y14.5M-1994 12 FN7388.10 January 4, 2008 EL5162, EL5163, EL5262, EL5263, EL5362 Small Outline Transistor Plastic Packages (SC70-5) P5.049 D VIEW C e1 5 LEAD SMALL OUTLINE TRANSISTOR PLASTIC PACKAGE INCHES 5 SYMBOL 4 E CL 1 2 CL 3 e E1 b CL 0.20 (0.008) M C C CL A A2 SEATING PLANE A1 -C- PLATING b1 0.043 0.80 1.10 - 0.004 0.00 0.10 - A2 0.031 0.039 0.80 1.00 - b 0.006 0.012 0.15 0.30 - b1 0.006 0.010 0.15 0.25 c 0.003 0.009 0.08 0.22 6 c1 0.003 0.009 0.08 0.20 6 D 0.073 0.085 1.85 2.15 3 E 0.071 0.094 1.80 2.40 - E1 0.045 0.053 1.15 1.35 3 e 0.0256 Ref 0.65 Ref - e1 0.0512 Ref 1.30 Ref - L2 c1 NOTES 0.031 0.010 0.018 0.017 Ref. 0.26 0.46 4 0.420 Ref. 0.006 BSC 0o N c MAX 0.000 α WITH MIN A L b MILLIMETERS MAX A1 L1 0.10 (0.004) C MIN - 0.15 BSC 8o 0o 5 8o - 5 5 R 0.004 - 0.10 - R1 0.004 0.010 0.15 0.25 Rev. 3 7/07 NOTES: BASE METAL 1. Dimensioning and tolerances per ASME Y14.5M-1994. 2. Package conforms to EIAJ SC70 and JEDEC MO-203AA. 4X θ1 3. Dimensions D and E1 are exclusive of mold flash, protrusions, or gate burrs. R1 4. Footlength L measured at reference to gauge plane. 5. “N” is the number of terminal positions. R GAUGE PLANE SEATING PLANE L C L1 α L2 6. These Dimensions apply to the flat section of the lead between 0.08mm and 0.15mm from the lead tip. 7. Controlling dimension: MILLIMETER. Converted inch dimensions are for reference only. 4X θ1 VIEW C 0.4mm 0.75mm 2.1mm 0.65mm TYPICAL RECOMMENDED LAND PATTERN 13 FN7388.10 January 4, 2008 EL5162, EL5163, EL5262, EL5263, EL5362 Mini SO Package Family (MSOP) 0.25 M C A B D MINI SO PACKAGE FAMILY (N/2)+1 N E MDP0043 A E1 MILLIMETERS PIN #1 I.D. 1 B (N/2) e H C SEATING PLANE 0.10 C N LEADS SYMBOL MSOP8 MSOP10 TOLERANCE NOTES A 1.10 1.10 Max. - A1 0.10 0.10 ±0.05 - A2 0.86 0.86 ±0.09 - b 0.33 0.23 +0.07/-0.08 - c 0.18 0.18 ±0.05 - D 3.00 3.00 ±0.10 1, 3 E 4.90 4.90 ±0.15 - E1 3.00 3.00 ±0.10 2, 3 e 0.65 0.50 Basic - L 0.55 0.55 ±0.15 - L1 0.95 0.95 Basic - N 8 10 Reference - 0.08 M C A B b Rev. D 2/07 NOTES: 1. Plastic or metal protrusions of 0.15mm maximum per side are not included. L1 2. Plastic interlead protrusions of 0.25mm maximum per side are not included. A 3. Dimensions “D” and “E1” are measured at Datum Plane “H”. 4. Dimensioning and tolerancing per ASME Y14.5M-1994. c SEE DETAIL "X" A2 GAUGE PLANE L A1 0.25 3° ±3° DETAIL X 14 FN7388.10 January 4, 2008 EL5162, EL5163, EL5262, EL5263, EL5362 Quarter Size Outline Plastic Packages Family (QSOP) MDP0040 A QUARTER SIZE OUTLINE PLASTIC PACKAGES FAMILY D (N/2)+1 N INCHES SYMBOL QSOP16 QSOP24 QSOP28 TOLERANCE NOTES E PIN #1 I.D. MARK E1 1 (N/2) A 0.068 0.068 0.068 Max. - A1 0.006 0.006 0.006 ±0.002 - A2 0.056 0.056 0.056 ±0.004 - b 0.010 0.010 0.010 ±0.002 - c 0.008 0.008 0.008 ±0.001 - D 0.193 0.341 0.390 ±0.004 1, 3 E 0.236 0.236 0.236 ±0.008 - E1 0.154 0.154 0.154 ±0.004 2, 3 e 0.025 0.025 0.025 Basic - L 0.025 0.025 0.025 ±0.009 - L1 0.041 0.041 0.041 Basic - N 16 24 28 Reference - B 0.010 C A B e H C SEATING PLANE 0.007 0.004 C b C A B Rev. F 2/07 NOTES: L1 A 1. Plastic or metal protrusions of 0.006” maximum per side are not included. 2. Plastic interlead protrusions of 0.010” maximum per side are not included. c SEE DETAIL "X" 3. Dimensions “D” and “E1” are measured at Datum Plane “H”. 4. Dimensioning and tolerancing per ASME Y14.5M-1994. 0.010 A2 GAUGE PLANE L A1 4°±4° DETAIL X All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 15 FN7388.10 January 4, 2008