GTL2008; GTL2107 12-bit GTL to LVTTL translator with power good control and high-impedance LVTTL and GTL outputs Rev. 02 — 26 September 2006 Product data sheet 1. General description The GTL2008/GTL2107 is a customized translator between dual Xeon processors, Platform Health Management, South Bridge and Power Supply LVTTL and GTL signals. Functionally and footprint identical to the GTL2007, the GTL2008/GTL2107 LVTTL and GTL outputs were changed to put them into a high-impedance state when EN1 and EN2 are LOW, with the exception of 11BO because its normal state is LOW, so it is forced LOW. EN1 and EN2 will remain LOW until VCC is at normal voltage, the other inputs are in valid states and VREF is at its proper voltage to assure that the outputs will remain high-impedance through power-up. Both the GTL2008/GTL2107 and the GTL2007 are derived from the GTL2006. They add an enable function that disables the error output to the monitoring agent for platforms that monitor the individual error conditions from each processor. This enable function can be used so that false error conditions are not passed to the monitoring agent when the system is unexpectedly powered down. This unexpected power-down could be from a power supply overload, a CPU thermal trip, or some other event of which the monitoring agent is unaware. A typical implementation would be to connect each enable line to the system power good signal or the individual enables to the VRD power good for each processor. Typically Xeon processors specify a VTT of 1.1 V to 1.2 V, as well as a nominal Vref of 0.73 V to 0.76 V. To allow for future voltage level changes that may extend Vref to 0.63 of VTT (minimum of 0.693 V with VTT of 1.1 V) the GTL2008/GTL2107 allows a minimum Vref of 0.66 V. Characterization results show that there is little DC or AC performance variation between these levels. The GTL2008 is the companion chip to the GTL2009 3-bit GTL Front-Side Bus frequency comparator that is used in dual-processor Xeon applications. The GTL2107 is the Intel designation for the GTL2008. 2. Features n Operates as a GTL to LVTTL sampling receiver or LVTTL to GTL driver n EN1 and EN2 disable error output n All LVTTL and GTL outputs are put in a high-impedance state when EN1 and EN2 are LOW n 3.0 V to 3.6 V operation n LVTTL I/O not 5 V tolerant GTL2008; GTL2107 Philips Semiconductors GTL translator with power good control and high-impedance outputs n Series termination on the LVTTL outputs of 30 Ω n ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per JESD22-A115, and 1000 V CDM per JESD22-C101 n Latch-up testing is done to JEDEC Standard JESD78 Class II, Level A which exceeds 500 mA n Package offered: TSSOP28 3. Quick reference data Table 1. Quick reference data Tamb = 25 °C Symbol Parameter Conditions Min Typ Max Unit Cio input/output capacitance A port; VO = 3.0 V or 0 V - 2.5 3.5 pF B port; VO = VTT or 0 V - 1.5 2.5 pF LOW-to-HIGH propagation delay nA to nBI; see Figure 4 1 4 8 ns nBI to nA or nAO (open-drain outputs); see Figure 14 2 13 18 ns HIGH-to-LOW propagation delay nA to nBI; see Figure 4 2 5.5 10 ns nBI to nA or nAO (open-drain outputs); see Figure 14 2 4 10 ns LOW-to-HIGH propagation delay nA to nBI; see Figure 4 1 4 8 ns nBI to nA or nAO (open-drain outputs); see Figure 14 2 13 18 ns HIGH-to-LOW propagation delay nA to nBI; see Figure 4 2 5.5 10 ns nBI to nA or nAO (open-drain outputs); see Figure 14 2 4 10 ns Vref = 0.73 V; VTT = 1.1 V tPLH tPHL Vref = 0.76 V; VTT = 1.2 V tPLH tPHL 4. Ordering information Table 2. Ordering information Tamb = −40 °C to +85 °C Type number Topside mark Package Name Description Version GTL2008PW GTL2008 TSSOP28 plastic thin shrink small outline package; 28 leads; body width 4.4 mm SOT361-1 GTL2107PW GTL2107 TSSOP28 plastic thin shrink small outline package; 28 leads; body width 4.4 mm SOT361-1 The GTL2107 is the Intel designation for the GTL2008 and is identical to the GTL2008 except for the type number and the topside markings. GTL2008_GTL2107_2 Product data sheet © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 02 — 26 September 2006 2 of 20 GTL2008; GTL2107 Philips Semiconductors GTL translator with power good control and high-impedance outputs 5. Functional diagram GTL2008/GTL2107 GTL VREF 1AO 2AO 5A LVTTL inputs/outputs (open-drain) 6A GTL input 27 2 1BI GTL inputs LVTTL outputs (open-drain) LVTTL input 1 EN1 11BI LVTTL input/output (open-drain) 11A GTL input 9BI 26 3 4 & 5 25 2BI 7BO1 GTL outputs & 24 7BO2 6 23 7 1 EN2 LVTTL input 11BO GTL output (2) 22 DELAY(1) 8 21 5BI DELAY(1) 9 20 6BI GTL inputs 3AO LVTTL outputs (open-drain) 4AO 19 10 18 11 1 10AI1 12 1 LVTTL inputs 10AI2 13 17 3BI 4BI 10BO1 GTL outputs 16 15 10BO2 9AO LVTTL output 002aab968 (1) The enable on 7BO1/7BO2 include a delay that prevents the transient condition where 5BI/6BI go from LOW to HIGH, and the LOW to HIGH on 5A/6A lags up to 100 ns from causing a LOW glitch on the 7BO1/7BO2 outputs. (2) The 11BO output is driven LOW after VCC is powered up with EN2 LOW to prevent reporting of a fault condition before EN2 goes HIGH. Fig 1. Logic diagram of GTL2008/GTL2107 GTL2008_GTL2107_2 Product data sheet © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 02 — 26 September 2006 3 of 20 GTL2008; GTL2107 Philips Semiconductors GTL translator with power good control and high-impedance outputs 6. Pinning information 6.1 Pinning VREF 1 28 VCC 1AO 2 27 1BI 2AO 3 26 2BI 5A 4 25 7BO1 6A 5 24 7BO2 EN1 6 11BI 7 11A 8 9BI 9 20 6BI 3AO 10 19 3BI 4AO 11 18 4BI 23 EN2 GTL2008PW GTL2107PW 22 11BO 21 5BI 10AI1 12 17 10BO1 10AI2 13 16 10BO2 GND 14 15 9AO 002aab969 Fig 2. Pin configuration for TSSOP28 6.2 Pin description Table 3. Pin description Symbol Pin Description VREF 1 GTL reference voltage 1AO 2 data output (LVTTL), open-drain 2AO 3 data output (LVTTL), open-drain 5A 4 data input/output (LVTTL), open-drain 6A 5 data input/output (LVTTL), open-drain EN1 6 enable input (LVTTL) 11BI 7 data input (GTL) 11A 8 data input/output (LVTTL), open-drain 9BI 9 data input (GTL) 3AO 10 data output (LVTTL), open-drain 4AO 11 data output (LVTTL), open-drain 10AI1 12 data input (LVTTL) 10AI2 13 data input (LVTTL) GND 14 ground (0 V) 9AO 15 data output (LVTTL), 3-state 10BO2 16 data output (GTL) 10BO1 17 data output (GTL) 4BI 18 data input (GTL) 3BI 19 data input (GTL) GTL2008_GTL2107_2 Product data sheet © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 02 — 26 September 2006 4 of 20 GTL2008; GTL2107 Philips Semiconductors GTL translator with power good control and high-impedance outputs Table 3. Pin description …continued Symbol Pin Description 6BI 20 data input (GTL) 5BI 21 data input (GTL) 11BO 22 data output (GTL) EN2 23 enable input (LVTTL) 7BO2 24 data output (GTL) 7BO1 25 data output (GTL) 2BI 26 data input (GTL) 1BI 27 data input (GTL) VCC 28 positive supply voltage 7. Functional description Refer to Figure 1 “Logic diagram of GTL2008/GTL2107”. 7.1 Function tables Table 4. GTL input signals H = HIGH voltage level; L = LOW voltage level. Input Output[1] 1BI/2BI/3BI/4BI/9BI 1AO/2AO/3AO/4AO/9AO L L H H [1] 1AO, 2AO, 3AO, 4AO and 5A/6A condition changed by ENn power good signal as described in Table 5 and Table 6. Table 5. EN1 power good signal H = HIGH voltage level; L = LOW voltage level. EN1 1AO and 2AO 5A L 1BI and 2BI disconnected (high-Z) 5BI disconnected H follows BI 5BI connected Table 6. EN2 power good signal H = HIGH voltage level; L = LOW voltage level. EN2 3AO and 4AO L 3BI and 4BI disconnected (high-Z) 6BI disconnected H follows BI 6BI connected GTL2008_GTL2107_2 Product data sheet 6A © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 02 — 26 September 2006 5 of 20 GTL2008; GTL2107 Philips Semiconductors GTL translator with power good control and high-impedance outputs Table 7. SMI signals H = HIGH voltage level; L = LOW voltage level; X = Don’t care. Inputs Output 10AI1/10AI2 EN2 9BI 10BO1/10BO2 L H L L L H H L H H L L H H H H L L X L H L X H Table 8. PROCHOT signals H = HIGH voltage level; L = LOW voltage level. Input Input/output Output 5BI/6BI 5A/6A (open-drain) 7BO1/7BO2 L L H[1] H L[2] L H H H [1] The enable on 7BO1/7BO2 includes a delay that prevents the transient condition where 5BI/6BI go from LOW to HIGH, and the LOW to HIGH on 5A/6A lags up to 100 ns from causing a low glitch on the 7BO1/7BO2 outputs. [2] Open-drain input/output terminal is driven to logic LOW state by other driver. Table 9. NMI signals H = HIGH voltage level; L = LOW voltage level; X = Don’t care. Inputs Input/output Output 11A (open-drain) 11BO 11BI EN2 L H H L L H L[1] H H H L H X L H L L L[1] H X [1] Open-drain input/output terminal is driven to logic LOW state by other driver. GTL2008_GTL2107_2 Product data sheet © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 02 — 26 September 2006 6 of 20 GTL2008; GTL2107 Philips Semiconductors GTL translator with power good control and high-impedance outputs 8. Application design-in information VTT VTT 56 Ω 1.5 kΩ to 1.2 kΩ 56 Ω R VCC 2R 1.5 kΩ PLATFORM HEALTH MANAGEMENT VCC VREF VCC CPU1 CPU1 1ERR_L 1AO 1BI IERR_L CPU1 THRMTRIP L 2AO 2BI THRMTRIP L CPU1 PROCHOT L 5A 7BO1 FORCEPR_L CPU2 PROCHOT L 6A 7BO2 EN1 EN2 11B1 11B0 GTL2008 11A GTL2107 5BI NMI_L PROCHOT L NMI CPU1 DISABLE_L FORCEPR_L 9BI 6BI PROCHOT L CPU2 IERR_L 3AO 3BI IERR_L CPU2 THRMTRIP L 4AO 4BI THRMTRIP L CPU1 SMI L 10AI1 10BO1 NMI CPU2 SMI L 10AI2 10BO2 CPU2 DISABLE_L SMI_BUFF_L GND 9AO CPU2 (1) SOUTHBRIDGE NMI SOUTHBRIDGE SMI_L power supply POWER GOOD 002aab970 (1) If 9AO needs to be HIGH before EN2 goes HIGH, a pull-up resistor is required because it is high-impedance until EN2 goes HIGH. All other outputs, both GTL and LVTTL, require pull-up resistors because they are open-drain. Fig 3. Typical application GTL2008_GTL2107_2 Product data sheet © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 02 — 26 September 2006 7 of 20 GTL2008; GTL2107 Philips Semiconductors GTL translator with power good control and high-impedance outputs 9. Limiting values Table 10. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Max Unit VCC supply voltage −0.5 +4.6 V IIK input clamping current VI < 0 V - −50 mA VI input voltage A port (LVTTL) −0.5[1] +4.6 V B port (GTL) −0.5[1] +4.6 V IOK output clamping current VO < 0 V - −50 mA VO output voltage output in OFF or HIGH state; A port −0.5[1] +4.6 V output in OFF or HIGH state; B port −0.5[1] +4.6 V A port - 32 mA B port - 30 mA A port - −32 mA −60 +150 °C - +125 °C current[2] IOL LOW-level output IOH HIGH-level output current[3] Tstg storage temperature Tj(max) [4] maximum junction temperature [1] The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed. [2] Current into any output in the LOW state. [3] Current into any output in the HIGH state. [4] The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150 °C. 10. Recommended operating conditions Table 11. Operating conditions Symbol Parameter Conditions Min Typ Max Unit VCC supply voltage 3.0 3.3 3.6 V VTT termination voltage GTL - 1.2 - V Vref reference voltage GTL 0.64 0.8 1.1 V VI input voltage A port 0 3.3 3.6 V B port 0 VTT 3.6 V VIH HIGH-level input voltage A port and ENn 2 - - V B port Vref + 0.050 - - V A port and ENn - - 0.8 V VIL LOW-level input voltage B port - - Vref − 0.050 V IOH HIGH-level output current A port - - −16 mA IOL LOW-level output current A port - - 16 mA B port - - 15 mA operating in free-air −40 - +85 °C Tamb ambient temperature GTL2008_GTL2107_2 Product data sheet © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 02 — 26 September 2006 8 of 20 GTL2008; GTL2107 Philips Semiconductors GTL translator with power good control and high-impedance outputs 11. Static characteristics Table 12. Static characteristics Recommended operating conditions; voltages are referenced to GND (ground = 0 V). Tamb = −40 °C to +85 °C Symbol VOH Typ[1] Max Unit 9AO; VCC = 3.0 V to 3.6 V; IOH = −100 µA [2] VCC − 0.2 3.0 - V 9AO; VCC = 3.0 V; IOH = −16 mA [2] 2.1 2.3 - V A port; VCC = 3.0 V; IOL = 4 mA [2] - 0.15 0.4 V A port; VCC = 3.0 V; IOL = 8 mA [2] - 0.3 0.55 V A port; VCC = 3.0 V; IOL = 16 mA [2] - 0.6 0.8 V B port; VCC = 3.0 V; IOL = 15 mA [2] Conditions HIGH-level output voltage LOW-level output voltage VOL Min Parameter - 0.13 0.4 V IOH HIGH-level output current open-drain outputs; A port other than 9AO; VO = VCC; VCC = 3.6 V - - ±1 µA II input current A port; VCC = 3.6 V; VI = VCC - - ±1 µA A port; VCC = 3.6 V; VI = 0 V - - ±1 µA B port; VCC = 3.6 V; VI = VTT or GND - - ±1 µA ICC supply current A or B port; VCC = 3.6 V; VI = VCC or GND; IO = 0 mA - 8 12 mA ∆ICC[3] additional supply current per input; A port or control inputs; VCC = 3.6 V; VI = VCC − 0.6 V - - 500 µA Cio input/output capacitance A port; VO = 3.0 V or 0 V - 2.5 3.5 pF B port; VO = VTT or 0 V - 1.5 2.5 pF [1] All typical values are measured at VCC = 3.3 V and Tamb = 25 °C. [2] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [3] This is the increase in supply current for each input that is at the specified LVTTL voltage level rather than VCC or GND. GTL2008_GTL2107_2 Product data sheet © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 02 — 26 September 2006 9 of 20 GTL2008; GTL2107 Philips Semiconductors GTL translator with power good control and high-impedance outputs 12. Dynamic characteristics Table 13. Dynamic characteristics VCC = 3.3 V ± 0.3 V Symbol Parameter Conditions Min Typ[1] Max Unit nA to nBI; see Figure 4 1 4 8 ns 9BI to 9AO; see Figure 5 2 5.5 10 ns nBI to nA or nAO (open-drain outputs); see Figure 14 2 13 18 ns Vref = 0.73 V; VTT = 1.1 V tPLH tPHL LOW-to-HIGH propagation delay HIGH-to-LOW propagation delay 9BI to 10BOn 2 6 11 ns 11A to 11BO; see Figure 10 1 4 8 ns 11BI to 11A; see Figure 9 2 7.5 11 ns 11BI to 11BO 2 8 13 ns 5BI to 7BO1 or 6BI to 7BO2; see Figure 7 4 7 12 ns nA to nBI; see Figure 4 2 5.5 10 ns 9BI to 9AO; see Figure 5 2 5.5 10 ns nBI to nA or nAO (open-drain outputs); see Figure 14 2 4 10 ns 9BI to 10BOn 2 6 11 ns 11A to 11BO; see Figure 10 1 5.5 10 ns 2 8.5 13 ns 2 14 21 ns 5BI to 7BO1 or 6BI to 7BO2; see Figure 7 100 205 350 ns EN1 to nAO or EN2 to nAO; see Figure 8 1 3 10 ns EN1 to 5A (I/O) or EN2 to 6A (I/O); see Figure 8 1 3 7 ns EN1 to nAO or EN2 to nAO; see Figure 8 2 7 10 ns EN1 to 5A (I/O) or EN2 to 6A (I/O); see Figure 8 2 7 10 ns 11BI to 11A; see Figure 9 11BI to 11BO tPLZ tPZL LOW to OFF-state propagation delay OFF-state to LOW propagation delay [2] tPHZ HIGH to OFF-state propagation delay EN2 to 9AO; see Figure 11 2 5 10 ns tPZH OFF-state to HIGH propagation delay EN2 to 9AO; see Figure 11 1 4 10 ns GTL2008_GTL2107_2 Product data sheet © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 02 — 26 September 2006 10 of 20 GTL2008; GTL2107 Philips Semiconductors GTL translator with power good control and high-impedance outputs Table 13. Dynamic characteristics …continued VCC = 3.3 V ± 0.3 V Symbol Parameter Conditions Min Typ[1] Max Unit nA to nBI; see Figure 4 1 4 8 ns Vref = 0.76 V; VTT = 1.2 V LOW-to-HIGH propagation delay tPLH HIGH-to-LOW propagation delay tPHL 9BI to 9AO; see Figure 5 2 5.5 10 ns nBI to nA or nAO (open-drain outputs); see Figure 14 2 13 18 ns 9BI to 10BOn 2 6 11 ns 11A to 11BO; see Figure 10 1 4 8 ns 11BI to 11A; see Figure 9 2 7.5 11 ns 11BI to 11BO 2 8 13 ns 5BI to 7BO1 or 6BI to 7BO2; see Figure 7 4 7 12 ns nA to nBI; see Figure 4 2 5.5 10 ns 9BI to 9AO; see Figure 5 2 5.5 10 ns nBI to nA or nAO (open-drain outputs); see Figure 14 2 4 10 ns 9BI to 10BOn 2 6 11 ns 11A to 11BO; see Figure 10 1 5.5 10 ns 2 8.5 13 ns 11BI to 11A; see Figure 9 2 14 21 ns 5BI to 7BO1 or 6BI to 7BO2; see Figure 7 100 205 350 ns EN1 to nAO or EN2 to nAO; see Figure 8 1 3 10 ns EN1 to 5A (I/O) or EN2 to 6A (I/O); see Figure 8 1 3 7 ns EN1 to nAO or EN2 to nAO; see Figure 8 2 7 10 ns EN1 to 5A (I/O) or EN2 to 6A (I/O); see Figure 8 2 7 10 ns 11BI to 11BO LOW to OFF-state propagation delay tPLZ OFF-state to LOW propagation delay tPZL [2] tPHZ HIGH to OFF-state propagation delay EN2 to 9AO; see Figure 11 2 5 10 ns tPZH OFF-state to HIGH propagation delay EN2 to 9AO; see Figure 11 2 4 10 ns [1] All typical values are at VCC = 3.3 V and Tamb = 25 °C. [2] Includes ~7.6 ns RC rise time of test load pull-up on 11A, 1.5 kΩ pull-up and 21 pF load on 11A has about 23 ns RC rise time. GTL2008_GTL2107_2 Product data sheet © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 02 — 26 September 2006 11 of 20 GTL2008; GTL2107 Philips Semiconductors GTL translator with power good control and high-impedance outputs 12.1 Waveforms VM = 1.5 V at VCC ≥ 3.0 V for A ports; VM = Vref for B ports. 3.0 V input 1.5 V 1.5 V 0V tPLH tp tPHL VTT VOH VM output VM Vref Vref VOL 0V 002aab000 002aaa999 VM = 1.5 V for A port and Vref for B port A port to B port a. Pulse duration b. Propagation delay times Fig 4. Voltage waveforms VTT input Vref Vref VTT input 1/ V 3 TT tPLH tPHL Vref Vref tPZL tPLZ 1/ V 3 TT VOH 1.5 V output 1.5 V VCC output 1.5 V VOL + 0.3 V VOL 002aab001 002aab002 PRR ≤ 10 MHz; Zo = 50 Ω; tr ≤ 2.5 ns; tf ≤ 2.5 ns Fig 5. Propagation delay, 9BI to 9AO Fig 6. nBI to nA (I/O) or nBI to nAO open-drain outputs VTT input Vref Vref tPLH tPHL 3.0 V input 1/ V 3 TT 1.5 V 1.5 V tPLZ tPZL 0V VTT output Vref VOH output Vref VOL 002aac195 Fig 7. 5BI to 7BO1 or 6BI to 7BO2 1.5 V VOL 002aab005 Fig 8. EN1 to 5A (I/O) or EN2 to 6A (I/O) or EN1 to nAO or EN2 to nAO GTL2008_GTL2107_2 Product data sheet VOL + 0.3 V © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 02 — 26 September 2006 12 of 20 GTL2008; GTL2107 Philips Semiconductors GTL translator with power good control and high-impedance outputs VTT input Vref Vref tPLZ tPZL 3.0 V input 1.5 V 1.5 V 0V 0V tPLH tPHL VTT VOH output VOL + 0.3 V output 1.5 V Vref Vref VOL VOL 002aac196 002aac197 Fig 9. 11BI to 11A Fig 10. 11A to 11BO 3.0 V input 1.5 V 1.5 V tPHZ tPZH 0V VOH output VOL + 0.3 V 1.5 V VOL 002aab980 Fig 11. EN2 to 9AO GTL2008_GTL2107_2 Product data sheet © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 02 — 26 September 2006 13 of 20 GTL2008; GTL2107 Philips Semiconductors GTL translator with power good control and high-impedance outputs 13. Test information VCC PULSE GENERATOR VI VO DUT RL 500 Ω CL 50 pF RT 002aab981 Fig 12. Load circuit for A outputs (9AO) VTT VCC 50 Ω VI PULSE GENERATOR VO DUT CL 30 pF RT 002aab264 Fig 13. Load circuit for B outputs VCC VCC PULSE GENERATOR VI RL 1.5 kΩ VO DUT CL 21 pF RT 002aab265 Fig 14. Load circuit for open-drain LVTTL I/O and open-drain outputs 6V VCC PULSE GENERATOR VI RL 500 Ω VO DUT RT CL 50 pF RL 500 Ω 002aab982 Fig 15. Load circuit for 9AO OFF-state to LOW and LOW to OFF-state RL — Load resistor CL — Load capacitance; includes jig and probe capacitance RT — Termination resistance; should be equal to Zo of pulse generators. GTL2008_GTL2107_2 Product data sheet © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 02 — 26 September 2006 14 of 20 GTL2008; GTL2107 Philips Semiconductors GTL translator with power good control and high-impedance outputs 14. Package outline TSSOP28: plastic thin shrink small outline package; 28 leads; body width 4.4 mm D SOT361-1 E A X c HE y v M A Z 15 28 Q A2 (A 3) A1 pin 1 index A θ Lp 1 L 14 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 9.8 9.6 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.8 0.5 8 o 0 o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT361-1 REFERENCES IEC JEDEC JEITA MO-153 EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 16. Package outline SOT361-1 (TSSOP28) GTL2008_GTL2107_2 Product data sheet © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 02 — 26 September 2006 15 of 20 GTL2008; GTL2107 Philips Semiconductors GTL translator with power good control and high-impedance outputs 15. Soldering 15.1 Introduction to soldering surface mount packages There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended. 15.2 Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Driven by legislation and environmental forces the worldwide use of lead-free solder pastes is increasing. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 seconds and 200 seconds depending on heating method. Typical reflow temperatures range from 215 °C to 260 °C depending on solder paste material. The peak top-surface temperature of the packages should be kept below: Table 14. SnPb eutectic process - package peak reflow temperatures (from J-STD-020C July 2004) Package thickness Volume mm3 < 350 Volume mm3 ≥ 350 < 2.5 mm 240 °C + 0/−5 °C 225 °C + 0/−5 °C ≥ 2.5 mm 225 °C + 0/−5 °C 225 °C + 0/−5 °C Table 15. Pb-free process - package peak reflow temperatures (from J-STD-020C July 2004) Package thickness Volume mm3 < 350 Volume mm3 350 to 2000 Volume mm3 > 2000 < 1.6 mm 260 °C + 0 °C 260 °C + 0 °C 260 °C + 0 °C 1.6 mm to 2.5 mm 260 °C + 0 °C 250 °C + 0 °C 245 °C + 0 °C ≥ 2.5 mm 250 °C + 0 °C 245 °C + 0 °C 245 °C + 0 °C Moisture sensitivity precautions, as indicated on packing, must be respected at all times. 15.3 Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results: • Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. • For packages with leads on two sides and a pitch (e): GTL2008_GTL2107_2 Product data sheet © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 02 — 26 September 2006 16 of 20 GTL2008; GTL2107 Philips Semiconductors GTL translator with power good control and high-impedance outputs – larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; – smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. • For packages with leads on four sides, the footprint must be placed at a 45° angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time of the leads in the wave ranges from 3 seconds to 4 seconds at 250 °C or 265 °C, depending on solder material applied, SnPb or Pb-free respectively. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 15.4 Manual soldering Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. When using a dedicated tool, all other leads can be soldered in one operation within 2 seconds to 5 seconds between 270 °C and 320 °C. 15.5 Package related soldering information Table 16. Suitability of surface mount IC packages for wave and reflow soldering methods Package[1] Soldering method Wave Reflow[2] BGA, HTSSON..T[3], LBGA, LFBGA, SQFP, SSOP..T[3], TFBGA, VFBGA, XSON not suitable suitable DHVQFN, HBCC, HBGA, HLQFP, HSO, HSOP, HSQFP, HSSON, HTQFP, HTSSOP, HVQFN, HVSON, SMS not suitable[4] suitable PLCC[5], SO, SOJ suitable suitable not recommended[5][6] suitable SSOP, TSSOP, VSO, VSSOP not recommended[7] suitable CWQCCN..L[8], not suitable LQFP, QFP, TQFP PMFP[9], WQCCN..L[8] [1] For more detailed information on the BGA packages refer to the (LF)BGA Application Note (AN01026); order a copy from your Philips Semiconductors sales office. [2] All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods. GTL2008_GTL2107_2 Product data sheet not suitable © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 02 — 26 September 2006 17 of 20 GTL2008; GTL2107 Philips Semiconductors GTL translator with power good control and high-impedance outputs [3] These transparent plastic packages are extremely sensitive to reflow soldering conditions and must on no account be processed through more than one soldering cycle or subjected to infrared reflow soldering with peak temperature exceeding 217 °C ± 10 °C measured in the atmosphere of the reflow oven. The package body peak temperature must be kept as low as possible. [4] These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. [5] If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. [6] Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. [7] Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. [8] Image sensor packages in principle should not be soldered. They are mounted in sockets or delivered pre-mounted on flex foil. However, the image sensor package can be mounted by the client on a flex foil by using a hot bar soldering process. The appropriate soldering profile can be provided on request. [9] Hot bar soldering or manual soldering is suitable for PMFP packages. 16. Abbreviations Table 17. Abbreviations Acronym Description CDM Charged Device Model CMOS Complementary Metal Oxide Semiconductor CPU Central Processing Unit DUT Device Under Test ESD ElectroStatic Discharge GTL Gunning Transceiver Logic HBM Human Body Model LVTTL Low Voltage Transistor-Transistor Logic MM Machine Model PRR Pulse Rate Repetition TTL Transistor-Transistor Logic VRD Voltage Regulator Down 17. Revision history Table 18. Revision history Document ID Release date Data sheet status Change notice Supersedes GTL2008_GTL2107_2 20060926 Product data sheet - GTL2008_1 Modifications: GTL2008_1 • • • Added type number GTL2017 • Table 10 “Limiting values”: removed (old) Table note 1 (information is now in Section 18 “Legal information”) • added “DUT” to Table 17 “Abbreviations” Section 1 “General description”: added new 7th paragraph Section 4 “Ordering information”: added type number GTL2107PW to Table 2 “Ordering information” and following paragraph 20060502 Product data sheet GTL2008_GTL2107_2 Product data sheet - © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 02 — 26 September 2006 18 of 20 GTL2008; GTL2107 Philips Semiconductors GTL translator with power good control and high-impedance outputs 18. Legal information 18.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.semiconductors.philips.com. 18.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. Philips Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local Philips Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 18.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, Philips Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — Philips Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — Philips Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of a Philips Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. Philips Semiconductors accepts no liability for inclusion and/or use of Philips Semiconductors products in such equipment or applications and therefore such inclusion and/or use is for the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — Philips Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.semiconductors.philips.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by Philips Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 18.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 19. Contact information For additional information, please visit: http://www.semiconductors.philips.com For sales office addresses, send an email to: [email protected] GTL2008_GTL2107_2 Product data sheet © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 02 — 26 September 2006 19 of 20 GTL2008; GTL2107 Philips Semiconductors GTL translator with power good control and high-impedance outputs 20. Contents 1 2 3 4 5 6 6.1 6.2 7 7.1 8 9 10 11 12 12.1 13 14 15 15.1 15.2 15.3 15.4 15.5 16 17 18 18.1 18.2 18.3 18.4 19 20 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 5 Function tables . . . . . . . . . . . . . . . . . . . . . . . . . 5 Application design-in information . . . . . . . . . . 7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 8 Recommended operating conditions. . . . . . . . 8 Static characteristics. . . . . . . . . . . . . . . . . . . . . 9 Dynamic characteristics . . . . . . . . . . . . . . . . . 10 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Test information . . . . . . . . . . . . . . . . . . . . . . . . 14 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 15 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Introduction to soldering surface mount packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 16 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 16 Manual soldering . . . . . . . . . . . . . . . . . . . . . . 17 Package related soldering information . . . . . . 17 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 18 Legal information. . . . . . . . . . . . . . . . . . . . . . . 19 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 19 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Contact information. . . . . . . . . . . . . . . . . . . . . 19 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © Koninklijke Philips Electronics N.V. 2006. All rights reserved. For more information, please visit: http://www.semiconductors.philips.com. For sales office addresses, email to: [email protected]. Date of release: 26 September 2006 Document identifier: GTL2008_GTL2107_2