TI1 CDCVF2310-EP 2.5-v to 3.3-v high-performance clock buffer Datasheet

CDCVF2310-EP
www.ti.com
SCAS934 – DECEMBER 2012
2.5-V TO 3.3-V HIGH-PERFORMANCE CLOCK BUFFER
Check for Samples: CDCVF2310-EP
FEATURES
1
•
•
•
•
•
•
High-Performance 1:10 Clock Driver
Operates up to 200 MHz at VDD 3.3 V
Pin-to-Pin Skew < 100 ps at VDD 3.3 V
VDD Range: 2.3 V to 3.6 V
Output Enable Glitch Suppression
Distributes One Clock Input to Two Banks of
Five Outputs
25-Ω On-Chip Series Damping Resistors
Packaged in 24-Pin TSSOP
•
•
APPLICATIONS
•
General-Purpose Applications
PW PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
GND
VDD
1Y0
1Y1
1Y2
GND
GND
1Y3
1Y4
VDD
1G
2Y4
24
23
22
21
20
19
18
17
16
15
14
13
CLK
VDD
VDD
2Y0
2Y1
GND
GND
2Y2
2Y3
VDD
VDD
2G
SUPPORTS DEFENSE, AEROSPACE,
AND MEDICAL APPLICATIONS
•
•
•
•
Controlled Baseline
One Assembly and Test Site
One Fabrication Site
Available in Military (–55°C to 125°C)
Temperature Range (1)
Extended Product Life Cycle
Extended Product-Change Notification
Product Traceability
•
•
•
(1)
Custom temperature ranges available
DESCRIPTION
The CDCVF2310 is a high-performance, low-skew clock buffer that operates up to 200 MHz. Two banks of five
outputs each provide low-skew copies of CLK. After power up, the default state of the outputs is low regardless
of the state of the control pins. For normal operation, the outputs of bank 1Y[0:4] or 2Y[0:4] can be placed in a
low state when the control pins (1G or 2G, respectively) are held low and a negative clock edge is detected on
the CLK input. The outputs of bank 1Y[0:4] or 2Y[0:4] can be switched into the buffer mode when the control pins
(1G and 2G) are held high and a negative clock edge is detected on the CLK input. The device operates in a
2.5-V and 3.3-V environment. The built-in output enable glitch suppression ensures a synchronized output enable
sequence to distribute full period clock signals.
The CDCVF2310 is characterized for operation from –55°C to 125°C.
Table 1. ORDERING INFORMATION (1)
TJ
–55°C to 125°C
(1)
PACKAGE
ORDERABLE PART NUMBER
TOP-SIDE MARKING
VID NUMBER
CDCVF2310MPWREP
CKV2310EP
V62/13603-01XE
CDCVF2310MPWEP
CKV2310EP
V62/13603-01XE-T
TSSOP - PW
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
Web site at www.ti.com.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2012, Texas Instruments Incorporated
CDCVF2310-EP
SCAS934 – DECEMBER 2012
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
FUNCTIONAL BLOCK DIAGRAM
3
1Y0
25 Ω
4
1Y1
25 Ω
5
1Y2
25 Ω
8
1Y3
25 Ω
9
1Y4
25 Ω
1G
2G
11
Logic Control
13
Logic Control
21
CLK
24
25 Ω
20
25 Ω
17
25 Ω
16
25 Ω
12
25 Ω
2
Submit Documentation Feedback
2Y0
2Y1
2Y2
2Y3
2Y4
Copyright © 2012, Texas Instruments Incorporated
Product Folder Links: CDCVF2310-EP
CDCVF2310-EP
www.ti.com
SCAS934 – DECEMBER 2012
Table 2. FUNCTION TABLE
INPUT
(1)
OUTPUT
1G
2G
CLK
1Y[0:4]
2Y[0:4]
L
L
L
↓
L
H
L
↓
CLK (1)
L
L
H
↓
L
CLK (1)
H
H
↓
CLK (1)
CLK (1)
After detecting one negative edge on the CLK input, the output
follows the input CLK if the control pin is held high.
Terminal Functions
TERMINAL
NAME
I/O
NO.
DESCRIPTION
1G
11
I
Output enable control for 1Y[0:4] outputs. This output enable is active-high, meaning the
1Y[0:4] clock outputs follow the input clock (CLK) if this pin is logic high.
2G
13
I
Output enable control for 2Y[0:4] outputs. This output enable is active-high, meaning the
2Y[0:4] clock outputs follow the input clock (CLK) if this pin is logic high.
1Y[0:4]
3, 4, 5, 8, 9
O
Buffered output clocks
2Y[0:4]
21, 20, 17, 16, 12
O
Buffered output clocks
24
I
Input reference frequency
CLK
GND
1, 6, 7, 18, 19
VDD
2, 10, 14, 15, 22, 23
Ground
DC power supply, 2.3 V – 3.6 V
ABSOLUTE MAXIMUM RATINGS
over operating junction temperature range (unless otherwise noted)
(1)
Supply voltage range, VDD
Input voltage range, VI
–0.5 V to 4.6 V
(2) (3)
Output voltage range, VO
–0.5 V to VDD + 0.5 V
(2) (3)
–0.5 V to VDD + 0.5 V
Input clamp current, IIK (VI < 0 or VI> VDD)
±50 mA
Output clamp current, IOK (VO < 0 or VO > VDD)
±50 mA
Continuous total output current, IO (VO = 0 to VDD)
±50 mA
Storage temperature range Tstg
(1)
(2)
(3)
–65°C to 150°C
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output negative voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
This value is limited to 4.6 V maximum.
Submit Documentation Feedback
Copyright © 2012, Texas Instruments Incorporated
Product Folder Links: CDCVF2310-EP
3
CDCVF2310-EP
SCAS934 – DECEMBER 2012
www.ti.com
THERMAL INFORMATION
CDCVF2310
THERMAL METRIC (1)
PW
UNITS
24 PINS
Junction-to-ambient thermal resistance (2)
θJA
91.7
(3)
θJCtop
Junction-to-case (top) thermal resistance
θJB
Junction-to-board thermal resistance (4)
46.4
ψJT
Junction-to-top characterization parameter (5)
1.5
ψJB
Junction-to-board characterization parameter (6)
45.8
θJCbot
Junction-to-case (bottom) thermal resistance (7)
N/A
(1)
(2)
(3)
(4)
(5)
(6)
(7)
31.2
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
Spacer
RECOMMENDED OPERATING CONDITIONS
(1)
Supply voltage, VDD
Low-level input voltage, VIL
High-level input voltage, VIH
High-level output current, IOH
Low-level output current, IOL
NOM
2.3
2.5
MAX
3.6
VDD = 3 V to 3.6 V
0.8
VDD = 2.3 V to 2.7 V
0.7
VDD = 3 V to 3.6 V
VDD = 2.3 V to 2.7 V
2
0
VDD
12
VDD = 2.3 V to 2.7 V
6
VDD = 3 V to 3.6 V
12
VDD = 2.3 V to 2.7 V
6
–55
UNIT
V
V
V
1.7
VDD = 3 V to 3.6 V
Operating junction temperature, TJ
4
MIN
3.3
Input voltage, VI
(1)
°C/W
125
V
mA
mA
°C
Unused inputs must be held high or low to prevent them from floating.
Submit Documentation Feedback
Copyright © 2012, Texas Instruments Incorporated
Product Folder Links: CDCVF2310-EP
CDCVF2310-EP
www.ti.com
SCAS934 – DECEMBER 2012
ELECTRICAL CHARACTERISTICS
over recommended operating junction temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VIK
Input voltage
VDD = 3 V,
II
Input current
VI = 0 V or VDD
IDD
(2)
MIN
TYP (1)
II = –18 mA
MAX
UNIT
–1.2
V
±5
μA
100
μA
Static device current
CLK = 0 V or VDD,
IO = 0 mA
CI
Input capacitance
VDD = 2.3 V to 3.6 V,
VI = 0 V or VDD
2.5
pF
CO
Output capacitance
VDD = 2.3 V to 3.6 V,
VI = 0 V or VDD
2.8
pF
VDD = min to max,
IOH = –100 μA
VDD – 0.2
IOH = –12 mA
2.1
IOH = –6 mA
2.4
VDD = 3.3 V ±0.3 V
VOH
High-level output voltage
VDD = 3 V
VDD = min to max,
VOL
IOH
IOL
Low-level output voltage
High-level output current
Low-level output current
VDD = 3 V
V
IOL = –100 μA
0.2
IOL = 12 mA
0.8
IOL = 6 mA
0.55
VDD = 3 V,
VO = 1 V
VDD = 3.3 V,
VO = 1.65 V
VDD = 3.6 V,
VO = 3.135 V
VDD = 3 V,
VO = 1.95 V
VDD = 3.3 V,
VO = 1.65 V
VDD = 3.6 V,
VO = 0.4 V
VDD = min to max,
IOH = –100 μA
VDD = 2.3 V
IOH = –6 mA
VDD = min to max,
IOL = 100 μA
VDD = 2.3 V
IOL = 6 mA
VDD = 2.3 V,
VO = 1 V
VDD = 2.5 V,
VO = 1.25 V
VDD = 2.7 V,
VO = 2.375 V
VDD = 2.3 V,
VO = 1.2 V
VDD = 2.5 V,
VO = 1.25 V
VDD = 2.7 V,
VO = 0.3 V
V
–28
–36
mA
–14
28
36
mA
14
VDD = 2.5 V ±0.2 V
VOH
High-level output voltage
VOL
Low-level output voltage
IOH
IOL
(1)
(2)
High-level output current
Low-level output current
VDD – 0.2
V
1.8
0.2
0.55
V
–15
–25
mA
–10
15
25
mA
10
All typical values are at respective nominal VDD.
For ICC over frequency, see Figure 6.
Submit Documentation Feedback
Copyright © 2012, Texas Instruments Incorporated
Product Folder Links: CDCVF2310-EP
5
CDCVF2310-EP
SCAS934 – DECEMBER 2012
www.ti.com
TIMING REQUIREMENTS
over recommended ranges of supply voltage and operating junction temperature
MIN NOM
fclk
Clock frequency
MAX
VDD = 3 V to 3.6 V
0
200
VDD = 2.3 V to 2.7 V
0
170
UNIT
MHz
JITTER CHARACTERISTICS
Characterized using CDCVF2310 Performance EVM when VDD=3.3 V. Outputs not under test are terminated to 50 Ω.
PARAMETER
tjitter
TEST CONDITIONS
Additive phase jitter from input to output 1Y0
MIN
TYP
12 kHz to 5 MHz, fout = 30.72 MHz
52
12 kHz to 20 MHz, fout = 125 MHz
45
MAX
UNIT
fs rms
SWITCHING CHARACTERISTICS
over recommended operating junction temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VDD = 3.3 V ±0.3 V (see Figure 2)
tPLH
f = 0 MHz to 200 MHz
For circuit load, see Figure 2.
CLK to Yn
tPHL
(1)
1.3
(see Figure 4)
3.3
ns
100
ps
ps
tsk(o)
Output skew (Ym to Yn)
tsk(p)
Pulse skew (see Figure 5)
570
tsk(pp)
Part-to-part skew
500
ps
tr
Rise time (see Figure 3)
VO = 0.4 V to 2 V
0.7
2.2
V/ns
tf
Fall time (see Figure 3)
VO = 2 V to 0.4 V
0.7
2.2
V/ns
tsu(en)
Enable setup time, G_high before CLK ↓
0.1
ns
tsu(dis)
Disable setup time, G_low before CLK ↓
0.1
ns
th(en)
Enable hold time, G_high after CLK ↓
0.4
ns
th(dis)
Disable hold time, G_low after CLK ↓
0.4
ns
VDD = 2.5 V ±0.2 V (see Figure 2)
tPLH
f = 0 MHz to 170 MHz
For circuit load, see Figure 2.
CLK to Yn
tPHL
(1)
1.5
ns
170
ps
680
ps
tsk(o)
Output skew (Ym to Yn)
tsk(p)
Pulse skew (see Figure 5)
tsk(pp)
Part-to-part skew
600
ps
tr
Rise time (see Figure 3)
VO = 0.4 V to 1.7 V
0.5
1.4
V/ns
tf
Fall time (see Figure 3)
VO = 1.7 V to 0.4 V
0.5
1.4
V/ns
tsu(en)
Enable setup time, G_high before CLK ↓
0.1
ns
tsu(dis)
Disable setup time, G_low before CLK ↓
0.1
ns
th(en)
Enable hold time, G_high after CLK ↓
0.4
ns
th(dis)
Disable hold time, G_low after CLK ↓
0.4
ns
(1)
6
(see Figure 4 )
4
The tsk(o) specification is only valid for equal loading of all outputs.
Submit Documentation Feedback
Copyright © 2012, Texas Instruments Incorporated
Product Folder Links: CDCVF2310-EP
CDCVF2310-EP
www.ti.com
SCAS934 – DECEMBER 2012
DETAILED DESCRIPTION
Output Enable Glitch Suppression Circuit
The purpose of the glitch suppression circuitry is to ensure the output enable sequence is synchronized with the
clock input such that the output buffer is enabled or disabled on the next full period of the input clock (negative
edge triggered by the input clock) (see Figure 1).
The G input must fulfill the timing requirements (tsu, th) according to the Switching Characteristics table for
predictable operation.
CLK
Gn
Yn
tsu(en)
th(en)
a) Enable Mode
CLK
Gn
Yn
tsu(dis)
th(dis)
b) Disable Mode
Figure 1. Enable and Disable Mode Relative to CLK↓
Submit Documentation Feedback
Copyright © 2012, Texas Instruments Incorporated
Product Folder Links: CDCVF2310-EP
7
CDCVF2310-EP
SCAS934 – DECEMBER 2012
www.ti.com
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
500 Ω
CL = 25 pF on Yn
A.
CL includes probe and jig capacitance.
B.
All input pulses are supplied by generators having the following characteristics: PRR ≤ 200 MHz, ZO = 50 Ω,
tr < 1.2 ns, tf < 1.2 ns.
Figure 2. Test Load Circuit
VDD
50% VDD
0V
CLK
tPLH
tPHL
1.7 V or 2 V
Yn
0.4 V
0.4 V
tr
VOH
50% VDD
VOL
tf
Figure 3. Voltage Waveforms Propagation Delay Times
VDD
CLK
0V
VOH
50% VDD
Any Y
VOL
VOH
50% VDD
Any Y
VOL
tsk(o)
tsk(o)
Figure 4. Output Skew
VDD
50% VDD
CLK
0V
tPLH
tPHL
VOH
Yn
50% VDD
VOL
NOTE: tsk(p) = | tPLH − tPHL |
Figure 5. Pulse Skew
8
Submit Documentation Feedback
Copyright © 2012, Texas Instruments Incorporated
Product Folder Links: CDCVF2310-EP
CDCVF2310-EP
www.ti.com
SCAS934 – DECEMBER 2012
PARAMETER MEASUREMENT INFORMATION (continued)
SUPPLY CURRENT
vs
FREQUENCY
220
VDD = 2.3 V to 3.6 V
CL(Yn) = 25 pF || 500 Ω
All Outputs Switching
TA = –40°C to 85°C
200
ICC – Supply Current – mA
180
VDD = 3.6 V
TA = –40°C
VDD = 3.6 V
TA = 85°C
160
140
120
100
80
VDD = 2.3 V
TA = 85°C
60
VDD = 2.3 V
TA = –40°C
40
20
0
0
20
40
60
80
100
120
140
160
180
200
f – Frequency – MHz
Figure 6.
Submit Documentation Feedback
Copyright © 2012, Texas Instruments Incorporated
Product Folder Links: CDCVF2310-EP
9
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
(4)
CDCVF2310MPWEP
ACTIVE
TSSOP
PW
24
60
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
CKV2310EP
CDCVF2310MPWREP
ACTIVE
TSSOP
PW
24
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
CKV2310EP
V62/13603-01XE
ACTIVE
TSSOP
PW
24
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
CKV2310EP
V62/13603-01XE-T
ACTIVE
TSSOP
PW
24
60
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
CKV2310EP
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
OTHER QUALIFIED VERSIONS OF CDCVF2310-EP :
• Catalog: CDCVF2310
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
13-Sep-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
CDCVF2310MPWREP
Package Package Pins
Type Drawing
TSSOP
PW
24
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2000
330.0
16.4
Pack Materials-Page 1
6.95
B0
(mm)
K0
(mm)
P1
(mm)
8.3
1.6
8.0
W
Pin1
(mm) Quadrant
16.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
13-Sep-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
CDCVF2310MPWREP
TSSOP
PW
24
2000
367.0
367.0
38.0
Pack Materials-Page 2
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and
complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale
supplied at the time of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
performed.
TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and
applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information
published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or
endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration
and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered
documentation. Information of third parties may be subject to additional restrictions.
Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service
voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.
TI is not responsible or liable for any such statements.
Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements
concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support
that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which
anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause
harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use
of any TI components in safety-critical applications.
In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to
help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and
requirements. Nonetheless, such components are subject to these terms.
No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties
have executed a special agreement specifically governing such use.
Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in
military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components
which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and
regulatory requirements in connection with such use.
TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of
non-designated products, TI will not be responsible for any failure to meet ISO/TS16949.
Products
Applications
Audio
www.ti.com/audio
Automotive and Transportation
www.ti.com/automotive
Amplifiers
amplifier.ti.com
Communications and Telecom
www.ti.com/communications
Data Converters
dataconverter.ti.com
Computers and Peripherals
www.ti.com/computers
DLP® Products
www.dlp.com
Consumer Electronics
www.ti.com/consumer-apps
DSP
dsp.ti.com
Energy and Lighting
www.ti.com/energy
Clocks and Timers
www.ti.com/clocks
Industrial
www.ti.com/industrial
Interface
interface.ti.com
Medical
www.ti.com/medical
Logic
logic.ti.com
Security
www.ti.com/security
Power Mgmt
power.ti.com
Space, Avionics and Defense
www.ti.com/space-avionics-defense
Microcontrollers
microcontroller.ti.com
Video and Imaging
www.ti.com/video
RFID
www.ti-rfid.com
OMAP Applications Processors
www.ti.com/omap
TI E2E Community
e2e.ti.com
Wireless Connectivity
www.ti.com/wirelessconnectivity
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2015, Texas Instruments Incorporated