ATMEL ATAR892X-YYY-TKQYZ Low-current microcontroller for wireless communication Datasheet

Features
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4-Kbyte ROM, 256 × 4-bit RAM
16 Bidirectional I/Os
Up to 7 External/Internal Interrupt Sources
Multifunction Timer/Counter with
IR Remote Control Carrier Generator
Bi-phase-, Manchester- and Pulse-width Modulator and Demodulator
Phase Control Function
Programmable System Clock with Prescaler and Five Different Clock Sources
Wide Supply-voltage Range (1.8V to 6.5V)
Very Low Sleep Current (< 1 µA)
32 × 16-bit EEPROM (ATAR092 only)
Synchronous Serial Interface (2-wire, 3-wire)
Watchdog, POR and Brown-out Function
Voltage Monitoring Inclusive Lo_BAT Detect
Flash Controller ATAM893 Available (SSO20)
1. Description
The ATAR092 and ATAR892 are members of Atmel ®’s family of 4-bit single-chip
microcontrollers. They offer highest integration for IR and RF data communication,
remote-control and phase-control applications. The ATAR092 and ATAR892 are suitable for the transmitter side as well as the receiver side. They contain ROM, RAM,
parallel I/O ports, two 8-bit programmable multifunction timer/counters with modulator
and demodulator function, voltage supervisor, interval timer with watchdog function
and a sophisticated on-chip clock generation with external clock input, integrated RC-,
32-kHz crystal- and 4-MHz crystal-oscillators. The ATAR892 has an additional
EEPROM as a second chip in one package.
Figure 1-1.
Low-current
Microcontroller
for Wireless
Communication
ATAR092
ATAR892
Block Diagram
VSS
VDD
Brown-out Protect
RESET
OSC1 OSC2
RC
Crystal
Oscillators Oscillators
Voltage Monitor
External Input
External
Clock Input
Clock Management
Port 1
BP13
ROM
RAM
4 K x 8 bit
256 x 4 bit
Timer 1
Interval- and
Watchdog Timer
Timer 2
8/12-bit Timer
with Modulator
VMI
BP10
UTCM
SSI
Serial Interface
BP22
Port 2
BP21
MARC4
Data Direction
BP20/NTE
Timer 3
8-bit
Timer/Counter
with Modulator
and Demodulator
4-bit CPU Core
I/O Bus
T2I
T2O
SD
SC
T3O
T3I
BP23
Data Direction +
Alternate Function
Data Direction +
Interrupt Control
Data Direction +
Alternate Function
Port 4
Port 5
Port 6
BP42
BP40
INT3
T2O
SC
BP41
BP43
VMI
INT3
T2I
SD
BP50
INT6
BP52
INT1
BP51
INT6
BP60
T3O
BP53
INT1
BP63
T31
4535E–4BMCU–05/07
2. Pin Configuration
Figure 2-1.
Pinning SSO20
VDD
BP40/INT3/SC
BP53/INT1
BP52/INT1
BP51/INT6
BP50/INT6
OSC1
OSC2
BP60/T3O
BP10
Table 2-1.
2
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
VSS
BP43/INT3/SD
BP42/T2O
BP41/VMI/T2I
BP23
BP22
BP21
BP20/NTE
BP63/T3I
BP13
Pin Description
Name
Type
Function
Alternate Function
Pin No.
Reset State
VDD
–
Supply voltage
–
1
NA
VSS
–
Circuit ground
–
20
NA
BP10
I/O
Bidirectional I/O line of Port 1.0
–
10
Input
BP13
I/O
Bidirectional I/O line of Port 1.3
–
11
Input
BP20
I/O
Bidirectional I/O line of Port 2.0
NTE-test mode enable, see section “Master Reset”
13
Input
BP21
I/O
Bidirectional I/O line of Port 2.1
–
14
Input
BP22
I/O
Bidirectional I/O line of Port 2.2
–
15
Input
BP23
I/O
Bidirectional I/O line of Port 2.3
–
16
Input
BP40
I/O
Bidirectional I/O line of Port 4.0
SC-serial clock or INT3 external interrupt input
2
Input
BP41
I/O
Bidirectional I/O line of Port 4.1
VMI voltage monitor input or T2I external clock
input Timer 2
17
Input
BP42
I/O
Bidirectional I/O line of Port 4.2
T2O Timer 2 output
18
Input
BP43
I/O
Bidirectional I/O line of Port 4.3
SD serial data I/O or INT3-external interrupt input
19
Input
BP50
I/O
Bidirectional I/O line of Port 5.0
INT6 external interrupt input
6
Input
BP51
I/O
Bidirectional I/O line of Port 5.1
INT6 external interrupt input
5
Input
BP52
I/O
Bidirectional I/O line of Port 5.2
INT1 external interrupt input
4
Input
BP53
I/O
Bidirectional I/O line of Port 5.3
INT1 external interrupt input
3
Input
BP60
I/O
Bidirectional I/O line of Port 6.0
T3O Timer 3 output
9
Input
BP63
I/O
Bidirectional I/O line of Port 6.3
T3I Timer 3 input
12
Input
7
Input
8
NA
OSC1
I
Oscillator input
4-MHz crystal input or 32-kHz crystal input or
external clock input or external trimming resistor
input
OSC2
O
Oscillator output
4-MHz crystal output or 32-kHz crystal output or
external clock input
ATAR092/ATAR892
4535E–4BMCU–05/07
ATAR092/ATAR892
3. Introduction
The ATAR092/ATAR892 are members of Atmel’s family of 4-bit single-chip microcontrollers.
They contain ROM, RAM, parallel I/O ports, two 8-bit programmable multi-function
timer/counters, voltage supervisor, interval timer with watchdog function and a sophisticated
on-chip clock generation with integrated RC-, 32-kHz crystal- and 4-MHz crystal oscillators.
Table 3-1.
Available Variants of ATAxx9x
Version
Type
ROM
E2PROM Peripheral
Packages
Flash device
ATAM893
4-Kbyte EEPROM
64 byte
SSO20
Production
ATAR092
4-Kbyte mask ROM
–
SSO20
Production
ATAR892
4-Kbyte mask ROM
64 byte
SSO20
4. MARC4 Architecture
4.1
General Description
The MARC4 microcontroller consists of an advanced stack-based, 4-bit CPU core and on-chip
peripherals. The CPU is based on the HARVARD architecture with physically separate program
memory (ROM) and data memory (RAM). Three independent buses, the instruction bus, the
memory bus and the I/O bus, are used for parallel communication between ROM, RAM and
peripherals. This enhances program execution speed by allowing both instruction prefetching,
and a simultaneous communication to the on-chip peripheral circuitry. The extremely powerful
integrated interrupt controller with associated eight prioritized interrupt levels supports fast and
efficient processing of hardware events. The MARC4 is designed for the high-level programming
language qFORTH. The core includes both an expression and a return stack. This architecture
enables high-level language programming without any loss of efficiency or code density.
Figure 4-1.
MARC4 Core
MARC4 CORE
Reset
Program
Memory
Reset
Clock
PC
Instruction
Bus
X
Y
SP
RP
Memory Bus
Instruction
Decoder
System
Clock
Sleep
RAM
256 x 4-bit
TOS
CCR
Interrupt
Controller
ALU
I/O Bus
On-chip Peripheral Modules
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4535E–4BMCU–05/07
4.2
Components of MARC4 Core
The core contains ROM, RAM, ALU, program counter, RAM address registers, instruction
decoder and interrupt controller. The following sections describe each functional block in more
detail.
4.2.1
ROM
The program memory (ROM) is mask programmed with the customer application program during the fabrication of the microcontroller. The 4 Kbyte ROM size is addressed by a 12-bit wide
program counter. An additional 1 Kbyte of ROM exists which is reserved for quality control
self-test software The lowest user ROM address segment is taken up by a 512-byte zero page
which contains predefined start addresses for interrupt service routines and special subroutines
accessible with single byte instructions (SCALL).
The corresponding memory map is shown in Figure 4-2 Look-up tables of constants can also be
held in ROM and are accessed via the MARC4’s built-in table instruction.
Figure 4-2.
ROM Map
1F8h
1F0h
1E8h
1E0h
FFFh
(4 K x 8 Bit)
7FFh
1FFh
Zero Page
000h
4.2.2
SCALL Addresses
ROM
020h
018h
010h
008h
000h
Zero
page
1E0h
INT7
1C0h
INT6
180h
INT5
140h
INT4
100h
INT3
0C0h
INT2
080h
INT1
040h
INT0
008h
000h
$AUTOSLEEP
$RESET
RAM
The ATAR092 and ATAR892 contain 256 x 4-bit wide static random access memory (RAM). It is
used for the expression stack, the return stack and data memory for variables and arrays. The
RAM is addressed by any of the four 8-bit wide RAM address registers SP, RP, X and Y.
4.2.2.1
4
Expression Stack
The 4-bit wide expression stack is addressed with the expression stack pointer (SP). All arithmetic, I/O and memory reference operations take their operands from, and return their results to
the expression stack. The MARC4 performs the operations with the top of stack items (TOS and
TOS-1). The TOS register contains the top element of the expression stack and works in the
same way as an accumulator. This stack is also used for passing parameters between subroutines and as a scratch pad area for temporary storage of data.
ATAR092/ATAR892
4535E–4BMCU–05/07
ATAR092/ATAR892
4.2.2.2
Return Stack
The 12-bit wide return stack is addressed by the return stack pointer (RP). It is used for storing
return addresses of subroutines, interrupt routines and for keeping loop index counts. The return
stack can also be used as a temporary storage area.
The MARC4 instruction set supports the exchange of data between the top elements of the
expression stack and the return stack. The two stacks within the RAM have a user definable
location and maximum depth.
Figure 4-3.
RAM Map
RAM
(256 x 4-bit)
Autosleep
RAM Address Register
FCh
3
FFh
0
TOS
TOS-1
SP
TOS-2
Global
Variables
X
4-bit
Y
SP
TOS-1
Expression
Stack
Return Stack
11
0
RP
04h
Return
Stack
Global
Variables
07h
00h
03h
RP
4.2.3
Expression Stack
12-bit
Registers
The MARC4 controller has seven programmable registers and one condition code register. They
are shown in the following programming model.
4.2.3.1
Program Counter (PC)
The program counter is a 12-bit register which contains the address of the next instruction to be
fetched from the ROM. Instructions currently being executed are decoded in the instruction
decoder to determine the internal micro-operations. For linear code (no calls or branches) the
program counter is incremented with every instruction cycle. If a branch-, call-, return-instruction
or an interrupt is executed, the program counter is loaded with a new address. The program
counter is also used with the table instruction to fetch 8-bit wide ROM constants.
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4535E–4BMCU–05/07
Figure 4-4.
Programming Model
11
0
PC
Program Counter
7
0
0
RP
7
0
Return Stack Pointer
0
SP
Expression Stack Pointer
7
0
7
0
X
RAM Address Register (X)
RAM Address Register (Y)
Y
3
0
3
0
Top of Stack Register
TOS
CCR
C
--
B
I
Condition Code Register
Interrupt Enable
Branch
Reserved
Carry/Borrow
4.2.3.2
RAM Address Registers
The RAM is addressed with the four 8-bit wide RAM address registers: SP, RP, X and Y. These
registers allow access to any of the 256 RAM nibbles.
4.2.3.3
Expression Stack Pointer (SP)
The stack pointer contains the address of the next-to-top 4-bit item (TOS-1) of the expression
stack. The pointer is automatically pre-incremented if a nibble is moved onto the stack or
post-decremented if a nibble is removed from the stack. Every post-decrement operation moves
the item (TOS-1) to the TOS register before the SP is decremented. After a reset the stack
pointer has to be initialized with >SP S0 to allocate the start address of the expression stack
area.
4.2.3.4
Return Stack Pointer (RP)
The return stack pointer points to the top element of the 12-bit wide return stack. The pointer
automatically pre-increments if an element is moved onto the stack, or it post-decrements if an
element is removed from the stack. The return stack pointer increments and decrements in
steps of 4. This means that every time a 12-bit element is stacked, a 4-bit RAM location is left
unwritten. This location is used by the qFORTH compiler to allocate 4-bit variables. After a reset
the return stack pointer has to be initialized via >RP FCh.
4.2.3.5
RAM Address Registers (X and Y)
The X and Y registers are used to address any 4-bit item in the RAM. A fetch operation moves
the addressed nibble onto the TOS. A store operation moves the TOS to the addressed RAM
location. By using either the pre-increment or post-decrement addressing mode arrays in the
RAM can be compared, filled or moved.
6
ATAR092/ATAR892
4535E–4BMCU–05/07
ATAR092/ATAR892
4.2.3.6
Top of Stack (TOS)
The top of stack register is the accumulator of the MARC4. All arithmetic/logic, memory reference and I/O operations use this register. The TOS register receives data from the ALU, ROM,
RAM or I/O bus.
4.2.3.7
Condition Code Register (CCR)
The 4-bit wide condition code register contains the branch, the carry and the interrupt enable
flag. These bits indicate the current state of the CPU. The CCR flags are set or reset by ALU
operations. The instructions SET_BCF, TOG_BF, CCR! and DI allow direct manipulation of the
condition code register.
4.2.3.8
Carry/Borrow (C)
The carry/borrow flag indicates that the borrowing or carrying out of Arithmetic Logic Unit (ALU)
occurred during the last arithmetic operation. During shift and rotate operations, this bit is used
as a fifth bit. Boolean operations have no affect on the C-flag.
4.2.3.9
Branch (B)
The branch flag controls the conditional program branching. Should the branch flag have been
set by a previous instruction, a conditional branch will cause a jump. This flag is affected by
arithmetic, logic, shift, and rotate operations.
4.2.3.10
4.2.4
Interrupt Enable (I)
The interrupt enable flag globally enables or disables the triggering of all interrupt routines with
the exception of the non-maskable reset. After a reset or while executing the DI instruction, the
interrupt enable flag is reset, thus disabling all interrupts. The core will not accept any further
interrupt requests until the interrupt enable flag has been set again by either executing an EI or
SLEEP instruction.
ALU
The 4-bit ALU performs all the arithmetic, logical, shift and rotate operations with the top two elements of the expression stack (TOS and TOS-1) and returns the result to the TOS. The ALU
operations affect the carry/borrow and branch flag in the condition code register (CCR).
Figure 4-5.
ALU Zero-address Operations
RAM
SP
TOS-1
TOS
TOS-2
TOS-3
TOS-4
ALU
CCR
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4535E–4BMCU–05/07
4.2.5
I/O Bus
The I/O ports and the registers of the peripheral modules are I/O mapped. All communication
between the core and the on-chip peripherals takes place via the I/O bus and the associated I/O
control. With the MARC4 IN and OUT instructions the I/O bus allows a direct read or write
access to one of the 16 primary I/O addresses. More about the I/O access to the on-chip peripherals is described in the section “Peripheral Modules”. The I/O bus is internal and is not
accessible by the customer on the final microcontroller device, but it is used as the interface for
the MARC4 emulation (see also the section “Emulation”).
4.2.6
Instruction Set
The MARC4 instruction set is optimized for the high level programming language qFORTH.
Many MARC4 instructions are qFORTH words. This enables the compiler to generate a fast and
compact program code. The CPU has an instruction pipeline allowing the controller to prefetch
an instruction from ROM at the same time as the present instruction is being executed. The
MARC4 is a zero-address machine, the instructions contain only the operation to be performed
and no source or destination address fields. The operations are implicitly performed on the data
placed on the stack. There are one and two byte instructions which are executed within 1 to 4
machine cycles. A MARC4 machine cycle is made up of two system clock cycles (SYSCL). Most
of the instructions are only one byte long and are executed in a single machine cycle. For more
information refer to the “MARC4 Programmer’s Guide”.
4.2.7
4.2.7.1
Interrupt Structure
The MARC4 can handle interrupts with eight different priority levels. They can be generated
from the internal and external interrupt sources or by a software interrupt from the CPU itself.
Each interrupt level has a hard-wired priority and an associated vector for the service routine in
the ROM (see Figure 4-2 on page 10). The programmer can postpone the processing of interrupts by resetting the interrupt enable flag (I) in the CCR. An interrupt occurrence will still be
registered, but the interrupt routine only started after the I flag is set. All interrupts can be
masked, and the priority individually software configured by programming the appropriate control
register of the interrupting module (see section “Peripheral Modules”).
Interrupt Processing
For processing the eight interrupt levels, the MARC4 includes an interrupt controller with two
8-bit wide interrupt pending and interrupt active registers. The interrupt controller samples all
interrupt requests during every non-I/O instruction cycle and latches these in the interrupt pending register. If no higher priority interrupt is present in the interrupt active register, it signals the
CPU to interrupt the current program execution. If the interrupt enable bit is set, the processor
enters an interrupt acknowledge cycle. During this cycle a short call (SCALL) instruction to the
service routine is executed and the current PC is saved on the return stack.
An interrupt service routine is completed with the RTI instruction. This instruction resets the corresponding bits in the interrupt pending/active register and fetches the return address from the
return stack to the program counter. When the interrupt enable flag is reset (triggering of interrupt routines are disabled), the execution of new interrupt service routines is inhibited but not the
logging of the interrupt requests in the interrupt pending register. The execution of the interrupt
is delayed until the interrupt enable flag is set again. Note that interrupts are only lost if an interrupt request occurs while the corresponding bit in the pending register is still set (i.e., the
interrupt service routine is not yet finished).
8
ATAR092/ATAR892
4535E–4BMCU–05/07
ATAR092/ATAR892
4.2.7.2
Interrupt Latency
The interrupt latency is the time from the occurrence of the interrupt to the interrupt service routine being activated. In MARC4 this is extremely short (taking between 3 to 5 machine cycles
depending on the state of the core).
Figure 4-6.
Interrupt Handling
INT7
INT7 Active
7
5
Priority Level
RTI
INT5
6
INT5 Active
RTI
INT3
4
3
INT2
INT3 Active
RTI
2
INT2 Pending
INT2 Active
SWI0
1
0
RTI
INT0 Pending
INT0 Active
RTI
Main/
Autosleep
Main/
Autosleep
Time
Table 4-1.
Interrupt Priority Table
Interrupt
Priority
ROM Address
Interrupt Opcode
Function
INT0
Lowest
040h
C8h (SCALL 040h)
Software interrupt (SWI0)
INT1
|
080h
D0h (SCALL 080h)
External hardware interrupt, any edge at BP52 or
BP53
INT2
|
0C0h
D8h (SCALL 0C0h)
Timer 1 interrupt
INT3
|
100h
E8h (SCALL 100h)
SSI interrupt or external hardware interrupt at BP40 or
BP43
INT4
|
140h
E8h (SCALL 140h)
Timer 2 interrupt
INT5
|
180h
F0h (SCALL 180h)
Timer 3 interrupt
INT6
↓
1C0h
F8h (SCALL 1C0h)
External hardware interrupt, at any edge at BP50 or
BP51
INT7
Highest
1E0h
FCh (SCALL 1E0h)
Voltage Monitor (VM) interrupt
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4535E–4BMCU–05/07
Table 4-2.
Hardware Interrupts
Interrupt Mask
Interrupt
Register
Bit
Interrupt Source
INT1
P5CR
P52M1, P52M2
P53M1, P53M2
Any edge at BP52
any edge at BP53
INT2
T1M
T1IM
Timer 1
INT3
SISC
SIM
SSI buffer full/empty or BP40/BP43 interrupt
INT4
T2CM
T2IM
Timer 2 compare match/overflow
INT5
T3CM1
T3CM2
T3C
T3IM1
T3IM2
T3EIM
Timer 3 compare register 1 match
Timer 3 compare register 2 match
Timer 3 edge event occurs (T3I)
INT6
P5CR
P50M1, P50M2
P51M1, P51M2
INT7
VCM
VIM
Any edge at BP50,
any edge at BP51
External/internal voltage monitoring
4.2.7.3
Software Interrupts
The programmer can generate interrupts by using the software interrupt instruction (SWI) which
is supported in qFORTH by predefined macros named SWI0...SWI7. The software triggered
interrupt operates exactly like any hardware triggered interrupt. The SWI instruction takes the
top two elements from the expression stack and writes the corresponding bits via the I/O bus to
the interrupt pending register. Therefore, by using the SWI instruction, interrupts can be re-prioritized or lower priority processes scheduled for later execution.
4.2.7.4
Hardware Interrupts
In the ATAR092, there are eleven hardware interrupt sources with seven different levels. Each
source can be masked individually by mask bits in the corresponding control registers. An overview of the possible hardware configurations is shown in Table 4-2.
4.3
Master Reset
The master reset forces the CPU into a well-defined condition. It is unmaskable and is activated
independent of the current program state. It can be triggered by either initial supply power-up, a
short collapse of the power supply, brown-out detection circuitry, watchdog time-out, or an external input clock supervisor stage (see Figure 4-7 on page 11).
A master reset activation will reset the interrupt enable flag, the interrupt pending register and
the interrupt active register. During the power-on reset phase the I/O bus control signals are set
to reset mode thereby initializing all on-chip peripherals. All bidirectional ports are set to input
mode.
Attention: During any reset phase, the BP20/NTE input is driven towards VDD by an additional
internal strong pull-up transistor. This pin must not be pulled down to VSS during reset by any
external circuitry representing a resistor of less than 150 kΩ.
Releasing the reset results in a short call instruction (opcode C1h) to the ROM address 008h.
This activates the initialization routine $RESET which in turn has to initialize all necessary RAM
variables, stack pointers and peripheral configuration registers (see Table 5-1 on page 22).
10
ATAR092/ATAR892
4535E–4BMCU–05/07
ATAR092/ATAR892
Figure 4-7.
Reset Configuration
VDD
Pull-up
CL
NRST
Reset
Reset
Timer
Internal
Timer
CL = SYSCL/4
4.3.1
Power-on
Reset
VDD
Brown-out
Detection
VDD
VSS
VSS
WatchReset
dog
CWD
Ext. Clock
Supervisor
Exin
Power-on Reset and Brown-out Detection
The ATAR092/ATAR892 have a fully integrated power-on reset and brown-out detection circuitry. For reset generation no external components are needed.
These circuits ensure that the core is held in the reset state until the minimum operating supply
voltage has been reached. A reset condition will also be generated should the supply voltage
drop momentarily below the minimum operating level except when a power down mode is activated (the core is in SLEEP mode and the peripheral clock is stopped). In this power-down
mode the brown-out detection is disabled. Two values for the brown-out voltage threshold are
programmable via the BOT-bit in the SC-register.
A power-on reset pulse is generated by a VDD rise across the default BOT voltage level (1.7V). A
brown-out reset pulse is generated when VDD falls below the brown-out voltage threshold. Two
values for the brown-out voltage threshold are programmable via the BOT-bit in the SC-register.
When the controller runs in the upper supply voltage range with a high system clock frequency,
the high threshold must be used. When it runs with a lower system clock frequency, the low
threshold and a wider supply voltage range may be chosen. For further details, see the electrical
specification and the SC-register description for BOT programming.
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4535E–4BMCU–05/07
Figure 4-8.
Brown-out Detection
VDD
2.0V
1.7V
t
td
CPU
Reset
BOT = 1
td
CPU
Reset
td
BOT = 0
td = 1.5 ms (Typically)
BOT = 1, Low Brown-out Voltage Threshold 1.7V (Reset Value).
BOT = 0, High Brown-out Voltage Threshold 2.0V.
4.3.2
Watchdog Reset
The watchdog’s function can be enabled at the WDC-register and triggers a reset with every
watchdog counter overflow. To suppress the watchdog reset, the watchdog counter must be
regularly reset by reading the watchdog register address (CWD). The CPU reacts in exactly the
same manner as a reset stimulus from any of the above sources.
4.3.3
External Clock Supervisor
The external input clock supervisor function can be enabled if the external input clock is selected
within the CM- and SC-registers of the clock module. The CPU reacts in exactly the same manner as a reset stimulus from any of the above sources.
4.4
Voltage Monitor
The voltage monitor consists of a comparator with internal voltage reference. It is used to supervise the supply voltage or an external voltage at the VMI-pin. The comparator for the supply
voltage has three internal programmable thresholds one lower threshold (2.2V), one middle
threshold (2.6V). and one higher threshold (3.0V). For external voltages at the VMI-pin, the comparator threshold is set to VBG = 1.3V. The VMS-bit indicates if the supervised voltage is below
(VMS = 0) or above (VMS = 1) this threshold. An interrupt can be generated when the VMS-bit is
set or reset to detect a rising or falling slope. A voltage monitor interrupt (INT7) is enabled when
the interrupt mask bit (VIM) is reset in the VMC-register.
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ATAR092/ATAR892
4535E–4BMCU–05/07
ATAR092/ATAR892
Figure 4-9.
Voltage Monitor
VDD
Voltage Monitor
BP41/
VMI
VMC
VM2 VM1 VM0 VIM
VMST
4.4.1
INT7
OUT
IN
-
-
res
VMS
Voltage Monitor Control/Status Register
Primary register address: ’F’hex
Bit 3
Bit 2
Bit 1
Bit 0
VMC: Write
VM2
VM1
VM0
VIM
Reset value: 1111b
VMST: Read
–
–
reserved
VMS
Reset value: xx11b
VM2: Voltage monitor Mode bit 2
VM1: Voltage monitor Mode bit 1
VM0: Voltage monitor Mode bit 0
Table 4-3.
Voltage Monitor Modes
VM2
VM1
VM0
Function
1
1
1
Disable voltage monitor
1
1
0
External (VIM input), internal reference threshold (1.3V), interrupt
with negative slope
1
0
1
Not allowed
1
0
0
External (VMI input), internal reference threshold (1.3V), interrupt
with positive slope
0
1
1
Internal (supply voltage), high threshold (3.0V), interrupt with
negative slope
0
1
0
Internal (supply voltage), middle threshold (2.6V), interrupt with
negative slope
0
0
1
Internal (supply voltage), low threshold (2.2V), interrupt with
negative slope
0
0
0
Not allowed
13
4535E–4BMCU–05/07
VIM
Voltage Interrupt Mask bit
VIM = 0, voltage monitor interrupt is enabled
VIM = 1, voltage monitor interrupt is disabled
VMS
Voltage Monitor Status bit
VMS = 0, the voltage at the comparator input is below VRef
VMS = 1, the voltage at the comparator input is above VRef
Figure 4-10. Internal Supply Voltage Supervisor
VMS = 1
VDD
Low Threshold
Middle Threshold
High Threshold
3.0V
2.6V
2.2V
Low Threshold
Middle Threshold
High Threshold
VMS = 0
Figure 4-11. External Input Voltage Supervisor
Internal Reference Level
VMI
Negative Slope
Interrupt Positive Slope
VMS = 1
VMS = 1
VMS = 0
VMS = 0
1.3V
Positive Slope
Interrupt Negative Slope
4.5
4.5.1
t
Clock Generation
Clock Module
The ATAR092/ATAR892 contains a clock module with 4 different internal oscillator types: two
RC-oscillators, one 4-MHz crystal oscillator and one 32-kHz crystal oscillator. The pins OSC1
and OSC2 are the interface to connect a crystal either to the 4-MHz, or to the 32-kHz crystal
oscillator. OSC1 can be used as input for external clocks or to connect an external trimming
resistor for the RC-oscillator 2. All necessary circuitry except the crystal and the trimming resistor is integrated on-chip. One of these oscillator types or an external input clock can be selected
to generate the system clock (SYSCL).
In applications that do not require exact timing, it is possible to use the fully integrated RC-oscillator 1 without any external components. The RC-oscillator 1 center frequency tolerance is
better than ±50%. The RC-oscillator 2 is a trimmable oscillator whereby the oscillator frequency
can be trimmed with an external resistor attached between OSC1 and VDD. In this configuration,
the RC-oscillator 2 frequency can be maintained stable with a tolerance of ±15% over the full
operating temperature and voltage range.
14
ATAR092/ATAR892
4535E–4BMCU–05/07
ATAR092/ATAR892
The clock module is programmable via software with the clock management register (CM) and
the system configuration register (SC). The required oscillator configuration can be selected with
the OS1-bit and the OS0-bit in the SC-register. A programmable 4-bit divider stage allows the
adjustment of the system clock speed. A special feature of the clock management is that an
external oscillator may be used and switched on and off via a port pin for the power-down mode.
Before the external clock is switched off, the internal RC-oscillator 1 must be selected with the
CCS-bit and then the SLEEP mode may be activated. In this state an interrupt can wake up the
controller with the RC-oscillator, and the external oscillator can be activated and selected by
software. A synchronization stage avoids too short clock periods if the clock source or the clock
speed is changed. If an external input clock is selected, a supervisor circuit monitors the external
input and generates a hardware reset if the external clock source fails or drops below 500 kHz
for more than 1 ms.
Figure 4-12. Clock Module
OSC1
Oscin
Ext. Clock
RC
Oscillator 1
ExOut
Stop
ExIn
*
RCOut 1 IN1
RC Oscillator 2
RCOut 2
Stop
RTrim
SYSCL
Stop
Cin
Control
IN2
/2
/2
4-MHz Oscillator
Oscin
4 Out
Oscout
Stop
OSC2
*
/2
Divider
32-kHz Oscillator
Oscout Oscin
Oscout
32 Out
Sleep
WDL
Osc-Stop
CM:
Cin/16
NSTOP CCS
CSS1 CSS0
BOT
---
Table 4-4.
OS1
SUBCL
32 kHz
* Mask Option
SC
/2
OS0
Clock Modes
Clock Source for SYSCL
Mode
OS1
OS0
CCS = 1
CCS = 0
Clock Source for
SUBCL
1
1
1
RC-oscillator 1 (internal)
External input clock
Cin/16
2
0
1
RC-oscillator 1 (internal)
RC-oscillator 2 with external
trimming resistor
Cin/16
3
1
0
RC-oscillator 1 (internal)
4-MHz oscillator
Cin/16
4
0
0
RC-oscillator 1 (internal)
32-kHz oscillator
32 kHz
The clock module generates two output clocks. One is the system clock (SYSCL) and the other
the periphery (SUBCL). The SYSCL can supply the core and the peripherals and the SUBCL
can supply only the peripherals with clocks. The modes for clock sources are programmable
with the OS1-bit and OS0-bit in the SC-register and the CCS-bit in the CM-register.
15
4535E–4BMCU–05/07
4.5.2
4.5.2.1
Oscillator Circuits and External Clock Input Stage
The ATAR092/ATAR892 series consists of four different internal oscillators: two RC-oscillators,
one 4-MHz crystal oscillator, one 32-kHz crystal oscillator and one external clock input stage.
RC-oscillator 1 Fully Integrated
For timing insensitive applications, it is possible to use the fully integrated RC oscillator 1. It
operates without any external components and saves additional costs. The RC-oscillator 1 center frequency tolerance is better than ±50% over the full temperature and voltage range. The
basic center frequency of the RC-oscillator 1 is fO ≈ 3.8 MHz. The RC oscillator 1 is selected by
default after power-on reset.
Figure 4-13. RC-oscillator 1
RC-oscillator 1
RcOut1
RcOut1
Osc-Stop
Stop
Control
4.5.2.2
External Input Clock
The OSC1 or OSC2 (mask option) can be driven by an external clock source provided it meets
the specified duty cycle, rise and fall times and input levels. Additionally the external clock stage
contains a supervisory circuit for the input clock. The supervisor function is controlled via the
OS1, OS0-bit in the SC-register and the CCS-bit in the CM-register. If the external input clock is
missing for more than 1 ms and CCS = 0 is set in the CM-register, the supervisory circuit generates a hardware reset.
Figure 4-14. External Input Clock
Ext. Input Clock
Ext.
Clock
OSC1
ExIn
Osc-Stop
Stop
or
Ext.
Clock
Table 4-5.
16
RcOut1
ExOut
CCS
OSC2
Clock Monitor
Reset
Supervisor Function Control Bits
OS1
OS0
CCS
Supervisor Reset Output (Res)
1
1
0
Enable
1
1
1
Disable
x
0
x
Disable
ATAR092/ATAR892
4535E–4BMCU–05/07
ATAR092/ATAR892
4.5.2.3
RC-oscillator 2 with External Trimming Resistor
The RC-oscillator 2 is a high resolution trimmable oscillator whereby the oscillator frequency can
be trimmed with an external resistor between OSC1 and V DD . In this configuration, the
RC-oscillator 2 frequency can be maintained stable with a tolerance of ±10% over the full operating temperature and a voltage range VDD from 2.5V to 6.0V.
For example: An output frequency at the RC-oscillator 2 of 2 MHz can be obtained by connecting a resistor Rext = 360 kΩ (see Figure 4-15).
Figure 4-15. RC-oscillator 2
VDD
RC-oscillator 2
Rext
RcOut2
OSC1
RcOut2
RTrim
Osc-Stop
Stop
OSC2
4.5.2.4
4-MHz Oscillator
The ATAR092/ATAR892 4-MHz oscillator options need a crystal or ceramic resonator connected
to the OSC1 and OSC2 pins to establish oscillation.
All the necessary oscillator circuitry is integrated, except the actual crystal, resonator, C3 and C4.
Figure 4-16. 4-MHz Crystal Oscillator
OSC1
Oscin
XTAL
4 MHz
*
C1
Oscout
OSC2
4Out
4Out
4 MHz
Oscillator
Stop
Osc-Stop
*
*
C2
Mask Option
Note:
Both, the 4-MHz and the 32-kHz crystal oscillator, use an integrated 14 stage divider circuit to stabilize oscillation before the oscillator output is used as system clock. This results in an additional
delay of about 4 ms for the 4-MHz crystal and about 500 ms for the 32-kHz crystal.
17
4535E–4BMCU–05/07
Figure 4-17. Ceramic Resonator
C3
OSC1
Oscin
Cer.
Res
C1
C4
Oscout
OSC2
Osc-Stop
C2
Mask Option
4.5.2.5
Stop
*
*
Note:
4Out
4Out
4 MHz
Oscillator
*
Both, the 4-MHz and the 32-kHz crystal oscillator, use an integrated 14 stage divider circuit to stabilize oscillation before the oscillator output is used as system clock. This results in an additional
delay of about 4 ms for the 4-MHz crystal and about 500 ms for the 32-kHz crystal.
32-kHz Oscillator
Some applications require long-term time keeping or low resolution timing. In this case, an
on-chip, low power 32-kHz crystal oscillator can be used to generate both the SUBCL and the
SYSCL. In this mode, power consumption is greatly reduced. The 32-kHz crystal oscillator can
not be stopped while the power-down mode is in operation.
Figure 4-18. 32-kHz Crystal Oscillator
OSC1
Oscin
XTAL
32 MHz
*
C1
32Out
32Out
32 kHz
Oscillator
Oscout
OSC2
*
*
C2
Mask Option
Note:
4.5.3
18
Both, the 4-MHz and the 32-kHz crystal oscillator, use an integrated 14 stage divider circuit to stabilize oscillation before the oscillator output is used as system clock. This results in an additional
delay of about 4 ms for the 4-MHz crystal and about 500 ms for the 32-kHz crystal.
Clock Management
The clock management register controls the system clock divider and synchronization stage.
Writing to this register triggers the synchronization cycle.
ATAR092/ATAR892
4535E–4BMCU–05/07
ATAR092/ATAR892
4.5.3.1
Clock Management Register (CM)
Auxiliary register address: ’3’hex
CM
Bit 3
Bit 2
Bit 1
Bit 0
NSTOP
CCS
CSS1
CSS0
NSTOP
Not STOP peripheral clock
NSTOP = 0, stops the peripheral clock while the core is in SLEEP mode
NSTOP = 1, enables the peripheral clock while the core is in SLEEP mode
CCS
Core Clock Select
CCS = 1, the internal RC-oscillator 1 generates SYSCL
CCS = 0, the 4-Mhz crystal oscillator, the 32-kHz crystal oscillator, an external
clock source or the RC-oscillator 2 with the external resistor at OSC1
generates SYSCL dependent on the setting of OS0 and OS1 in the
system configuration register
CSS1
Core Speed Select 1
CSS0
Core Speed Select 0
Table 4-6.
4.5.3.2
Reset value: 1111b
Core Speed Select
CSS1
CSS0
Divider
0
0
16
1
1
8
1
0
4
0
1
2
Note
Reset value
System Configuration Register (SC)
Primary register address: ’3’hex
SC: write
Bit 3
Bit 2
Bit 1
Bit 0
BOT
–
OS1
OS0
Reset value: 1x11b
BOT
Brown-Out Threshold
BOT = 1, low brown-out voltage threshold (1.7 V)
BOT = 0, high brown-out voltage threshold (2.0 V)
OS1
Oscillator Select 1
OS0
Oscillator Select 0
19
4535E–4BMCU–05/07
Table 4-7.
Mode
OS1
OS0
Input for SUBCL
1
1
1
Cin/16
RC-oscillator 1 and external input clock
2
0
1
Cin/16
RC-oscillator 1 and RC-oscillator 2
3
1
0
Cin/16
RC-oscillator 1 and 4-MHz crystal oscillator
4
0
0
32 kHz
RC-oscillator 1 and 32-kHz crystal oscillator
Note:
4.6
Oscillator Select
Selected Oscillators
If the bit CCS = 0 in the CM-register the RC-oscillator 1 always stops.
Power-down Modes
The sleep mode is a shut-down condition which is used to reduce the average system power
consumption in applications where the microcontroller is not fully utilized. In this mode, the system clock is stopped. The sleep mode is entered via the SLEEP instruction. This instruction sets
the interrupt enable bit (I) in the condition code register to enable all interrupts and stops the
core. During the sleep mode the peripheral modules remain active and are able to generate
interrupts. The microcontroller exits the sleep mode by carrying out any interrupt or a reset.
The sleep mode can only be kept when none of the interrupt pending or active register bits are
set. The application of the $AUTOSLEEP routine ensures the correct function of the sleep
mode. For standard applications use the $AUTOSLEEP routine to enter the power-down mode.
Using the SLEEP instruction instead of the $AUTOSLEEP following an I/O instruction requires
to insert 3 non I/O instruction cycles (for example NOP NOP NOP) between the IN or OUT command and the SLEEP command.
The total power consumption is directly proportional to the active time of the microcontroller. For
a rough estimation of the expected average system current consumption, the following formula
should be used:
Itotal (VDD,fsyscl) = ISleep + (IDD × tactive/ttotal)
IDD depends on VDD and fsyscl
The ATAR092/ATAR892 has various power-down modes. During the sleep mode the clock for
the MARC4 core is stopped. With the NSTOP-bit in the clock management register (CM) it is
programmable if the clock for the on-chip peripherals is active or stopped during the sleep mode.
If the clock for the core and the peripherals is stopped the selected oscillator is switched off. An
exception is the 32-kHz oscillator, if it is selected it runs continuously independent of the
NSTOP-bit. If the oscillator is stopped or the 32-kHz oscillator is selected, power consumption is
extremely low.
Table 4-8.
Mode
Brown-out
Function
RC-Oscillator 1
RC-Oscillator 2
4-MHz Oscillator
32-kHz
Oscillator
External
Input Clock
NO
Active
RUN
RUN
YES
CPU Core Osc-Stop(1)
Active
RUN
Power-down
SLEEP
NO
Active
RUN
RUN
YES
SLEEP
SLEEP
YES
STOP
STOP
RUN
STOP
Note:
20
Power-down Modes
Osc-Stop = SLEEP and NSTOP and WDL
ATAR092/ATAR892
4535E–4BMCU–05/07
ATAR092/ATAR892
5. Peripheral Modules
5.1
Addressing Peripherals
Accessing the peripheral modules takes place via the I/O bus (see Figure 5-1). The IN or OUT
instructions allow direct addressing of up to 16 I/O modules. A dual register addressing scheme
has been adopted to enable direct addressing of the primary register. To address the auxiliary
register, the access must be switched with an auxiliary switching module. Thus a single IN (or
OUT) to the module address will read (or write into) the module primary register. Accessing the
auxiliary register is performed with the same instruction preceded by writing the module address
into the auxiliary switching module. Byte wide registers are accessed by multiple IN- (or OUT-)
instructions. For more complex peripheral modules, with a larger number of registers, extended
addressing is used. In this case a bank of up to 16 subport registers are indirectly addressed
with the subport address. The first OUT-instruction writes the subport address to the sub
address register, the second IN- or OUT-instruction reads data from or writes data to the
addressed subport.
Figure 5-1.
Example of I/O Addressing
Module ASW
Module M1
Module M2
Module M3
(Address Pointer)
Auxiliary Switch
Module
Subaddress Reg.
1)
Bank of
Primary Regs.
Auxiliary Reg.
Subport FH
5)
Subport EH
Subport 1
Primary Reg.
Subport 0
Primary Reg.
Primary Reg.
2)
3)
6)
4)
I/O bus
To Other Modules
Indirect Subport Access
Dual Register Access
Single Register Access
(Subport Register Write)
(Primary Register Write)
(Primary Register Write)
1) Addr. (SPort) Addr. (M1) OUT
2) SPort_Data Addr. (M1) OUT
3) Prim._Data Addr. (M2) OUT
6) Prim._Data Addr. (M3) OUT
(Primary Register Read)
(Auxiliary Register Write)
(Subport Register Read)
1) Addr. (SPort) Addr. (M1) OUT
2)
Addr. (M1) IN
Example of
qFORTH
Program
Code
(Subport Register Write Byte)
1) Addr. (SPort) Addr. (M1) OUT
2) SPort_Data (lo) Addr. (M1) OUT
2) SPort_Data (hi) Addr. (M1) OUT
(Subport Register Read Byte)
1) Addr. (SPort) Addr. (M1) OUT
2)
Addr. (M1) IN (hi)
2)
Addr. (M1) IN (lo)
Addr. (ASW) = Auxiliary Switch Module Address
Addr. (Mx) = Module Mx Address
Addr. (SPort) = Subport Address
Prim._Data = Data to be written into Primary Register
Aux._Data = Data to be written into Auxiliary Register
Aux._Data (lo) = Data to Be Written into Auxiliary Register
(low nibble)
4) Addr. (M2) Addr. (ASW) OUT
5) Aux._Data Addr. (M2) OUT
6)
Addr. (M3) IN
(Primary Register Read)
3)
Addr. (M2) IN
(Auxiliary Register Read)
4) Addr. (M2) Addr. (ASW) OUT
5)
Addr. (M2) IN
(Auxiliary Register Write Byte)
4) Addr. (M2) Addr. (ASW) OUT
5) Aux._Data (lo) Addr. (M2) OUT
5) Aux._Data (hi) Addr. (M2) OUT
Aux._Data (hi) = Data to be written into Auxiliary Register (high nibble)
SPort_Data(lo) = Data to be written into Subport (low nibble)
SPort_Data(hi) = Data to be written into Subport (high nibble)
(lo) = SPort_Data (low nibble)
(hi) = SPort_Data (high nibble)
21
4535E–4BMCU–05/07
Table 5-1.
Peripheral Addresses
Port Address
1
2
Auxiliary
3
Auxiliary
4
Auxiliary
5
Auxiliary
6
Auxiliary
7
Module
Type
See
Page
Port 1 - data register/input data
M3
23
1111b
Port 2 - data register/pin data
M2
25
1111b
Port 2 - control register
Name
Write/Read
Reset Value
Register Function
P1DAT
W/R
1xx1b
P2DAT
W/R
P2CR
W
SC
W
1x11b
System configuration register
M3
19
CWD
R
xxxxb
Watchdog reset
M3
12
CM
W
1111b
Clock management register
M2
19
P4DAT
W/R
1111b
Port 4 - data register/pin data
M2
28
P4CR
W
1111 1111b
Port 4 - control register (byte)
P5DAT
W/R
1111b
Port 5 - data register/pin data
P5CR
W
1111 1111b
Port 5 - control register (byte)
P6DAT
W/R
1xx1b
Port 6 - data register/pin data
P6CR
W
1111b
Port 6 - control register (byte)
T12SUB
W
–
25
28
M2
27
27
M2
29
29
Data to Timer 1/2 subport
M1
21
Subport address
0
T2C
W
0000b
Timer 2 control register
M1
42
1
T2M1
W
1111b
Timer 2 mode register 1
M1
42
2
T2M2
W
1111b
Timer 2 mode register 2
M1
44
3
T2CM
W
0000b
Timer 2 compare mode register
M1
44
4
T2CO1
W
1111b
Timer 2 compare register 1
M1
45
5
T2CO2
W
1111 1111b
Timer 2 compare register 2 (byte)
M1
45
6
–
–
–
Reserved
Reserved
7
–
–
–
8
T1C1
W
1111b
Timer 1 control register 1
M1
32
9
T1C2
W
x111b
Timer 1 control register 2
M1
33
A
WDC
W
1111b
Watchdog control register
M1
33
ASW
21
M2
70
B-F
Reserved
8
ASW
W
1111b
9
STB
W
xxxx xxxxb
Serial transmit buffer (byte)
SRB
R
xxxx xxxxb
Serial receive buffer (byte)
71
SIC1
W
1111b
Serial interface control register 1
68
SISC
W/R
1x11b
Serial interface status/control register
SIC2
W
1111b
Serial interface control register 2
T3SUB
W/R
–
0
T3M
W
1111b
1
T3CS
W
1111b
2
T3CM1
W
3
T3CM2
4
Auxiliary
A
Auxiliary
B
Auxiliary/switch register
Data to/from Timer 3 subport
M2
70
69
M1
21
Timer 3 mode register
M1
55
Timer 3 clock select register
M1
57
0000b
Timer 3 compare mode register 1
M1
58
W
0000b
Timer 3 compare mode register 2
M1
58
T3CO1
W
1111 1111b
Timer 3 compare register 1 (byte)
M1
59
4
T3CP
R
xxxx xxxxb
Timer 3 capture register (byte)
M1
59
5
T3CO2
W
1111 1111b
Timer 3 compare register 2 (byte)
M1
58
Subport address
6-F
C
D
22
–
Reserved
T3C
W
0000b
Timer 3 control register
M3
56
T3ST
R
x000b
Timer 3 status register
M3
56
–
–
Reserved
–
Reserved
E
–
F
VMC
W
1111b
Voltage monitor control register
M3
13
VMST
R
xx11b
Voltage monitor status register
M3
13
ATAR092/ATAR892
4535E–4BMCU–05/07
ATAR092/ATAR892
5.2
Bidirectional Ports
With the exception of Port 1 and Port 6, all other ports (2, 4 and 5) are 4 bits wide. Port 1 and
Port 6 have a data width of 2 bits (bit 0 and bit 3). All ports may be used for data input or output.
All ports are equipped with Schmitt trigger inputs and a variety of mask options for open drain,
open source, full complementary outputs, pull up and pull down transistors. All Port Data Registers (PxDAT) are I/O mapped to the primary address register of the respective port address and
the Port Control Register (PxCR), to the corresponding auxiliary register.
There are five different directional ports available:
5.2.1
Port 1
2-bit wide bidirectional ports with automatic full bus width direction switching.
Port 2
4-bit wide bitwise-programmable I/O port.
Port 5
4-bit wide bitwise-programmable bidirectional port with optional strong
pull-ups and programmable interrupt logic.
Port 4
4-bit wide bitwise-programmable bidirectional port also provides the I/O
interface to Timer 2, SSI, voltage monitor input and external interrupt input.
Port 6
2-bit wide bitwise-programmable bidirectional port also provides the I/O
interface to Timer 3 and external interrupt input.
Bidirectional Port 1
In Port 1 the data direction register is not independently software programmable, the direction of
the complete port being switched automatically when an I/O instruction occurs (see Figure 5-2).
The port is switched to output mode via an OUT instruction and to input via an IN instruction.
The data written to a port will be stored into the output data latches and appears immediately at
the port pin following the OUT instruction. After RESET all output latches are set to “1” and the
port is switched to input mode. An IN instruction reads the condition of the associated pins.
Note:
Care must be taken when switching the bidirectional port from output to input. The capacitive pin
loading at this port in conjunction with the high resistance pull-ups may cause the CPU to read the
contents of the output data register rather than the external input state. To avoid this, one of the
following programming techniques should be used:
Use two IN-instructions and DROP the first data nibble. The first IN switches the port from output
to input and the DROP removes the first invalid nibble. The second IN reads the valid pin state.
Use an OUT-instruction followed by an IN-instruction. Via the OUT-instruction, the capacitive load
is charged or discharged depending on the optional pull-up/pull-down configuration. Write a ‘1’ for
pins with pull-up resistors and a ‘0’ for pins with pull-down resistors.
23
4535E–4BMCU–05/07
Figure 5-2.
Bidirectional Port 1
VDD
I/O Bus
1)
(Data Out)
D
1)
Q
Static
Pull-up
Switched
Pull-up
BP1y
P1DATy
R
1)
VDD
Reset
(Direction)
1)
OUT
S
Q
1) Mask Options
IN
R
Static
Pull-down
Switched
Pull-down
NQ
Master Reset
5.2.2
Bidirectional Port 2
As all other bidirectional ports, this port includes a bitwise programmable Control Register
(P2CR), which enables the individual programming of each port bit as input or output. It also
opens up the possibility of reading the pin condition when in output mode. This is a useful feature for self testing and for serial bus applications.
Port 2, however, has an increased drive capability and an additional low resistance
pull-up/-down transistor mask option.
Note:
Care should be taken connecting external components to BP20/NTE. During any reset phase, the
BP20/NTE input is driven towards VDD by an additional internal strong pull-up transistor. This pin
must not be pulled down (active or passive) to VSS during reset by any external circuitry representing a resistor of less than 150 kΩ. This prevents the circuit from unintended switching to test mode
enable through the application circuitry at pin BP20/NTE. Resistors less than 150 kΩ might lead to
an undefined state of the internal test logic thus disabling the application firmware.
To avoid any conflict with the optional internal pull-down transistors, BP20 handles the pull-down
options in a different way than all other ports. BP20 is the only port that switches off the pull-down
transistors during reset.
Figure 5-3.
Bidirectional Port 2
VDD
I/O Bus
1)
(Data Out)
1)
I/O Bus
D
Q
1)
Static
Pull-up
Switched
Pull-up
P2DATy
BP2y
S
1)
Master Reset
I/O Bus
D
S
VDD
1)
Q
P2CRy
1) Mask Options
Switched
Pull-down
1)
Static
Pull-down
(Direction)
24
ATAR092/ATAR892
4535E–4BMCU–05/07
ATAR092/ATAR892
5.2.2.1
Port 2 Data Register (P2DAT)
Primary register address: '2'hex
P2DAT
Bit 3
Bit 2
Bit 1
Bit 0
P2DAT3
P2DAT2
P2DAT1
P2DAT0
Reset value: 1111b
Bit 3 = MSB, Bit 0 = LSB
5.2.2.2
Port 2 Control Register (P2CR)
Auxiliary register address: '2'hex
P2CR
Bit 3
Bit 2
Bit 1
Bit 0
P2CR3
P2CR2
P2CR1
P2CR0
Reset value: 1111b
Value 1111b means all pins in input mode
Table 5-2.
Code
3210
5.2.3
Port 2 Control Register
Function
xxx1
BP20 in input mode
xxx0
BP20 in output mode
xx1x
BP21 in input mode
xx0x
BP21 in output mode
x1xx
BP22 in input mode
x0xx
BP22 in output mode
1xxx
BP23 in input mode
0xxx
BP23 in output mode
Bidirectional Port 5
As all other bidirectional ports, this port includes a bitwise programmable Control Register
(P5CR), which allows the individual programming of each port bit as input or output. It also
opens up the possibility of reading the pin condition when in output mode. This is a useful feature for self testing and for serial bus applications.
The port pins can also be used as external interrupt inputs (see Figure 5-4 on page 26 and Figure 5-5 on page 26). The interrupts (INT1 and INT6) can be masked or independently configured
to trigger on either edge. The interrupt configuration and port direction is controlled by the Port 5
Control Register (P5CR). An additional low resistance pull-up/-down transistor mask option provides an internal bus pull-up for serial bus applications.
The Port 5 Data Register (P5DAT) is I/O mapped to the primary address register of address ‘5’h
and the Port 5 Control Register (P5CR) to the corresponding auxiliary register. The P5CR is a
byte-wide register and is configured by writing first the low nibble and then the high nibble (see
section “Addressing Peripherals”).
25
4535E–4BMCU–05/07
Figure 5-4.
Bidirectional Port 5
VDD
I/O Bus
1)
1)
VDD
(Data Out)
1)
I/O Bus
D
Q
Static
Pull-up
Switched
Pull-up
P5DATy
BP5y
S
1)
Master Reset
IN Enable
1)
1) Mask Options
Figure 5-5.
VDD
1)
Switched
Pull-down
Static
Pull-down
Port 5 External Interrupts
INT1
Data In
INT6
Data in
BP52
BP51
Bidir. Port
Bidir. Port
IN_Enable
IN_Enable
I/O-bus
I/O-bus
Data In
Data in
BP53
BP50
Bidir. Port
Bidir. Port
IN_Enable
IN_Enable
Decoder
P5CR:
26
Decoder
P53M2 P53M1 P52M2
Decoder
Decoder
P52M1 P51M2 P51M1 P50M2
P50M1
ATAR092/ATAR892
4535E–4BMCU–05/07
ATAR092/ATAR892
5.2.3.1
Port 5 Data Register (P5DAT)
Primary register address: '5'hex
P5DAT
5.2.3.2
Bit 3
Bit 2
Bit 1
Bit 0
P5DAT3
P5DAT2
P5DAT1
P5DAT0
Reset value: 1111b
Port 5 Control Register (P5CR) Byte Write
Auxiliary register address: '5'hex
P5CR
First write cycle
Second write cycle
Bit 3
Bit 2
Bit 1
P51M2
P51M1
P50M2
Bit 7
Bit 6
Bit 5
P53M2
P53M1
P52M2
Bit 0
P50M1 Reset value: 1111b
Bit 4
P52M1 Reset value: 1111b
P5xM2, P5xM1 – Port 5x Interrupt Mode/Direction Code
Table 5-3.
Port 5 Control Register
Auxiliary Address: '5'hex First Write Cycle
Second Write Cycle
Code
3210
Function
Code
3210
xx11
BP50 in input mode – interrupt disabled
xx11
BP52 in input mode – interrupt disabled
xx01
BP50 in input mode – rising edge interrupt
xx01
BP52 in input mode – rising edge interrupt
xx10
BP50 in input mode – falling edge interrupt
xx10
BP52 in input mode – falling edge interrupt
xx00
BP50 in output mode – interrupt disabled
xx00
BP52 in output mode – interrupt disabled
Function
11xx
BP51 in input mode – interrupt disabled
11xx
BP53 in input mode – interrupt disabled
01xx
BP51 in input mode – rising edge interrupt
01xx
BP53 in input mode – rising edge interrupt
10xx
BP51 in input mode – falling edge interrupt
10xx
BP53 in input mode – falling edge interrupt
00xx
BP51 in output mode – interrupt disabled
00xx
BP53 in output mode – interrupt disabled
27
4535E–4BMCU–05/07
5.2.4
Bidirectional Port 4
The bidirectional Port 4 is a bitwise configurable I/O port and provides the external pins for the
Timer 2, SSI and the voltage monitor input (VMI). As a normal port, it performs in exactly the
same way as bidirectional Port 2 (see Figure 5-3 on page 24). Two additional multiplexes allow
data and port direction control to be passed over to other internal modules (Timer 2, VM or SSI).
The I/O-pins for SC and SD line have an additional mode to generate an SSI-interrupt.
All four Port 4 pins can be individually switched by the P4CR-register. Figure 5-6 shows the
internal interfaces to bidirectional Port 4.
Figure 5-6.
Bidirectional Port 4 and Port 6
I/O Bus
VDD
Intx
PxMRy
1)
Pin
1)
VDD
Static
Pull-up
POut
1)
I/O Bus
D
Switched
Pull-up
Q
BPxy
PxDATy
1)
S
VDD
Master Reset
(Direction)
I/O Bus
D
S
1)
PxCRy
Switched
Pull-down
1) Mask Options
PDir
5.2.4.1
1)
Q
Static
Pull-down
Port 4 Data Register (P4DAT)
Primary register address: '4'hex
P4DAT
5.2.4.2
Bit 3
Bit 2
Bit 1
Bit 0
P4DAT3
P4DAT2
P4DAT1
P4DAT0
Reset value: 1111b
Port 4 Control Register (P4CR) Byte Write
Auxiliary register address: '4'hex
P4CR
First write cycle
Second write cycle
Bit 3
Bit 2
Bit 1
P41M2
P41M1
P40M2
Bit 7
Bit 6
Bit 5
P43M2
P43M1
P42M2
Bit 0
P40M1 Reset value: 1111b
Bit 4
P42M1 Reset value: 1111b
P4xM2, P4xM1 – Port 4x Interrupt Mode/Direction Code
28
ATAR092/ATAR892
4535E–4BMCU–05/07
ATAR092/ATAR892
Table 5-4.
Port 4 Control Register
Auxiliary Address: '4'hex First Write Cycle
Second Write Cycle
Code
3210
Function
Code
3210
Function
xx11
BP40 in input mode
xx11
BP42 in input mode
xx10
BP40 in output mode
xx10
BP42 in output mode
xx01
BP40 enable alternate function (SC for SSI)
xx0x
BP42 enable alternate function (T2O for Timer 2)
xx00
BP40 enable alternate function (falling edge interrupt
input for INT3)
11xx
BP43 in input mode
11xx
BP41 in input mode
10xx
BP43 in output mode
10xx
BP41 in output mode
01xx
BP43 enable alternate function (SD for SSI)
01xx
BP41 enable alternate function (VMI for voltage
monitor input)
00xx
BP43 enable alternate function (falling edge interrupt
input for INT3)
00xx
BP41 enable alternate function (T2I external clock
input for Timer 2)
5.2.5
5.2.5.1
–
–
Bidirectional Port 6
The bidirectional Port 6 is a bitwise configurable I/O port and provides the external pins for the
Timer 3. As a normal port, it performs in exactly the same way as bidirectional Port 6 (see Figure
5-6 on page 28). Two additional multiplexes allow data and port direction control to be passed
over to other internal module (Timer 3). The I/O-pin for T3I line has an additional mode to generate a Timer 3-interrupt. All two Port 6 pins can be individually switched by the P6CR register.
Figure 5-6 on page 28 shows the internal interfaces to bidirectional Port 6.
Port 6 Data Register (P6DAT)
Primary register address: '6'hex
P6DAT
5.2.5.2
Bit 3
Bit 2
Bit 1
Bit 0
P6DAT3
–
–
P6DAT0
Reset value: 1xx1b
Port 6 Control Register (P6CR)
Primary register address: '6'hex
P6CR
Bit 3
Bit 2
Bit 1
Bit 0
P63M2
P63M1
P60M2
P60M0
Reset value: 1111b
P6xM2, P6xM1 - Port 6x Interrupt mode/direction code
Table 5-5.
Port 6 Control Register
Auxiliary Address: ‘6’hex
Write Cycle
Code
3210
Function
Code
3210
Function
xx11
BP60 in input mode
11xx
BP63 in input mode
xx10
BP60 in output mode
10xx
BP63 in output mode
xx0x
BP60 enable alternate port function (T3O for Timer 3)
0xxx
BP63 enable alternate port function (T3I for Timer 3)
29
4535E–4BMCU–05/07
5.3
Universal Timer/Counter/ Communication Module (UTCM)
The Universal Timer/counter/Communication Module (UTCM) consists of three timers
(Timer 1,Timer 2, Timer 3) and a Synchronous Serial Interface (SSI).
• Timer 1 is an interval timer that can be used to generate periodical interrupts and as
prescaler for Timer 2, Timer 3, the serial interface and the watchdog function.
• Timer 2 is an 8/12-bit timer with an external clock input (T2I) and an output (T2O).
• Timer 3 is an 8-bit timer/counter with its own input (T3I) and output (T3O).
• The SSI operates as two wire serial interface or as shift register for modulation and
demodulation. The modulator and demodulator units work together with the timers and shift
the data bits into or out of the shift register.
There is a multitude of modes in which the timers and the serial interface can work together.
Figure 5-7.
UTCM Block Diagram
SYSCL
From Clock Module
SUBCL
Timer 1
Watchdog
NRST
MUX
INT2
Interval/Prescaler
Timer 3
T1OUT
Capture 3
T3I
Control
8-bit Counter 3
Demodulator 3
Compare 3/1
Modulator 3
MUX
T3O
INT5
Compare 3/2
Timer 2
TOG3
8-bit Counter 2/1
MUX
Compare 2/1
Modulator 2
T2O
I/O Bus
Control
T2I
POUT
8-bit Counter 2/2
MUX
DCG
INT4
Compare 2/2
SSI
TOG2
SCL
Receive Buffer
MUX
8-bit Shift Register
Transmit Buffer
30
Control
SC
SD
INT3
ATAR092/ATAR892
4535E–4BMCU–05/07
ATAR092/ATAR892
5.3.1
Timer 1
The Timer 1 is an interval timer which can be used to generate periodical interrupts and as prescaler for Timer 2, Timer 3, the serial interface and the watchdog function.
The Timer 1 consists of a programmable 14-stage divider that is driven by either SUBCL or
SYSCL. The timer output signal can be used as prescaler clock or as SUBCL and as source for
the Timer 1 interrupt. Because of other system requirements the Timer 1 output T1OUT is synchronized with SYSCL. Therefore, in the power-down mode SLEEP (CPU core -> sleep and
OSC-Stop -> yes), the output T1OUT is stopped (T1OUT = 0). Nevertheless, the Timer 1 can be
active in SLEEP and generate Timer 1 interrupts. The interrupt is maskable via the T1IM bit and
the SUBCL can be bypassed via the T1BP bit of the T1C2 register. The time interval for the
timer output can be programmed via the Timer 1 control register T1C1.
This timer starts running automatically after any power-on reset! If the watchdog function is not
activated, the timer can be restarted by writing into the T1C1 register with T1RM = 1.
Timer 1 can also be used as a watchdog timer to prevent a system from stalling. The watchdog
timer is a 3-bit counter that is supplied by a separate output of Timer 1. It generates a system
reset when the 3-bit counter overflows. To avoid this, the 3-bit counter must be reset before it
overflows. The application software has to accomplish this by reading the CWD register.
After power-on reset the watchdog must be activated by software in the $RESET initialization
routine. There are two watchdog modes, in one mode the watchdog can be switched on and off
by software, in the other mode the watchdog is active and locked. This mode can only be
stopped by carrying out a system reset.
The watchdog timer operation mode and the time interval for the watchdog reset can be programmed via the watchdog control register (WDC).
Figure 5-8.
Timer 1 Module
SYSCL
WDCL
CL1
SUBCL
MUX
14-bit
Prescaler
4-bit
Watchdog
NRST
INT2
T1CS
T1BP
T1MUX
T1IM
T1OUT
31
4535E–4BMCU–05/07
Figure 5-9.
Timer 1 and Watchdog
T1C1 T1RM T1C2 T1C1 T1C0
T1C2
T1BP T1IM
3
Write of the
T1C1 Register
T1IM = 0
T1MUX
Decoder
T1IM = 1
RES Q1
CL1
INT2
MUX for Interval Timer
Q2 Q3
Q4
Q5
CL
Q6
Q8
Q11
Q14 SUBCL
Q8
Q11
Q14
T1OUT
Watchdog
Divider/8
Decoder
MUX for Watchdog Timer
RESET
(NRST)
Divider
RESET
2
WDCL
RES
WDC WDL WDR WDT1 WDT0
Read of the
CWD Register
Watchdog
Mode Control
5.3.1.1
Timer 1 Control Register 1 (T1C1)
Address: '7'hex - Subaddress: '8'hex
T1C1
Bit 3
Bit 2
Bit 1
Bit 0
T1RM
T1C2
T1C1
T1C0
Reset value: 1111b
Bit 3 = MSB, Bit 0 = LSB
T1RM
Timer 1 Restart Mode
T1RM = 0, write access without Timer 1 restart
T1RM = 1, write access with Timer 1 restart
Note: if WDL = 0, Timer 1 restart is impossible
T1C2
Timer 1 Control bit 2
T1C1
Timer 1 Control bit 1
T1C0
Timer 1 Control bit 0
The three bits T1C[2:0] select the divider for Timer 1. The resulting time interval depends on this
divider and the Timer 1 input clock source. The timer input can be supplied by the system clock,
the 32-kHz oscillator or via clock management. If the clock management generates the SUBCL,
the selected input clock from the RC-oscillator, 4-MHz oscillator or an external clock is divided
by 16.
32
ATAR092/ATAR892
4535E–4BMCU–05/07
ATAR092/ATAR892
Table 5-6.
5.3.1.2
Timer 1 Control Bits
T1C2
T1C1
T1C0
Divider
Time Interval with
SUBCL
Time Interval with
SUBCL = 32 kHz
Time Interval with
SYSCL = 2/1 MHz
0
0
0
2
SUBCL/2
61 µs
1 µs/2 µs
0
0
1
4
SUBCL/4
122 µs
2 µs/4 µs
0
1
0
8
SUBCL/8
244 µs
4 µs/8 µs
0
1
1
16
SUBCL/16
488 µs
8 µs/16 µs
1
0
0
32
SUBCL/32
0.977 ms
16 µs/32 µs
1
0
1
256
SUBCL/256
7.812 ms
128 µs/256 µs
1
1
0
2048
SUBCL/2048
62.5 ms
1024 µs/2048 µs
1
1
1
16384
SUBCL/16384
500 ms
8192 µs/16384 µs
Timer 1 Control Register 2 (T1C2)
Address: ’7’hex - Subaddress: ’9’hex
T1C2
Bit 3
Bit 2
Bit 1
Bit 0
–
T1BP
T1CS
T1IM
Reset value: x111b
Bit 3 = MSB, Bit 0 = LSB
5.3.1.3
T1BP
Timer 1 SUBCL ByPassed
T1BP = 1, TIOUT = T1MUX
T1BP = 0, T1OUT = SUBCL
T1CS
Timer 1 input Clock Select
T1CS = 1, CL1 = SUBCL (see Figure 5-8 on page 31)
T1CS = 0, CL1 = SYSCL (see Figure 5-8 on page 31)
T1IM
Timer 1 Interrupt Mask
T1IM = 1, disables Timer 1 interrupt
T1IM = 0, enables Timer 1 interrupt
Watchdog Control Register (WDC)
Address: ’7’hex - Subaddress: ’A’hex
WDC
Bit 3
Bit 2
Bit 1
Bit 0
WDL
WDR
WDT1
WDT0
Reset value: 1111b
Bit 3 = MSB, Bit 0 = LSB
WDL
WatchDog Lock mode
WDL = 1, the watchdog can be enabled and disabled by using the WDR-bit
WDL = 0, the watchdog is enabled and locked. In this mode the WDR-bit has no
effect. After the WDL-bit is cleared, the watchdog is active until a system
reset or power-on reset occurs.
WDR
WatchDog Run and stop mode
WDR = 1, the watchdog is stopped/disabled
WDR = 0, the watchdog is active/enabled
33
4535E–4BMCU–05/07
WDT1
WatchDog Time 1
WDT0
WatchDog Time 0
Both these bits control the time interval for the watchdog reset.
Table 5-7.
5.3.2
Watchdog Time Control Bits
Divider
Delay Time to Reset with
SUBCL = 32 kHz
Delay Time to Reset with
SYSCL = 2/1 MHz
0
512
15.625 ms
0.256 ms/0.512 ms
1
2048
62.5 ms
1.024 ms/2.048 ms
1
0
16384
0.5 s
8.2 ms/16.4 ms
1
1
131072
4s
65.5 ms/131 ms
WDT1
WDT0
0
0
Timer 2
Timer 2 is an 8-/12-bit timer used for:
• Interrupt, square-wave, pulse and duty cycle generation
• Baud-rate generation for the internal shift register
• Manchester and Bi-phase modulation together with the SSI
• Carrier frequency generation and modulation together with the SSI
Timer 2 can be used as interval timer for interrupt generation, as signal generator or as
baud-rate generator and modulator for the serial interface. It consists of a 4-bit and an 8-bit up
counter stage which both have compare registers. The 4-bit counter stages of Timer 2 are cascadable as 12-bit timer or as 8-bit timer with 4-bit prescaler. The timer can also be configured as
8-bit timer and separate 4-bit prescaler.
The Timer 2 input can be supplied via the system clock, the external input clock (T2I), the Timer
1 output clock, the Timer 3 output clock or the shift clock of the serial interface. The external
input clock T2I is not synchronized with SYSCL. Therefore, it is possible to use Timer 2 with a
higher clock speed than SYSCL. Furthermore with that input clock the Timer 2 operates in the
power-down mode SLEEP (CPU core -> sleep and OSC-Stop -> yes) as well as in the
POWER-DOWN (CPU core -> sleep and OSC-Stop -> no). All other clock sources supplied no
clock signal in SLEEP if NSTOP = 0. The 4-bit counter stages of Timer 2 have an additional
clock output (POUT).
Its output has a modulator stage that allows the generation of pulses as well as the generation
and modulation of carrier frequencies. The Timer 2 output can modulate with the shift register
data output to generate Bi-phase- or Manchester code.
If the serial interface is used to modulate a bitstream, the 4-bit stage of Timer 2 has a special
task. The shift register can only handle bitstream lengths divisible by 8. For other lengths, the
4-bit counter stage can be used to stop the modulator after the right bitcount is shifted out.
If the timer is used for carrier frequency modulation, the 4-bit stage works together with an additional 2-bit duty cycle generator like a 6-bit prescaler to generate carrier frequency and duty
cycle. The 8-bit counter is used to enable and disable the modulator output for a programmable
count of pulses.
34
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4535E–4BMCU–05/07
ATAR092/ATAR892
For programming the time interval, the timer has a 4-bit and an 8-bit compare register. For programming the timer function, it has four mode and control registers. The comparator output of
stage 2 is controlled by a special compare mode register (T2CM). This register contains mask
bits for the actions (counter reset, output toggle, timer interrupt) which can be triggered by a
compare match event or the counter overflow. This architecture enables the timer function for
various modes.
The Timer 2 has a 4-bit compare register (T2CO1) and an 8-bit compare register (T2CO2). Both
these compare registers are cascadable as a 12-bit compare register, or 8-bit compare register
and 4-bit compare register.
For 12-bit compare data value:
For 8-bit compare data value:
For 4-bit compare data value:
m=x+1
n=y+1
l=z+1
0 ≤x ≤4095
0 ≤y ≤255
0 ≤z ≤15
Figure 5-10. Timer 2
I/O-bus
T2M1
P4CR
T2M2
T2I
DCGO
SYSCL
T1OUT
TOG3
SCL
CL2/1
T2O
CL2/2
4-bit Counter 2/1
RES
DCG
OVF1
POUT
OUTPUT
8-bit Counter 2/2
OVF2
RES
TOG2
T2C
Compare 2/1
Control
M2
Compare 2/1
MOUT
to
Modulator 3
INT4
Bi-phase
Manchester
Modulator
CM1
T2CO1
T2CM
T2CO2
Timer 2
Modulator
Output-stage
SSI POUT
SO
Control
I/O-bus
SSI
SSI
35
4535E–4BMCU–05/07
5.3.2.1
Timer 2 Modes
Mode 1: 12-bit Compare Counter
The 4-bit stage and the 8-bit stage work together as a 12-bit compare counter. A compare match
signal of the 4-bit and the 8-bit stage generates the signal for the counter reset, toggle flip-flop or
interrupt. The compare action is programmable via the compare mode register (T2CM). The
4-bit counter overflow (OVF1) supplies the clock output (POUT) with clocks. The duty cycle generator (DCG) has to be bypassed in this mode.
Figure 5-11. 12-bit Compare Counter
POUT (CL2/1 /16)
CL2/1
OVF2
4-bit Counter
DCG
8-bit Counter
RES
TOG2
RES
INT4
4-bit Compare
8-bit Compare
CM1
CM2
Timer 2
Output Mode
and T2OTM-bit
4-bit Register
T2D1, 0
8-bit Register
T2RM
T2OTM
T2IM
T2CTM
Mode 2: 8-bit Compare Counter with 4-bit Programmable Prescaler
The 4-bit stage is used as programmable prescaler for the 8-bit counter stage. In this mode, a
duty cycle stage is also available. This stage can be used as an additional 2-bit prescaler or for
generating duty cycles of 25%, 33% and 50%. The 4-bit compare output (CM1) supplies the
clock output (POUT) with clocks.
Figure 5-12. 8-bit Compare Counter
DCGO
POUT
CL2/1
OVF2
4-bit Counter
DCG
8-bit Counter
RES
TOG2
RES
INT4
4-bit Compare
CM1
8-bit Compare
CM2
Timer 2
Output Mode
and T2OTM-bit
4-bit Register
36
T2D1, 0
8-bit Register
T2RM
T2OTM
T2IM
T2CTM
ATAR092/ATAR892
4535E–4BMCU–05/07
ATAR092/ATAR892
Mode 3/4: 8-bit Compare Counter and 4-bit Programmable Prescaler
In these modes the 4-bit and the 8-bit counter stages work independently as a 4-bit prescaler
and an 8-bit timer with an 2-bit prescaler or as a duty cycle generator. Only in the mode 3 and
mode 4, can the 8-bit counter be supplied via the external clock input (T2I) which is selected via
the P4CR register. The 4-bit prescaler is started via activating of mode 3 and stopped and reset
in mode 4. Changing mode 3 and 4 has no effect for the 8-bit timer stage. The 4-bit stage can be
used as prescaler for Timer 3, the SSI or to generate the stop signal for modulator 2 and
modulator 3.
Figure 5-13. 4-/8-bit Compare Counter
DCGO
CL2/2
T2I
OVF2
DCG
SYSCL
8-bit Counter
RES
INT4
8-bit Compare
CM2
Timer 2
Output Mode
and T2OTM-bit
P4CR P41M2, 1
TOG3
T1OUT
SYSCL
SCL
T2D1, 0
8-bit Register
T2RM
T2OTM
T2IM
T2CTM
POUT
MUX
4-bit Counter
RES
4-bit Compare
T2CS1, 0
4-bit Register
37
4535E–4BMCU–05/07
5.3.2.2
Timer 2 Output Modes
The signal at the timer output is generated via modulator 2. In the toggle mode, the compare
match event toggles the output T2O. For high resolution duty cycle modulation 8 bits or 12 bits
can be used to toggle the output. In the duty cycle burst modulator modes the DCG output is
connected to T2O and switched on and off either by the toggle flipflop output or the serial data
line of the SSI. Modulator 2 also has 2 modes to output the content of the serial interface as
Bi-phase or Manchester code.
The modulator output stage can be configured by the output control bits in the T2M2 register.
The modulator is started with the start of the shift register (SIR = 0) and stopped either by carrying out a shift register stop (SIR = 1) or compare match event of stage 1 (CM1) of Timer 2. For
this task, Timer 2 mode 3 must be used and the prescaler has to be supplied with the internal
shift clock (SCL).
Figure 5-14. Timer 2 Modulator Output Stage
DCGO
SO
TOG2
RE
T2O
Bi-phase/
Manchester
Modulator
FE
SSI
CONTROL
S1
S3
M2
Toggle
S2
RES/SET
Modulator 3
OMSK
M2
T2M2
5.3.2.3
T2OS2, 1, 0 T2TOP
Timer 2 Output Signals
Timer 2 Output Mode 1
Toggle Mode A: A Timer 2 compare match toggles the output flip-flop (M2) -> T2O
Figure 5-15. Interrupt Timer/Square Wave Generator – the Output Toggles with Each Edge
Compare Match Event
Input
Counter 2
T2R
0
0
0
1
2
3
4
0
1
2
3
4
0
1
2
3
4
0
1
Counter 2
CMx
INT4
T2O
38
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4535E–4BMCU–05/07
ATAR092/ATAR892
Toggle Mode B: A Timer 2 compare match toggles the output flip-flop (M2) -> T2O
Figure 5-16. Pulse Generator – the Timer Output Toggles with the Timer Start if the T2TS-bit
Is Set
Input
Counter 2
T2R
0
0
0
1
2
3
4
5
6
7
4095/
255
0
1
2
3
4
5
6
Counter 2
CMx
INT4
T2O
T2O
Toggle
by Start
Toggle Mode C: A Timer 2 compare match toggles the output flip-flop (M2) -> T2O
Figure 5-17. Pulse Generator – the Timer Toggles with Timer Overflow and Compare Match
Input
Counter 2
T2R
0
0
0
1
2
3
4
5
6
7
4095/
255
0
1
2
3
4
5
6
Counter 2
CMx
OVF2
INT4
T2O
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4535E–4BMCU–05/07
Timer 2 Output Mode 2
Duty Cycle Burst Generator 1: The DCG output signal (DCGO) is given to the output, and
gated by the output flip-flop (M2)
Figure 5-18. Carrier Frequency Burst Modulation with Timer 2 Toggle Flip-flop Output
DCGO
1 2 0 1 2 0 1 2 3 4 5 0 1 2 0 1 2 3 4 5 6 7 8 0 1 2 3 4 5 6 7 8 9 10 0 1 2 3 4 5
Counter 2
TOG2
M2
T2O
Counter = Compare Register (= 2)
Timer 2 Output Mode 3
Duty Cycle Burst Generator 2: The DCG output signal (DCGO) is given to the output, and
gated by the SSI internal data output (SO)
Carrier Frequency Burst Modulation with the SSI Data Output
DCGO
1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1
Counter 2
Counter = Compare Register (= 2)
TOG2
SO
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
Bit 9
Bit 10
Bit 11
Bit 12
Bit 13
T2O
Timer 2 Output Mode 4
Bi-phase Modulator: Timer 2 Modulates the SSI Internal Data Output (SO) to Bi-phase Code.
Figure 5-19. Bi-phase Modulation
TOG2
SC
8-bit SR Data
SO
0
0
0
0
1
1
0
1
0
Bit 7
T2O
1
Bit 0
1
1
0
1
0
1
Data: 00110101
40
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ATAR092/ATAR892
Timer 2 Output Mode 5
Manchester Modulator: Timer 2 Modulates the SSI internal data output (SO) to Manchester
code
Figure 5-20. Manchester Modulation
TOG2
SC
8-bit SR Data
0
SO
1
0
1
0
1
0
1
Bit 0
Bit 7
0
T2O
0
1
1
0
1
0
1
Bit 0
Bit 7
Data: 00110101
Timer 2 Output Mode 7
PWM Mode: Pulse-width modulation output on Timer 2 output pin (T2O)
In this mode the timer overflow defines the period and the compare register defines the duty
cycle. During one period only the first compare match occurrence is used to toggle the timer output flip-flop, until the overflow all further compare match are ignored. This avoids the situation
that changing the compare register causes the occurrence of several compare match during one
period. The resolution at the pulse-width modulation Timer 2 mode 1 is 12-bit and all other
Timer 2 modes are 8-bit.
Figure 5-21. PWM Modulation
Input Clock
Counter 2/2
T2R
0
0
50
255 0
255 0
100
150 255 0 50
255 0
100
Counter 2/2
CM2
OVF2
Load the Next
Compare Value
INT4
T2O
T1
T2
T
load
T2CO2 = 150
T3
T
load
T1
T
T2
T
T
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4535E–4BMCU–05/07
5.3.2.4
Timer 2 Registers
Timer 2 has 6 control registers to configure the timer mode, the time interval, the input clock and
its output function. All registers are indirectly addressed using extended addressing as
described in section “Addressing Peripherals”. The alternate functions of the Ports BP41 or
BP42 must be selected with the Port 4 control register P4CR, if one of the Timer 2 modes
require an input at T2I/BP41 or an output at T2O/BP42.
5.3.2.5
Timer 2 Control Register (T2C)
Address: '7'hex - Subaddress: '0'hex
T2C
Bit 3
Bit 2
Bit 1
Bit 0
T2CS1
T2CS0
T2TS
T2R
T2CS1
Timer 2 Clock Select bit 1
T2CS0
Timer 2 Clock Select bit 0
Table 5-8.
5.3.2.6
Reset value: 0000b
Timer 2 Clock Select Bits
T2CS1
T2CS0
Input Clock (CL 2/1) of Counter Stage 2/1
0
0
System clock (SYSCL)
0
1
Output signal of Timer 1 (T1OUT)
1
0
Internal shift clock of SSI (SCL)
1
1
Output signal of Timer 3 (TOG3)
T2TS
Timer 2 Toggle with Start
T2TS = 0, the output flip-flop of Timer 2 is not toggled with the timer start
T2TS = 1, the output flip-flop of Timer 2 is toggled when the timer is started with T2R
T2R
Timer 2 Run
T2R = 0, Timer 2 stop and reset
T2R = 1, Timer 2 run
Timer 2 Mode Register 1 (T2M1)
Address: '7'hex - Subaddress: '1'hex
T2M1
42
Bit 3
Bit 2
Bit 1
Bit 0
T2D1
T2D0
T2MS1
T2MS0
T2D1
Timer 2 Duty cycle bit 1
T2D0
Timer 2 Duty cycle bit 0
Reset value: 1111b
ATAR092/ATAR892
4535E–4BMCU–05/07
ATAR092/ATAR892
Table 5-9.
Timer 2 Duty Cycle Bits
T2D1
T2D0
1
1
Bypassed (DCGO0)
/1
1
0
Duty cycle 1/1 (DCGO1)
/2
0
1
Duty cycle 1/2 (DCGO2)
/3
0
0
Duty cycle 1/3 (DCG03)
/4
T2MS1
Timer 2 Mode Select bit 1
T2MS0
Timer 2 Mode Select bit 0
Table 5-10.
Additional Divider Effect
Timer 2 Mode Select Bits
Mode
T2MS1
T2MS0
1
1
2
1
3
0
4
5.3.2.7
Function of Duty Cycle Generator (DCG)
0
Clock Output (POUT)
Timer 2 Modes
1
4-bit counter overflow (OVF1)
12-bit compare counter, the DCG
have to be bypassed in this mode
0
4-bit compare output (CM1)
8-bit compare counter with 4-bit
programmable prescaler and duty
cycle generator
4-bit compare output (CM1)
8-bit compare counter clocked by
SYSCL or the external clock input
T2I, 4-bit prescaler run, the
counter 2/1 starts after writing
mode 3
4-bit compare output (CM1)
8-bit compare counter clocked by
SYSCL or the external clock input
T2I, 4-bit prescaler stop and
resets
1
0
Duty Cycle Generator
The duty cycle generator generates duty cycles of 25%, 33% or 50%. The frequency at the duty
cycle generator output depends on the duty cycle and the Timer 2 prescaler setting. The
DCG-stage can also be used as additional programmable prescaler for Timer 2.
Figure 5-22. DCG Output Signals
DCGIN
DCGO0
DCGO1
DCGO2
DCGO3
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4535E–4BMCU–05/07
5.3.2.8
Timer 2 Mode Register 2 (T2M2)
Address: '7'hex - Subaddress: '2'hex
T2M2
Bit 3
Bit 2
Bit 1
Bit 0
T2TOP
T2OS2
T2OS1
T2OS0
Reset value: 1111b
T2TOP
Timer 2 Toggle Output Preset
This bit allows the programmer to preset the Timer 2 output T2O.
T2TOP = 0, resets the toggle outputs with the write cycle (M2 = 0)
T2TOP = 1, sets toggle outputs with the write cycle (M2 = 1)
Note: If T2R = 1, no output preset is possible
T2OS2
Timer 2 Output Select bit 2
T2OS1
Timer 2 Output Select bit 1
T2OS0
Timer 2 Output Select bit 0
Table 5-11.
Timer 2 Output Select Bits
Output Mode
T2OS2
T2MS1
T2MS0
Clock Output
1
1
1
1
Toggle mode: a Timer 2 compare match toggles
the output flip-flop (M2) →T2O
2
1
1
0
Duty cycle burst generator 1: the DCG output
signal (DCG0) is given to the output and gated by
the output flip-flop (M2)
3
1
0
1
Duty cycle burst generator 2: the DCG output
signal (DCGO) is given to the output and gated by
the SSI internal data output (SO)
4
1
0
0
Bi-phase modulator: Timer 2 modulates the SSI
internal data output (SO) to Bi-phase code
5
0
1
1
Manchester modulator: Timer 2 modulates the
SSI internal data output (SO) to Manchester code
6
0
1
0
SSI output: T2O is used directly as SSI internal
data output (SO)
7
0
0
1
PWM mode: an 8/12-bit PWM mode
8
0
0
0
Not allowed
If one of these output modes is used the T2O alternate function of Port 4 must also be activated.
5.3.2.9
Timer 2 Compare and Compare Mode Registers
Timer 2 has two separate compare registers, T2CO1 for the 4-bit stage and T2CO2 for the 8-bit
stage of Timer 2. The timer compares the contents of the compare register current counter value
and if it matches it generates an output signal. Dependent on the timer mode, this signal is used
to generate a timer interrupt, to toggle the output flip-flop as SSI clock or as a clock for the next
counter stage.
In the 12-bit timer mode, T2CO1 contains bits 0 to 3 and T2CO2 bits 4 to 11 of the 12-bit compare value. In all other modes, the two compare registers work independently as a 4- and 8-bit
compare register. When assigned to the compare register a compare event will be suppressed.
44
ATAR092/ATAR892
4535E–4BMCU–05/07
ATAR092/ATAR892
5.3.2.10
Timer 2 Compare Mode Register (T2CM)
Address: '7'hex - Subaddress: '3'hex
T2CM
Bit 3
Bit 2
Bit 1
Bit 0
T2OTM
T2CTM
T2RM
T2IM
T2OTM
Timer 2 Overflow Toggle Mask bit
T2OTM = 0, disable overflow toggle
T2OTM = 1, enable overflow toggle, a counter overflow (OVF2) toggles the output
flip-flop (TOG2). If the T2OTM-bit is set, only a counter overflow
can generate an interrupt except on the Timer 2 output mode 7.
T2CTM
Timer 2 Compare Toggle Mask bit
T2CTM = 0, disable compare toggle
T2CTM = 1, enable compare toggle, a match of the counter with the compare
register toggles output flip-flop (TOG2). In Timer 2 output mode 7
and when the T2CTM-bit is set, only a match of the counter with the
compare register can generate an interrupt.
T2RM
Timer 2 Reset Mask bit
T2RM = 0, disable counter reset
T2RM = 1, enable counter reset, a match of the counter with the compare register
resets the counter
T2IM
Timer 2 Interrupt Mask bit
T2IM = 0, disable Timer 2 interrupt
T2IM = 1, enable Timer 2 interrupt
Table 5-12.
5.3.2.11
Reset value: 0000b
Timer 2 Toggle Mask Bits
Timer 2 Output Mode
T2OTM
T2CTM
Timer 2 Interrupt Source
1, 2, 3, 4, 5 and 6
0
x
1, 2, 3, 4, 5 and 6
1
x
Overflow (OVF2)
7
x
1
Compare match (CM2)
Compare match (CM2)
Timer 2 COmpare Register 1 (T2CO1)
Address: '7'hex -Subaddress: '4'hex
T2CO1
Write cycle
Bit 3
Bit 2
Bit 1
Bit 0
Reset value: 1111b
In prescaler mode the clock is bypassed if the compare register T2CO1 contains 0.
5.3.2.12
Timer 2 COmpare Register 2 (T2CO2) Byte Write
Address: '7'hex - Subaddress: '5'hex
T2CO2
First write cycle
Bit 3
Bit 2
Bit 1
Bit 0
Reset value: 1111b
Second write cycle
Bit 7
Bit 6
Bit 5
Bit 4
Reset value: 1111b
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4535E–4BMCU–05/07
5.3.3
Timer 3
5.3.3.1
Features
• 2 compare registers
• Capture register
• Edge sensitive input with zero cross detection capability
• Trigger and single action modes
• Output control modes
• Automatically modulation and demodulation modes
• FSK modulation
• Pulse width Modulation (PWM)
• Manchester demodulation together with SSI
• Bi-phase demodulation together with SSI
• Pulse-width demodulation together with SSI
Figure 5-23. Timer 3
I/O-bus
T3CS
T3M
T3I
SCI
T3EX
T3I
CP3
T3CP
Demodulator 3
CM31
SI
RES
T3EX
SYSCL
T1OUT
POUT
INT5
CL3
8-bit Counter 3
T3C
T3ST
TOG3
SO
Control
M2
RES
Compare 3/1
Compare 3/2
T3CO1
T3CO2
I/O-bus
Control
T3CM1
T3O
Modulator 3
T3CM2
Timer 2
SSI
SSI
Timer 3 consists of an 8-bit up-counter with two compare registers and one capture register. The
timer can be used as event counter, timer and signal generator. Its output can be programmed
as modulator and demodulator for the serial interface. The two compare registers enable various
modes of signal generation, modulation and demodulation. The counter can be driven by internal and external clock sources. For external clock sources, it has a programmable
edge-sensitive input which can be used as counter input, capture signal input or trigger input.
This timer input is synchronized with SYSCL. Therefore, in the power-down mode SLEEP (CPU
core -> sleep and OSC-Stop -> yes), this timer input is stopped too. The counter is readable via
its capture register while it is running. In capture mode, the counter value can be captured by a
programmable capture event from the Timer 3 input or Timer 2 output.
46
ATAR092/ATAR892
4535E–4BMCU–05/07
ATAR092/ATAR892
A special feature of this timer is the trigger- and single-action mode. In trigger mode, the counter
starts counting triggered by the external signal at its input. In single-action mode, the counter
counts only one time up to the programmed compare match event. These modes are very useful
for modulation, demodulation, signal generation, signal measurement and phase controlling. For
phase controlling, the timer input is protected against negative voltages and has zero-cross
detection capability.
Timer 3 has a modulator output stage and input functions for demodulation. As modulator it
works together with Timer 2 or the serial interface. When the shift register is used for modulation
the data shifted out of the register is encoded bitwise. In all demodulation modes, the decoded
data bits are shifted automatically into the shift register.
5.3.3.2
Timer/Counter Modes
Timer 3 has 6 timer modes and 6 modulator/demodulator modes. The mode is set via the Timer
3 Mode Register T3M.
In all these modes, the compare register and the compare-mode register belonging to it define
the counter value for a compare match and the action of a compare match. A match of the current counter value with the content of one compare register triggers a counter reset, a Timer 3
interrupt or the toggling of the output flip-flop. The compare mode registers T3M1 and T3M2
contain the mask bits for enabling or disabling these actions.
The counter can also be enabled to execute single actions with one or both compare registers. If
this mode is set the corresponding compare match event is generated only once after the
counter start.
Most of the timer modes use their compare registers alternately. After the start has been activated, the first comparison is carried out via the compare register 1, the second is carried out via
the compare register 2, the third is carried out again via the compare register 1 and so on. This
makes it easy to generate signals with constant periods and variable duty cycle or to generate
signals with variable pulse and space widths.
If single-action mode is set for one compare register, the comparison is always carried out after
the first cycle via the other compare register.
The counter can be started and stopped via the control register T3C. This register also controls
the initial level of the output before start. T3C contains the interrupt mask for a T3I input
interrupt.
Via the Timer 3 clock-select register, the internal or external clock source can be selected. This
register selects also the active edge of the external input. An edge at the external input T3I can
generate also an interrupt if the T3EIM-bit is set and the Timer 3 is stopped (T3R = 0) in the
T3C-register.
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4535E–4BMCU–05/07
Figure 5-24. Counter 3 Stage
TOG2 T3I
T3EIM
Control
INT5
Capture Register
D
NQ
CL3
T3SM1
T3RM1
T3IM1
T3TM1
: T3M1
RES
8-bit Counter
CM31
Control
8-bit Comparator
TOG3
C31
C32
CM32
Compare Register 1
NQ
T3SM2
D
T3RM2
T3IM2
T3TM2
: T3M2
Compare Register 2
The status of the timer as well as the occurrence of a compare match or an edge detect of the
input signal is indicated by the status register T2ST. This allows identification of the interrupt
source because all these events share only one timer interrupt.
Timer 3 compares data values
The Timer 3 has two 8-bit compare registers (T3CO1, T3CO2). The compare data value can be
‘m’ for each of the Timer 3 compare registers.
The compare data value for the compare registers is:
m = x +1
0 ≤ x ≤ 255
Timer 3 – Mode 1:
Timer/Counter
The selected clock from an internal or external source increments the 8-bit counter. In this mode,
the timer can be used as event counter for external clocks at T3I or as timer for generating interrupts and pulses at T3O. The counter value can be read by the software via the capture register.
Figure 5-25. Counter Reset with Each Compare Match
T3R
0
0
0
1
2
3
0
1
2
3
4
5
0
1
2
3
0
1
2
3
Counter 3
CM31
CM32
INT5
T3O
48
ATAR092/ATAR892
4535E–4BMCU–05/07
ATAR092/ATAR892
Figure 5-26. Counter Reset with Compare Register 2 and Toggle with Start
CL3
T3R
0
0
0
1
2
3
4
5
6
7
8
9
0
1
2
3
4
5
6
Counter 3
CM31
CM32
INT5
T2O
T3O
Toggle
by start
Figure 5-27. Single Action of Compare Register 1
T3R
0 0 1 2 3 4 5 6 7 8 9 10 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1
Counter 3
CM31
CM32
T3O
Toggle by Start
Timer 3 – Mode 2:
Timer/Counter, External Trigger Restart and External
Capture (with T3I Input)
The counter is driven by an internal clock source. After starting with T3R, the first edge from the
external input T3I starts the counter. The following edges at T3I load the current counter value
into the capture register, reset the counter and restart it. The edge can be selected by the programmable edge decoder of the timer input stage. If single-action mode is activated for one or
both compare registers the trigger signal restarts the single action.
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4535E–4BMCU–05/07
Figure 5-28. Externally Triggered Counter Reset and Start Combined with Single-action Mode
T3R
0 0 0 0 0 0 0 0 1 2 3 4 5 6 7 8 9 10 0 1 2 X X X 0 1 2 3 4 5 6 7 8 9 10 0 1 2 X X X X
Counter 3
T3EX
CM31
CM32
T3O
Timer 3 – Mode 3:
Timer/Counter, Internal Trigger Restart and Internal Capture
(with TOG2)
The counter is driven by an internal or external (T3I) clock source. The output toggle signal of
Timer 2 resets the counter. The counter value before the reset is saved in the capture register. If
single-action mode is activated for one ore both compare registers, the trigger signal restarts the
single actions. This mode can be used for frequency measurements or as event counter with
time gate (see combination mode 10).
Figure 5-29. Event Counter with Time Gate
T3R
T3I
0 0 1 2 3 4 5 6 7 8 9 10
11
0 1
2
3
4
0 1 2
Counter 3
TOG2
T3CP
Register
Capture Value = 0
Timer 3 – Mode 4:
Capture Value = 11
Capt. Val. = 4
Timer/Counter
The timer runs as timer/counter in mode 1, but its output T3O is used as output for the Timer 2
output signal.
Timer 3 – Mode 5:
Timer/Counter, External Trigger Restart and External
Capture (with T3I Input)
The Timer 3 runs as timer/counter in mode 2, but its output T3O is used as output for the Timer
2 output signal.
50
ATAR092/ATAR892
4535E–4BMCU–05/07
ATAR092/ATAR892
5.3.3.3
Timer 3 Modulator/Demodulator Modes
Timer 3 – Mode 6: Carrier Frequency Burst Modulation Controlled by Timer 2
Output Toggle Flip-Flop (M2)
The Timer 3 counter is driven by an internal or external clock source. Its compare- and compare
mode registers must be programmed to generate the carrier frequency via the output toggle
flip-flop. The output toggle flip-flop of Timer 2 is used to enable or disable the Timer 3 output.
Timer 2 can be driven by the toggle output signal of Timer 3 or any other clock source (see combination mode 11).
Timer 3 – Mode 7:
Carrier Frequency Burst Modulation Controlled by SSI
Internal Output (SO)
The Timer 3 counter is driven by an internal or external clock source. Its compare- and compare
mode registers must be programmed to generate the carrier frequency via the output toggle
flip-flop. The output (SO) of the SSI is used to enable or disable the Timer 3 output. The SSI
should be supplied with the toggle signal of Timer 2 (see combination mode 12).
Timer 3 – Mode 8:
FSK Modulation with Shift Register Data (SO)
The two compare registers are used for generating two different time intervals. The SSI internal
data output (SO) selects which compare register is used for the output frequency generation. A
‘0’ level at the SSI data output enables the compare register 1. A ‘1’ level enables compare register 2. The compare- and compare mode registers must be programmed to generate the two
frequencies via the output toggle flip-flop. The SSi can be supplied with the toggle signal of
Timer 2. The Timer 3 counter is driven by an internal or external clock source. The Timer 2
counter is driven by the Counter 3 (TOG3) (see also combination mode 13).
Figure 5-30. FSK Modulation
T3R
0 1 2 3 4 0 1 2 3 4 0 1 2 3 4 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 3 4 0 1
Counter 3
CM31
CM32
SO
0
1
0
T3O
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4535E–4BMCU–05/07
Timer 3 – Mode 9:
Pulse-width Modulation with the Shift Register
The two compare registers are used for generating two different time intervals. The SSI internal
data output (SO) selects which compare register is used for the output pulse generation. In this
mode both compare- and compare mode registers must be programmed for generating the two
pulse widths. It is also useful to enable the single-action mode for extreme duty cycles. Timer 2
is used as baudrate generator and for the trigger restart of Timer 3. The SSI must be supplied
with a toggle signal of Timer 2. The counter is driven by an internal or external clock source (see
combination mode 7).
Figure 5-31. Pulse-width Modulation
TOG2
SIR
0
SO
1
0
1
SCO
T3R
Counter 3
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 3 4 5 6 7 8 9 10 1112131415 0 1 2 3 4 5 6 7 8 9 101112131415 0 1 2 3 4
CM31
CM32
T3O
Timer 3 – Mode 10: Manchester Demodulation/Pulse-width Demodulation
For Manchester demodulation, the edge detection stage must be programmed to detect each
edge at the input. These edges are evaluated by the demodulator stage. The timer stage is used
to generate the shift clock for the SSI. The compare register 1 match event defines the correct
moment for shifting the state from the input T3I as the decoded bit into shift register – after that
the demodulator waits for the next edge to synchronize the timer by a reset for the next bit. The
compare register 2 can also be used to detect a time-out error and handle it with an interrupt
routine (see also combination mode 8).
Figure 5-32. Timer 3 – Manchester Demodulation
Timer 3
Mode
Manchester Demodulation Mode
Synchronize
T3I
1
0
1
1
1
0
0
1
1
0
T3EX
SI
CM3 = SCI
SR-DATA
52
1
1
1
0
0
1
1
BIT 0
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
0
ATAR092/ATAR892
4535E–4BMCU–05/07
ATAR092/ATAR892
Timer 3 – Mode 11: Bi-phase Demodulation
In the Bi-phase demodulation mode, the timer operates like in Manchester demodulation mode.
The difference is that the bits are decoded via a toggle flip-flop. This flip-flop samples the edge in
the middle of the bitframe and the compare register 1 match event shifts the toggle flip-flop output into shift register (see also combined mode 9).
Figure 5-33. Timer 3 – Bi-phase Demodulation
Timer 3
Mode
Synchronize
0
Biphase Demodulation Mode
1
0
1
0
1
0
1
0
T3I
T3EX
Q1 = SI
CM31 = SCI
Reset
Counter 3
0
1
BIT 0
BIT 1
SR-DATA
1
BIT 2
0
1
0
1
BIT 3
BIT 4
BIT 5
BIT 6
0
Timer 3 – Mode 12: Timer/Counter with External Capture Mode (T3I)
The counter is driven by an internal clock source and an edge at the external input T3I loads the
counter value into the capture register. The edge can be selected with the programmable edge
detector of the timer input stage. This mode can be used for signal and pulse measurements.
Figure 5-34. External Capture Mode
T3R
T3I
0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41
Counter 3
T3CP
Register
Capture Value = X
Capture Value = 17
Capture Value = 35
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4535E–4BMCU–05/07
5.3.3.4
Timer 3 Modulator for Carrier Frequency Burst Modulation
If the output stage operates as pulse-width modulator for the shift register the output can be
stopped with stage 1 of Timer 2. For this task, the timer mode 3 must be used and the prescaler
must be supplied by the internal shift clock of the shift register.
The modulator can be started with the start of the shift register (SIR = 0) and stopped either by a
shift register stop (SIR = 1) or compare match event of stage 1 of Timer 2. For this task, the
Timer 2 must be used in mode 3 and the prescaler stage must be supplied by the internal shift
clock of the shift register.
Figure 5-35. Modulator 3
0
TOG3
T3
M3
1
Set Res
T3 TOP
2
T3O
MUX
Timer 3 Mode
SO
M2
6
7
9
other
3
SSI/
Control
T3O
MUX 1
MUX 2
MUX 3
MUX 0
OMSK
T3M
5.3.3.5
Timer 3 Demodulator for Bi-phase, Manchester and Pulse-width-modulated Signals
The demodulator stage of Timer 3 can be used to decode Bi-phase, Manchester and
pulse-width-coded signals.
Figure 5-36. Timer 3 – Demodulator 3
T3M
SCI
T3I
Demodulator 3
SI
Res
T3EX
CM31
Counter 3
Reset
Counter 3
Control
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5.3.3.6
Timer 3 Registers
5.3.3.7
Timer 3 Mode Register (T3M)
Address: 'Bhex - Subaddress: '0'hex
T3M
Bit 3
Bit 2
Bit 1
Bit 0
T3M3
T3M2
T3M1
T3M0
T3M3
Timer 3 Mode select bit 3
T3M2
Timer 3 Mode select bit 2
T3M1
Timer 3 Mode select bit 1
T3M0
Timer 3 Mode select bit 0
Table 5-13.
Reset value: 1111b
Timer 3 Mode Select Bits
Mode
T3M3
T3M2
T3M1
T3M0
1
1
1
1
1
Timer/counter with a read access
2
1
1
1
0
Timer/counter, external capture and external trigger
restart mode (T3I)
3
1
1
0
1
Timer/counter, internal capture and internal trigger
restart mode (TOG2)
4
1
1
0
0
Timer/counter mode 1 without output
(T2O -> T3O)
5
1
0
1
1
Timer/counter mode 2 without output
(T2O -> T3O)
6
1
0
1
0
Burst modulation with Timer 2 (M2)
7
1
0
0
1
Burst modulation with shift register (SO)
8
1
0
0
0
FSK modulation with shift register (SO)
9
0
1
1
1
Pulse-width modulation with shift register (SO) and
Timer 2 (TOG2), internal trigger restart (SCO) ->
counter reset
10
0
1
1
0
Manchester demodulation/pulse-width demodulation (1)
(T2O -> T3O)
11
0
1
0
1
Biphase demodulation (T2O -> T3O)
12
0
1
0
0
Timer/counter with external capture mode (T3I)
13
0
0
1
1
Not allowed
14
0
0
1
0
Not allowed
15
0
0
0
1
Not allowed
16
0
0
0
0
Not allowed
Note:
Timer 3 Modes
1. In this mode, the SSI can be used only as demodulator (8-bit NRZ rising edge). All other SSI
modes are not allowed.
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4535E–4BMCU–05/07
5.3.3.8
Timer 3 Control Register 1 (T3C) Write
Primary register address: ’C’hex - Write
Write
Bit 2
Bit 1
Bit 0
T3EIM
T3TOP
T3TS
T3R
Reset value: 0000b
T3EIM
Timer 3 Edge Interrupt Mask
T3EIM = 0, disables the interrupt when an edge event for Timer 3 occurs (T3I)
T3EIM = 1, enables the interrupt when an edge event for Timer 3 occurs (T3I)
T3TOP
Timer 3 Toggle Output Preset T3TOP = 0, sets toggle output (M3) to ‘0’
.............. ...... T3TOP = 1, sets toggle output (M3) to ‘1’
.............. ...... Note: If T3R = 1, no output preset is possible
T3TS
Timer 3 Toggle with Start . T3TS = 0, Timer 3 output is not toggled during the start
....... ...... T3TS = 1, Timer 3 output is toggled if started with T3R
T3R
5.3.3.9
Bit 3
Timer 3 Run
....... ...... T3R = 0, Timer 3 stop and reset
....... ...... T3R = 1, Timer 3 run
Timer 3 Status Register 1 (T3ST) Read
Primary register address: ’C’hex - Read
Read
Bit 2
Bit 1
Bit 0
–
T3ED
T3C2
T3C1
Reset value: x000b
T3ED
Timer 3 Edge Detect
This bit will be set by the edge-detect logic of Timer 3 input (T3I)
T3C2
Timer 3 Compare 2
This bit will be set when a match occurs between Counter 3 and T3CO2
T3C1
Timer 3 Compare 1
This bit will be set when a match occurs between Counter 3 and T3CO1
Note:
56
Bit 3
The status bits T3C1, T3C2 and T3ED will be reset after a READ access to T3ST.
ATAR092/ATAR892
4535E–4BMCU–05/07
ATAR092/ATAR892
5.3.3.10
Timer 3 Clock Select Register (T3CS)
Address: ‘B’hex - Subaddress: ‘1’hex
T3CS
Bit 3
Bit 2
Bit 1
Bit 0
T3E1
T3E0
T3CS1
T3CS0
T3E1
Timer 3 Edge select bit 1
T3E0
Timer 3 Edge select bit 0
Table 5-14.
External Input Edge Select Bits
T3E1
T3E0
1
1
–
1
0
Positive edge at T3I pin
0
1
Negative edge at T3I pin
0
0
Each edge at T3I pin
Timer 3 Input Edge Select (T3I)
T3CS1
Timer 3 Clock Source select bit 1
T3CS0
Timer 3 Clock Source select bit 0
Table 5-15.
5.3.3.11
Reset value: 1111b
Select Clock Source Bits
T3CS1
TCS0
1
1
Counter 3 Input Signal (CL3)
System clock (SYSCL)
1
0
Output signal of Timer 2 (POUT)
0
1
Output signal of Timer 1 (T1OUT)
0
0
External input signal from T3I edge detect
Timer 3 Compare- and Compare Mode Register
Timer 3 has two separate compare registers T3CO1 and T3CO2 for the 8-bit stage of Timer 3.
The timer compares the content of the compare register with the current counter value. If both
match, it generates a signal. This signal can be used for the counter reset, to generate a timer
interrupt, for toggling the output flip-flop, as SSI clock or as clock for the next counter stage. For
each compare register, a compare-mode register exists. These registers contain mask bits to
enable or disable the generation of an interrupt, a counter reset, or an output toggling with the
occurrence of a compare match of the corresponding compare register. The mask bits for activating the single-action mode can also be located in the compare mode registers. When
assigned to the compare register a compare event will be suppressed.
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5.3.3.12
Timer 3 Compare Mode Register 1 (T3CM1)
Address: ‘B’hex - Subaddress: ‘2’hex
T3CM1
Bit 3
Bit 2
Bit 1
Bit 0
T3SM1
T3TM1
T3RM1
T3IM1
Reset value: 0000b
T3SM1
Timer 3 Single action Mask bit 1
T3SM1 = 0, disables single-action compare mode
T3SM1 = 1, enables single-compare mode. After this bit is set, the compare
register (T3CO1) is used until the next compare match.
T3TM1
Timer 3 compare Toggle action Mask bit 1
T3TM1 = 0, disables compare toggle
T3TM1 = 1, enables compare toggle. A match of Counter 3 with the compare
register (T3CO1) toggles the output flip-flop (TOG3).
T3RM1
Timer 3 Reset Mask bit 1
T3RM1 = 0, disables counter reset
T3RM1 = 1, enables counter reset. A match of Counter 3 with the compare
register (T3CO1) resets the Counter 3.
T3IM1
Timer 3 Interrupt Mask bit 1
T3RM1 = 0, disables Timer 3 interrupt for T3CO1 register.
T3RM1 = 1, enables Timer 3 interrupt for T3CO1 register.
T3CM1 contains the mask bits for the match event of the Counter 3 compare register 1
5.3.3.13
Timer 3 Compare Mode Register 2 (T3CM2)
Address: ‘B’hex - Subaddress: ‘3’hex
T3CM2
Bit 3
Bit 2
Bit 1
Bit 0
T3SM2
T3TM2
T3RM2
T3IM2
Reset value: 0000b
T3SM2
Timer 3 Single action Mask bit 2
T3SM2 = 0, disables single-action compare mode
T3SM2 = 1, enables single-compare mode. After this bit is set, the compare
register (T3CO2) is used until the next compare match.
T3TM2
Timer 3 compare Toggle action Mask bit 2
T3TM2 = 0, disables compare toggle
T3TM2 = 1, enables compare toggle. A match of Counter 3 with the compare
register (T3CO2) toggles the output flip-flop (TOG3).
T3RM2
Timer 3 Reset Mask bit 2
T3RM2 = 0, disables counter reset
T3RM2 = 1, enables counter reset. A match of Counter 3 with the compare
register (T3CO2) resets the Counter 3.
T3IM2
Timer 3 Interrupt Mask bit 2
T3RM2 = 0, disables Timer 3 interrupt for T3CO2 register.
T3RM2 = 1, enables Timer 3 interrupt for T3CO2 register.
T3CM2 contains the mask bits for the match event of Counter 3 compare register 2
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The compare registers and corresponding counter reset masks can be used to program the
counter time intervals and the toggle masks can be used to program output signal. The single-action mask can also be used in this mode. It starts operating after the timer started with
T3R.
5.3.3.14
Timer 3 COmpare Register 1 (T3CO1) Byte Write
Address: ‘B’hex - Subaddress: ‘4’hex
High Nibble
Second write cycle
Bit 7
Bit 6
Bit 5
Bit 4
Reset value: 1111b
Bit 0
Reset value: 1111b
Low Nibble
First write cycle
5.3.3.15
Bit 3
Bit 2
Bit 1
Timer 3 COmpare Register 2 (T3CO2) Byte Write
Address: ‘B’hex - Subaddress: ‘5’hex
High Nibble
Second write cycle
Bit 7
Bit 6
Bit 5
Bit 4
Reset value: 1111b
Bit 0
Reset value: 1111b
Low Nibble
First write cycle
Bit 3
Bit 2
Bit 1
5.3.3.16
Timer 3 Capture Register
The counter content can be read via the capture register. There are two ways to use the capture
register. In modes 1 and 4, it is possible to read the current counter value directly out of the capture register. In the capture modes 2, 3, 5 and 12, a capture event like an edge at the Timer 3
input or a signal from Timer 2 stores the current counter value into the capture register. This
counter value can be read from the capture register.
5.3.3.17
Timer 3 CaPture Register (T3CP) Byte Read
Address: ‘B’hex - Subaddress: ‘4’hex
High Nibble
First read cycle
Bit 7
Bit 6
Bit 5
Bit 4
Reset value: xxxxb
Bit 0
Reset value: xxxxb
Low Nibble
Second read cycle
Bit 3
Bit 2
Bit 1
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4535E–4BMCU–05/07
5.3.4
5.3.4.1
Synchronous Serial Interface (SSI)
SSI Features
• 2- and 3-wire NRZ
• 2-wire mode, additional internal 2-wire link for multi-chip packaging solutions
• With Timer 2:
– Bi-phase modulation
– Manchester modulation
– Pulse-width demodulation
– Burst modulation
• With Timer 3:
– Pulse-width modulation (PWM)
– FSK modulation
– Bi-phase demodulation
– Manchester demodulation
– Pulse-width demodulation
– Pulse position Demodulation
5.3.4.2
SSI Peripheral Configuration
The synchronous serial interface (SSI) can be used either for serial communication with external
devices such as EEPROMs, shift registers, display drivers, other microcontrollers, or as a
means for generating and capturing on-chip serial streams of data. External data communication
takes place via the Port 4 (BP4),a multi-functional port which can be software configured by writing the appropriate control word into the P4CR register. The SSI can be configured in any of the
following ways:
1. 2-wire external interface for bidirectional data communication with one data terminal
and one shift clock. The SSI uses the Port BP43 as a bidirectional serial data line (SD)
and BP40 as shift clock line (SC).
2. 3-wire external interface for simultaneous input and output of serial data, with a serial
input data terminal (SI), a serial output data terminal (SO) and a shift clock (SC). The
SSI uses BP40 as shift clock (SC), while the serial data input (SI) is applied to BP43
(configured in P4CR as input!). Serial output data (SO) in this case is passed through to
BP42 (configured in P4CR to T2O) via the Timer 2 output stage (T2M2 configured in
mode 6).
3. Timer/SSI combined modes – the SSI used together with Timer 2 or Timer 3 is capable
of performing a variety of data modulation and demodulation functions (see Timer Section). The modulating data is converted by the SSI into a continuous serial stream of
data which is in turn modulated in one of the timer functional blocks. Serial demodulated data can be serially captured in the SSI and read by the controller. In the Timer 3
modes 10 and 11 (demodulation modes) the SSI can only be used as demodulator.
4. Multi-chip link (MCL) – the SSI can also be used as an interchip data interface for use in
single package multi-chip modules or hybrids. For such applications, the SSI is provided with two dedicated pads (MCL_SD and MCL_SC) which act as a two-wire
chip-to-chip link. The MCL can be activated by the MCL control bit. Should these MCL
pads be used by the SSI, the standard SD and SC pins are not required and the corresponding Port 4 ports are available as conventional data ports.
60
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Figure 5-37. Block Diagram of the Synchronous Serial Interface
I/O-bus
Timer 2 /Timer 3
SIC1
SIC2
SO
SISC
Control
SC
SI SCI
INT3
SC
SSI-Control
MCL_SC
TOG2
POUT
T1OUT
SYSCL
Output
/2
SO
Shift_CL
8-bit Shift Register
MSB
LSB
STB
SI
MCL_SD
SD
SRB
Transmit
Buffer
Receive
Buffer
I/O-bus
5.3.4.3
General SSI Operation
The SSI is comprised essentially of an 8-bit shift register with two associated 8-bit buffers - the
receive buffer (SRB) for capturing the incoming serial data and a transmit buffer (STB) for intermediate storage of data to be serially output. Both buffers are directly accessible by software.
Transferring the parallel buffer data into and out of the shift register is controlled automatically by
the SSI control, so that both single byte transfers or continuous bit streams can be supported.
The SSI can generate the shift clock (SC) either from one of several on-chip clock sources or
accept an external clock. The external shift clock is output on, or applied to the Port BP40.
Selection of an external clock source is performed by the Serial Clock Direction control bit
(SCD). In the combinational modes, the required clock is selected by the corresponding timer
mode.
The SSI can operate in three data transfer modes – synchronous 8-bit shift mode, a 9-bit
Multi-Chip Link mode (MCL), containing 8-bit data and 1-bit acknowledge, and a corresponding
8-bit MCL mode without acknowledge. In both MCL modes the data transmission begins after a
valid start condition and ends with a valid stop condition.
External SSI clocking is not supported in these modes. The SSI should thus generate and have
full control over the shift clock so that it can always be regarded as an MCL-bus master device.
All directional control of the external data port used by the SSI is handled automatically and is
dependent on the transmission direction set by the Serial Data Direction (SDD) control bit. This
control bit defines whether the SSI is currently operating in transmit (TX) mode or receive (RX)
mode.
Serial data is organized in 8-bit telegrams which are shifted with the most significant bit first. In
the 9-bit MCL mode, an additional acknowledge bit is appended to the end of the telegram for
handshaking purposes (see MCL protocol).
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4535E–4BMCU–05/07
At the beginning of every telegram, the SSI control loads the transmit buffer into the shift register
and proceeds immediately to shift data serially out. At the same time, incoming data is shifted
into the shift register input. This incoming data is automatically loaded into the receive buffer
when the complete telegram has been received. Thus, data can be simultaneously received and
transmitted if required.
Before data can be transferred, the SSI must first be activated. This is performed by means of
the SSI reset control (SIR) bit. All further operation then depends on the data directional mode
(TX/RX) and the present status of the SSI buffer registers shown by the Serial Interface Ready
Status Flag (SRDY). This SRDY flag indicates the (empty/full) status of either the transmit buffer
(in TX mode), or the receive buffer (in RX mode). The control logic ensures that data shifting is
temporarily halted at any time, if the appropriate receive/transmit buffer is not ready (SRDY = 0).
The SRDY status will then automatically be set back to “1” and data shifting resumed as soon as
the application software loads the new data into the transmit register (in TX mode) or frees the
shift register by reading it into the receive buffer (in RX mode).
A further activity status (ACT) bit indicates the present status of the serial communication. The
ACT bit remains high for the duration of the serial telegram or if MCL stop or start conditions are
currently being generated. Both the current SRDY and ACT status can be read in the SSI status
register. To deactivate the SSI, the SIR bit must be set high.
5.3.4.4
8-bit Synchronous Mode
Figure 5-38. 8-bit Synchronous Mode
SC
(Rising Edge)
SC
(Falling Edge)
0
DATA
0
1
1
0
1
0
0
1
1
0
1
0
Bit 7
0
SD/TO2
1
Bit 0
Bit 0
Data: 00110101
In the 8-bit synchronous mode, the SSI can operate as either a 2- or 3-wire interface (see SSI
peripheral configuration). The serial data (SD) is received or transmitted in NRZ format, synchronized to either the rising or falling edge of the shift clock (SC). The choice of clock edge is
defined by the Serial Mode Control bits (SM0,SM1). It should be noted that the transmission
edge refers to the SC clock edge with which the SD changes. To avoid clock skew problems, the
incoming serial input data is shifted in with the opposite edge.
When used together with one of the timer modulator or demodulator stages, the SSI must be set
in the 8-bit synchronous mode 1.
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In RX mode, as soon as the SSI is activated (SIR = 0), 8 shift clocks are generated and the
incoming serial data is shifted into the shift register. This first telegram is automatically transferred into the receive buffer and the SRDY set to 0 indicating that the receive buffer contains
valid data. At the same time an interrupt (if enabled) is generated. The SSI then continues shifting in the following 8-bit telegram. If, during this time the first telegram has been read by the
controller, the second telegram will also be transferred in the same way into the receive buffer
and the SSI will continue clocking in the next telegram. Should, however, the first telegram not
have been read (SRDY = 1), then the SSI will stop, temporarily holding the second telegram in
the shift register until a certain point of time when the controller is able to service the receive
buffer. In this way no data is lost or overwritten.
Deactivating the SSI (SIR = 1) in mid-telegram will immediately stop the shift clock and latch the
present contents of the shift register into the receive buffer. This can be used for clocking in a
data telegram of less than 8 bits in length. Care should be taken to read out the final complete
8-bit data telegram of a multiple word message before deactivating the SSI (SIR = 1) and terminating the reception. After termination, the shift register contents will overwrite the receive
buffer.
Figure 5-39. Example of 8-bit Synchronous Transmit Operation
SC
lsb
msb
SD
7 6 5 4 3 2 1 0
msb
lsb msb
lsb
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
tx data 1
tx data 2
tx data 3
SIR
SRDY
ACT
Interrupt
(IFN = 0)
Interrupt
(IFN = 1)
Write STB
(tx data 1)
Write STB
(tx data 2)
Write STB
(tx data 3)
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Figure 5-40. Example of 8-bit Synchronous Receive Operation
SC
lsb msb
msb
SD
lsb
msb
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
rx data 1
lsb
7 6 5 4 3 2 1 0 7 6 5 4
rx data 2
rx data 3
SIR
SRDY
ACT
Interrupt
(IFN = 0)
Interrupt
(IFN = 1)
Read SRB
(rx data 1)
5.3.4.5
Read SRB
(rx data 2)
Read SRB
(rx data 3)
9-bit Shift Mode
In the 9-bit shift mode, the SSI is able to handle the MCL protocol (described below). It always
operates as an MCL master device, i.e., SC is always generated and output by the SSI. Both the
MCL start and stop conditions are automatically generated whenever the SSI is activated or
deactivated by the SIR-bit. In accordance with the MCL protocol, the output data is always
changed in the clock low phase and shifted in on the high phase.
Before activating the SSI (SIR = 0) and commencing an MCL dialog, the appropriate data direction for the first word must be set using the SDD control bit. The state of this bit controls the
direction of the data port (BP43 or MCL_SD). Once started, the 8 data bits are, depending on
the selected direction, either clocked into or out of the shift register. During the 9th clock period,
the port direction is automatically switched over so that the corresponding acknowledge bit can
be shifted out or read in. In transmit mode, the acknowledge bit received from the device is captured in the SSI Status Register (TACK) where it can be read by the controller. In receive mode,
the state of the acknowledge bit to be returned to the device is predetermined by the SSI Status
Register (RACK).
Changing the directional mode (TX/RX) should not be performed during the transfer of an MCL
telegram. One should wait until the end of the telegram which can be detected using the SSI
interrupt (IFN = 1) or by interrogating the ACT status.
Once started, a 9-bit telegram will always run to completion and will not be prematurely terminated by the SIR bit. So, if the SIR-bit is set to “1” in within the telegram, the SSI will complete
the current transfer and terminate the dialog with an MCL stop condition.
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ATAR092/ATAR892
Figure 5-41. Example of MCL Transmit Dialog
Start
Stop
SC
msb
lsb
7 6 5 4 3 2 1 0 A
SD
msb
lsb
7 6 5 4 3 2 1 0 A
tx data 1
tx data 2
SRDY
ACT
Interrupt
(IFN = 0)
Interrupt
(IFN = 1)
SIR
SDD
Write STB
(tx data 1)
Write STB
(tx data 2)
Figure 5-42. Example of MCL Receive Dialog
Start
Stop
SC
msb
lsb
7 6 5 4 3 2 1 0 A
SD
tx data 1
msb
lsb
7 6 5 4 3 2 1 0 A
rx data 2
SRDY
ACT
Interrupt
(IFN = 0)
Interrupt
(IFN = 1)
SIR
SDD
Write STB
(tx data 1)
Read SRB
(rx data 2)
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5.3.4.6
8-bit Pseudo MCL Mode
In this mode, the SSI exhibits all the typical MCL operational features except for the acknowledge-bit which is never expected or transmitted.
5.3.4.7
MCL Bus Protocol
The MCL protocol constitutes a simple 2-wire bidirectional communication highway via which
devices can communicate control and data information. Although the MCL protocol can support
multi-master bus configurations, the SSI in MCL mode is intended for use purely as a master
controller on a single master bus system. So all reference to multiple bus control and bus contention will be omitted at this point.
All data is packaged into 8-bit telegrams plus a trailing handshaking or acknowledge-bit. Normally the communication channel is opened with a so-called start condition, which initializes all
devices connected to the bus. This is then followed by a data telegram, transmitted by the master controller device. This telegram usually contains an 8-bit address code to activate a single
slave device connected onto the MCL bus. Each slave receives this address and compares it
with its own unique address. The addressed slave device, if ready to receive data, will respond
by pulling the SD line low during the 9th clock pulse. This represents a so-called MCL acknowledge. The controller detecting this affirmative acknowledge then opens a connection to the
required slave. Data can then be passed back and forth by the master controller, each 8-bit telegram being acknowledged by the respective recipient. The communication is finally closed by
the master device and the slave device put back into standby by applying a stop condition onto
the bus.
Figure 5-43. MCL Bus Protocol 1
(2)
(4)
Start
Condition
Data
Valid
(4)
(3)
Data
Valid
Stop
Condition
(1)
SC
SD
66
Data
Change
Bus not busy (1)
Both data and clock lines remain HIGH.
Start data transfer (2)
A HIGH to LOW transition of the SD line while the clock (SC)
is HIGH defines a START condition
Stop data transfer (3)
A LOW to HIGH transition of the SD line while the clock (SC)
is HIGH defines a STOP condition.
Data valid (4)
The state of the data line represents valid data when,
after START condition, the data line is stable for the
duration of the HIGH period of the clock signal.
ATAR092/ATAR892
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ATAR092/ATAR892
Acknowledge
All address and data words are serially transmitted to and
from the device in eight-bit words. The receiving device
returns a zero on the data line during the ninth clock cycle to
acknowledge word receipt.
Figure 5-44. MCL Bus Protocol 2
SC
1
SD
5.3.4.8
Start
1st Bit
n
8
8th Bit
9
ACK
Stop
SSI Interrupt
The SSI interrupt INT3 can be generated either by an SSI buffer register status (i.e., transmit
buffer empty or receive buffer full), the end of SSI data telegram or on the falling edge of the
SC/SD pins on Port 4 (see P4CR). SSI interrupt selection is performed by the Interrupt FunctioN
control bit (IFN). The SSI interrupt is usually used to synchronize the software control of the SSI
and inform the controller of the present SSI status. The Port 4 interrupts can be used together
with the SSI or, if the SSI itself is not required, as additional external interrupt sources. In either
case this interrupt is capable of waking the controller out of sleep mode.
To enable and select the SSI relevant interrupts use the SSI interrupt mask (SIM) and the Interrupt Function (IFN) while the Port 4 interrupts are enabled by setting appropriate control bits in
P4CR register.
5.3.4.9
Modulation and Demodulation
If the shift register is used together with Timer 2 or Timer 3 for modulation or demodulation purposes, the 8-bit synchronous mode must be used. In this case, the unused Port 4 pins can be
used as conventional bidirectional ports.
The modulation and demodulation stages, if enabled, operate as soon as the SSI is activated
(SIR = 0) and cease when deactivated (SIR = 1).
Due to the byte-orientated data control, the SSI (when running normally) generates serial bit
streams which are submultiples of 8 bits. An SSI output masking (OMSK) function permits, however, the generation of bit streams of any length. The OMSK signal is derived indirectly from the
4-bit prescaler of the Timer 2 and masks out a programmable number of unrequired trailing data
bits during the shifting out of the final data word in the bit stream. The number of non-masked
data bits is defined by the value pre-programmed in the prescaler compare register. To use output masking, the modulator stop mode bit (MSM) must be set to ‘0’ before programming the final
data word into the SSI transmit buffer. This in turn, enables shift clocks to the prescaler when
this final word is shifted out. On reaching the compare value, the prescaler triggers the OMSK
signal and all following data bits are blanked.
5.3.4.10
Internal 2-wire Multi-chip Link
Two additional on-chip pads (MCL_SC and MCL_SD) for the SC and the SD line can be used as
chip-to-chip link for multi-chip applications. These pads can be activated by setting the MCL-bit
in the SISC-register.
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4535E–4BMCU–05/07
Figure 5-45. Multi-chip Link
U505M
SCL
SDA
Multi-chip Link
MCL_SC
MCL_SD
VSS
VDD
BP40/SC
BP43/SD
ATAR092
BP10
BP13
Figure 5-46. SSI Output Masking Function
CL2/1
Timer 2
4-bit counter 2/1
Compare 2/1
CM1
OMSK
SO
SC
Output
SO
TOG2
POUT
T1OUT
SYSCL
/2
8-bit Shift Register
Shift_CL
5.3.4.11
Serial Interface Registers
5.3.4.12
Serial Interface Control Register 1 (SIC1)
MSB
LSB
Auxiliary register address: '9'hex
SIC1
Bit 2
Bit 1
Bit 0
SIR
SCD
SCS1
SCS0
Reset value: 1111b
SIR
Serial Interface Reset
SIR = 1, SSI inactive
SIR = 0, SSI active
SCD
Serial Clock Direction
SCD = 1, SC line used as output
SCD = 0, SC line used as input
Note: This bit has to be set to '1' during the MCL mode and the Timer 3 mode 10 or
11
SCS1
Serial Clock source Select bit 1
SCS0
Serial Clock source Select bit 0
Note:
68
Bit 3
With SCD = “0” the bits SCS1 and SCS0 are insignificant
ATAR092/ATAR892
4535E–4BMCU–05/07
ATAR092/ATAR892
Table 5-16.
Serial Clock Source Select Bits
SCS1
SCS0
Internal Clock for SSI
1
1
SYSCL/2
1
0
T1OUT/2
0
1
POUT/2
0
0
TOG2/2
• In Transmit mode (SDD = 1) shifting starts only if the transmit buffer has been loaded
(SRDY = 1).
• Setting SIR-bit loads the contents of the shift register into the receive buffer (synchronous
8-bit mode only).
• In MCL modes, writing a 0 to SIR generates a start condition and writing a 1 generates a stop
condition.
5.3.4.13
Serial Interface Control Register 2 (SIC2)
Auxiliary register address: ’A’hex
SIC2
Bit 3
Bit 2
Bit 1
Bit 0
MSM
SM1
SM0
SDD
Reset value: 1111b
Modular Stop Mode
MSM = 1, modulator stop mode disabled (output masking off)
MSM = 0, modulator stop mode enabled (output masking on) - used in modulation
modes for generating bit-streams which are not sub-multiples of 8 bits.
MSM
SM1
Serial Mode control bit 1
SM0
Serial Mode control bit 0
Table 5-17.
Serial Mode Control Bits
Mode
SM1
SM0
1
1
1
8-bit NRZ-data changes with the rising edge of SC
2
1
0
8-bit NRZ-data changes with the falling edge of SC
3
0
1
9-bit two-wire MCL mode
4
0
0
8-bit two-wire pseudo MCL mode (no acknowledge)
SDD
Note:
SSI Mode
Serial Data Direction
SDD = 1, transmit mode – SD line used as output (transmit data). SRDY is set by
a transmit buffer write access
SDD = 0, receive mode – SD line used as input (receive data). SRDY is set by a
receive buffer read access
SDD controls port directional control and defines the reset function for the SRDY-flag
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4535E–4BMCU–05/07
5.3.4.14
Serial Interface Status and Control Register (SISC)
Primary register address: ’A’hex
5.3.4.15
Bit 3
Bit 2
Bit 1
Bit 0
Write
MCL
RACK
SIM
IFN
Reset value: 1111b
Read
–
TACK
ACT
SRDY
Reset value: xxxxb
MCL
Multi-Chip Link activation
MCL = 1, multi-chip link disabled. This bit has to be set to 0 during
transactions to/from the EEPROM of the ATAR892
MCL = 0, connects SC and SD additionally to the internal multi-chip link pads
RACK
Receive ACKnowledge status/control bit for MCL mode
RACK = 0, transmit acknowledge in next receive telegram
RACK = 1, transmit no acknowledge in last receive telegram
TACK
Transmit ACKnowledge status/control bit for MCL mode
TACK = 0, acknowledge received in last transmit telegram
TACK = 1, no acknowledge received in last transmit telegram
SIM
Serial Interrupt Mask
SIM = 1, disable interrupts
SIM = 0, enable serial interrupt. An interrupt is generated.
IFN
Interrupt FuNction
IFN = 1, the serial interrupt is generated at the end of the telegram
IFN = 0, the serial interrupt is generated when the SRDY goes low
(i.e., buffer becomes empty/full in transmit/receive mode)
SRDY
Serial interface buffer ReaDY status flag
SRDY = 1, in receive mode: receive buffer empty
in transmit mode: transmit buffer full
SRDY = 0, in receive mode: receive buffer full
in transmit mode: transmit buffer empty
ACT
Transmission ACTive status flag
ACT = 1, transmission is active, i.e., serial data transfer. Stop or start
conditions are currently in progress.
ACT = 0, transmission is inactive
Serial Transmit Buffer (STB) – Byte Write
Primary register address: ’9’hex
STB
First write cycle
Bit 3
Bit 2
Bit 1
Bit 0
Reset value: xxxxb
Second write cycle
Bit 7
Bit 6
Bit 5
Bit 4
Reset value: xxxxb
The STB is the transmit buffer of the SSI. The SSI transfers the transmit buffer into the shift register and starts shifting with the most significant bit.
70
ATAR092/ATAR892
4535E–4BMCU–05/07
ATAR092/ATAR892
5.3.4.16
Serial Receive Buffer (SRB) – Byte Read
Primary register address: ’9’hex
SRB
First read cycle
Bit 7
Bit 6
Bit 5
Bit 4
Reset value: xxxxb
Second read cycle
Bit 3
Bit 2
Bit 1
Bit 0
Reset value: xxxxb
The SRB is the receive buffer of the SSI. The shift register clocks serial data in (most significant
bit first) and loads content into the receive buffer when complete telegram has been received.
5.3.5
Combination Modes
The UTCM consists of two timers (Timer 2 and Timer 3) and a serial interface. There is a multitude of modes in which the timers and serial interface can work together.
The 8-bit wide serial interface operates as shift register for modulation and demodulation. The
modulator and demodulator units work together with the timers and shift the data bits into or out
of the shift register.
5.3.5.1
Combination Mode Timer 2 and SSI
Figure 5-47. Combination Timer 2 and SSI
I/O-bus
P4CR
T2M1
T2M2
T2I
DCGO
SYSCL
T1OUT
TOG3
SCL
CL2/1
4-bit Counter 2/1
RES
T2C
OVF1
T2O
CL2/2
DCG
POUT
Compare 2/1
8-bit Counter 2/2
RES
Timer 2 - Control
Output
OVF2
TOG2
Compare 2/2
MOUT
INT4
POUT
T2CO1
Bi-phase
Manchester
Modulator
CM1
T2CM
T2CO2
Timer 2
Modulator
Output-stage
TOG2
SO
Control
I/O-bus
SIC1
SIC2
SISC
Control
TOG2
POUT
T1OUT
SYSCL
INT3
SCLI
SO
SC
SSI-control
MCL_SC
SCL
Output
SO
Shift_CL
MSB
8-bit Shift Register
STB
SI
MCL_SD
SD
LSB
SRB
Transmit
Buffer
Receive
Buffer
I/O-bus
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4535E–4BMCU–05/07
Combination Mode 1: Burst Modulation
SSI mode 1:
8-bit NRZ and internal data SO output to the Timer 2
modulator stage
Timer 2 mode 1, 2, 3 or 4:
8-bit compare counter with 4-bit programmable prescaler
and DCG
Duty cycle burst generator
Timer 2 output mode 3:
Figure 5-48. Carrier Frequency Burst Modulation with the SSI Internal Data Output
DCGO
1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1
Counter 2
Counter = Compare Register (= 2)
TOG2
SO
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
Bit 9
Bit 10
Bit 11
Bit 12
Bit 13
T2O
Combination Mode 2: Bi-phase Modulation 1
SSI mode 1:
8-bit shift register internal data output (SO) to the Timer 2
modulator stage
Timer 2 mode 1, 2, 3 or 4:
8-bit compare counter with 4-bit programmable prescaler
Timer 2 output mode 4:
The modulator 2 of Timer 2 modulates the SSI internal
data output to Bi-phase code
Figure 5-49. Bi-phase Modulation 1
TOG2
SC
8-bit SR Data
SO
0
0
1
1
0
1
0
Bit 7
T2O
0
1
Bit 0
0
1
1
0
1
0
1
Data: 00110101
72
ATAR092/ATAR892
4535E–4BMCU–05/07
ATAR092/ATAR892
Combination Mode 3: Manchester Modulation 1
SSI mode 1:
8-bit shift register internal data output (SO) to the Timer 2
modulator stage
Timer 2 mode 1, 2, 3 or 4:
8-bit compare counter with 4-bit programmable prescaler
Timer 2 output mode 5:
The modulator 2 of Timer 2 modulates the SSI internal
data output to Manchester code
Figure 5-50. Manchester Modulation 1
TOG2
SC
8-bit SR Data
0
SO
0
1
1
0
1
0
1
Bit 0
Bit 7
0
0
1
1
0
1
0
1
T2O
Bit 7
Bit 0
Data: 00110101
Combination Mode 4: Manchester Modulation 2
SSI mode 1:
8-bit shift register internal data output (SO) to the Timer 2
modulator stage
Timer 2 mode 3:
8-bit compare counter and 4-bit prescaler
Timer 2 output mode 5:
The modulator 2 of Timer 2 modulates the SSI data output
to Manchester code
The 4-bit stage can be used as prescaler for the SSI to generate the stop signal for modulator 2.
The SSI has a special mode to supply the prescaler with the shift clock. The control output signal
(OMSK) of the SSI is used as stop signal for the modulator. Figure 5-51 shows an example for a
12-bit Manchester telegram.
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4535E–4BMCU–05/07
Figure 5-51. Manchester Modulation 2
SCLI
Buffer full
SIR
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
SO
SC
MSM
Timer 2
Mode 3
SCL
Counter 2/1
0
0
0
0
0
Counter 2/1 = Compare Register 2/1 (= 4)
0
0
0
0
1
2
3
4
0
1
2
3
OMSK
T2O
Combination Mode 5: Bi-phase Modulation 2
SSI mode 1:
8-bit shift register internal data output (SO) to the Timer 2
modulator stage
Timer 2 mode 3:
Timer 2 output mode 4:
8-bit compare counter and 4-bit prescaler
The modulator 2 of Timer 2 modulates the SSI data output
to Bi-phase code
The 4-bit stage can be used as prescaler for the SSI to generate the stop signal for modulator 2.
The SSI has a special mode to supply the prescaler via the shift clock. The control output signal
(OMSK) of the SSI is used as stop signal for the modulator. Figure 5-52 shows an example for a
13-bit Bi-phase telegram.
Figure 5-52. Bi-phase Modulation 2
SCLI
Buffer full
SIR
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
SO
SC
MSM
Timer 2
Mode 3
SCL
Counter 2/1
0
0
0
0
0
Counter 2/1 = Compare Register 2/1 (= 5)
0
0
0
0
1
2
3
4
5
0
1
2
OMSK
T2O
74
ATAR092/ATAR892
4535E–4BMCU–05/07
ATAR092/ATAR892
5.3.5.2
Combination Mode Timer 3 and SSI
Figure 5-53. Combination Timer 3 and SSI
I/O-bus
T3CS
T3M
T3I
SC
T3EX
T3I
T3EX
SYSCL
T1OUT
POUT
CL3
CM31
CP3
T3CP
SI
RES
8-bit Counter 3
T3C
INT5
T3ST
TOG3
SO
Control
RES
Compare 3/1
Demodulator 3
Compare 3/2
Timer 3 - Control
T3O
Modulator 3
M2
T3CO1
T3CO2
T3CM1
T3CM2
SI
SC
SIC1
TOG2
POUT
T1OUT
SYSCL
SISC
SIC2
Control
INT3
SCLI
SC
SSI-control
MCL_SC
Output
SO
SI
Shift_CL
MSB
8-bit Shift Register
STB
Transmit Buffer
5.3.5.3
MCL_SD
SI
LSB
SRB
I/O-bus
Receive Buffer
Combination Mode 6: FSK Modulation
SSI mode 1:
8-bit shift register internal data output (SO) to the Timer 3
Timer 3 mode 8:
FSK modulation with shift register data (SO)
The two compare registers are used to generate two varied time intervals. The SSI data output
selects which compare register is used for the output frequency generation. A ‘0’-level at the SSI
data output enables the compare register 1 and a ‘1’-level enables the compare register 2. The
compare and compare mode registers must be programmed to generate the two frequencies via
the output toggle flip-lop. The SSI can be supplied with the toggle signal of Timer 2 or any other
clock source. The Timer 3 counter is driven by an internal or external clock source.
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4535E–4BMCU–05/07
Figure 5-54. FSK Modulation 1
T3R
0 1 2 3 4 0 1 2 3 4 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 3 4 0 1 2 3 4 0
Counter 3
CM31
CM32
SO
1
0
0
T3O
Combination Mode 7: Pulse-width Modulation (PWM)
SSI mode 1:
8-bit shift register internal data output (SO) to the Timer 3
Timer 3 mode 9:
Pulse-width modulation with the shift register data (SO)
The two compare registers are used to generate two varied time intervals. The SSI data output
selects which compare register is used for the output pulse generation. In this mode, both compare and compare mode registers must be programmed to generate the two pulse width. It is
also useful to enable the single-action mode for extreme duty cycles. Timer 2 is used as
baudrate generator and for the triggered restart of Timer 3. The SSI must be supplied with the
toggle signal of Timer 2. The counter is driven by an internal or external clock source.
Figure 5-55. Pulse-width Modulation
TOG2
SIR
0
SO
1
0
1
SCO
T3R
Counter 3
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 3 4 5 6 7 8 9 10 1112131415 0 1 2 3 4 5 6 7 8 9 101112131415 0 1 2 3 4
CM31
CM32
T3O
76
ATAR092/ATAR892
4535E–4BMCU–05/07
ATAR092/ATAR892
Combination Mode 8: Manchester Demodulation/ Pulse-width Demodulation
SSI mode 1:
8-bit shift register internal data input (SI) and the internal shift clock
(SCI) from the Timer 3
Timer 3 mode 10:
Manchester demodulation/pulse-width demodulation with Timer 3
For Manchester demodulation, the edge detection stage must be programmed to detect each
edge at the input. These edges are evaluated by the demodulator stage. The timer stage is used
to generate the shift clock for the SSI. A compare register 1 match event defines the correct
moment for shifting the state from the input T3I as the decoded bit into shift register. After that,
the demodulator waits for the next edge to synchronize the timer by a reset for the next bit. The
compare register 2 can be used to detect a time error and handle it with an interrupt routine.
Before activating the demodulator mode the timer and the demodulator stage must be synchronized with the bitstream. The Manchester code timing consists of parts with the half bitlength
and the complete bitlength. A synchronization routine must start the demodulator after an interval with the complete bitlength.
The counter can be driven by any internal clock source. The output T3O can be used by Timer 2
in this mode. The Manchester decoder can also be used for pulse-width demodulation. The input
must programmed to detect the positive edge. The demodulator and timer must be synchronized
with the leading edge of the pulse. After that a counter match with the compare register 1 shifts
the state at the input T3I into the shift register. The next positive edge at the input restarts the
timer.
Figure 5-56. Manchester Demodulation
Timer 3
Mode
T3I
Synchronize
1
Manchester Demodulation Mode
0
1
1
1
0
0
1
1
0
T3EX
SI
CM3 = SCI
SR-DATA
1
1
1
0
0
1
1
BIT 0
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
0
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Combination Mode 9: Bi-phase Demodulation
SSI mode 1:
8-bit shift register internal data input (SI) and the internal shift clock
(SCI) from the Timer 3
Timer 3 mode 11:
Bi-phase demodulation with Timer 3
In the Bi-phase demodulation mode the timer works like in the Manchester demodulation mode.
The difference is that the bits are decoded with the toggle flip-flop. This flip-flop samples the
edge in the middle of the bitframe and the compare register 1 match event shifts the toggle
flip-flop output into shift register. Before activating the demodulation the timer and the demodulation stage must be synchronized with the bitstream. The Bi-phase code timing consists of parts
with the half bitlength and the complete bitlength. The synchronization routine must start the
demodulator after an interval with the complete bitlength.
The counter can be driven by any internal clock source and the output T3O can be used by
Timer 2 in this mode.
Figure 5-57. Bi-phase Demodulation
Timer 3
Mode
Synchronize
T3I
0
Biphase Demodulation Mode
0
1
1
0
1
1
0
1
0
1
BIT 0
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
0
1
0
1
0
T3EX
Q1 = SI
CM31 = SCI
Reset
Counter 3
SR-DATA
78
0
ATAR092/ATAR892
4535E–4BMCU–05/07
ATAR092/ATAR892
5.3.5.4
Combination Mode Timer 2 and Timer 3
Figure 5-58. Combination Timer 3 and Timer 2
I/O-bus
T3CS
T3M
T3I
SCI
T3EX
T3I
T3EX
SYSCL
T1OUT
POUT
CL3
CM31
CP3
T3CP
SI
Demodulator 3
RES
8-bit Counter 3
T3C
INT5
T3ST
TOG3
RES
SO
Control
Compare 3/1
Compare 3/2
T3CO1
T3CO2
M2
TOG2
T3CM1
T3O
Modulator 3
Timer 3 - Control
T3CM2
I/O-bus
P4CR
T2I
SSI
T2M2
T2M1
DCGO
T2O
TOG3
SYSCL
T1OUT
SCL
CL2/1
CL2/2
4-bit Counter 2/1
RES
OVF1
POUT
Compare 2/1
T2C
DCG
RES
Timer 2 - Control
OUTPUT
8-bit Counter 2/2
OVF2
TOG2
MOUT
M2
Compare 2/2
Bi-phase
Manchester
Modulator
INT4
CM1
POUT
T2CO1
I/O-bus
T2CM
T2CO2
SO
Timer 2
Modulator 2
Output-stage
SSI
SSI
Control
(RE, FE, SCO, OMSK)
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4535E–4BMCU–05/07
Combination Mode 10: Frequency Measurement or Event Counter with Time Gate
Timer 2 mode 1/2:
12-bit compare counter/8-bit compare counter and
4-bit prescaler
Timer 2 compare match toggles (TOG2) to the Timer 3
Timer/Counter; internal trigger restart and internal capture
(with Timer 2 TOG2-signal)
Timer 2 output mode 1/6:
Timer 3 mode 3:
The counter is driven by an external (T3I) clock source. The output signal (TOG2) of Timer 2
resets the counter. The counter value before reset is saved in the capture register. If single-action mode is activated for one or both compare registers, the trigger signal restarts also
the single actions. This mode can be used for frequency measurements or as event counter with
time gate.
Figure 5-59. Frequency Measurement
T3R
T3I
Counter 3
0 0 1 2 3 4 5 6 7 8 9 10 1112 131415 16 17 0 1 2 3 4 5 6 7 8 9 101112 13141516 1718 0 1 2 3 4 5
TOG2
T3CPRegister
Capture Value = 0
Capture Value = 17
Capt. Value = 18
2
4
Figure 5-60. Event Counter with Time Gate
T3R
T3I
0 0 1 2 3 4 5 6 7 8 9 10
11
0 1
3
0 1 2
Counter 3
TOG2
T3CP
Register
80
Capture Value = 0
Capture Value = 11
Capt. Val. = 4
ATAR092/ATAR892
4535E–4BMCU–05/07
ATAR092/ATAR892
Combination Mode 11: Burst Modulation 1
Timer 2 mode 1/2:
Timer 2 output mode 1/6:
Timer 3 mode 6:
12-bit compare counter/8-bit compare counter and
4-bit prescaler
Timer 2 compare match toggles the output flip-flop (M2)
to the Timer 3
Carrier frequency burst modulation controlled by Timer 2
output (M2)
The Timer 3 counter is driven by an internal or external clock source. Its compare and compare
mode registers must be programmed to generate the carrier frequency with the output toggle
flip-flop. The output toggle flip-flop (M2) of Timer 2 is used to enable and disable the Timer 3 output. The Timer 2 can be driven by the toggle output signal of Timer 3 (TOG3) or any other clock
source.
Figure 5-61. Burst Modulation 1
CL3
Counter 3
0 1 01 2 34 5 01 0 12 3 45 0 10 1 23 4 50 1 01
50 1 01
50 1 01
501 01
501 01
501 01
501 01
5 01 01
501 01
501 01
CM1
CM2
TOG3
M3
Counter 2/2
3
0
1
2
3
3
0
1
2
3
TOG2
M2
T3O
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4535E–4BMCU–05/07
5.3.5.5
Combination Mode Timer 2, Timer 3 and SSI
Figure 5-62. Combination Timer 2, Timer 3 and SSI
I/O-bus
T3CS
T3M
T3I
T3EX
SCI
Demodulator 3
T3I
CP3
T3CP
SI
CM31
RES
T3EX
SYSCL
T1OUT
POUT
CL3
T3C
8-bit Counter 3
INT5
T3ST
TOG3
RES
SO
Control
Compare 3/1
Compare 3/2
T3O
Modulator 3
Timer 3 - Control
M2
TOG2
T3CO2
T3CO1
T3CM1
T3CM2
SSI
I/O-bus
P4CR
T2M1
T2M2
T2I
DCGO
T2O
TOG3
SYSCL
T1OUT
CL2/1
RES
SCL
T2C
CL2/2
4-bit Counter 2/1
OVF1
DCG
POUT
Compare 2/1
OUTPUT
8-bit Counter 2/2
RES
OVF2
TOG2
MOUT
M2
Compare 2/2
Timer 2 - Control
Bi-phase
Manchester
modulator
INT4
CM1
POUT
T2CO1
T2CO2
T2CM
SO
Control
I/O-bus
SIC1
SIC2
SISC
TOG2
POUT
T1OUT
SYSCL
INT3
SCLI
SC
SSI-control
MCL_SC
Output
SO
SI
SCL
Shift_CL
MSB
8-bit Shift Register
STB
Transmit Buffer
82
Timer 2
Modulator 2
Output-stage
Control
(RE, FE,
SCO, OMSK)
LSB
MCL_SD
SI
SRB
I/O-bus
Receive Buffer
ATAR092/ATAR892
4535E–4BMCU–05/07
ATAR092/ATAR892
Combination Mode 12: Burst Modulation 2
SSI mode 1:
8-bit shift register internal data output (SO) to the Timer 3
Timer 2 output mode 2:
8-bit compare counter and 4-bit prescaler
Timer 2 output mode 1/6:
Timer 2 compare match toggles (TOG2) to the SSI
Timer 3 mode 7:
Carrier frequency burst modulation controlled by the internal
output (SO) of SSI
The Timer 3 counter is driven by an internal or external clock source. Its compare and compare
mode registers must be programmed to generate the carrier frequency with the output toggle
flip-flop (M3). The internal data output (SO) of the SSI is used to enable and disable the Timer 3
output. The SSI can by supplied with the toggle signal of Timer 2.
Figure 5-63. Burst Modulation 2
CL3
Counter 3
0 1 01 2 34 5 01 0 12 3 45 0 10 1 23 4 50 1 01
5 0 1 01
5 0 1 01
5 01 01
5 0 1 01
501 01
5 01 01
501 01
501 01
5 0 1 01
CM31
CM32
TOG3
M3
Counter 2/2
3
0
1
2
3
3
0
1
2
3
TOG2
SO
T3O
Combination Mode 13: FSK Modulation
SSI mode 1:
8-bit shift register internal data output (SO) to the Timer 3
Timer 2 output mode 3:
8-bit compare counter and 4-bit prescaler
Timer 2 output mode 1/6:
Timer 2 4-bit compare match signal (POUT) to the SSI
Timer 3 mode 8:
FSK modulation with shift register data output (SO)
The two compare registers are used to generate two different time intervals. The SSI data output
selects which compare register is used for the output frequency generation. A “0” level at the SSI
data output enables the compare register 1 and a “1” level enables the compare register 2. The
compare- and compare mode registers must be programmed to generate the two frequencies
via the output toggle flip-flop. The SSI can be supplied with the toggle signal of Timer 2 or any
other clock source. The Timer 3 counter is driven by an internal or external clock source.
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4535E–4BMCU–05/07
Figure 5-64. FSK Modulation
T3R
0 1 2 3 4 0 1 2 3 4 0 1 2 3 4 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 3 4 0 1
Counter 3
CM31
CM32
0
SO
1
0
T3O
6. ATAR892
The ATAR892 is a multichip device which offers a combination of a MARC4-based microcontroller and a serial E2PROM data memory in a single package. As microcontroller the ATAR092 is
used and as serial E2PROM the U505M. Two internal lines can be used as chip-to-chip link in a
single package. The maximum internal data communication frequency between the ATAR092
and the U505M over the chip link (MCL_SC and MCL_SD) is fSC_MCL = 500 kHz.
The microcontroller and the EEPROM portions of this multi-chip device are equivalent to their
respective individual component chips, except for the electrical specification.
6.1
Internal 2-wire Multi-chip Link
Two additional on-chip pads (MCL_SC and MCL_SD) for the SC and the SD line can be used as
chip-to-chip link for multi-chip applications. These pads can be activated by setting the MCL-bit
in the SISC-register.
Figure 6-1.
Multi-chip Link
U505M
SCL
SDA
Multi-chip Link
MCL_SC
MCL_SD
VSS
VDD
BP40/SC
BP10
6.2
BP43/SD
ATAR092
BP13
U505M EEPROM
The U505M is a 512-bit EEPROM internally organized as 32 x 16 bits. The programming voltage
as well as the write-cycle timing is generated on-chip. The U505M features a serial interface
allowing operation on a simple two-wire bus with an MCL protocol. Its low power consumption
makes it well suited for battery applications.
84
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ATAR092/ATAR892
Figure 6-2.
Block Diagram EEPROM
VDD
VSS
Timing Control
HV-generator
Address
Control
EEPROM
32 x 16
Mode
Control
SCL
I/O
Control
16-bit Read/Write Buffer
8-bit Data Register
SDA
6.2.1
Serial Interface
The U505M has a two-wire serial interface to the microcontroller for read and write accesses to
the EEPROM. The U505M is considered to be a slave in all these applications. That means, the
controller has to be the master that initiates the data transfer and provides the clock for transmit
and receive operations.
The serial interface is controlled by the ATAR892 microcontroller which generates the serial
clock and controls the access via the SCL-line and SDA-line. SCL is used to clock the data into
and out of the device. SDA is a bidirectional line that is used to transfer data into and out of the
device. The following protocol is used for the data transfers.
6.2.1.1
Serial Protocol
• Data states on the SDA-line changing only while SCL is low.
• Changes on the SDA-line while SCL is high are interpreted as START or STOP condition.
• A START condition is defined as high to low transition on the SDA-line while the SCL-line is
high.
• A STOP condition is defined as low to high transition on the SDA-line while the SCL-line is
high.
• Each data transfer must be initialized with a START condition and terminated with a STOP
condition. The START condition wakes the device from standby mode and the STOP
condition returns the device to standby mode.
• A receiving device generates an acknowledge (A) after the reception of each byte. This
requires an additional clock pulse, generated by the master. If the reception was successful
the receiving master or slave device pulls down the SDA-line during that clock cycle. If an
acknowledge is not detected (N) by the interface in transmit mode, it will terminate further
data transmissions and go into receive mode. A master device must finish its read operation
by a non-acknowledge and then send a stop condition to bring the device into a known state.
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Figure 6-3.
MCL Protocol
SCL
SDA
Stand-by Start
Condition
Data
Valid
Data
Change
Stop Stand-by
Condition
Data/
Acknowledge
Valid
• Before the START condition and after the STOP condition the device is in standby mode and
the SDA line is switched as input with pull-up resistor.
• The control byte that follows the START condition determines the following operation. It
consists of the 5-bit row address, 2 mode control bits and the READ/ NWRITE bit that is used
to control the direction of the following transfer. A ‘0’ defines a write access and a ‘1’ a read
access.
6.2.1.2
Control Byte Format
EEPROM Address
Start
Start
6.2.2
A4
A3
Control byte
A2
Ackn
A1
A0
Data byte
Mode
Control Bits
Read/
NWrite
C1
R/NW
Ackn
C0
Data byte
Ackn
Ackn
Stop
EEPROM
The EEPROM has a size of 512 bits and is organized as 32 x 16-bit matrix. To read and write
data to and from the EEPROM the serial interface must be used. The interface supports one and
two byte write accesses and one to n-byte read accesses to the EEPROM.
6.2.2.1
EEPROM – Operating Modes
The operating modes of the EEPROM are defined via the control byte. The control byte contains
the row address, the mode control bits and the read/not-write bit that is used to control the direction of the following transfer. A ‘0’ defines a write access and a ‘1’ a read access. The five
address bits select one of the 32 rows of the EEPROM memory to be accessed. For all
accesses the complete 16-bit word of the selected row is loaded into a buffer. The buffer must
be read or overwritten via the serial interface. The two mode control bits C1 and C2 define in
which order the accesses to the buffer are performed: High byte – low byte or low byte – high
byte. The EEPROM also supports autoincrement and autodecrement read operations. After
sending the start address with the corresponding mode, consecutive memory cells can be read
row by row without transmission of the row addresses.
Two special control bytes enable the complete initialization of EEPROM with ‘0’ or with ‘1’.
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ATAR092/ATAR892
6.2.2.2
Write Operations
The EEPROM permits 8-bit and 16-bit write operations. A write access starts with the START
condition followed by a write control byte and one or two data bytes from the master. It is completed via the STOP condition from the master after the acknowledge cycle. The programming
cycle consists of an erase cycle (write ‘zeros’) and the write cycle (write ‘ones’). Both cycles
together take about 10 ms.
6.2.2.3
Acknowledge Polling
If the EEPROM is busy with an internal write cycle, all inputs are disabled and the EEPROM will
not acknowledge until the write cycle is finished. This can be used to detect the end of the write
cycle. The master must perform acknowledge polling by sending a start condition followed by
the control byte. If the device is still busy with the write cycle, it will not return an acknowledge
and the master has to generate a stop condition or perform further acknowledge polling
sequences. If the cycle is complete, it returns an acknowledge and the master can proceed with
the next read or write cycle.
6.2.2.4
Write One Data Byte
Start
6.2.2.5
Data byte 1
A
Stop
Control byte
A
Data byte 1
A
Data byte 2
A
Stop
A
Stop
Write Control Byte Only
Start
6.2.2.7
A
Write Two Data Bytes
Start
6.2.2.6
Control byte
Control byte
Write Control Bytes
MSB
Write low byte first
A4
LSB
A3
A2
A1
A0
Row address
Byte order
LB(R)
C1
C0
R/NW
0
1
0
C1
C0
R/NW
1
0
0
HB(R)
MSB
Write high byte first
A4
LSB
A3
A2
A1
A0
Row address
Byte order
HB(R)
LB(R)
A: acknowledge; HB: high byte; LB: low byte; R: row address
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6.2.2.8
Read Operations
The EEPROM allows byte-, word- and current address read operations. The read operations are
initiated in the same way as write operations. Every read access is initiated by sending the
START condition followed by the control byte which contains the address and the read mode.
When the device has received a read command, it returns an acknowledge, loads the addressed
word into the read/write buffer and sends the selected data byte to the master. The master has
to acknowledge the received byte if it wants to proceed the read operation. If two bytes are read
out from the buffer the device increments respectively decrements the word address automatically and loads the buffer with the next word. The read mode bits determines if the low or high
byte is read first from the buffer and if the word address is incremented or decremented for the
next read access. If the memory address limit is reached, the data word address will ‘roll over’
and the sequential read will continue. The master can terminate the read operation after every
byte by not responding with an acknowledge (N) and by issuing a stop condition.
6.2.2.9
Read One Data Byte
Start
6.2.2.10
Data byte 1
N
Stop
Control byte
A
Data byte 1
A
Data byte 2
N
Stop
Read n Data Bytes
Start
6.2.2.12
A
Read Two Data Bytes
Start
6.2.2.11
Control byte
Control byte
A
Data byte 1
A
Data byte 2
A ---
Data byte n
N Stop
Read Control Bytes
MSB
Read low byte first,
address increment
A4
LSB
A3
A2
A1
A0
Row address
Byte order
LB(R)
HB(R)
LB(R+1)
HB(R+1)
C1
C0
R/NW
0
1
1
---
LB(R+n)
MSB
Read high byte first,
address decrement
A4
LSB
A3
A2
A1
A0
Row address
Byte order
HB(R)
LB(R)
HB(R+n)
HB(R-1)
LB(R-1)
---
C1
C0
R/NW
1
0
1
HB(R-n)
LB(R-n)
A: acknowledge, N: no acknowledge; HB: high byte; LB: low byte, R: row address
88
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ATAR092/ATAR892
6.2.2.13
Initialization After a Reset Condition
The EEPROM with the serial interface has its own reset circuitry. In systems with microcontrollers that have their own reset circuitry for power-on reset, watchdog reset or brown-out reset, it
may be necessary to bring the U505M into a known state independent of its internal reset. This
is performed by writing:
Start
Control byte
A
Data byte 1
N
Stop
to the serial interface. If the U505M acknowledges this sequence it is in a defined state. Maybe it
is necessary to perform this sequence twice.
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7. Absolute Maximum Ratings
Voltages are given relative to VSS.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
All inputs and outputs are protected against high electrostatic voltages or electric fields. However, precautions to minimize the build-up of
electrostatic charges during handling are recommended. Reliability of operation is enhanced if unused inputs are connected to an
appropriate logic voltage level (e.g., VDD).
Parameters
Symbol
Value
Unit
Supply voltage
VDD
–0.3 to + 6.5
V
Input voltage (on any pin)
VIN
VSS –0.3 ≤ VIN ≤ VDD +0.3
V
Output short circuit duration
tshort
indefinite
s
Operating temperature range
Tamb
–40 to +85
°C
Storage temperature range
Tstg
–40 to +130
°C
Soldering temperature (t ≤ 10s)
Tsld
260
°C
Symbol
Value
Unit
RthJA
140
K/W
8. Thermal Resistance
Parameter
Thermal resistance (SSO20)
9. DC Operating Characteristics
VSS = 0V, Tamb = –40°C to 85°C unless otherwise specified.
Parameters
Test Conditions
Symbol
Min.
VDD
VPOR
Typ.
Max.
Unit
6.5
V
200
300
700
400
µA
µA
µA
40
70
200
150
µA
µA
µA
Power Supply
Operating voltage at VDD
Active current
CPU active
fSYSCL = 1 MHz
VDD = 1.8V
VDD = 3.0V
VDD = 6.5V
IDD
Power down current
(CPU sleep,
RC oscillator active,
4-MHz quartz oscillator active)
fSYSCL = 1 MHz
VDD = 1.8V
VDD = 3.0V
VDD = 6.5V
IPD
Sleep current (CPU sleep,
32-kHz quartz oscillator active
4-MHz quartz oscillator inactive)
VDD = 1.8V
VDD = 3.0V
VDD = 6.5V
Sleep current
(CPU sleep,
32-kHz quartz oscillator inactive
4-MHz quartz oscillator inactive)
VDD = 1.8V for ATAR092
VDD = 3.0V for ATAR092
VDD = 6.5V for ATAR092
VDD = 6.5V for ATAR892
Pin capacitance
Any pin to VSS
90
ISleep
0.4
0.6
0.8
1.3
1.8
µA
µA
µA
ISleep
0.1
0.3
0.5
0.6
0.5
0.8
1.0
µA
µA
µA
µA
CL
7
10
pF
ATAR092/ATAR892
4535E–4BMCU–05/07
ATAR092/ATAR892
9. DC Operating Characteristics (Continued)
VSS = 0V, Tamb = –40°C to 85°C unless otherwise specified.
Parameters
Test Conditions
Symbol
Min.
Typ.
Max.
Unit
VPOR
1.6
VPOR
1.85
1.7
1.8
V
2.0
2.15
V
Power-on Reset Threshold Voltage
POR threshold voltage
POR threshold voltage
BOT = 1
BOT = 0
POR hysteresis
50
VPOR
mV
Voltage Monitor Threshold Voltage
VM high threshold voltage
VDD > VM, VMS = 1
VMThh
VM high threshold voltage
VDD < VM, VMS = 0
VMThh
3.0
VM middle threshold voltage
VDD > VM, VMS = 1
VMThm
VM middle threshold voltage
VDD < VM, VMS = 0
VMThm
VM low threshold voltage
VDD > VM, VMS = 1
VMThl
VM low threshold voltage
VDD < VM, VMS = 0
VMThl
VMI
VDD = 3V, VMS = 1
VVMI
VMI
VDD = 3V, VMS = 0
VVMI
1.2
Input voltage LOW
VDD = 1.8V to 6.5V
VIL
VSS
0.2 ×
VDD
V
Input voltage HIGH
VDD = 1.8V to 6.5V
VIH
0.8 ×
VDD
VDD
V
Input LOW current
(switched pull-up)
VDD = 2.0V,
VDD = 3.0V, VIL = VSS
VDD = 6.5V
IIL
–2
–10
–50
–4
–20
–100
–12
–40
–200
µA
µA
µA
Input HIGH current
(switched pull-down)
VDD = 2.0V,
VDD = 3.0V, VIH = VDD
VDD = 6.5V
IIH
2
10
50
4
20
100
12
40
200
µA
µA
µA
Input LOW current
(static pull-up)
VDD = 2.0V
VDD = 3.0V, VIL = VSS
VDD = 6.5V
IIL
–20
–80
–300
–50
–160
–600
–100
–320
–1200
µA
µA
µA
Input LOW current
(static pull-down)
VDD = 2.0V
VDD = 3.0V, VIH = VDD
VDD = 6.5V
IIH
20
80
300
50
160
600
100
320
1200
µA
µA
µA
Input leakage current
VIL= VSS
IIL
100
nA
Input leakage current
VIH= VDD
IIH
100
nA
Output LOW current
VOL = 0.2 × VDD
VDD = 2.0V
VDD = 3.0V,
VDD = 6.5V
IOL
Output HIGH current
VOH = 0.8 × VDD
VDD = 2.0V
VDD = 3.0V,
VDD = 6.5V
IOH
2.8
3.25
3.0
2.6
2.4
2.6
2.0
2.2
2.2
V
V
2.8
V
V
2.4
V
V
External Input Voltage
1.3
1.4
1.3
V
V
All Bidirectional Ports
Note:
0.6
3
8
1.2
5
15
2.5
8
22
mA
mA
mA
–0.6
–3
–8
–1.2
–5
–16
–2.5
–8
–24
mA
mA
mA
The Pin BP20/NTE has a static pull-up resistor during the reset-phase of the microcontroller
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4535E–4BMCU–05/07
10. AC Characteristics
Supply voltage VDD = 1.8V to 6.5V, VSS = 0V, Tamb = 25°C unless otherwise specified.
Parameters
Test Conditions
Symbol
Min.
VDD = 1.8V to 6.5V
Tamb = –40°C to +85°C
tSYSCL
VDD = 2.4V to 6.5V
Tamb = –40°C to +85°C
tSYSCL
Typ.
Max.
Unit
500
2000
ns
250
2000
ns
5
MHz
Operation Cycle Time
System clock cycle
Timer 2 input Timing Pin T2I
Timer 2 input clock
fT2I
Timer 2 input LOW time
Rise/fall time < 10 ns
tT2IL
100
ns
Timer 2 input HIGH time
Rise/fall time < 10 ns
tT2IH
100
ns
Timer 3 input LOW time
Rise/fall time < 10 ns
tT3IL
2 tSYSCL
ns
Timer 3 input HIGH time
Rise/fall time < 10 ns
tT3IH
2 tSYSCL
ns
Timer 3 Input Timing Pin T3I
Timer 3 input clock
SYSCL/2
fT3I
MHz
Interrupt Request Input Timing
Interrupt request LOW time
Rise/fall time < 10 ns
tIRL
100
ns
Interrupt request HIGH time
Rise/fall time < 10 ns
tIRH
100
ns
Rise/fall time < 10 ns
fEXSCL
0.5
4
MHz
EXSCL at OSC1, ECM = DI
Rise/fall time < 10 ns
fEXSCL
0.02
4
MHz
Input HIGH time
Rise/fall time < 10 ns
tIH
0.1
External System Clock
EXSCL at OSC1, ECM = EN
µs
Reset Timing
Power-on reset time
VDD > VPOR
tPOR
1.5
fRcOut1
3.8
5
ms
RC Oscillator 1
Frequency
VDD = 2.0V to 6.5V
Tamb = –40°C to +85°C
Stability
∆f/f
MHz
±50
%
RC Oscillator 2 – External Resistor
Frequency
Rext = 170 kΩ
Stability
VDD = 2.0V to 6.5V
Tamb = –40°C to +85°C
Stabilization time
fRcOut2
4
MHz
∆f/f
±15
%
tS
10
µs
4-MHz Crystal Oscillator (Operating Range VDD = 2.2V to 6.5V)
Frequency
fX
4
MHz
Start-up time
tSQ
5
ms
Stability
Integrated input/output capacitances
(mask programmable)
Note:
92
CIN/COUT programmable in steps of
0.63 pF
∆f/f
–10
+10
ppm
CIN
COUT
0
0
20
20
pF
pF
1. Endurance and data retention independent and separately characterized.
ATAR092/ATAR892
4535E–4BMCU–05/07
ATAR092/ATAR892
10. AC Characteristics (Continued)
Supply voltage VDD = 1.8V to 6.5V, VSS = 0V, Tamb = 25°C unless otherwise specified.
Parameters
Test Conditions
Symbol
Min.
Typ.
Max.
Unit
32-kHz Crystal Oscillator (Operating Range VDD = 2.0V to 6.5V)
fX
32.768
kHz
Start-up time
tSQ
0.5
s
Stability
∆f/f
–10
+10
ppm
CIN
COUT
0
0
20
20
pF
pF
Frequency
Integrated input/output capacitances
(mask programmable)
CIN/COUT programmable in steps of
0.63 pF
External 32-kHz Crystal Parameters
Crystal frequency
fX
32.768
kHz
Serial resistance
RS
30
Static capacitance
C0
1.5
pF
Dynamic capacitance
C1
3
fF
Crystal frequency
fX
4.0
MHz
Serial resistance
RS
40
150
Ω
Static capacitance
C0
1.4
3
pF
Dynamic capacitance
C1
3
IWR
600
50
kΩ
External 4-MHz Crystal Parameters
fF
EEPROM
Operating current during erase/write
cycle
Endurance
Erase-/write cycles
at 25°C
at 60°C
at 85°C
(1)
ED
Data erase/write cycle time
Data retention time
(1)
500,000 1,000,000
200,000
100,000
tDEW
At 25°C
tDR
1300
9
µA
Cycles
12
10
ms
Years
Power-up to read operation
tPUR
0.2
ms
Power-up to write operation
tPUW
0.2
ms
500
kHz
Serial Interface
SCL clock frequency
Note:
100
fSC_MCL
1. Endurance and data retention independent and separately characterized.
11. Recommendations for the 32-kHz Crystal Oscillator
Recommended Parameters for 32-kHz Crystals (for example MicroCrystal MS1V, Daishinku SM-14J)
Series Resistance
Load Capacitance
Maximum Load Capacitance
RSmax = 35 kΩ
8 pF < CLeff > 10 pF
12 pF
RSmax = 50 kΩ
7 pF < CLeff > 9 pF
10 pF
RSmax = 70 kΩ, typically 50 kΩ
6 pF < CL, eff > 7 pF
8 pF
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4535E–4BMCU–05/07
12. Recommended Values for Integrated Input/Output Capacitances
(Mask Option)
CL, eff (pF)
6
7
8
9
10
11
12
Copt (pF)
3.8
5.6
7.5
10
11.9
13.8
15.6
CL, eff: Effective load capacitance of the crystal for the nominal frequency of 32678 Hz
Copt: Recommended value for the integrated capacitance to meet, together with the parasitic pin capacitance,
the related CL, eff.
13. Crystal Characteristics
Figure 13-1. Crystal Equivalent Circuit
C1
L
Equivalent
Circuit
OSCIN
RS
OSCOUT
SCLOUT
SCLIN
C0
Figure 13-2. Active Supply Current versus Frequency
2.5
Tamb = -25˚C
VDD = 6.5V
2.0
IDDact (mA)
5V
1.5
3V
1.0
2V
0.5
0.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
fSYSCLK (MHz)
94
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4535E–4BMCU–05/07
ATAR092/ATAR892
Figure 13-3. Active Supply Current versus VDD
0.8
0.7
fSYSCLK = 500 kHz
0.6
Tamb = 25˚C
IDDact (mA)
0.5
0.4
0.3
0.2
0.1
0.0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
1.8
2.0
VDD (V)
Figure 13-4. Power-down Supply Current versus Frequency
400
350
Tamb = -25˚C
VDD = 6.5V
300
IPD (µA)
250
5V
200
4V
150
3V
100
2V
50
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
fSYSCLK (MHz)
Figure 13-5. Power-down Supply Current versus VDD
120
100
fSYSCLK = 500 kHz
Tamb = 25˚C
IPD (µA)
80
60
40
20
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
VDD (V)
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Figure 13-6. Sleep Current versus Tamb – ATAR092
1.0
0.9
0.8
IDDsleep (µA)
0.7
0.6
0.5
0.4
VDD = 6.5V
0.3
5V
0.2
0.1
3V
0.0
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
90
80
90
Tamb (˚C)
Figure 13-7. Sleep Current versus Tamb – ATAR892
1.0
0.9
0.8
IDDsleep (µA)
0.7
0.6
VDD = 6.5V
0.5
0.4
0.3
5V
0.2
3V
0.1
0.0
-40
-30
-20
-10
0
10
20
30
40
50
60
70
Tamb (˚C)
Figure 13-8. Internal RC Frequency versus VDD
fRC_INT (MHz)
5.0
4.5
Tamb = -40˚C
4.0
25˚C
85˚C
3.5
3.0
2.5
2.0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
VDD (V)
96
ATAR092/ATAR892
4535E–4BMCU–05/07
ATAR092/ATAR892
Figure 13-9. Internal RC Frequency versus Tamb
5.0
4.5
fRC_INT (MHz)
4.0
VDD = 6.5V
3.5
2V
3V
3.0
2.5
2.0
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
90
Tamb (˚C)
Figure 13-10. External RC Frequency versus VDD
4.6
4.4
fRC_EXT (MHz)
4.2
Tamb = -40˚C
4.0
85˚C
25˚C
3.8
3.6
3.4
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
VDD (V)
Figure 13-11. External RC Frequency versus Tamb
4.6
4.4
fRC_EXT (MHz)
4.2
VDD = 6.5V
3V
4.0
2V
3.8
3.6
3.4
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
90
Tamb (˚C)
97
4535E–4BMCU–05/07
Figure 13-12. System Clock versus VDD
10.00
SYSCLKmax
fSYSCLK (MHz)
1.00
SYSCLKmin
0.10
0.01
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
VDD (V)
Figure 13-13. External RC Frequency versus Rext
8.0
Tamb = 25˚C
7.0
VDD = 3V
fRC_EXT (MHz)
6.0
5.0
4.0
max.
3.0
typ.
2.0
min.
1.0
100.0
150.0
200.0
250.0
300.0
350.0
400.0
Rext (kOhm)
Figure 13-14. Pull-up Resistor versus VDD
1000.0
VIL = VSS
RPU (kΩ)
Tamb = 85˚C
25˚C
100.0
-40˚C
10.0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
RDD (V)
98
ATAR092/ATAR892
4535E–4BMCU–05/07
ATAR092/ATAR892
Figure 13-15. Pull-down Resistor versus VDD
1000.0
VIL = VSS
Tamb = 85˚C
RPD (kΩ)
25˚C
100.0
-40˚C
10.0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
VDD (V)
Figure 13-16. Static Pull-up Resistor versus VDD
100.0
RSPU (kΩ)
VIL = VSS
Tamb = 85˚C
25˚C
-40˚C
10.0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
5.0
5.5
6.0
6.5
RDD (V)
Figure 13-17. Static Pull-down Resistor versus VDD
100.0
RSPD (kΩ)
VIL = VSS
Tamb = 85˚C
25˚C
-40˚C
10.0
2.0
2.5
3.0
3.5
4.0
4.5
VDD (V)
99
4535E–4BMCU–05/07
Figure 13-18. Output High Current versus VDD – Output High Voltage
0.0
VDD = 2.0V
-5.0
-10.0
3.0V
IOH (mA)
-15.0
4.0V
-20.0
-25.0
5.0V
Tamb = 25˚C
-30.0
6.5V
-35.0
-40.0
0.0
0.5
1.0
1.5 2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
VDD - VOH (V)
Figure 13-19. Output Low Current versus Output Low Voltage
30.0
Tamb = 25˚C
VDD = 6.5V
25.0
20.0
IOL (mA)
5.0V
15.0
4.0V
10.0
3.0V
5.0
2.0V
0.0
0.0
0.5
1.0
1.5 2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
VOL (V)
Figure 13-20. Output High Current versus Tamb, VDD = 6.5 V, VOH = 0.8 × VDD
0
-5
min.
IOH (mA)
-10
typ.
-15
max.
-20
-25
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
90
Tamb (˚C)
100
ATAR092/ATAR892
4535E–4BMCU–05/07
ATAR092/ATAR892
Figure 13-21. Output Low Current versus Tamb, VDD = 6.5 V, VOL = 0.2 × VDD
25
20
max.
IOL (mA)
15
typ.
10
min.
5
0
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
90
Tamb (˚C)
14. Emulation
The basic function of emulation is to test and evaluate the customer's program and hardware in
real time. This therefore enables the analysis of any timing, hardware or software problem. For
emulation purposes, all MARC4 controllers include a special emulation mode. In this mode, the
internal CPU core is inactive and the I/O buses are available via Port 0 and Port 1 to allow an
external access to the on-chip peripherals. The MARC4 emulator uses this mode to control the
peripherals of any MARC4 controller (target chip) and emulates the lost ports for the application.
The MARC4 emulator can stop and restart a program at specified points during execution, making it possible for the applications engineer to view the memory contents and those of various
registers during program execution. The designer also gains the ability to analyze the executed
instruction sequences and all the I/O activities.
Figure 14-1. MARC4 Emulation
Emulator Target Board
MARC4 Emulator
MARC4
Emulation-CPU
I/O Bus
Trace
Memory
Port 0
MARC4 Target Chip
CORE
I/O Control
Port 1
Program
Memory
CORE
(Inactive)
Peripherals
Port 0
Control
Logic
Port 1
Emulation Control
SYSCL/
TCL,
TE, NRST
Application-specific Hardware
Personal Computer
101
4535E–4BMCU–05/07
15. Option Settings for Ordering
[ ] ATAR092
(-40°C to +85°C)
[ ] ATAR892
(-40°C to +85°C)
Please select the option settings from the list below and insert ROM CRC.
Output(1)
Input
Port 1
Output
Input
Port 5
BP10 [
]
CMOS
[
]
Switched pull-up
BP50 [
]
CMOS
[
]
Switched pull-up
[
]
Open drain [N]
[
]
Switched pull-down
[
]
Open drain [N]
[
]
Switched pull-down
[
]
Open drain [P]
[
]
Static pull-up
[
]
Open drain [P]
[
]
Static pull-up
[
]
Static pull-down
[
]
Static pull-down
BP13 [
]
CMOS
[
]
Switched pull-up
BP51 [
]
CMOS
[
]
Switched pull-up
[
]
Open drain [N]
[
]
Switched pull-down
[
]
Open drain [N]
[
]
Switched pull-down
[
]
Open drain [P]
[
]
Static pull-up
[
]
Open drain [P]
[
]
Static pull-up
[
]
Static pull-down
[
]
Static pull-down
Port 2
BP52 [
]
CMOS
[
]
Switched pull-up
BP20(2) [
]
CMOS
[
]
Switched pull-up
[
]
Open drain [N]
[
]
Switched pull-down
[
]
Open drain [N]
[
]
Switched pull-down
[
]
Open drain [P]
[
]
Static pull-up
[
]
Open drain [P]
[
]
Static pull-up
[
]
Static pull-down
[
]
Static pull-down
BP53 [
]
CMOS
[
]
Switched pull-up
BP21 [
]
CMOS
[
]
Switched pull-up
[
]
Open drain [N]
[
]
Switched pull-down
[
]
Open drain [N]
[
]
Switched pull-down
[
]
Open drain [P]
[
]
Static pull-up
[
]
Open drain [P]
[
]
Static pull-up
[
]
Static pull-down
[
]
Static pull-down
Port 6
BP22 [
]
CMOS
[
]
Switched pull-up
BP60 [
]
CMOS
[
]
Switched pull-up
[
]
Open drain [N]
[
]
Switched pull-down
[
]
Open drain [N]
[
]
Switched pull-down
[
]
Open drain [P]
[
]
Static pull-up
[
]
Open drain [P]
[
]
Static pull-up
[
]
Static pull-down
[
]
Static pull-down
BP23 [
]
CMOS
[
]
Switched pull-up
BP63 [
]
CMOS
[
]
Switched pull-up
[
]
Open drain [N]
[
]
Switched pull-down
[
]
Open drain [N]
[
]
Switched pull-down
[
]
Open drain [P]
[
]
Static pull-up
[
]
Open drain [P]
[
]
Static pull-up
[
]
Static pull-down
[
]
Static pull-down
Port 4
BP40 [
]
CMOS
[
]
Switched pull-up
[
]
Open drain [N]
[
]
Switched pull-down
[
]
No integrated capacitance
[
]
Open drain [P]
[
]
Static pull-up
[
]
Internal capacitance (0 to 20 pF) [ _____pF]
[
]
Static pull-down
BP41 [
]
CMOS
[
]
Switched pull-up
[
]
No integrated capacitance
[
]
Open drain [N]
[
]
Switched pull-down
[
]
Internal capacitance (0 to 20 pF) [ _____pF]
[
]
Open drain [P]
BP42 [
]
CMOS
[
]
Static pull-up
[
]
Static pull-down
[
]
Switched pull-up
OSC1
OSC2
Clock Used
[
]
External resistor
[
]
External clock OSC1
[
]
Open drain [N]
[
]
Switched pull-down
[
]
External clock OSC2
[
]
Open drain [P]
[
]
Static pull-up
[
]
32-kHz crystal
[
]
Static pull-down
[
]
4-MHz crystal
BP43 [
]
CMOS
[
]
Switched pull-up
[
]
Open drain [N]
[
]
Switched pull-down
[
]
Open drain [P]
[
]
Static pull-up
[
]
Enable
[
]
Static pull-down
[
]
Disable
ECM (External Clock Monitor)
Please attach this page to the approval form.
Filename: ___________________________ .HEX
Date: ____________
Notes:
CRC: ___________________________ (HEX)
Signature: _______________________ Company: _________________________
1. It is required to select an output option for each port pin (Port 1, Port 2, Port 4, Port 5, Port 6).
2. Don’t use external components at BP20 that pull to VSS during reset representing a resistor < 150k.
102
ATAR092/ATAR892
4535E–4BMCU–05/07
ATAR092/ATAR892
16. Ordering Information
Extended Type Number
Program Memory
Data-EEPROM
Package
ATAR092x-yyy-TKQYz
4 kB ROM
No
SSO20
Taped and reeled
ATAR092x-yyy-TKSYz
4 kB ROM
No
SSO20
Tubes
ATAR892x-yyy-TKQYz
4 kB ROM
512 Bit
SSO20
Taped and reeled
ATAR892x-yyy-TKSYz
4 kB ROM
512 Bit
SSO20
Tubes
Note:
1. x =
yyy =
Y =
z =
Delivery
Hardware revision
Customer specific ROM-version
Lead-free
Operating temperature range: blank = –40°C to +85°C
Package Information
5.4±0.2
1.3±0.05
0.05+0.1
0.25±0.05
6.45±0.15
0.65±0.05
0.15±0.05
4.4±0.1
6.75-0.25
5.85±0.05
20
11
Package: SSO20
Dimensions in mm
technical drawings
according to DIN
specifications
1
10
Drawing-No.: 6.543-5056.01-4
Issue: 1; 10.03.04
103
4535E–4BMCU–05/07
17. Revision History
Please note that the following page numbers referred to in this section refer to the specific revision
mentioned, not to this document.
Revision No.
History
4535E-4BMCU-05/07
• Put datasheet in a new template
• Pb-free logo on page 1 deleted
4535D-4BMCU-12/04
•
•
•
•
•
•
•
•
•
Put datasheet in a new template
Pb-free logo on page 1 added
Section “ROM” on page 4 changed
Section “Interrupt Processing” on pages 7 to 8 changed
Section “4-MHz Oscillator” on pages 16 to 17 changed
Section “32-kHz Oscillator” on page 17 changed
Table “AC Characteristics” on pages 85 to 86 changed
Table “Option Settings for Ordering” on page 95 changed
Table “Ordering Information” on page 96 changed
•
•
•
•
•
•
•
•
Put datasheet in a new template
Features on page 1 changed
Table 1 “Available Variants of ATAxx9x” changed
Table 10 “Peripheral Addresses” on page 21 changed
Section “Timer 2” on page 33 changed
Table 20 “Timer 2 Output Select Bits” on page 42 changed
Figure 44 on page 44 changed
New heading rows at table “Absolute Maximum Ratings” on page 83
added
Figure 107 on page 93 changed
Section “Emulation” on page 94 added
Table name on page 95 changed
Table “Ordering Information” on page 96 added
4535C-4BMCU-02/04
•
•
•
•
104
ATAR092/ATAR892
4535E–4BMCU–05/07
ATAR092/ATAR892
18. Table of Contents
Features ..................................................................................................... 1
1
Description ............................................................................................... 1
2
Pin Configuration ..................................................................................... 2
3
Introduction .............................................................................................. 3
4
MARC4 Architecture ................................................................................ 3
4.1
General Description .............................................................................................3
4.2 Components of MARC4 Core ..............................................................................4
4.2.1 ROM ................................................................................................................4
4.2.2 RAM ................................................................................................................4
4.2.3 Registers .........................................................................................................5
4.2.4 ALU .................................................................................................................7
4.2.5 I/O Bus ............................................................................................................8
4.2.6 Instruction Set .................................................................................................8
4.2.7 Interrupt Structure ...........................................................................................8
4.3 Master Reset ......................................................................................................10
4.3.1 Power-on Reset and Brown-out Detection ....................................................11
4.3.2 Watchdog Reset ...........................................................................................12
4.3.3 External Clock Supervisor .............................................................................12
4.4 Voltage Monitor ..................................................................................................12
4.4.1 Voltage Monitor Control/Status Register .......................................................13
4.5 Clock Generation ...............................................................................................14
4.5.1 Clock Module ................................................................................................14
4.5.2 Oscillator Circuits and External Clock Input Stage .......................................16
4.5.3 Clock Management .......................................................................................18
4.6
5
Power-down Modes ...........................................................................................20
Peripheral Modules ................................................................................ 21
5.1
Addressing Peripherals ......................................................................................21
5.2 Bidirectional Ports ..............................................................................................23
5.2.1 Bidirectional Port 1 ........................................................................................23
5.2.2 Bidirectional Port 2 ........................................................................................24
5.2.3 Bidirectional Port 5 ........................................................................................25
5.2.4 Bidirectional Port 4 ........................................................................................28
5.2.5 Bidirectional Port 6 ........................................................................................29
105
4535E–4BMCU–05/07
5.3 Universal Timer/Counter/ Communication Module (UTCM) ...............................30
5.3.1 Timer 1 ..........................................................................................................31
5.3.2 Timer 2 ..........................................................................................................34
5.3.3 Timer 3 ..........................................................................................................46
5.3.4 Synchronous Serial Interface (SSI) ...............................................................60
5.3.5 Combination Modes ......................................................................................71
6
ATAR892 ................................................................................................. 84
6.1
Internal 2-wire Multi-chip Link ............................................................................84
6.2 U505M EEPROM ...............................................................................................84
6.2.1 Serial Interface ..............................................................................................85
6.2.2 EEPROM ......................................................................................................86
7
Absolute Maximum Ratings .................................................................. 90
8
Thermal Resistance ............................................................................... 90
9
DC Operating Characteristics ............................................................... 90
10 AC Characteristics ................................................................................. 92
11 Recommendations for the 32-kHz Crystal Oscillator ......................... 93
12 Recommended Values for Integrated Input/Output Capacitances
(Mask Option) ......................................................................................... 94
13 Crystal Characteristics .......................................................................... 94
14 Emulation .............................................................................................. 101
15 Option Settings for Ordering .............................................................. 102
16 Ordering Information ........................................................................... 103
17 Revision History ................................................................................... 104
18 Table of Contents ................................................................................. 105
106
ATAR092/ATAR892
4535E–4BMCU–05/07
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4535E–4BMCU–05/07