LTC1257
Complete Single Supply
12-Bit Voltage Output
DAC in SO-8
U
DESCRIPTIO
FEATURES
■
■
■
■
■
■
■
■
■
8-Pin SO Package
Buffered Voltage Output
Built-In 2.048V Reference
500µV/LSB with 2.048V Full Scale
1/2LSB Max DNL Error
Guaranteed 12-Bit Monotonic
3-Wire Cascadable Serial Interface
Wide Single Supply Range: VCC = 4.75V to 15.75V
Low Power: ICC Typ = 350µA with 5V Supply
UO
APPLICATI
■
■
■
S
Digital Offset/Gain Adjustment
Industrial Process Control
Automatic Test Equipment
The LTC ®1257 is a complete single supply, 12-bit voltage
output D/A converter (DAC) in an SO-8 package. The
LTC1257 includes an output buffer amplifier, 2.048V
voltage reference and an easy to use three-wire cascadable
serial interface. An external reference can be used to
override the internal reference and extend the output
voltage range to 12V. The power supply current is a low
350µA when operating from a 5V supply, making the
LTC1257 ideal for battery-powered applications. The spacesaving 8-pin SO package and operation with no external
components provide the smallest 12-bit D/A system
available.
, LTC and LT are registered trademarks of Linear Technology Corporation.
UO
TYPICAL APPLICATI
Daisy-Chained Control Outputs
Differential Nonlinearity
vs Input Code
5V
CONTROL OUTPUT 1
0.5
VCC
VOUT LTC1257
GND VREF
0.1µF
CONTROL OUTPUT 2
VCC
VOUT LTC1257
GND VREF
DIN
CLK
µP
LOAD
DNL ERROR (LSBs)
0.1µF
DOUT
DIN
0.0
CLK
LOAD
DOUT
–0.5
0
TO NEXT DAC
1257 TA01
512 1024 1536 2048 2560 3072 3584 4098
CODE
1257 TA05
1
LTC1257
U
W W
W
VCC to GND ............................................ – 0.5V to 16.5V
TTL Input Voltage .......................... – 0.5V to VCC + 0.5V
VOUT .............................................. – 0.5V to VCC + 0.5V
REF ................................................ – 0.5V to VCC + 0.5V
Operating Temperature Range
LTC1257C ............................................. 0°C to 70°C
LTC1257I......................................... – 40°C to 85°C
Maximum Junction Temperature
Plastic Package ............................. – 65°C to 125°C
Storage Temperature Range ................ – 65°C to 150°C
Lead Temperature (Soldering, 10 sec)................. 300°C
U
RATI GS
W
AXI U
U
ABSOLUTE
PACKAGE/ORDER I FOR ATIO
TOP VIEW
CLK 1
8 VCC
DIN 2
7 VOUT
LOAD 3
6 REF
DOUT 4
5 GND
ORDER PART
NUMBER
LTC1257CN8
LTC1257IN8
N8 PACKAGE
8-LEAD PDIP
TJMAX = 125°C, θJA = 100°C/W
TOP VIEW
CLK 1
8 VCC
DIN 2
7 VOUT
LOAD 3
6 REF
DOUT 4
5 GND
LTC1257CS8
LTC1257IS8
S8 PART MARKING
1257
1257I
S8 PACKAGE
8-LEAD PLASTIC SO
TJMAX = 125°C, θJA = 150°C/W
Consult factory for Military grade parts.
ELECTRICAL CHARACTERISTICS
VCC = 4.75V to 15.75V, internal or external reference
(2.475V ≤ VREF ≤ VCC – 2.7V), IOUT ≤ 2mA, TA = TMIN to TMAX, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
DAC
Resolution
●
12
Bits
DNL
Differential Nonlinearity
Guaranteed Monotonic
●
±0.5
LSB
INL
Integral Nonlinearity
LTC1257C
LTC1257I
●
●
±3.5
±4.0
LSB
LSB
OFF
Offset Error
When Using Internal Reference, LTC1257C
When Using Internal Reference, LTC1257I
●
●
±8
±10
LSB
LSB
When Using External Reference, LTC1257C
When Using External Reference, LTC1257I
●
●
±4
±5
mV
mV
When Using Internal Reference (Note 1)
When Using External Reference (Note 1)
●
●
±0.02
±15
±0.066
±30
●
0.5
±2
± 0.01
±0.02
LSB/°C
2.048
2.068
2.078
V
V
OFFTC
Offset Error Tempco
FSE
Full-Scale Error
FSETC
Full-Scale Error Tempco
(Note 1)
●
Reference Output Voltage
IOUT = 0, LTC1257C
IOUT = 0, LTC1257I
●
●
Reference Output Tempco
IOUT = 0
●
Reference Line Regulation
IOUT = 0, LTC1257C
IOUT = 0, LTC1257I
●
●
Reference Load Regulation
0 ≤ IOUT ≤ 100µA
●
Reference Input Range
VCC > VREF + 2.7V
●
2.475
●
8
LSB/°C
µV/°C
LSB
Reference
Reference Input Resistance
2
Reference Input Capacitance
(Note 1)
Short-Circuit Current
VOUT Shorted to GND
2.028
2.018
±0.06
LSB/°C
±0.4
±0.7
14
±1
LSB
12
V
18
kΩ
15
●
LSB/ V
LSB/V
pF
90
mA
LTC1257
ELECTRICAL CHARACTERISTICS
VCC = 4.75V to 15.75V, internal or external reference
(2.475V ≤ VREF ≤ VCC – 2.7V), IOUT ≤ 2mA, TA = TMIN to TMAX, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
15.75
V
600
1500
µA
µA
60
mA
60
mA
400
Ω
Power Supply
VCC
Positive Supply Voltage
For Specified Performance
●
ICC
Supply Current
4.75V ≤ VCC ≤ 5.25V
4.75V ≤ VCC ≤ 15.75V
●
●
Short-Circuit Current Low
VOUT Shorted to GND
●
Short-Circuit Current High
VOUT Shorted to VCC
●
Output Impedance to GND
Input Code = 0
●
Voltage Output Slew Rate
5kΩ in Parallel with 100pF
●
Voltage Output Settling Time
To ±1/2LSB, 5kΩ in Parallel with 100pF
●
Digital Feedthrough
(Notes 1,2)
4.75
350
800
Op Amp DC Performance
150
AC Performance
1.0
V/µs
6
50
µs
nV/s
Digital I/O
VIH
Digital Input High Voltage
●
VIL
Digital Input Low Voltage
●
2.4
V
VOH
Digital Output High Voltage
IOUT = –1mA, DOUT Only
●
VCC – 1
V
VOL
Digital Output Low Voltage
IOUT = 1mA, DOUT Only
●
0.4
V
ILEAK
Digital Input Leakage
VIN = GND to VCC
●
±10
µA
CIN
Digital Input Capacitance
(Note 1)
●
10
pF
0.8
V
Switching (Note 1)
t1
DIN Valid to CLK Setup
●
t2
DIN Valid to CLK Hold
●
25
ns
t3
CLK High Time
●
350
ns
t4
CLK Low Time
●
350
ns
t5
LOAD Pulse Width
●
150
ns
t6
LSB CLK to LOAD
●
0
ns
t7
LOAD High to CLK
●
0
ns
t8
DOUT Output Delay
●
35
fCLK
Maximum Clock Frequency
CLOAD = 15pF
The ● denotes specifications which apply over the full operating
temperature range.
100
ns
150
ns
1.4
MHz
Note 1: Guaranteed by design; not subject to test.
Note 2: DAC switched from all 1s to all 0s, and all 0s to all 1s code.
3
LTC1257
U W
TYPICAL PERFORMANCE CHARACTERISTICS
Minimum Supply Voltage
vs Load Current #2
Minimum Supply Voltage
vs Load Current #1
4.4
4.2
4.0
3.8
3.6
3.4
3.2
3.0
0.01
0.1
1
OUTPUT LOAD CURRENT (mA)
0.38
VREF = 10V
VOUT = FULL SCALE
TA = 25°C
14.5
14.0
13.5
13.0
12.5
12.0
0.1
1
OUTPUT LOAD CURRENT (mA)
OUTPUT VOLTAGE SWING (V)
0.44
4.0
FULL SCALE
RL TIED TO GND
3.5
3.0
ZERO SCALE
RL TIED TO VCC
2.5
2.0
1.5
1.0
0.5
1
3
2
LOGIC VOLTAGE (V)
4
100
1k
LOAD RESISTANCE (Ω)
10
5
Full-Scale Voltage vs
Temperature
ZERO-SCALE VOLTAGE (mV)
0.8
2.0480
2.0475
COLD
125
1257 G07
ROOM
1
1
10
100
OUTPUT SINK CURRENT (µA)
Integral Nonlinearity (INL)
VCC = 5V
INTERNAL REFERENCE
1.6
1.2
0.7
0.8
0.6
0.5
0.4
0.3
0.4
0
–0.4
–0.8
0.2
–1.2
0.1
–1.6
0
–50
1000
2.0
2.0470
100
HOT
1257 G06
ERROR (LSB)
VCC = 5V
INTERNAL REFERENCE
50
25
75
0
TEMPERATURE (°C)
10
0.1
10k
0.9
2.0465
–50 –25
100
Zero-Scale Voltage vs
Temperature
2.0495
125
Pull-Down Voltage vs Output Sink
Current Capability
1257 G05
1257 G04
2.0485
100
1257 G03
0
0.34
0
50
25
75
0
TEMPERATURE (°C)
1000
VCC = 5V
4.5
0.39
FULL-SCALE VOLTAGE (V)
0.31
–50 –25
10
5.0
VCC = 5V
TA = 25°C
4
VCC = 4.75V
0.33
Output Swing vs Load Resistance
0.59
2.0490
0.34
1257 G02
Supply Current vs
Logic Input Voltage
0.49
VCC = 5V
0.35
0.32
1257 G01
0.54
VCC = 5.25V
0.36
11.5
11.0
0.01
10
0.37
OUTPUT PULL-DOWN VOLTAGE (mV)
MINIMUM SUPPLY VOLTAGE (V)
4.6
MINIMUM SUPPLY VOLTAGE (V)
VREF = INTERNAL
VOUT = FULL SCALE
TA = 25°C
4.8
SUPPLY CURRENT (mA)
Supply Current vs Temperature
15.0
SUPPLY CURRENT (mA)
5.0
VCC = 5V
INTERNAL REFERENCE
TA = 25°C
–2.0
–25
0
25
50
75
TEMPERATURE (°C)
100
125
1257 G08
0
512 1024 1536 2048 2560 3072 3584 4096
CODE
1257 G09
LTC1257
U W
TYPICAL PERFORMANCE CHARACTERISTICS
Reference Compensation
Resistance vs CL
Differential Nonlinearity (DNL)
0.0
–0.5
0
512 1024 1536 2048 2560 3072 3584 4098
CODE
Broadband Noise
70
CODE = FFFH
BW = 3Hz TO 1MHz
GAIN = 1100×
60
50
0.1V/DIV
REFERENCE COMPENSATION RESISTANCE (Ω)
DNL ERROR (LSBs)
0.5
40
30
20
10
0
0.01
0.1
1257 TA05
1
CL (µF)
10
100
TIME = 5ms/DIV
1257 G12
1257 G11
U
U
U
PI FU CTIO S
CLK (Pin 1): The TTL level input for the serial interface
clock.
DIN (Pin 2): The TTL level input for the serial interface data.
Data on the DIN pin is latched into the shift register on the
rising edge of the serial clock.
LOAD (Pin 3): The TTL level input for the serial interface
load control. Data is loaded from the shift register into the
DAC register, thus updating the DAC output when LOAD is
pulled low. The DAC register is transparent as long as
LOAD is held low.
DOUT(Pin 4): The output of the shift register which
becomes valid on the rising edge of the serial clock. The
DOUT pin is driven from GND to VCC by an internal CMOS
inverter. Multiple LTC1257s may be cascaded by connecting the DOUT pin to the DIN pin of the next chip.
GND (Pin 5): Ground.
REF (Pin 6): The output of the 2.048V reference and the
input to the DAC resistor ladder. An external reference with
voltage from 2.475V to VCC – 2.7V may be used to override
the internal reference.
VOUT (Pin 7): The buffered DAC output is capable of
sourcing 2mA over temperature while pulling within 2.7V
of VCC. The output will pull to ground through an internal
200Ω equivalent resistance.
VCC (Pin 8): The positive supply input. 4.75V ≤ VCC ≤
15.75V. Requires a bypass capacitor to ground.
5
LTC1257
U
U
DEFI ITIO S
LSB: The least significant bit or the ideal voltage difference
between two successive codes.
LSB =
n =
VOS =
VFS =
(VFS – VOS)/2n – 1
The number of digital input bits
The zero code error or offset of the DAC
The full-scale output voltage of the DAC
measured when all bits are set to 1
Resolution: The resolution is the number of DAC output
states (2n) that divide the full-scale range. The resolution
does not imply linearity.
INL: End-point integral nonlinearity is the maximum deviation from a straight line passing through the end-points
of the DAC transfer curve. Because the part operates from
a single supply and the output cannot go below ground,
the linearity is measured between full-scale and the first
code that guarantees a positive output. The INL error at a
given input code is calculated as follows:
INL = (VOUT – VIDEAL)/LSB
VIDEAL = (Code)(LSB) + VOS
VOUT = The output voltage of the DAC measured at
the given input code
Offset Error: The theoretical voltage at the output when
the DAC is loaded with all zeros. The output amplifier can
have a true negative offset, but because the part is operated from a single supply, the output cannot go below
ground. If the offset is negative, the output will remain near
0V resulting in the transfer curve shown in Figure 1.
OUTPUT
VOLTAGE
NEGATIVE
OFFSET
{
0V
DAC CODE
1257 F01
Figure 1. Effect of Negative Offset
The offset of the part is measured at the first code that
produces an output voltage 0.5LSB greater than the previous code:
VOS = VOUT – [(Code)(VFS)/(2n – 1)]
Full-Scale Error: Full-scale error is the difference between the ideal and measured DAC output voltages with all
bits set to one (Code = 4095). The full-scale error includes
the offset error and is calculated as follows:
DNL: Differential nonlinearity is the difference between
the measured change and the ideal 1LSB change between
any two adjacent codes. The DNL error between any two
codes is calculated as follows:
FSE = (VOUT – VIDEAL)/LSB
VIDEAL = (VREF)(1 – 2–n) – VOS
VREF = The reference voltage, either internal or
external
DNL = (∆VOUT – LSB)/LSB
∆VOUT = The measured voltage difference between
two adjacent codes
Digital Feedthrough: The glitch that appears at the analog
output caused by AC coupling from the digital inputs when
they change state. The area of the glitch is specified in
(nV)(sec).
6
LTC1257
W
BLOCK DIAGRA
LOGIC
SUPPLY
CLK
DIN
5V REGULATOR
VCC
12-BIT
SHIFT REGISTER
DOUT
12
LOAD
GND
12-BIT LATCH
12
REF
2.048V REFERENCE
+
DAC
VOUT
–
1257 BD
WU
W
TI I G DIAGRA
t1
t2
t6
CLK
t4
B11
MSB
DIN
t7
t3
B0
LSB
B1
B10
t5
LOAD
t8
DOUT
B11
(PREVIOUS WORD)
B10
B1
B0
B11
CURRENT WORD
1257 TD
7
LTC1257
U
OPERATIO
Serial Interface
Reference
The data on the DIN input is loaded into the shift register
on the rising edge of the clock. The MSB is loaded first and
the LSB last. The DAC register loads the data from the shift
register when LOAD is pulled low, and remains transparent until LOAD is pulled high and the data is latched.
The LTC1257 includes an internal 2.048V reference, making 1LSB equal to 500µV. The internal reference output is
turned off when the pin is forced above the reference
voltage, allowing an external reference to be connected to
the reference pin. The external reference must be greater
than 2.475V and less than VCC – 2.7V, and be capable of
driving the 10k minimum DAC resistor ladder.
An internal 5V regulator provides the supply for the digital
logic. By limiting the internal digital signal swings to 5V,
digital noise is reduced. The buffered output of the 12-bit
shift register is available on the DOUT pin which will swing
from GND to VCC.
Multiple LTC1257s may be daisy chained together by
connecting the DOUT pin to the DIN pin of the next chip,
while the clock and load signals remain common to all
chips in the daisy chain. The serial data is clocked to all of
the chips, then the LOAD signal is pulled low to update all
of them simultaneously. The maximum clocking rate is
1.4MHz.
If the reference output is driving a large capacitive load, a
series resistor must be added to insure stability. For any
capacitive load greater than 1µF, a 10Ω series resistor will
suffice.
Voltage Output
The LTC1257 voltage output is able to pull within 2.7V of
VCC while sourcing 2mA. A internal NMOS transistor with
a 200Ω equivalent impedance pulls the output to ground.
The output is protected against short circuits and is able
to drive up to a 500pF capacitive load without oscillation.
If digital noise on the output causes a problem, a simple
100Ω, 0.1µF RC circuit can be used to filter the noise.
UO
TYPICAL APPLICATI
S
DAC with External Reference
Filtering VREF and VOUT
15V
VCC
IN
0.1µF
LT1021-10
GND
OUT
0.1µF
DIN
CLK
VCC
CONTROL OUTPUT
VREF
VOUT LTC1257
GND
DIN
CLK
LOAD
LOAD
µP
100Ω
5%
LTC1257 VOUT
DOUT GND
VOUT
0.1µF
VREF
1µF
DOUT
1257 TA06
1257 TA03
8
VCC
10Ω
5%
LTC1257
UO
TYPICAL APPLICATI
S
Auto Ranging 8-Channel ADC with Shutdown
22µF
5V
VCC
CH0
8 ANALOG
INPUT CHANNELS
CS
DOUT
•
•
•
LTC1296
µP
CLK
DIN
CH7
COM
REF + REF –
SSO
50k
50k
5V
74HC04
0.1µF
VCC
DIN
100Ω
VOUT LTC1257
0.1µF
DIN
100Ω
VOUT LTC1257
GND VREF
0.1µF
LOAD
DOUT
GND VREF
VCC
CLK
CLK
LOAD
DOUT
1257 TA02
12-Bit Single 5V Control System with Shutdown
5V
100k
10k
10µF
2N3906
VCC
–IN
–
J
DATA
CLK
GND COMMON
µP
DAC LOAD
LTC1297
ADC
LT1025A
+
CLK
DOUT
0.1µF
VIN
CB/POWER DOWN
CS
+IN
GND
+
10µF
VREF
47k
LTC1050
–
1µF
1µF
100k
VREF
74k
1k
CONTORL
OUTPUT
VCC
DIN
CLK
VOUT LTC1257
LOAD
GND
DOUT
1257 TA04
9
LTC1257
U
PACKAGE DESCRIPTIO
Dimensions in inches (millimeters) unless otherwise noted.
N8 Package
8-Lead PDIP (Narrow 0.300)
(LTC DWG # 05-08-1510)
0.400*
(10.160)
MAX
8
7
6
5
1
2
3
4
0.255 ± 0.015*
(6.477 ± 0.381)
0.300 – 0.325
(7.620 – 8.255)
0.009 – 0.015
(0.229 – 0.381)
(
+0.035
0.325 –0.015
8.255
+0.889
–0.381
)
0.045 – 0.065
(1.143 – 1.651)
0.065
(1.651)
TYP
0.100 ± 0.010
(2.540 ± 0.254)
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)
10
0.130 ± 0.005
(3.302 ± 0.127)
0.125
(3.175) 0.020
MIN
(0.508)
MIN
0.018 ± 0.003
(0.457 ± 0.076)
N8 1197
LTC1257
U
PACKAGE DESCRIPTIO
Dimensions in inches (millimeters) unless otherwise noted.
S8 Package
8-Lead Plastic Small Outline (Narrow 0.150)
(LTC DWG # 05-08-1610)
0.189 – 0.197*
(4.801 – 5.004)
8
7
6
5
0.150 – 0.157**
(3.810 – 3.988)
0.228 – 0.244
(5.791 – 6.197)
1
0.010 – 0.020
× 45°
(0.254 – 0.508)
0.008 – 0.010
(0.203 – 0.254)
0.053 – 0.069
(1.346 – 1.752)
0°– 8° TYP
0.016 – 0.050
0.406 – 1.270
0.014 – 0.019
(0.355 – 0.483)
2
3
4
0.004 – 0.010
(0.101 – 0.254)
0.050
(1.270)
TYP
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
SO8 0996
11
LTC1257
UO
TYPICAL APPLICATI
Driving LTC1257 with Optoisolators
12V
VOUT
VIN
LT1021-5
2k
5%
MOC5008
CLK
CLK VCC VREF
DIN
VOUT
LOAD LTC1257
6
1
4
2
0.1µF
2k
5%
2k
5%
DOUT
VOUT
GND
5
MOC5008
DIN
6
1
4
2
5
MOC5008
LOAD
1
6
4
2
5
1257 TA07
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTC1446/LTC1446L
Dual 12-Bit VOUT DACs in SO-8 Package
LTC1446: VCC = 4.5V to 5.5V, VOUT = 0V to 4.095V
LTC1446L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V
LTC1448
Dual 12-Bit VOUT DAC in SO-8 Package, VCC: 2.7V to 5.5V
Output Swings from GND to REF,
REF Input Can Be Tied to VCC
LTC1450/LTC1450L
Single 12-Bit VOUT DACs with Parallel Interface
LTC1450: VCC = 4.5V to 5.5V, VOUT = 0V to 4.095V
LTC1450L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V
LTC1451
Single Rail-to-Rail 12-Bit VOUT DAC, Full Scale: 4.095V, VCC: 4.5V to
5.5V, Internal 2.048V Reference Brought Out to Pin
Low Power, Complete VOUT DAC in SO-8 Package
LTC1452
Single Rail-to-Rail 12-Bit VOUT Multiplying DAC, VCC: 2.7V to 5.5V
Low Power, Multiplying VOUT DAC with Rail-to-Rail
Buffer Amplifier in SO-8 Package
LTC1453
Single Rail-to-Rail 12-Bit VOUT DAC, Full Scale: 2.5V, VCC: 2.7V to 5.5V
3V, Low Power, Complete VOUT DAC in SO-8 Package
LTC1454/LTC1454L
Dual 12-Bit VOUT DACs in SO-16 Package with Added Functionality
LTC1454: VCC = 4.5V to 5.5V, VOUT = 0V to 4.095V
LTC1454L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V
LTC1456
Single Rail-to-Rail Output 12-Bit DAC with Clear Pin,
Full Scale: 4.095V, VCC: 4.5V to 5.5V
Low Power, Complete VOUT DAC in SO-8
Package with Clear Pin
LTC1458/LTC1458L
Quad 12 Bit Rail-to-Rail Output DACs with Added Functionality
LTC1458: VCC = 4.5V to 5.5V, VOUT = 0V to 4.095V
LTC1458L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V
LTC1659
Single Rail-to-Rail 12-Bit VOUT DAC in MSOP-8 Package,
VCC = 2.7V to 5.5V
Output Swings from GND to REF,
REF Input Can Be Tied to VCC
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Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417 ● (408) 432-1900
FAX: (408) 434-0507● TELEX: 499-3977 ● www.linear-tech.com
1257fa LT/TP 0198 REV A 4K • PRINTED IN USA
LINEAR TECHNOLOGY CORPORATION 1994