Cypress CY7C1011BV33-12ZI 128k x 16 static ram Datasheet

CY7C1011BV33
128K x 16 Static RAM
Features
• 3.0 – 3.6V Operation
• High speed
— tAA = 12, 15 ns
• CMOS for optimum speed/power
• Low active power
— 684 mW (Max.)
• Automatic power-down when deselected
• Independent control of upper and lower bits
• Available in 44-pin TSOP II
Functional Description
The CY7C1011BV33 is a high-performance CMOS static
RAM organized as 131,072 words by 16 bits. This device has
an automatic power-down feature that significantly reduces
power consumption when deselected.
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O1 through I/O8), is
written into the location specified on the address pins (A0
through A15). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O9 through I/O16) is written into the location
specified on the address pins (A0 through A16).
Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write
Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then
data from the memory location specified by the address pins
will appear on I/O1 to I/O8. If Byte High Enable (BHE) is LOW,
then data from memory will appear on I/O9 to I/O16. See the
truth table at the back of this data sheet for a complete description of read and write modes.
The input/output pins (I/O1 through I/O16) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), the BHE and BLE
are disabled (BHE, BLE HIGH), or during a write operation (CE
LOW, and WE LOW).
The CY7C1011BV33 is available in standard 44-pin TSOP
Type II package.
Logic Block Diagram
128K x 16
RAM Array
512 X 2048
SENSE AMPS
A7
A6
A5
A4
A3
A2
A1
A0
ROW DECODER
DATA IN DRIVERS
I/O1–I/O8
I/O9–I/O16
COLUMN DECODER
A8
A9
A10
A11
A12
A13
A14
A15
A16
BHE
WE
CE
OE
BLE
1011B-1
Cypress Semiconductor Corporation
Document #: 38-05021 Rev. *A
•
3901 North First Street
•
San Jose
•
CA 95134 • 408-943-2600
Revised June 6, 2001
CY7C1011BV33
Pin Configuration
TSOP II
Top View
A4
A3
A2
A1
A0
CE
I/O1
I/O2
I/O3
I/O4
VCC
VSS
I/O5
I/O6
I/O7
I/O8
WE
A16
A15
A14
A13
A12
1
44
2
3
43
42
4
41
40
39
38
5
6
7
8
9
10
11
12
37
36
35
34
33
32
31
30
29
28
27
13
14
15
16
17
18
19
20
21
22
26
25
24
23
A5
A6
A7
OE
BHE
BLE
I/O16
I/O15
I/O14
I/O13
VSS
VCC
I/O12
I/O11
I/O10
I/O9
NC
A8
A9
A10
A11
NC
1011B-2
Selection Guide
1011BV33-12
1011BV33-15
Maximum Access Time (ns)
Commercial
12
15
Maximum Operating Current (mA)
Commercial
190
170
Maximum CMOS Standby Current (mA)
Commercial
10
10
Maximum Ratings
Current into Outputs (LOW) ........................................ 20 mA
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Supply Voltage on VCC to Relative GND[1] .... –0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State[1] ......................................–0.5V to VCC+0.5V
DC Input Voltage[1] ..................................–0.5V to VCC+0.5V
Static Discharge Voltage ........................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current..................................................... >200 mA
Operating Range
Range
Commercial
Industrial
Ambient
Temperature[2]
VCC
0°C to +70°C
3.3V ± 10%
–40°C to +85°C
3.3V ± 10%
Electrical Characteristics Over the Operating Range
Parameter
Description
Test
Conditions
VOH
Output HIGH Voltage VCC = Min.,
IOH = –4.0 mA
VOL
Output LOW Voltage
Document #: 38-05021 Rev. *A
VCC = Min.,
IOL = 8.0 mA
1011BV33-12
Min.
Max.
2.4
1011BV33-15
Min.
Max.
2.4
0.4
Unit
V
0.4
V
Page 2 of 10
CY7C1011BV33
Electrical Characteristics Over the Operating Range (continued)
Parameter
Description
VIH
1011BV33-12
Test
Conditions
Min.
Input HIGH Voltage
1011BV33-15
Max.
Min.
2.2
[1]
Max.
Unit
2.2
V
VIL
Input LOW Voltage
–0.3
0.8
–0.3
0.8
V
IIX
Input Load Current
GND < VI < VCC
–1
+1
–1
+1
µA
IOZ
Output
Leakage
Current
GND < VI < VCC,
Output Disabled
–1
+1
–1
+1
µA
IOS
Output Short
Circuit
Current[3]
VCC = Max.,
VOUT = GND
–300
–300
mA
ICC
VCC
Operating
Supply
Current
VCC = Max.,
IOUT = 0 mA,
f = fMAX = 1/tRC
190
170
mA
ISB1
Automatic CE
Power-Down Current
—TTL Inputs
Max. VCC,
CE > VIH
VIN > VIH or
VIN < VIL,
f = fMAX
40
40
mA
ISB2
Automatic CE
Power-Down Current
—CMOS
Inputs
Max. VCC,
CE > VCC – 0.3V, VIN L
> VCC – 0.3V,
or VIN < 0.3V, f = 0
10
10
mA
0.5
0.5
Capacitance[4]
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
VCC = 5.0V
Max.
Unit
8
pF
8
pF
AC Test Loads and Waveforms
R 481 Ω
R 481 Ω
5V
5V
OUTPUT
90%
OUTPUT
30 pF
R2
255Ω
INCLUDING
JIG AND
SCOPE
(a)
ALL INPUT PULSES
3.0V
R2
255Ω
5 pF
INCLUDING
JIG AND
SCOPE
(b)
GND
10%
Rise Time: 1 V/ns
10%
Fall Time:1 V/ns
1011B-3
167
OUTPUT
Equivalent to: THÉVENIN
EQUIVALENT
90%
1011B-4
1.73V
30 pF
Notes:
1. VIL (min.) = –2.0V for pulse durations of less than 20 ns.
2. TA is the “instant on” case temperature.
3. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
Document #: 38-05021 Rev. *A
Page 3 of 10
CY7C1011BV33
Switching Characteristics[5] Over the Operating Range
1011BV33-12
Parameter
Description
Min.
Max.
1011BV33-15
Min.
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
tAA
Address to Data Valid
12
tOHA
Data Hold from Address Change
tACE
CE LOW to Data Valid
tDOE
OE LOW to Data Valid
tLZOE
OE LOW to Low Z[6]
3
OE HIGH to High Z
tLZCE
CE LOW to Low Z[6]
3
6
0
6
ns
ns
7
ns
ns
7
3
6
ns
15
0
3
[6, 7]
ns
15
12
[6, 7]
tHZOE
15
12
ns
ns
tHZCE
CE HIGH to High Z
tPU
CE LOW to Power-Up
tPD
CE HIGH to Power-Down
12
15
ns
tDBE
Byte Enable to Data Valid
6
7
ns
tLZBE
Byte Enable to Low Z
tHZBE
Byte Disable to High Z
0
7
0
0
ns
0
6
ns
ns
7
ns
Notes:
4. Tested initially and after any design or process changes that may affect these parameters.
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and 30-pF load capacitance.
6. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
7. tHZOE, tHZBE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
Document #: 38-05021 Rev. *A
Page 4 of 10
CY7C1011BV33
Switching Characteristics[5] Over the Operating Range
1011BV33-12
Parameter
Description
Min.
Max.
1011BV33-15
Min.
Max.
Unit
[8]
WRITE CYCLE
tWC
Write Cycle Time
12
15
ns
tSCE
CE LOW to Write End
10
12
ns
tAW
Address Set-Up to Write End
10
12
ns
tHA
Address Hold from Write End
0
0
ns
tSA
Address Set-Up to Write Start
0
0
ns
tPWE
WE Pulse Width
10
12
ns
tSD
Data Set-Up to Write End
7
8
ns
tHD
Data Hold from Write End
0
0
ns
tLZWE
WE HIGH to Low Z[6]
3
3
ns
[6, 7]
tHZWE
WE LOW to High Z
tBW
Byte Enable to End of Write
6
10
7
12
ns
ns
Switching Waveforms
Read Cycle No. 1 [9, 10]
tRC
ADDRESS
tAA
tOHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
1011B-5
Note:
8. The internal write time of the memory is defined by the overlap of CE LOW, WE LOW and BHE / BLE LOW. CE, WE and BHE / BLE must be LOW to initiate a write,
and the transition of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
9. Device is continuously selected. OE, CE, BHE and/or BHE = VIL.
10. WE is HIGH for read cycle.
Document #: 38-05021 Rev. *A
Page 5 of 10
CY7C1011BV33
Switching Waveforms (continued)
Read Cycle No. 2 (OE Controlled)[10, 11]
ADDRESS
tRC
CE
tACE
OE
tHZOE
tDOE
BHE, BLE
tLZOE
tHZCE
tDBE
tLZBE
DATA OUT
tHZBE
HIGH IMPEDANCE
DATA VALID
tLZCE
VCC
SUPPLY
CURRENT
HIGH
IMPEDANCE
tPD
tPU
IICC
CC
50%
50%
IISB
SB
1011B-6
Write Cycle No. 1 (CE Controlled) [12, 13]
tWC
ADDRESS
CE
tSA
tSCE
tAW
tHA
tPWE
WE
tBW
BHE, BLE
tSD
tHD
DATA I/O
1011B-7
Notes:
11. Address valid prior to or coincident with CE transition LOW.
12. Data I/O is high impedance if OE or BHE and/or BLE= VIH.
13. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
Document #: 38-05021 Rev. *A
Page 6 of 10
CY7C1011BV33
Switching Waveforms (continued)
Write Cycle No. 2 (BLE or BHE Controlled)
tWC
ADDRESS
tSA
BHE, BLE
tBW
tAW
tHA
tPWE
WE
tSCE
CE
tSD
tHD
DATA I/O
1011B-8
Write Cycle No. 3 (WE Controlled, OE LOW)
tWC
ADDRESS
tSCE
CE
tAW
tHA
tSA
tPWE
WE
tBW
BHE, BLE
tHZWE
tSD
tHD
DATA I/O
tLZWE
Document #: 38-05021 Rev. *A
1011B-10
Page 7 of 10
CY7C1011BV33
Truth Table
CE
OE
WE
H
X
L
L
L
X
BLE
BHE
X
X
X
High Z
High Z
Power-Down
Standby (ISB)
H
L
L
Data Out
Data Out
Read - All bits
Active (ICC)
L
H
Data Out
High Z
Read - Lower bits only
Active (ICC)
H
L
High Z
Data Out
Read - Upper bits only
Active (ICC)
L
L
Data In
Data In
Write - All bits
Active (ICC)
L
H
Data In
High Z
Write - Lower bits only
Active (ICC)
L
I/O1–I/O8
I/O9–I/O16
Mode
Power
H
L
High Z
Data In
Write - Upper bits only
Active (ICC)
L
H
H
X
X
High Z
High Z
Selected, Outputs Disabled
Active (ICC)
L
X
X
H
H
High Z
High Z
Selected, Outputs Disabled
Active (ICC)
Document #: 38-05021 Rev. *A
Page 8 of 10
CY7C1011BV33
Ordering Information
Speed
(ns)
12
15
Ordering Code
Package
Name
Package Type
Operating
Range
CY7C1011BV33-12ZI
Z44
44-Lead TSOP Type II
Industrial
CY7C1011BV33-12ZC
Z44
44-Lead TSOP Type II
Commercial
CY7C1011BV33-15ZC
Z44
44-Lead TSOP Type II
Commercial
CY7C1011BV33-15ZI
Z44
44-Lead TSOP Type II
Industrial
Package Diagrams
44-Pin TSOP II Z44
51-85087-A
Document #: 38-05021 Rev. *A
Page 9 of 10
© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C1011BV33
Document Title: CY7C1011BV33 128K X 16 Static RAM
Document Number: 38-05021
ECN NO.
Issue
Date
Orig. of
Change
**
106652
04/26/01
MPR
New Data Sheet
*A
107728
07/11/01
DFP
Remove SOJ TQFP Packages. Remove 8, 10 ns. changed Low Active Power
to 684. Change words/array/ added 2 addresses.
REV.
Document #: 38-05021 Rev. *A
Description of Change
Page 10 of 10
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