TI MSP430F5419IPZR Mixed signal microcontroller Datasheet

MSP430F543x, MSP430F541x
MSP430F543xA, MSP430F541xA
www.ti.com.......................................................................................................................................................................................... SLAS612 – SEPTEMBER 2008
MIXED SIGNAL MICROCONTROLLER
FEATURES
1
• Low Supply-Voltage Range
– 2.2 V to 3.6 V
MSP430F543x, MSP430F541x
– 1.8 V to 3.6 V
MSP430F543xA, MSP430F541xA
• Ultralow Power Consumption
– Active Mode (AM): 165 µA/MHz at 8 MHz
– Standby Mode (LPM3 RTC Mode): 2.60 µA
– Off Mode (LPM4 RAM Retention): 1.69 µA
– Shutdown Mode (LPM5): 0.1 µA
• Wake-Up From Standby Mode in Less Than
5 µs
• 16-Bit RISC Architecture
– Extended Memory
– Up to 18-MHz System Clock
MSP430F543x, MSP430F541x
– Up to 25-MHz System Clock
MSP430F543xA, MSP430F541xA
• Flexible Power Management System
– Fully Integrated LDO With Programmable
Regulated Core Supply Voltage
– Supply Voltage Supervision, Monitoring,
and Brownout
• Unified Clock System
– FLL Control Loop for Frequency
Stabilization
– Low-Power/Low-Frequency Internal Clock
Source (VLO)
– Low-Frequency Trimmed Internal Reference
Source (REFO)
– 32-kHz Crystals
– High-Frequency Crystals up to 32 MHz
• 16-Bit Timer0_A5 With Five Capture/Compare
Registers
• 16-Bit Timer1_A3 With Three Capture/Compare
Registers
• 16-Bit Timer_B7 With Seven Capture/Compare
Shadow Registers
2
•
•
•
•
•
•
•
(1)
Up to Four Universal Serial Communication
Interfaces
– Enhanced UART Supporting Auto-Baudrate
Detection
– IrDA Encoder and Decoder
– Synchronous SPI
– I2C™
12-Bit Analog-to-Digital (A/D) Converter
– Internal Reference
– Sample-and-Hold
– Autoscan Feature
– 12 External Channels, 4 Internal Channels
Hardware Multiplier Supporting 32-Bit
Operations
Serial Onboard Programming, No External
Programming Voltage Needed
Three Channel Internal DMA
Basic Timer With Real Time Clock Feature
Family Members Include:
– MSP430F5438, MSP430F5438A (1)
– 256KB+512B Flash Memory
– 16KB RAM
– Four Universal Serial Communication
Interfaces
– MSP430F5437, MSP430F5437A (1)
– 256KB+512B Flash Memory
– 16KB RAM
– Two Universal Serial Communication
Interfaces
– MSP430F5436, MSP430F5436A (1)
– 192KB+512B Flash Memory
– 16KB RAM
– Four Universal Serial Communication
Interfaces
– MSP430F5435, MSP430F5435A (1)
– 192KB+512B Flash Memory
– 16KB RAM
– Two Universal Serial Communication
Interfaces
Product Preview
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2008, Texas Instruments Incorporated
MSP430F543x, MSP430F541x
MSP430F543xA, MSP430F541xA
SLAS612 – SEPTEMBER 2008.......................................................................................................................................................................................... www.ti.com
– MSP430F5419, MSP430F5419A (1)
– 128KB+512B Flash Memory
– 16KB RAM
– Four Universal Serial Communication
Interfaces
•
– MSP430F5418, MSP430F5418A (1)
– 128KB+512B Flash Memory
– 16KB RAM
– Two Universal Serial Communication
Interfaces
For Complete Module Descriptions, See the
MSP430x5xx Family User's Guide (SLAU208)
DESCRIPTION
The Texas Instruments MSP430 family of ultralow-power microcontrollers consists of several devices featuring
different sets of peripherals targeted for various applications. The architecture, combined with five low-power
modes is optimized to achieve extended battery life in portable measurement applications. The device features a
powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code efficiency.
The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less than 5 µs.
The MSP430F543x(A) and MSP430F541x(A) series are microcontroller configurations with three 16-bit timers, a
high performance 12-bit analog-to-digital (A/D) converter, up to four universal serial communication interfaces
(USCI), hardware multiplier, DMA, real time clock module with alarm capabilities, and up to 87 I/O pins.
Typical applications for this device include analog and digital sensor systems, digital motor control, remote
controls, thermostats, digital timers, hand-held meters, etc.
ORDERING INFORMATION (1)
PACKAGED DEVICES (2)
TA
–40°C to
85°C
(1)
(2)
(3)
2
PLASTIC 100-PIN TQFP
(PZ)
PLASTIC 80-PIN TQFP (PN)
PLASTIC 113-BALL BGA
(ZQW)
MSP430F5438IPZ
MSP430F5437IPN
MSP430F5438IZQW (3)
MSP430F5436IPZ
MSP430F5435IPN
MSP430F5436IZQW (3)
MSP430F5419IPZ
MSP430F5418IPN
MSP430F5419IZQW (3)
MSP430F5438AIPZ (3)
MSP430F5437AIPN (3)
MSP430F5438AIZQW (3)
MSP430F5436AIPZ
(3)
MSP430F5435AIPN
(3)
MSP430F5436AIZQW (3)
MSP430F5419AIPZ
(3)
MSP430F5418AIPN
(3)
MSP430F5419AIZQW (3)
For the most current package and ordering information, see the Package Option Addendum at the end
of this document, or see the TI web site at www.ti.com.
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
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MSP430F543x, MSP430F541x
MSP430F543xA, MSP430F541xA
www.ti.com.......................................................................................................................................................................................... SLAS612 – SEPTEMBER 2008
Pin Designation, MSP430F5438(A)IPZ, MSP430F5436(A)IPZ, MSP430F5419(A)IPZ
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
MSP430F5438IPZ
MSP430F5436IPZ
MSP430F5419IPZ
MSP430F5438AIPZ
MSP430F5436AIPZ
MSP430F5419AIPZ
P9.7
P9.6
P9.5/UCA2RXDUCA2SOMI
P9.4/UCA2TXD/UCA2SIMO
P9.3/UCB2CLK/UCA2STE
P9.2/UCB2SOMI/UCB2SCL
P9.1/UCB2SIMO/UCB2SDA
P9.0/UCB2STE/UCA2CLK
P8.7
P8.6/TA1.1
P8.5/TA1.0
DVCC2
DVSS2
VCORE
P8.4/TA0.4
P8.3/TA0.3
P8.2/TA0.2
P8.1/TA0.1
P8.0/TA0.0
P7.3/TA1.2
P7.2/TBOUTH/SVMOUT
P5.7/UCA1RXD/UCA1SOMI
P5.6/UCA1TXD/UCA1SIMO
P5.5/UCB1CLK/UCA1STE
P5.4/UCB1SOMI/UCB1SCL
P2.1/TA1.0
P2.2/TA1.1
P2.3/TA1.2
P2.4/RTCCLK
P2.5
P2.6/ACLK
P2.7/ADC12CLK/DMAE0
P3.0/UCB0STE/UCA0CLK
P3.1/UCB0SIMO/UCB0SDA
P3.2/UCB0SOMI/UCB0SCL
P3.3/UCB0CLK/UCA0STE
DVSS3
DVCC3
P3.4/UCA0TXD/UCA0SIMO
P3.5/UCA0RXD/UCA0SOMI
P3.6/UCB1STE/UCA1CLK
P3.7/UCB1SIMO/UCB1SDA
P4.0/TB0
P4.1/TB1
P4.2/TB2
P4.3/TB3
P4.4/TB4
P4.5/TB5
P4.6/TB6
P4.7/TBCLK/SMCLK
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
P6.4/A4
P6.5/A5
P6.6/A6
P6.7/A7
P7.4/A12
P7.5/A13
P7.6/A14
P7.7/A15
P5.0/VREF+/VeREF+
P5.1/VREF−/VeREF−
AVCC
AVSS
P7.0/XIN
P7.1/XOUT
DVSS1
DVCC1
P1.0/TA0CLK/ACLK
P1.1/TA0.0
P1.2/TA0.1
P1.3/TA0.2
P1.4/TA0.3
P1.5/TA0.4
P1.6/SMCLK
P1.7
P2.0/TA1CLK/MCLK
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
P6.3/A3
P6.2/A2
P6.1/A1
P6.0/A0
RST/NMI/SBWTDIO
PJ.3/TCK
PJ.2/TMS
PJ.1/TDI/TCLK
PJ.0/TDO
TEST/SBWTCK
P5.3/XT2OUT
P5.2/XT2IN
DVSS4
DVCC4
P11.2/SMCLK
P11.1/MCLK
P11.0/ACLK
P10.7
P10.6
P10.5/UCA3RXDUCA3SOMI
P10.4/UCA3TXD/UCA3SIMO
P10.3/UCB3CLK/UCA3STE
P10.2/UCB3SOMI/UCB3SCL
P10.1/UCB3SIMO/UCB3SDA
P10.0/UCB3STE/UCA3CLK
PZ PACKAGE
(TOP VIEW)
Copyright © 2008, Texas Instruments Incorporated
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MSP430F543x, MSP430F541x
MSP430F543xA, MSP430F541xA
SLAS612 – SEPTEMBER 2008.......................................................................................................................................................................................... www.ti.com
Pin Designation, MSP430F5437(A)IPN, MSP430F5435(A)IPN, MSP430F5418(A)IPN
P6.3/A3
P6.2/A2
P6.1/A1
P6.0/A0
RST/NMI/SBWTDIO
PJ.3/TCK
PJ.2/TMS
PJ.1/TDI/TCLK
PJ.0/TDO
TEST/SBWTCLK
P5.3/XT2OUT
P5.2/XT2IN
DVSS4
DVCC4
P8.6/TA1.1
P8.5/TA1.0
P8.4/TA0.4
P8.3/TA0.3
P8.2/TA0.2
P8.1/TA0.1
PN PACKAGE
(TOP VIEW)
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
P6.4/A4
P6.5/A5
P6.6/A6
P6.7/A7
P7.4/A12
P7.5/A13
P7.6/A14
P7.7/A15
P5.0/VREF+/VeREF+
P5.1/VREF−/VeREF−
AVCC
AVSS
P7.0/XIN
P7.1/XOUT
DVSS1
DVCC1
P1.0/TA0CLK/ACLK
P1.1/TA0.0
P1.2/TA0.1
P1.3/TA0.2
1
60
2
59
3
58
4
57
5
56
6
55
7
54
53
8
MSP430F5437IPN
MSP430F5435IPN
MSP430F5418IPN
MSP430F5437AIPN
MSP430F5435AIPN
MSP430F5418AIPN
9
10
11
12
52
51
50
49
13
48
14
47
15
46
16
45
17
44
18
43
19
42
41
20
P8.0/TA0.0
P7.3/TA1.2
P7.2/TBOUTH/SVMOUT
P5.7/UCA1RXD/UCA1SOMI
P5.6/UCA1TXD/UCA1SIMO
P5.5/UCB1CLK/UCA1STE
P5.4/UCB1SOMI/UCB1SCL
P4.7/TBCLK/SMCLK
P4.6/TB6
DVCC2
DVSS2
VCORE
P4.5/TB5
P4.4/TB4
P4.3/TB3
P4.2/TB2
P4.1/TB1
P4.0/TB0
P3.7/UCB1SIMO/UCB1SDA
P3.6/UCB1STE/UCA1CLK
P1.4/TA0.3
P1.5/TA0.4
P1.6/SMCLK
P1.7
P2.0/TA1CLK/MCLK
P2.1/TA1.0
P2.2/TA1.1
P2.3/TA1.2
P2.4/RTCCLK
DVSS3
DVCC3
P2.5
P2.6/ACLK
P2.7/ADC12CLK/DMAE0
P3.0/UCB0STE/UCA0CLK
P3.1/UCB0SIMO/UCB0SDA
P3.2/UCB0SOMI/UCB0SCL
P3.3/UCB0CLK/UCA0STE
P3.4/UCA0TXD/UCA0SIMO
P3.5/UCA0RXD/UCA0SOMI
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
4
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MSP430F543x, MSP430F541x
MSP430F543xA, MSP430F541xA
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Functional Block Diagram, MSP430F5438(A)IPZ, MSP430F5436(A)IPZ, MSP430F5419(A)IPZ
XIN XOUT
DVCC
DVSS
AVCC
AVSS
RST/NMI
P1.x
XT2IN
ACLK
Unified
Clock
System
XT2OUT
256KB
192KB
128KB
SMCLK
Flash
MCLK
Power
Management
16KB
SYS
LDO
SVM/SVS
Brownout
RAM
Watchdog
PA
P2.x
P3.x
I/O Ports
P1/P2
2×8 I/Os
Interrupt
Capability
PA
1×16 I/Os
PB
P4.x
PC
P6.x
P5.x
PD
P8.x
P7.x
PE
P9.x P10.x
PF
P11.x
I/O Ports
P3/P4
2×8 I/Os
I/O Ports
P5/P6
2×8 I/Os
I/O Ports
P7/P8
2×8 I/Os
I/O Ports
P9/P10
2×8 I/Os
I/O Ports
P11
1×3 I/Os
PB
1×16 I/Os
PC
1×16 I/Os
PD
1×16 I/Os
PE
1×16 I/Os
PF
1×3 I/Os
MAB
CPUXV2
and
Working
Registers
DMA
MDB
3 Channel
EEM
(L: 8+2)
ADC12_A
USCI0,1,2,3
Timer0_A5
JTAG/
SBW
Interface
MPY32
5 CC
Registers
Timer1_A3
3 CC
Registers
Timer_B7
7 CC
Registers
RTC_A
CRC16
Ax: UART,
IrDA, SPI
Bx: SPI, I2C
12 Bit
200 KSPS
16 Channels
(12 ext/4 int)
Autoscan
Functional Block Diagram, MSP430F5437(A)IPN, MSP430F5435(A)IPN, MSP430F5418(A)IPN
XIN XOUT
DVCC
DVSS
AVCC
AVSS
RST/NMI
P1.x
XT2IN
XT2OUT
Unified
Clock
System
Power
Management
ACLK
SMCLK
256KB
192KB
128KB
RAM
MCLK
CPUXV2
and
Working
Registers
SYS
16KB
Flash
LDO
SVM/SVS
Brownout
Watchdog
PA
P2.x
I/O Ports
P1/P2
2×8 I/Os
Interrupt
Capability
PA
1×16 I/Os
P3.x
PB
P4.x
P5.x
PC
P6.x
P7.x
PD
P8.x
I/O Ports
P3/P4
2×8 I/Os
I/O Ports
P5/P6
2×8 I/Os
I/O Ports
P7/P8
2×8 I/Os
PB
1×16 I/Os
PC
1×16 I/Os
PD
1×16 I/Os
MAB
DMA
MDB
3 Channel
EEM
(L: 8+2)
ADC12_A
USCI0,1
JTAG/
SBW
Interface
MPY32
Timer0_A5
Timer1_A3
Timer_B7
5 CC
Registers
3 CC
Registers
7 CC
Registers
RTC_A
CRC16
Ax: UART,
IrDA, SPI
Bx: SPI, I2C
Copyright © 2008, Texas Instruments Incorporated
12 Bit
200 KSPS
16 Channels
(12 ext/4 int)
Autoscan
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MSP430F543x, MSP430F541x
MSP430F543xA, MSP430F541xA
SLAS612 – SEPTEMBER 2008.......................................................................................................................................................................................... www.ti.com
TERMINAL FUNCTIONS
TERMINAL
NAME
I/O (1)
NO.
DESCRIPTION
PZ
PN
P6.4/A4
1
1
I/O
General-purpose digital I/O
Analog input A4 – ADC
P6.5/A5
2
2
I/O
General-purpose digital I/O
Analog input A5 – ADC
P6.6/A6
3
3
I/O
General-purpose digital I/O
Analog input A6 – ADC
P6.7/A7
4
4
I/O
General-purpose digital I/O
Analog input A7 – ADC
P7.4/A12
5
5
I/O
General-purpose digital I/O
Analog input A12 –ADC
P7.5/A13
6
6
I/O
General-purpose digital I/O
Analog input A13 – ADC
P7.6/A14
7
7
I/O
General-purpose digital I/O
Analog input A14 – ADC
P7.7/A15
8
8
I/O
General-purpose digital I/O
Analog input A15 – ADC
P5.0/VREF+/VeREF+
9
9
I/O
General-purpose digital I/O
Output of reference voltage to the ADC
Input for an external reference voltage to the ADC
P5.1/VREF-/VeREF-
10
10
I/O
General-purpose digital I/O
Negative terminal for the ADC's reference voltage for both sources, the internal
reference voltage, or an external applied reference voltage
AVCC
11
11
Analog power supply
AVSS
12
12
Analog ground supply
P7.0/XIN
13
13
I/O
General-purpose digital I/O
Input terminal for crystal oscillator XT1
P7.1/XOUT
14
14
I/O
General-purpose digital I/O
Output terminal of crystal oscillator XT1
DVSS1
15
15
Digital ground supply
DVCC1
16
16
Digital power supply
P1.0/TA0CLK/ACLK
17
17
I/O
General-purpose digital I/O with port interrupt
Timer0_A5 clock signal TACLK input
ACLK output (divided by 1, 2, 4, or 8)
P1.1/TA0.0
18
18
I/O
General-purpose digital I/O with port interrupt
Timer0_A5 CCR0 capture: CCI0A input, compare: Out0 output
BSL transmit output
P1.2/TA0.1
19
19
I/O
General-purpose digital I/O with port interrupt
Timer0_A5 CCR1 capture: CCI1A input, compare: Out1 output
BSL receive input
P1.3/TA0.2
20
20
I/O
General-purpose digital I/O with port interrupt
Timer0_A5 CCR2 capture: CCI2A input, compare: Out2 output
P1.4/TA0.3
21
21
I/O
General-purpose digital I/O with port interrupt
Timer0_A5 CCR3 capture: CCI3A input compare: Out3 output
P1.5/TA0.4
22
22
I/O
General-purpose digital I/O with port interrupt
Timer0_A5 CCR4 capture: CCI4A input, compare: Out4 output
P1.6/SMCLK
23
23
I/O
General-purpose digital I/O with port interrupt
SMCLK output
P1.7
24
24
I/O
General-purpose digital I/O with port interrupt
P2.0/TA1CLK/MCLK
25
25
I/O
General-purpose digital I/O with port interrupt
Timer1_A3 clock signal TA1CLK input
MCLK output
P2.1/TA1.0
26
26
I/O
General-purpose digital I/O with port interrupt
Timer1_A3 CCR0 capture: CCI0A input, compare: Out0 output
(1)
6
I = input, O = output, N/A = not available on this package offering
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MSP430F543xA, MSP430F541xA
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TERMINAL FUNCTIONS (continued)
TERMINAL
NAME
I/O (1)
NO.
DESCRIPTION
PZ
PN
P2.2/TA1.1
27
27
I/O
General-purpose digital I/O with port interrupt
Timer1_A3 CCR1 capture: CCI1A input, compare: Out1 output
P2.3/TA1.2
28
28
I/O
General-purpose digital I/O with port interrupt
Timer1_A3 CCR2 capture: CCI2A input, compare: Out2 output
P2.4/RTCCLK
29
29
I/O
General-purpose digital I/O with port interrupt
RTCCLK output
P2.5
30
32
I/O
General-purpose digital I/O with port interrupt
P2.6/ACLK
31
33
I/O
General-purpose digital I/O with port interrupt
ACLK output (divided by 1, 2, 4, 8, 16, or 32)
P2.7/ADC12CLK/DMAE0
32
34
I/O
General-purpose digital I/O with port interrupt
Conversion clock input ADC
DMA external trigger input
P3.0/UCB0STE/UCA0CLK
33
35
I/O
General-purpose digital I/O
Slave transmit enable – USCI_B0 SPI mode
Clock signal input – USCI_A0 SPI slave mode
Clock signal output – USCI_A0 SPI master mode
P3.1/UCB0SIMO/UCB0SDA
34
36
I/O
General-purpose digital I/O
Slave in, master out – USCI_B0 SPI mode
I2C data – USCI_B0 I2C mode
P3.2/UCB0SOMI/UCB0SCL
35
37
I/O
General-purpose digital I/O
Slave out, master in – USCI_B0 SPI mode
I2C clock – USCI_B0 I2C mode
I/O
General-purpose digital I/O
Clock signal input – USCI_B0 SPI slave mode
Clock signal output – USCI_B0 SPI master mode
Slave transmit enable – USCI_A0 SPI mode
P3.3/UCB0CLK/UCA0STE
36
38
DVSS3
37
30
Digital ground supply
DVCC3
38
31
Digital power supply
P3.4/UCA0TXD/UCA0SIMO
39
39
I/O
General-purpose digital I/O
Transmit data – USCI_A0 UART mode
Slave in, master out – USCI_A0 SPI mode
P3.5/UCA0RXD/UCA0SOMI
40
40
I/O
General-purpose digital I/O
Receive data – USCI_A0 UART mode
Slave out, master in – USCI_A0 SPI mode
P3.6/UCB1STE/UCA1CLK
41
41
I/O
General-purpose digital I/O
Slave transmit enable – USCI_B1 SPI mode
Clock signal input – USCI_A1 SPI slave mode
Clock signal output – USCI_A1 SPI master mode
P3.7/UCB1SIMO/UCB1SDA
42
42
I/O
General-purpose digital I/O
Slave in, master out – USCI_B1 SPI mode
I2C data – USCI_B1 I2C mode
P4.0/TB0
43
43
I/O
General-purpose digital I/O
Timer_B7 capture CCR0: CCI0A/CCI0B input, compare: Out0 output
P4.1/TB1
44
44
I/O
General-purpose digital I/O
Timer_B7 capture CCR1: CCI1A/CCI1B input, compare: Out1 output
P4.2/TB2
45
45
I/O
General-purpose digital I/O
Timer_B7 capture CCR2: CCI2A/CCI2B input, compare: Out2 output
P4.3/TB3
46
46
I/O
General-purpose digital I/O
Timer_B7 capture CCR3: CCI3A/CCI3B input, compare: Out3 output
P4.4/TB4
47
47
I/O
General-purpose digital I/O
Timer_B7 capture CCR4: CCI4A/CCI4B input, compare: Out4 output
P4.5/TB5
48
48
I/O
General-purpose digital I/O
Timer_B7 capture CCR5: CCI5A/CCI5B input, compare: Out5 output
P4.6/TB6
49
52
I/O
General-purpose digital I/O
Timer_B7 capture CCR6: CCI6A/CCI6B input, compare: Out6 output
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TERMINAL FUNCTIONS (continued)
TERMINAL
NAME
I/O (1)
NO.
DESCRIPTION
PZ
PN
P4.7/TBCLK/SMCLK
50
53
I/O
General-purpose digital I/O
Timer_B7 clock input
SMCLK output
P5.4/UCB1SOMI/UCB1SCL
51
54
I/O
General-purpose digital I/O
Slave out, master in – USCI_B1 SPI mode
I2C clock – USCI_B1 I2C mode
P5.5/UCB1CLK/UCA1STE
52
55
I/O
General-purpose digital I/O
Clock signal input – USCI_B1 SPI slave mode
Clock signal output – USCI_B1 SPI master mode
Slave transmit enable – USCI_A1 SPI mode
P5.6/UCA1TXD/UCA1SIMO
53
56
I/O
General-purpose digital I/O
Transmit data – USCI_A1 UART mode
Slave in, master out – USCI_A1 SPI mode
P5.7/UCA1RXD/UCA1SOMI
54
57
I/O
General-purpose digital I/O
Receive data – USCI_A1 UART mode
Slave out, master in – USCI_A1 SPI mode
P7.2/TBOUTH/SVMOUT
55
58
I/O
General-purpose digital I/O
Switch all PWM outputs high impedance – Timer_B
SVM output
P7.3/TA1.2
56
59
I/O
General-purpose digital I/O
Timer1_A3 CCR2 capture: CCI2B input, compare: Out2 output
P8.0/TA0.0
57
60
I/O
General-purpose digital I/O
Timer0_A5 CCR0 capture: CCI0B input, compare: Out0 output
P8.1/TA0.1
58
61
I/O
General-purpose digital I/O
Timer0_A5 CCR1 capture: CCI1B input, compare: Out1 output
P8.2/TA0.2
59
62
I/O
General-purpose digital I/O
Timer0_A5 CCR2 capture: CCI2B input, compare: Out2 output
P8.3/TA0.3
60
63
I/O
General-purpose digital I/O
Timer0_A5 CCR3 capture: CCI3B input, compare: Out3 output
P8.4/TA0.4
61
64
I/O
General-purpose digital I/O
Timer0_A5 CCR4 capture: CCI4B input, compare: Out4 output
VCORE
62
49
Regulated core power supply
DVSS2
63
50
Digital ground supply
DVCC2
64
51
Digital power supply
P8.5/TA1.0
65
65
I/O
General-purpose digital I/O
Timer1_A3 CCR0 capture: CCI0B input, compare: Out0 output
P8.6/TA1.1
66
66
I/O
General-purpose digital I/O
Timer1_A3 CCR1 capture: CCI1B input, compare: Out1 output
P8.7
67
N/A
I/O
General-purpose digital I/O
P9.0/UCB2STE/UCA2CLK
68
N/A
I/O
General-purpose digital I/O
Slave transmit enable – USCI_B2 SPI mode
Clock signal input – USCI_A2 SPI slave mode
Clock signal output – USCI_A2 SPI master mode
P9.1/UCB2SIMO/UCB2SDA
69
N/A
I/O
General-purpose digital I/O
Slave in, master out – USCI_B2 SPI mode
I2C data – USCI_B2 I2C mode
P9.2/UCB2SOMI/UCB2SCL
70
N/A
I/O
General-purpose digital I/O
Slave out, master in – USCI_B2 SPI mode
I2C clock – USCI_B2 I2C mode
P9.3/UCB2CLK/UCA2STE
71
N/A
I/O
General-purpose digital I/O
Clock signal input – USCI_B2 SPI slave mode
Clock signal output – USCI_B2 SPI master mode
Slave transmit enable – USCI_A2 SPI mode
8
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TERMINAL FUNCTIONS (continued)
TERMINAL
NAME
I/O (1)
NO.
DESCRIPTION
PZ
PN
P9.4/UCA2TXD/UCA2SIMO
72
N/A
I/O
General-purpose digital I/O
Transmit data – USCI_A2 UART mode
Slave in, master out – USCI_A2 SPI mode
P9.5/UCA2RXD/UCA2SOMI
73
N/A
I/O
General-purpose digital I/O
Receive data – USCI_A2 UART mode
Slave out, master in – USCI_A2 SPI mode
P9.6
74
N/A
I/O
General-purpose digital I/O
P9.7
75
N/A
I/O
General-purpose digital I/O
P10.0/UCB3STE/UCA3CLK
76
N/A
I/O
General-purpose digital I/O
Slave transmit enable – USCI_B3 SPI mode
Clock signal input – USCI_A3 SPI slave mode
Clock signal output – USCI_A3 SPI master mode
P10.1/UCB3SIMO/UCB3SDA
77
N/A
I/O
General-purpose digital I/O
Slave in, master out – USCI_B3 SPI mode
I2C data – USCI_B3 I2C mode
P10.2/UCB3SOMI/UCB3SCL
78
N/A
I/O
General-purpose digital I/O
Slave out, master in – USCI_B3 SPI mode
I2C clock – USCI_B3 I2C mode
P10.3/UCB3CLK/UCA3STE
79
N/A
I/O
General-purpose digital I/O
Clock signal input – USCI_B3 SPI slave mode
Clock signal output – USCI_B3 SPI master mode
Slave transmit enable – USCI_A3 SPI mode
P10.4/UCA3TXD/UCA3SIMO
80
N/A
I/O
General-purpose digital I/O
Transmit data – USCI_A3 UART mode
Slave in, master out – USCI_A3 SPI mode
P10.5/UCA3RXD/UCA3SOMI
81
N/A
I/O
General-purpose digital I/O
Receive data – USCI_A3 UART mode
Slave out, master in – USCI_A3 SPI mode
P10.6
82
N/A
I/O
General-purpose digital I/O
P10.7
83
N/A
I/O
General-purpose digital I/O
P11.0/ACLK
84
N/A
I/O
General-purpose digital I/O
ACLK output (divided by 1, 2, 4, 8, 16, or 32)
P11.1/MCLK
85
N/A
I/O
General-purpose digital I/O
MCLK output
P11.2/SMCLK
86
N/A
I/O
General-purpose digital I/O
SMCLK output
DVCC4
87
67
Digital power supply
DVSS4
88
68
Digital ground supply
P5.2/XT2IN
89
69
I/O
General-purpose digital I/O
Input terminal for crystal oscillator XT2
P5.3/XT2OUT
90
70
I/O
General-purpose digital I/O
Output terminal of crystal oscillator XT2
TEST/SBWTCK
91
71
I
PJ.0/TDO
92
72
I/O
General-purpose digital I/O
Test data output port
PJ.1/TDI/TCLK
93
73
I/O
General-purpose digital I/O
Test data input or test clock input
PJ.2/TMS
94
74
I/O
General-purpose digital I/O
Test mode select
PJ.3/TCK
95
75
I/O
General-purpose digital I/O
Test clock
RST/NMI/SBWTDIO
96
76
I/O
Reset input active low
Non-maskable interrupt input
Spy-bi-wire data input/output
Copyright © 2008, Texas Instruments Incorporated
Test mode pin – select digital I/O on JTAG pins
Spy-bi-wire input clock
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TERMINAL FUNCTIONS (continued)
TERMINAL
NAME
I/O (1)
NO.
DESCRIPTION
PZ
PN
P6.0/A0
97
77
I/O
General-purpose digital I/O
Analog input A0 – ADC
P6.1/A1
98
78
I/O
General-purpose digital I/O
Analog input A1 – ADC
P6.2/A2
99
79
I/O
General-purpose digital I/O
Analog input A2 – ADC
P6.3/A3
100
80
I/O
General-purpose digital I/O
Analog input A3 – ADC
10
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SHORT-FORM DESCRIPTION
CPU
The MSP430 CPU has a 16-bit RISC architecture
that is highly transparent to the application. All
operations, other than program-flow instructions, are
performed as register operations in conjunction with
seven addressing modes for source operand and four
addressing modes for destination operand.
Program Counter
PC/R0
Stack Pointer
SP/R1
Status Register
Constant Generator
SR/CG1/R2
CG2/R3
General-Purpose Register
R4
General-Purpose Register
R5
General-Purpose Register
R6
General-Purpose Register
R7
General-Purpose Register
R8
General-Purpose Register
R9
Peripherals are connected to the CPU using data,
address, and control buses, and can be handled with
all instructions.
General-Purpose Register
R10
General-Purpose Register
R11
Instruction Set
General-Purpose Register
R12
The instruction set consists of the original 51
instructions with three formats and seven address
modes and additional instructions for the expanded
address range. Each instruction can operate on word
and byte data. Table 1 shows examples of the three
types of instruction formats; the address modes are
listed in Table 2.
General-Purpose Register
R13
General-Purpose Register
R14
General-Purpose Register
R15
The CPU is integrated with 16 registers that provide
reduced
instruction
execution
time.
The
register-to-register operation execution time is one
cycle of the CPU clock.
Four of the registers, R0 to R3, are dedicated as
program counter, stack pointer, status register, and
constant generator, respectively. The remaining
registers are general-purpose registers.
Table 1. Instruction Word Formats
Dual operands, source-destination
e.g., ADD
Single operands, destination only
e.g., CALL
Relative jump, un/conditional
e.g., JNE
R4,R5
R8
R4 + R5 → R5
PC → (TOS), R8 → PC
Jump-on-equal bit = 0
Table 2. Address Mode Descriptions
(1)
ADDRESS MODE
S (1)
D (1)
Register
+
+
MOV Rs,Rd
MOV R10,R11
R10 → R11
Indexed
+
+
MOV X(Rn),Y(Rm)
MOV 2(R5),6(R6)
M(2+R5) → M(6+R6)
Symbolic (PC relative)
+
+
MOV EDE,TONI
Absolute
+
+
MOV & MEM, & TCDAT
Indirect
+
MOV @Rn,Y(Rm)
MOV @R10,Tab(R6)
M(R10) → M(Tab+R6)
Indirect autoincrement
+
MOV @Rn+,Rm
MOV @R10+,R11
M(R10) → R11
R10 + 2 → R10
Immediate
+
MOV #X,TONI
MOV #45,TONI
#45 → M(TONI)
SYNTAX
EXAMPLE
OPERATION
M(EDE) → M(TONI)
M(MEM) → M(TCDAT)
S = source, D = destination
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Operating Modes
The MSP430 has one active mode and six software selectable low-power modes of operation. An interrupt event
can wake up the device from any of the five low-power modes, service the request, and restore back to the
low-power mode on return from the interrupt program.
The following seven operating modes can be configured by software:
• Active mode (AM)
– All clocks are active
• Low-power mode 0 (LPM0)
– CPU is disabled
– ACLK and SMCLK remain active, MCLK is disabled
– FLL loop control remains active
• Low-power mode 1 (LPM1)
– CPU is disabled
– FLL loop control is disabled
– ACLK and SMCLK remain active, MCLK is disabled
• Low-power mode 2 (LPM2)
– CPU is disabled
– MCLK and FLL loop control and DCOCLK are disabled
– DCO's dc-generator remains enabled
– ACLK remains active
• Low-power mode 3 (LPM3)
– CPU is disabled
– MCLK, FLL loop control, and DCOCLK are disabled
– DCO's dc generator is disabled
– ACLK remains active
• Low-power mode 4 (LPM4)
– CPU is disabled
– ACLK is disabled
– MCLK, FLL loop control, and DCOCLK are disabled
– DCO's dc generator is disabled
– Crystal oscillator is stopped
– Complete data retention
• Low-power mode 5 (LPM5) (A versions only)
– Internal regulator disabled
– No data retention
– Wakeup from RST, digital I/O
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Interrupt Vector Addresses
The interrupt vectors and the power-up start address are located in the address range 0FFFFh to 0FF80h. The
vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.
Interrupt Sources, Flags, and Vectors
INTERRUPT SOURCE
INTERRUPT FLAG
SYSTEM
INTERRUPT
WORD
ADDRESS
PRIORITY
System Reset
Power-Up
External Reset
Watchdog Timeout, Key Violation
Flash Memory Key Violation
WDTIFG, KEYV (SYSRSTIV) (1) (2)
Reset
0FFFEh
63, highest
System NMI
PMM
Vacant Memory Access
JTAG Mailbox
SVMLIFG, SVMHIFG, DLYLIFG, DLYHIFG,
VLRLIFG, VLRHIFG, VMAIFG, JMBNIFG,
JMBOUTIFG (SYSSNIV) (1)
(Non)maskable
0FFFCh
62
User NMI
NMI
Oscillator Fault
Flash Memory Access Violation
NMIIFG, OFIFG, ACCVIFG (SYSUNIV) (1) (2)
(Non)maskable
0FFFAh
61
Timer_B7
(3)
Maskable
0FFF8h
60
Timer_B7
TBCCR1 CCIFG1 ... TBCCR6 CCIFG6,
TBIFG (TBIV) (1) (3)
Maskable
0FFF6h
59
Watchdog Timer_A Interval Timer
Mode
WDTIFG
Maskable
0FFF4h
58
USCI_A0 Receive/Transmit
UCA0RXIFG, UCA0TXIFG (UCA0IV) (1) (3)
Maskable
0FFF2h
57
USCI_B0 Receive/Transmit
(3)
(4)
UCB0RXIFG, UCB0TXIFG (UCAB0IV)
(1) (3)
Maskable
0FFF0h
56
ADC12_A
ADC12IFG0 ... ADC12IFG15 (ADC12IV) (1) (3)
Maskable
0FFEEh
55
Timer0_A5
TA0CCR0 CCIFG0 (3)
Maskable
0FFECh
54
Timer0_A5
TA0CCR1 CCIFG1 ... TA0CCR4 CCIFG4,
TA0IFG (TA0IV) (1) (3)
Maskable
0FFEAh
53
USCI_A2 Receive/Transmit
UCA2RXIFG, UCA2TXIFG (UCA2IV)
(1) (3)
Maskable
0FFE8h
52
USCI_B2 Receive/Transmit
UCB2RXIFG, UCB2TXIFG (UCB2IV) (1) (3)
Maskable
0FFE6h
51
DMA
(1)
(2)
TBCCR0 CCIFG0
DMA0IFG, DMA1IFG, DMA2IFG (DMAIV)
(1) (3)
Maskable
0FFE4h
50
Timer1_A3
TA1CCR0 CCIFG0 (3)
Maskable
0FFE2h
49
Timer1_A3
TA1CCR1 CCIFG1 ... TA1CCR2 CCIFG2,
TA1IFG (TA1IV) (1) (3)
Maskable
0FFE0h
48
I/O Port P1
P1IFG.0 to P1IFG.7 (P1IV) (1) (3)
Maskable
0FFDEh
47
USCI_A1 Receive/Transmit
UCA1RXIFG, UCA1TXIFG (UCA1IV) (1) (3)
Maskable
0FFDCh
46
USCI_B1 Receive/Transmit
UCB1RXIFG, UCB1TXIFG (UCB1IV) (1) (3)
Maskable
0FFDAh
45
USCI_A3 Receive/Transmit
UCA3RXIFG, UCA3TXIFG (UCA3IV)
(1) (3)
Maskable
0FFD8h
44
USCI_B3 Receive/Transmit
UCB3RXIFG, UCB3TXIFG (UCB3IV) (1) (3)
Maskable
0FFD6h
43
I/O Port P2
P2IFG.0 to P2IFG.7 (P2IV) (1) (3)
Maskable
0FFD4h
42
RTC_A
RTCRDYIFG, RTCTEVIFG, RTCAIFG,
RT0PSIFG, RT1PSIFG (RTCIV) (1) (3)
Maskable
0FFD2h
41
0FFD0h
40
Reserved
Reserved (4)
⋮
⋮
0FF80h
0, lowest
Multiple source flags
A reset is generated if the CPU tries to fetch instructions from within peripheral space or vacant memory space.
(Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable cannot disable it.
Interrupt flags are located in the module.
Reserved interrupt vectors at addresses are not used in this device and can be used for regular program code if necessary. To maintain
compatibility with other devices, it is recommended to reserve these locations.
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Special Function Registers (SFRs)
The MSP430 SFRs are located in the lowest address space and can be accessed via word or byte formats.
<br/>
Legend
rw:
rw-0,1:
rw-(0,1):
rw-[0,1]:
Bit can
Bit can
Bit can
Bit can
–
be
be
be
be
read and written.
read and written. It is reset or set by PUC.
read and written. It is reset or set by POR.
read and written. It is reset or set by BOR.
SFR bit is not present in device.
Table 1. Interrupt Enable 1
15
14
13
12
11
10
9
8
–
–
–
–
–
–
–
–
7
6
5
4
3
2
1
0
JMBOUTIE
JMBINIE
ACCVIE
NMIIE
VMAIE
–
OFIE
WDTIE
rw-0
rw-0
rw-0
rw-0
rw-0
rw-0
rw-0
WDTIE
Watchdog timer interrupt enable. Inactive if watchdog mode is selected. Active if watchdog timer is configured as a
general-purpose timer.
OFIE
Oscillator fault interrupt enable
VMAIE
Vacant memory access interrupt enable
NMIIE
Nonmaskable interrupt enable
ACCVIE
Flash access violation interrupt enable
JMBINIE
JTAG mailbox input interrupt enable
JMBOUTIE
JTAG mailbox output interrupt enable
Table 2. Interrupt Flag 1
15
14
13
12
11
10
9
8
–
–
–
–
–
–
–
–
7
6
5
4
3
2
1
0
JMBOUTIFG
JMBINIFG
–
NMIIFG
VMAIFG
–
OFIFG
WDTIFG
rw-[0]
rw-[0]
rw-0
rw-0
rw-0
rw-0
WDTIFG
Set on watchdog timer overflow (in watchdog mode) or security key violation
Reset on VCC power-on or a reset condition at the RST/NMI pin in reset mode
OFIFG
Flag set on oscillator fault
VMAIFG
Set on vacant memory access
NMIIFG
Set via RST/NMI pin
JMBINIFG
Set on JTAG mailbox input message
JMBOUTIFG
Set on JTAG mailbox output register ready for next message
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Memory Organization
Memory
Main: interrupt vector
Main: code memory
MSP430F5419(A)
MSP430F5418(A)
MSP430F5436(A)
MSP430F5435(A)
MSP430F5438(A)
MSP430F5437(A)
Size
Flash
Flash
128 KB
00FFFFh–00FF80h
025BFFh–005C00h
192 KB
00FFFFh–00FF80h
035BFFh–005C00h
256 KB
00FFFFh–00FF80h
045BFFh–005C00h
Size
16 KB
16 KB
16 KB
Sector 3
4 KB
005BFFh–004C00h
005BFFh–004C00h
4 KB
005BFFh–004C00h
4 KB
Sector 2
4 KB
004BFFh–003C00h
004BFFh–003C00h
4 KB
004BFFh–003C00h
4 KB
Sector 1
4 KB
003BFFh–002C00h
003BFFh–002C00h
4 KB
003BFFh–002C00h
4 KB
Sector 0
4 KB
002BFFh–001C00h
002BFFh–001C00h
4 KB
002BFFh–001C00h
4 KB
Info A
128 B
0019FFh–001980h
128 B
0019FFh–001980h
128 B
0019FFh–001980h
Info B
128 B
00197Fh–001900h
128 B
00197Fh–001900h
128 B
00197Fh–001900h
Info C
128 B
0018FFh–001880h
128 B
0018FFh–001880h
128 B
0018FFh–001880h
Info D
128 B
00187Fh–001800h
128 B
00187Fh–001800h
128 B
00187Fh–001800h
BSL 3
512 B
0017FFh–001600h
512 B
0017FFh–001600h
512 B
0017FFh–001600h
BSL 2
512 B
0015FFh–001400h
512 B
0015FFh–001400h
512 B
0015FFh–001400h
BSL 1
512 B
0013FFh–001200h
512 B
0013FFh–001200h
512 B
0013FFh–001200h
BSL 0
512 B
0011FFh–001000h
512 B
0011FFh–001000h
512 B
0011FFh–001000h
Size
4KB
000FFFh–000000h
4KB
000FFFh–000000h
4KB
000FFFh–000000h
RAM
Information memory
(Flash)
Bootstrap loader
(BSL) (1) memory (Flash)
Peripherals
(1)
For non-A versions, the BSL area contains a Texas Instruments provided BSL and cannot be modified. For A versions, the BSL can be
modified by the user.
Bootstrap Loader (BSL)
The BSL enables users to program the flash memory or RAM using a UART serial interface. Access to the
device memory via the BSL is protected by user-defined password. For complete description of the features of
the BSL and its implementation, see the application report Features of the MSP430 Bootstrap Loader, TI
literature number SLAA089.
BSL FUNCTION
PZ PACKAGE PINS
PN PACKAGE PINS
Data transmit
18 – P1.1
18 – P1.1
Data receive
19 – P1.2
19 – P1.2
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Flash Memory
The flash memory can be programmed via the JTAG port, Spy-Bi-Wire (SBW), the BSL, or in-system by the
CPU. The CPU can perform single-byte, single-word, and long-word writes to the flash memory. Features of the
flash memory include:
• Flash memory has n segments of main memory and four segments of information memory (A to D) of
128 bytes each. Each segment in main memory is 512 bytes in size.
• Segments 0 to n may be erased in one step, or each segment may be individually erased.
• Segments A to D can be erased individually, or as a group with segments 0 to n. Segments A to D are also
called information memory.
• Segment A can be locked separately.
RAM Memory
The RAM memory is made up of n sectors. Each sector can be completely powered down to save leakage,
however all data is lost. Features of the RAM memory include:
• RAM memory has n sectors. The size of a sector can be found in the Memory Organization section.
• Each sector 0 to n can be complete disabled, however data retention is lost.
• Each sector 0 to n automatically enters low power retention mode when possible.
• For Devices that contain USB memory, the USB memory can be used as normal RAM if USB is not required.
16
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Peripherals
Peripherals are connected to the CPU through data, address, and control buses and can be handled using all
instructions. For complete module descriptions, see the MSP430x5xx Family User's Guide, literature number
SLAU208.
Digital I/O
There are up to ten 8-bit I/O ports implemented: For 100-pin options, P1 through P10 are complete. P11 contains
three individual I/O ports.For 80-pin options, P1 through P7 are complete. P8 contains seven individual I/O ports.
P9 through P11 do not exist. Port PJ contains four individual I/O ports, common to all devices.
• All individual I/O bits are independently programmable.
• Any combination of input, output, and interrupt conditions is possible.
• Pullup or pulldown on all ports is programmable.
• Drive strength on all ports is programmable.
• Edge-selectable interrupt and LPM5 wakeup input capability is available for all bits of ports P1 and P2.
• Read/write access to port-control registers is supported by all instructions.
• Ports can be accessed byte-wise (P1 through P11) or word-wise in pairs (PA through PF).
Oscillator and System Clock
The clock system in the MSP430x5xx family of devices is supported by the Unified Clock System (UCS) module
that includes support for a 32-kHz watch crystal oscillator (XT1 LF mode), an internal very-low-power
low-frequency oscillator (VLO), an internal trimmed low-frequency oscillator (REFO), an integrated internal
digitally controlled oscillator (DCO), and a high-frequency crystal oscillator (XT1 HF mode or XT2). The UCS
module is designed to meet the requirements of both low system cost and low power consumption. The UCS
module features digital frequency locked loop (FLL) hardware that, in conjunction with a digital modulator,
stabilizes the DCO frequency to a programmable multiple of the watch crystal frequency. The internal DCO
provides a fast turn-on clock source and stabilizes in less than 5 µs. The UCS module provides the following
clock signals:
• Auxiliary clock (ACLK), sourced from a 32-kHz watch crystal, a high-frequency crystal, the internal
low-frequency oscillator (VLO), the trimmed low-frequency oscillator (REFO), or the internal digitally controlled
oscillator DCO.
• Main clock (MCLK), the system clock used by the CPU. MCLK can be sourced by same sources made
available to ACLK.
• Sub-Main clock (SMCLK), the subsystem clock used by the peripheral modules. SMCLK can be sourced by
same sources made available to ACLK.
• ACLK/n, the buffered output of ACLK, ACLK/2, ACLK/4, ACLK/8, ACLK/16, ACLK/32.
Power Management Module (PMM)
The PMM includes an integrated voltage regulator that supplies the core voltage to the device and contains
programmable output levels to provide for power optimization. The PMM also includes supply voltage supervisor
(SVS) and supply voltage monitoring (SVM) circuitry, as well as brownout protection. The brownout circuit is
implemented to provide the proper internal reset signal to the device during power-on and power-off. The
SVS/SVM circuitry detects if the supply voltage drops below a user-selectable level and supports both supply
voltage supervision (the device is automatically reset) and supply voltage monitoring (SVM, the device is not
automatically reset). SVS and SVM circuitry is available on the primary supply and core supply.
Hardware Multiplier
The multiplication operation is supported by a dedicated peripheral module. The module performs operations with
32-bit, 24-bit, 16-bit, and 8-bit operands. The module is capable of supporting signed and unsigned multiplication
as well as signed and unsigned multiply and accumulate operations.
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Real-Time Clock (RTC_A)
The RTC_A module can be used as a general-purpose 32-bit counter (counter mode) or as an integrated
real-time clock (RTC) (calendar mode). In counter mode, the RTC_A also includes two independent 8-bit timers
that can be cascaded to form a 16-bit timer/counter. Both timers can be read and written by software. Calendar
mode integrates an internal calendar which compensates for months with less than 31 days and includes leap
year correction. The RTC_A also supports flexible alarm functions and offset-calibration hardware.
Watchdog Timer (WDT_A)
The primary function of the watchdog timer (WDT_A) module is to perform a controlled system restart after a
software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog
function is not needed in an application, the module can be configured as an interval timer and can generate
interrupts at selected time intervals.
System Module (SYS)
The SYS module handles many of the system functions within the device. These include power on reset and
power up clear handling, NMI source selection and management, reset interrupt vector generators, boot strap
loader entry mechanisms, as well as, configuration management (device descriptors). It also includes a data
exchange mechanism via JTAG called a JTAG mailbox that can be used in the application.
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Table 3. System Module Interrupt Vector Registers
INTERRUPT VECTOR
REGISTER
SYSRSTIV , System Reset
SYSSNIV , System NMI
INTERRUPT EVENT
WORD ADDRESS
No interrupt pending
00h
Brownout (BOR)
02h
RSTNMI (BOR)
04h
DoBOR (BOR)
06h
Reserved
08h
Security violation (BOR)
0Ah
SVSL (POR)
0Ch
SVSH (POR)
0Eh
SVML_OVP (POR)
SVMH_OVP (POR)
019Eh
14h
16h
WDT key violation (PUC)
18h
KEYV flash key violation (PUC)
1Ah
FLL unlock (PUC)
1Ch
Peripheral area fetch (PUC)
1Eh
PMM key violation (PUC)
20h
Reserved
22h - 3Eh
No interrupt pending
00h
SVMLIFG
02h
SVMHIFG
04h
DLYLIFG
06h
DLYHIFG
08h
019Ch
0Ch
JMBOUTIFG
0Eh
VLRLIFG
10h
VLRHIFG
12h
Reserved
14h - 1Eh
No interrupt pending
00h
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02h
019Ah
Lowest
Highest
0Ah
JMBINIFG
OFIFG
Highest
12h
DoPOR (POR)
VMAIFG
PRIORITY
10h
WDT timeout (PUC)
NMIFG
SYSUNIV, User NMI
OFFSET
Lowest
Highest
04h
ACCVIFG
06h
Reserved
08h - 1Eh
Lowest
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DMA Controller
The DMA controller allows movement of data from one memory address to another without CPU intervention. For
example, the DMA controller can be used to move data from the ADC12_A conversion memory to RAM. Using
the DMA controller can increase the throughput of peripheral modules. The DMA controller reduces system
power consumption by allowing the CPU to remain in sleep mode, without having to awaken to move data to or
from a peripheral.
Table 4. DMA Trigger Assignments
Trigger
(1)
20
(1)
Channel
0
1
2
0
DMAREQ
DMAREQ
DMAREQ
1
TA0CCR0 CCIFG
TA0CCR0 CCIFG
TA0CCR0 CCIFG
2
TA0CCR2 CCIFG
TA0CCR2 CCIFG
TA0CCR2 CCIFG
3
TA1CCR0 CCIFG
TA1CCR0 CCIFG
TA1CCR0 CCIFG
4
TA1CCR2 CCIFG
TA1CCR2 CCIFG
TA1CCR2 CCIFG
5
TBCCR0 CCIFG
TBCCR0 CCIFG
TBCCR0 CCIFG
6
TBCCR2 CCIFG
TBCCR2 CCIFG
TBCCR2 CCIFG
7
Reserved
Reserved
Reserved
8
Reserved
Reserved
Reserved
9
Reserved
Reserved
Reserved
10
Reserved
Reserved
Reserved
11
Reserved
Reserved
Reserved
12
Reserved
Reserved
Reserved
13
Reserved
Reserved
Reserved
14
Reserved
Reserved
Reserved
15
Reserved
Reserved
Reserved
16
UCA0RXIFG
UCA0RXIFG
UCA0RXIFG
17
UCA0TXIFG
UCA0TXIFG
UCA0TXIFG
18
UCB0RXIFG
UCB0RXIFG
UCB0RXIFG
19
UCB0TXIFG
UCB0TXIFG
UCB0TXIFG
20
UCA1RXIFG
UCA1RXIFG
UCA1RXIFG
21
UCA1TXIFG
UCA1TXIFG
UCA1TXIFG
22
UCB1RXIFG
UCB1RXIFG
UCB1RXIFG
23
UCB1TXIFG
UCB1TXIFG
UCB1TXIFG
24
ADC12IFGx
ADC12IFGx
ADC12IFGx
25
Reserved
Reserved
Reserved
26
Reserved
Reserved
Reserved
27
Reserved
Reserved
Reserved
28
Reserved
Reserved
Reserved
29
MPY ready
MPY ready
MPY ready
30
DMA2IFG
DMA0IFG
DMA1IFG
31
DMAE0
DMAE0
DMAE0
Reserved DMA triggers may be used by other devices in the family. Reserved DMA triggers will not
cause any DMA trigger event when selected.
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Universal Serial Communication Interface (USCI)
The USCI modules are used for serial data communication. The USCI module supports synchronous
communication protocols such as SPI (3 or 4 pin) and I2C, and asynchronous communication protocols such as
UART, enhanced UART with automatic baudrate detection, and IrDA. Each USCI module contains two portions,
A and B.
The USCI_An module provides support for SPI (3 pin or 4 pin), UART, enhanced UART, or IrDA.
The USCI_Bn module provides support for SPI (3 pin or 4 pin) or I2C.
The MSP430F5438(A), MSP430F5436(A), and MSP430F5419(A) include four complete USCI modules
(n = 0 to 3). The MSP430F5437(A), MSP430F5435(A), and MSP430F5418(A) include two complete USCI
modules (n = 0 to 1).
Timer0_A5
Timer0_A5 is a 16-bit timer/counter with five capture/compare registers. Timer0_A5 can support multiple
capture/compares, PWM outputs, and interval timing. Timer0_A5 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
Table 5. Timer0_A5 Signal Connections
INPUT PIN NUMBER
PZ
PN
DEVICE
INPUT
SIGNAL
17-P1.0
17-P1.0
TA0CLK
MODULE
INPUT
SIGNAL
TACLK
ACLK
ACLK
SMCLK
SMCLK
17-P1.0
17-P1.0
TA0CLK
TACLK
18-P1.1
18-P1.1
TA0.0
CCI0A
57-P8.0
60-P8.0
TA0.0
CCI0B
DVSS
GND
MODULE
BLOCK
MODULE
OUTPUT
SIGNAL
DEVICE
OUTPUT
SIGNAL
Timer
NA
NA
CCR0
TA0
TA0.0
OUTPUT PIN NUMBER
PZ
PN
18-P1.1
18-P1.1
57-P8.0
60-P8.0
ADC12
(internal)
ADC12
(internal)
DVCC
VCC
19-P1.2
19-P1.2
TA0.1
CCI1A
19-P1.2
19-P1.2
58-P8.1
59-P8.1
TA0.1
CCI1B
58-P8.1
59-P8.1
DVSS
GND
DVCC
VCC
CCR1
TA1
TA0.1
20-P1.3
20-P1.3
TA0.2
CCI2A
20-P1.3
20-P1.3
59-P8.2
62-P8.2
TA0.2
CCI2B
59-P8.2
62-P8.2
DVSS
GND
21-P1.4
21-P1.4
60-P8.3
63-P8.3
DVCC
VCC
21-P1.4
21-P1.4
TA0.3
CCI3A
60-P8.3
63-P8.3
TA0.3
CCI3B
DVSS
GND
DVCC
VCC
CCR2
CCR3
TA2
TA3
TA0.2
TA0.3
22-P1.5
22-P1.5
TA0.4
CCI4A
22-P1.5
22-P1.5
61-P8.4
63-P8.4
TA0.4
CCI4B
61-P8.4
63-P8.4
DVSS
GND
DVCC
VCC
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CCR4
TA4
TA0.4
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Timer1_A3
Timer1_A3 is a 16-bit timer/counter with three capture/compare registers. Timer1_A3 can support multiple
capture/compares, PWM outputs, and interval timing. Timer1_A3 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
Table 6. Timer1_A3 Signal Connections
INPUT PIN NUMBER
22
PZ
PN
DEVICE
INPUT
SIGNAL
MODULE
INPUT
SIGNAL
25-P2.0
25-P2.0
TA1CLK
TACLK
ACLK
ACLK
SMCLK
SMCLK
25-P2.0
25-P2.0
TA1CLK
TACLK
26-P2.1
26-P2.1
TA1.0
CCI0A
65-P8.5
65-P8.5
TA1.0
CCI0B
DVSS
GND
DVCC
VCC
27-P2.2
27-P2.2
TA1.1
CCI1A
66-P8.6
66-P8.6
TA1.1
CCI1B
DVSS
GND
DVCC
VCC
MODULE
BLOCK
MODULE
OUTPUT
SIGNAL
DEVICE
OUTPUT
SIGNAL
Timer
NA
NA
CCR0
CCR1
TA0
TA1
TA1.0
TA1.1
OUTPUT PIN NUMBER
PZ
PN
26-P2.1
26-P2.1
65-P8.5
65-P8.5
27-P2.2
27-P2.2
66-P8.6
66-P8.6
28-P2.3
28-P2.3
TA1.2
CCI2A
28-P2.3
28-P2.3
56-P7.3
59-P7.3
TA1.2
CCI2B
56-P7.3
59-P7.3
DVSS
GND
DVCC
VCC
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CCR2
TA2
TA1.2
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Timer_B7
Timer_B7 is a 16-bit timer/counter with seven capture/compare registers. Timer_B7 can support multiple
capture/compares, PWM outputs, and interval timing. Timer_B7 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
Table 7. Timer_B7 Signal Connections
INPUT PIN NUMBER
PZ
PN
DEVICE
INPUT
SIGNAL
MODULE
INPUT
SIGNAL
50-P4.7
50-P4.7
TBCLK
TBCLK
ACLK
ACLK
SMCLK
SMCLK
50-P4.7
50-P4.7
TBCLK
TBCLK
43-P4.0
43-P4.0
TB0
CCI0A
43-P4.0
43-P4.0
TB0
CCI0B
44-P4.1
44-P4.1
44-P4.1
44-P4.1
CCR0
TB0
TB0
43-P4.0
43-P4.0
ADC12
(internal)
ADC12
(internal)
CCI1A
44-P4.1
44-P4.1
TB1
CCI1B
ADC12
(internal)
ADC12
(internal)
DVSS
GND
45-P4.2
45-P4.2
46-P4.3
46-P4.3
47-P4.4
47-P4.4
48-P4.5
48-P4.5
49-P4.6
52-P4.6
DVCC
VCC
45-P4.2
TB2
CCI2B
DVSS
GND
DVCC
VCC
TB3
CCI3A
TB3
CCI3B
DVSS
GND
DVCC
VCC
47-P4.4
47-P4.4
TB4
CCI4A
47-P4.4
47-P4.4
TB4
CCI4B
DVSS
GND
DVCC
VCC
48-P4.5
48-P4.5
TB5
CCI5A
48-P4.5
48-P4.5
TB5
CCI5B
DVSS
GND
52-P4.6
NA
PN
TB1
45-P4.2
49-P4.6
NA
PZ
VCC
CCI2A
46-P4.3
Timer
OUTPUT PIN NUMBER
GND
TB2
46-P4.3
DEVICE
OUTPUT
SIGNAL
DVSS
45-P4.2
46-P4.3
MODULE
OUTPUT
SIGNAL
DVCC
45-P4.2
46-P4.3
MODULE
BLOCK
DVCC
VCC
TB6
CCI6A
ACLK
(internal)
CCI6B
DVSS
GND
DVCC
VCC
CCR1
CCR2
CCR3
CCR4
CCR5
CCR6
TB1
TB2
TB3
TB4
TB5
TB6
TB1
TB2
TB3
TB4
TB5
TB6
ADC12_A
The ADC12_A module supports fast, 12-bit analog-to-digital conversions. The module implements a 12-bit SAR
core, sample select control, reference generator and a 16 word conversion-and-control buffer. The
conversion-and-control buffer allows up to 16 independent ADC samples to be converted and stored without any
CPU intervention.
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CRC16
The CRC16 module produces a signature based on a sequence of entered data values and can be used for data
checking purposes. The CRC16 module signature is based on the CRC-CCITT standard.
Peripheral File Map
Table 8. Peripherals
MODULE NAME
Timer_B7
Timer0_A5
24
REGISTER DESCRIPTION
REGISTER
BASE
ADDRESS
Timer_B7 interrupt vector
TBIV
Timer_B7 expansion register 0
TBEX0
20h
Capture/compare register 6
TBCCR6
1Eh
Capture/compare register 5
TBCCR5
1Ch
Capture/compare register 4
TBCCR4
1Ah
Capture/compare register 3
TBCCR3
18h
Capture/compare register 2
TBCCR2
16h
Capture/compare register 1
TBCCR1
14h
Capture/compare register 0
TBCCR0
12h
Timer_B7 register
TBR
10h
Capture/compare control 6
TBCCTL6
0Eh
Capture/compare control 5
TBCCTL5
0Ch
Capture/compare control 4
TBCCTL4
0Ah
Capture/compare control 3
TBCCTL3
08h
Capture/compare control 2
TBCCTL2
06h
Capture/compare control 1
TBCCTL1
04h
Capture/compare control 0
TBCCTL0
02h
Timer_B7 control
TBCTL
Timer0_A5 interrupt vector
TA0IV
Timer0_A5 expansion register 0
TA0EX0
20h
Capture/compare register 4
TA0CCR4
1Ah
Capture/compare register 3
TA0CCR3
18h
Capture/compare register 2
TA0CCR2
16h
Capture/compare register 1
TA0CCR1
14h
Capture/compare register 0
TA0CCR0
12h
Timer0_A5 register
TA0R
10h
Capture/compare control 4
TA0CCTL4
0Ah
Capture/compare control 3
TA0CCTL3
08h
Capture/compare control 2
TA0CCTL2
06h
Capture/compare control 1
TA0CCTL1
04h
Capture/compare control 0
TA0CCTL0
02h
Timer0_A5 control
TA0CTL
00h
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03C0h
OFFSET
2Eh
00h
0340h
2Eh
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Table 8. Peripherals (continued)
MODULE NAME
Timer1_A3
Hardware
Multiplier
DMA Channel 2
DMA Channel 1
REGISTER DESCRIPTION
REGISTER
BASE
ADDRESS
Timer1_A3 interrupt vector
TA1IV
Timer1_A3 expansion register 0
TA1EX0
20h
Capture/compare register 2
TA1CCR2
16h
Capture/compare register 1
TA1CCR1
14h
Capture/compare register 0
TA1CCR0
12h
Timer1_A3 register
TA1R
10h
Capture/compare control 2
TA1CCTL2
06h
Capture/compare control 1
TA1CCTL1
04h
Capture/compare control 0
TA1CCTL0
02h
Timer1_A3 control
TA1CTL
MPY32 control register 0
MPY32CTL0
32 × 32 result 3 – most significant word
RES3
2Ah
32 × 32 result 2
RES2
28h
32 × 32 result 1
RES1
26h
32 × 32 result 0 – least significant word
RES0
24h
32-bit operand 2 – high word
OP2H
22h
32-bit operand 2 – low word
OP2L
20h
32-bit operand 1 – signed multiply accumulate high word
MACS32H
1Eh
32-bit operand 1 – signed multiply accumulate low word
MACS32L
1Ch
32-bit operand 1 – multiply accumulate high word
MAC32H
1Ah
32-bit operand 1 – multiply accumulate low word
MAC32L
18h
32-bit operand 1 – signed multiply high word
MPYS32H
16h
32-bit operand 1 – signed multiply low word
MPYS32L
14h
32-bit operand 1 – multiply high word
MPY32H
12h
32-bit operand 1 – multiply low word
MPY32L
10h
16 × 16 sum extension register
SUMEXT
0Eh
16 × 16 result high word
RESHI
0Ch
16 × 16 result low word
RESLO
0Ah
16-bit operand 2
OP2
08h
16-bit operand 1 – signed multiply accumulate
MACS
06h
16-bit operand 1 – multiply accumulate
MAC
04h
16-bit operand 1 – signed multiply
MPYS
02h
16-bit operand 1 – multiply
MPY
DMA channel 2 transfer size
DMA2SZ
DMA channel 2 destination address high
DMA2DAH
08h
DMA channel 2 destination address low
DMA2DAL
06h
DMA channel 2 source address high
DMA2SAH
04h
DMA channel 2 source address low
DMA2SAL
02h
DMA channel 2 control
DMA2CTL
00h
DMA channel 1 transfer size
DMA1SZ
DMA channel 1 destination address high
DMA1DAH
08h
DMA channel 1 destination address low
DMA1DAL
06h
DMA channel 1 source address high
DMA1SAH
04h
DMA channel 1 source address low
DMA1SAL
02h
DMA channel 1 control
DMA1CTL
00h
Copyright © 2008, Texas Instruments Incorporated
0380h
OFFSET
2Eh
00h
04C0h
2Ch
00h
0530h
0520h
0Ah
0Ah
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Table 8. Peripherals (continued)
MODULE NAME
DMA Channel 0
DMA
26
REGISTER DESCRIPTION
REGISTER
BASE
ADDRESS
DMA channel 0 transfer size
DMA0SZ
DMA channel 0 destination address high
DMA0DAH
08h
DMA channel 0 destination address low
DMA0DAL
06h
DMA channel 0 source address high
DMA0SAH
04h
DMA channel 0 source address low
DMA0SAL
02h
DMA channel 0 control
DMA0CTL
DMA interrupt vector
DMAIV
DMA module control 4
DMACTL4
08h
DMA module control 3
DMACTL3
06h
DMA module control 2
DMACTL2
04h
DMA module control 1
DMACTL1
02h
DMA module control 0
DMACTL0
00h
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0510h
OFFSET
0Ah
00h
0500h
0Eh
Copyright © 2008, Texas Instruments Incorporated
MSP430F543x, MSP430F541x
MSP430F543xA, MSP430F541xA
www.ti.com.......................................................................................................................................................................................... SLAS612 – SEPTEMBER 2008
Table 8. Peripherals (continued)
MODULE NAME
ADC12_A
REGISTER DESCRIPTION
REGISTER
BASE
ADDRESS
Conversion memory 15
ADC12MEM15
Conversion memory 14
ADC12MEM14
3Ch
Conversion memory 13
ADC12MEM13
3Ah
Conversion memory 12
ADC12MEM12
38h
Conversion memory 11
ADC12MEM11
36h
Conversion memory 10
ADC12MEM10
34h
Conversion memory 9
ADC12MEM9
32h
Conversion memory 8
ADC12MEM8
30h
Conversion memory 7
ADC12MEM7
2Eh
Conversion memory 6
ADC12MEM6
2Ch
Conversion memory 5
ADC12MEM5
2Ah
Conversion memory 4
ADC12MEM4
28h
Conversion memory 3
ADC12MEM3
26h
Conversion memory 2
ADC12MEM2
24h
Conversion memory 1
ADC12MEM1
22h
Conversion memory 0
ADC12MEM0
20h
ADC memory-control register 15
ADC12MCTL15
1Fh
ADC memory-control register 14
ADC12MCTL14
1Eh
ADC memory-control register 13
ADC12MCTL13
1Dh
ADC memory-control register 12
ADC12MCTL12
1Ch
ADC memory-control register 11
ADC12MCTL11
1Bh
ADC memory-control register 10
ADC12MCTL10
1Ah
ADC memory-control register 9
ADC12MCTL9
19h
ADC memory-control register 8
ADC12MCTL8
18h
ADC memory-control register 7
ADC12MCTL7
17h
ADC memory-control register 6
ADC12MCTL6
16h
ADC memory-control register 5
ADC12MCTL5
15h
ADC memory-control register 4
ADC12MCTL4
14h
ADC memory-control register 3
ADC12MCTL3
13h
ADC memory-control register 2
ADC12MCTL2
12h
ADC memory-control register 1
ADC12MCTL1
11h
ADC memory-control register 0
ADC12MCTL0
10h
Interrupt-vector-word register
ADC12IV
0Eh
Interrupt-enable register
ADC12IE
0Ch
Interrupt-enable register
ADC12IFG
0Ah
Control register 2
ADC12CTL2
04h
Control register 1
ADC12CTL1
02h
Control register 0
ADC12CTL0
00h
Copyright © 2008, Texas Instruments Incorporated
0700h
OFFSET
3Eh
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MSP430F543x, MSP430F541x
MSP430F543xA, MSP430F541xA
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Table 8. Peripherals (continued)
MODULE NAME
USCI0
28
REGISTER DESCRIPTION
REGISTER
BASE
ADDRESS
USCI interrupt vector word
UCB0IV
USCI interrupt flags
UCB0IFG
3Dh
USCI interrupt enable
UCB0IE
3Ch
USCI I2C slave address
UCB0I2CSA
32h
USCI I2C own address
UCB0I2COA
30h
USCI synchronous transmit buffer
UCB0TXBUF
2Eh
USCI synchronous receive buffer
UCB0RXBUF
2Ch
USCI synchronous status
UCB0STAT
2Ah
USCI I2C interrupt enable
UCB0I2CIE
28h
USCI synchronous bit rate 1
UCB0BR1
27h
USCI synchronous bit rate 0
UCB0BR0
26h
USCI synchronous control 1
UCB0CTL1
21h
USCI synchronous control 0
UCB0CTL0
20h
USCI interrupt vector word
UCA0IV
1Eh
USCI interrupt flags
UCA0IFG
1Dh
USCI interrupt enable
UCA0IE
1Ch
USCI IrDA receive control
UCA0IRRCTL
13h
USCI IrDA transmit control
UCA0IRTCTL
12h
USCI LIN control
UCA0ABCTL
10h
USCI transmit buffer
UCA0TXBUF
0Eh
USCI receive buffer
UCA0RXBUF
0Ch
USCI status
UCA0STAT
0Ah
USCI modulation control
UCA0MCTL
08h
USCI baud rate 1
UCA0BR1
07h
USCI baud rate 0
UCA0BR0
06h
USCI control 1
UCA0CTL0
01h
USCI control 0
UCA0CTL1
00h
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05C0h
OFFSET
3Eh
Copyright © 2008, Texas Instruments Incorporated
MSP430F543x, MSP430F541x
MSP430F543xA, MSP430F541xA
www.ti.com.......................................................................................................................................................................................... SLAS612 – SEPTEMBER 2008
Table 8. Peripherals (continued)
MODULE NAME
USCI1
REGISTER DESCRIPTION
REGISTER
BASE
ADDRESS
USCI interrupt vector word
UCB1IV
USCI interrupt flags
UCB1IFG
3Dh
USCI interrupt enable
UCB1IE
3Ch
USCI I2C slave address
UCB1I2CSA
32h
USCI I2C own address
UCB1I2COA
30h
USCI synchronous transmit buffer
UCB1TXBUF
2Eh
USCI synchronous receive buffer
UCB1RXBUF
2Ch
USCI synchronous status
UCB1STAT
2Ah
USCI I2C interrupt enable
UCB1I2CIE
28h
USCI synchronous bit rate 1
UCB1BR1
27h
USCI synchronous bit rate 0
UCB1BR0
26h
USCI synchronous control 1
UCB1CTL1
21h
USCI synchronous control 0
UCB1CTL0
20h
USCI interrupt vector word
UCA1IV
1Eh
USCI interrupt flags
UCA1IFG
1Dh
USCI interrupt enable
UCA1IE
1Ch
USCI IrDA receive control
UCA1IRRCTL
13h
USCI IrDA transmit control
UCA1IRTCTL
12h
USCI LIN control
UCA1ABCTL
10h
USCI transmit buffer
UCA1TXBUF
0Eh
USCI receive buffer
UCA1RXBUF
0Ch
USCI status
UCA1STAT
0Ah
USCI modulation control
UCA1MCTL
08h
USCI baud rate 1
UCA1BR1
07h
USCI baud rate 0
UCA1BR0
06h
USCI control 1
UCA1CTL0
01h
USCI control 0
UCA1CTL1
00h
Copyright © 2008, Texas Instruments Incorporated
0600h
OFFSET
3Eh
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MSP430F543x, MSP430F541x
MSP430F543xA, MSP430F541xA
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Table 8. Peripherals (continued)
MODULE NAME
USCI2
30
REGISTER DESCRIPTION
REGISTER
BASE
ADDRESS
USCI interrupt vector word
UCB2IV
USCI interrupt flags
UCB3IFG
3Dh
USCI interrupt enable
UCB2IE
3Ch
USCI I2C slave address
UCB2I2CSA
32h
USCI I2C own address
UCB2I2COA
30h
USCI synchronous transmit buffer
UCB2TXBUF
2Eh
USCI synchronous receive buffer
UCB2RXBUF
2Ch
USCI synchronous status
UCB2STAT
2Ah
USCI I2C interrupt enable
UCB2I2CIE
28h
USCI synchronous bit rate 1
UCB2BR1
27h
USCI synchronous bit rate 0
UCB2BR0
26h
USCI synchronous control 1
UCB2CTL1
21h
USCI synchronous control 0
UCB2CTL0
20h
USCI interrupt vector word
UCA2IV
1Eh
USCI interrupt flags
UCA2IFG
1Dh
USCI interrupt enable
UCA2IE
1Ch
USCI IrDA receive control
UCA2IRRCTL
13h
USCI IrDA transmit control
UCA2IRTCTL
12h
USCI LIN control
UCA2ABCTL
10h
USCI transmit buffer
UCA2TXBUF
0Eh
USCI receive buffer
UCA2RXBUF
0Ch
USCI status
UCA2STAT
0Ah
USCI modulation control
UCA2MCTL
08h
USCI baud rate 1
UCA2BR1
07h
USCI baud rate 0
UCA2BR0
06h
USCI control 1
UCA2CTL0
01h
USCI control 0
UCA2CTL1
00h
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0640h
OFFSET
3Eh
Copyright © 2008, Texas Instruments Incorporated
MSP430F543x, MSP430F541x
MSP430F543xA, MSP430F541xA
www.ti.com.......................................................................................................................................................................................... SLAS612 – SEPTEMBER 2008
Table 8. Peripherals (continued)
MODULE NAME
USCI3
REGISTER DESCRIPTION
REGISTER
BASE
ADDRESS
USCI interrupt vector word
UCB3IV
USCI interrupt flags
UCB3IFG
3Dh
USCI interrupt enable
UCB3IE
3Ch
USCI I2C slave address
UCB3I2CSA
32h
USCI I2C own address
UCB3I2COA
30h
USCI synchronous transmit buffer
UCB3TXBUF
2Eh
USCI synchronous receive buffer
UCB3RXBUF
2Ch
USCI synchronous status
UCB3STAT
2Ah
USCI I2C interrupt enable
UCB3I2CIE
28h
USCI synchronous bit rate 1
UCB3BR1
27h
USCI synchronous bit rate 0
UCB3BR0
26h
USCI synchronous control 1
UCB3CTL1
21h
USCI synchronous control 0
UCB3CTL0
20h
USCI interrupt vector word
UCA3IV
1Eh
USCI interrupt flags
UCA3IFG
1Dh
USCI interrupt enable
UCA3IE
1Ch
USCI IrDA receive control
UCA3IRRCTL
13h
USCI IrDA transmit control
UCA3IRTCTL
12h
USCI LIN control
UCA3ABCTL
10h
USCI transmit buffer
UCA3TXBUF
0Eh
USCI receive buffer
UCA3RXBUF
0Ch
USCI status
UCA3STAT
0Ah
USCI modulation control
UCA3MCTL
08h
USCI baud rate 1
UCA3BR1
07h
USCI baud rate 0
UCA3BR0
06h
USCI control 1
UCA3CTL0
01h
USCI control 0
UCA3CTL1
00h
Copyright © 2008, Texas Instruments Incorporated
0680h
OFFSET
3Eh
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MSP430F543x, MSP430F541x
MSP430F543xA, MSP430F541xA
SLAS612 – SEPTEMBER 2008.......................................................................................................................................................................................... www.ti.com
Table 8. Peripherals (continued)
MODULE NAME
RTC_A
Port P11
Port P10
Port P9
Port P8
32
REGISTER DESCRIPTION
REGISTER
BASE
ADDRESS
RTC alarm days
RTCADAY
RTC alarm day of week
RTCADOW
1Ah
RTC alarm hours
RTCAHOUR
19h
RTC alarm minutes
RTCAMIN
18h
RTC year high
RTCYEARH
17h
RTC year low
RTCYEARL
16h
RTC month
RTCMON
15h
RTC days
RTCDAY
14h
RTC day of week/counter register 4
RTCDOW/RTCNT4
13h
RTC hours/counter register 3
RTCHOUR/RTCNT3
12h
RTC minutes/counter register 2
RTCMIN/RTCNT2
11h
RTC seconds/counter register 1
RTCSEC/RTCNT1
10h
RTC interrupt vector word
RTCIV
0Eh
RTC prescaler 1
RTCPS1
0Dh
RTC prescaler 0
RTCPS0
0Ch
RTC prescaler 1 control
RTCPS1CTL
0Ah
RTC prescaler 0 control
RTCPS0CTL
08h
RTC control 3
RTCCTL3
03h
RTC control 2
RTCCTL2
02h
RTC control 1
RTCCTL1
01h
RTC control 0
RTCCTL0
Port P11 selection
P11SEL
Port P11 drive strength
P11DS
08h
Port P11 pullup/pulldown enable
P11REN
06h
Port P11 direction
P11DIR
04h
Port P11 output
P11OUT
02h
Port P11 input
P11IN
Port P10 selection
P10SEL
Port P10 drive strength
P10DS
09h
Port P10 pullup/pulldown enable
P10REN
07h
Port P10 direction
P10DIR
05h
Port P10 output
P10OUT
03h
Port P10 input
P10IN
Port P9 selection
P9SEL
Port P9 drive strength
P9DS
08h
Port P9 pullup/pulldown enable
P9REN
06h
Port P9 direction
P9DIR
04h
Port P9 output
P9OUT
02h
Port P9 input
P9IN
00h
Port P8 selection
P8SEL
Port P8 drive strength
P8DS
09h
Port P8 pullup/pulldown enable
P8REN
07h
Port P8 direction
P8DIR
05h
Port P8 output
P8OUT
03h
Port P8 input
P8IN
01h
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04A0h
OFFSET
1Bh
00h
02A0h
0Ah
00h
0280h
0Bh
01h
0280h
0260h
0Ah
0Bh
Copyright © 2008, Texas Instruments Incorporated
MSP430F543x, MSP430F541x
MSP430F543xA, MSP430F541xA
www.ti.com.......................................................................................................................................................................................... SLAS612 – SEPTEMBER 2008
Table 8. Peripherals (continued)
MODULE NAME
Port P7
Port P6
Port P5
Port P4
Port P3
Port P2
REGISTER DESCRIPTION
REGISTER
BASE
ADDRESS
Port P7 selection
P7SEL
Port P7 drive strength
P7DS
08h
Port P7 pullup/pulldown enable
P7REN
06h
Port P7 direction
P7DIR
04h
Port P7 output
P7OUT
02h
Port P7 input
P7IN
Port P6 selection
P6SEL
Port P6 drive strength
P6DS
09h
Port P6 pullup/pulldown enable
P6REN
07h
Port P6 direction
P6DIR
05h
Port P6 output
P6OUT
03h
Port P6 input
P6IN
01h
Port P5 selection
P5SEL
Port P5 drive strength
P5DS
08h
Port P5 pullup/pulldown enable
P5REN
06h
Port P5 direction
P5DIR
04h
Port P5 output
P5OUT
02h
Port P5 input
P5IN
Port P4 selection
P4SEL
Port P4 drive strength
P4DS
09h
Port P4 pullup/pulldown enable
P4REN
07h
Port P4 direction
P4DIR
05h
Port P4 output
P4OUT
03h
Port P4 input
P4IN
Port P3 selection
P3SEL
Port P3 drive strength
P3DS
08h
Port P3 pullup/pulldown enable
P3REN
06h
Port P3 direction
P3DIR
04h
Port P3 output
P3OUT
02h
Port P3 input
P3IN
Port P2 interrupt flag
P2IFG
Port P2 interrupt enable
P2IE
1Bh
Port P2 interrupt edge select
P2IES
19h
Port P2 interrupt vector word
P2IV
1Eh
Port P2 selection
P2SEL
0Bh
Port P2 drive strength
P2DS
09h
Port P2 pullup/pulldown enable
P2REN
07h
Port P2 direction
P2DIR
05h
Port P2 output
P2OUT
03h
Port P2 input
P2IN
01h
Copyright © 2008, Texas Instruments Incorporated
0260h
OFFSET
0Ah
00h
0240h
0240h
0Bh
0Ah
00h
0220h
0Bh
01h
0220h
0Ah
00h
0200h
1Dh
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MSP430F543x, MSP430F541x
MSP430F543xA, MSP430F541xA
SLAS612 – SEPTEMBER 2008.......................................................................................................................................................................................... www.ti.com
Table 8. Peripherals (continued)
MODULE NAME
Port P1
REGISTER DESCRIPTION
REGISTER
BASE
ADDRESS
Port P1 interrupt flag
P1IFG
Port P1 interrupt enable
P1IE
1Ah
Port P1 interrupt edge select
P1IES
18h
Port P1 interrupt vector word
P1IV
0Eh
Port P1 selection
P1SEL
0Ah
Port P1 drive strength
P1DS
08h
Port P1 pullup/pulldown enable
P1REN
06h
Port P1 direction
P1DIR
04h
Port P1 output
P1OUT
02h
Port P1 input
P1IN
Port PJ drive strength
PJDS
Port PJ pullup/pulldown enable
PJREN
06h
Port PJ direction
PJDIR
04h
Port PJ output
PJOUT
02h
Port PJ input
PJIN
00h
Reset vector generator
SYSRSTIV
System NMI vector generator
SYSSNIV
1Ch
User NMI vector generator
SYSUNIV
1Ah
JTAG mailbox output 1
SYSJMBO1
0Eh
JTAG mailbox output 0
SYSJMBO0
0Ch
JTAG mailbox input 1
SYSJMBI1
0Ah
JTAG mailbox input 0
SYSJMBI0
08h
JTAG mailbox control
SYSJMBC
06h
Bootstrap configuration area
SYSBSLC
02h
System control
SYSCTL
00h
UCS control 8
UCSCTL8
UCS control 7
UCSCTL7
0Eh
UCS control 6
UCSCTL6
0Ch
UCS control 5
UCSCTL5
0Ah
UCS control 4
UCSCTL4
08h
UCS control 3
UCSCTL3
06h
UCS control 2
UCSCTL2
04h
UCS control 1
UCSCTL1
02h
UCS control 0
UCSCTL0
WDT_A
Watchdog timer control
WDTCTL
0150h
0Ch
RAM Control
RAM control 0
RCCTL0
0150h
08h
CRC16
CRC result
CRC16INIRES
0150h
04h
CRC data input
CRC16DI
Flash control 4
FCTL4
Flash control 3
FCTL3
04h
Flash control 1
FCTL1
00h
Port PJ
SYS
UCS
Flash Control
34
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0200h
OFFSET
1Ch
00h
0320h
0180h
0160h
08h
1Eh
10h
00h
00h
0140h
06h
Copyright © 2008, Texas Instruments Incorporated
MSP430F543x, MSP430F541x
MSP430F543xA, MSP430F541xA
www.ti.com.......................................................................................................................................................................................... SLAS612 – SEPTEMBER 2008
Table 8. Peripherals (continued)
MODULE NAME
PMM
REGISTER DESCRIPTION
REGISTER
BASE
ADDRESS
PMM interrupt enable
PMMIE
PMM interrupt flags
PMMIFG
0Ch
SVS low side control
SVSMLCTL
06h
SVS high side control
SVSMHCTL
04h
PMM control 1
PMMCTL1
02h
PMM control 0
PMMCTL0
Special Functions SFR reset pin control
SFRRPCR
0120h
OFFSET
0Eh
00h
0100h
04h
SFR interrupt flag
SFRIFG1
02h
SFR interrupt enable
SFRIE1
00h
Copyright © 2008, Texas Instruments Incorporated
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MSP430F543x, MSP430F541x
MSP430F543xA, MSP430F541xA
SLAS612 – SEPTEMBER 2008.......................................................................................................................................................................................... www.ti.com
Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
Voltage applied at VCC to VSS
–0.3 V to 4.1 V
Voltage applied to any pin (excluding VCORE) (2)
–0.3 V to VCC + 0.3 V
Diode current at any device pin
Storage temperature range, Tstg
(1)
(2)
(3)
±2 mA
Unprogrammed device
(3)
–55°C to 150°C
Programmed device (3)
–40°C to 105°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages referenced to VSS. VCORE is for internal device usage only. No external DC loading or voltage should be applied.
Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow
temperatures not higher than classified on the device label on the shipping boxes or reels.
Recommended Operating Conditions
MIN NOM MAX UNIT
Supply voltage during program execution and
flash programming
(AVCC = DVCC1/2/3/4 = DVCC) (1)
VCC
VSS
Supply voltage (AVSS = DVSS1/2/3/4 = DVSS)
TA
Operating free-air temperature
CVCORE
Capacitor at VCORE
'F5438A, 'F5436A, 'F5419A
'F5437A, 'F5435A, 'F5418A
(A versions only)
1.8
3.6
V
'F5438, 'F5436, 'F5419
'F5437, 'F5435, 'F5418
2.2
3.6
V
85
°C
0
–40
470
CDVCC/C
Capacitor ratio of DVCC to VCORE
VCORE
fSYSTEM
Processor frequency (maximum MCLK
frequency) (2) (3) (see Figure 1)
(2)
(3)
36
nF
10
PMMCOREVx = 0,
1.8 V ≤ VCC ≤ 3.6 V
'F5438A, 'F5436A,
'F5419A
'F5437A, 'F5435A,
'F5418A
(A versions only)
0
12.0
PMMCOREVx = 1,
2.0 V ≤ VCC ≤ 3.6 V
'F5438A, 'F5436A,
'F5419A
'F5437A, 'F5435A,
'F5418A
(A versions only)
0
16.0
'F5438, 'F5436, 'F5419
'F5437, 'F5435, 'F5418
0
18.0
'F5438A, 'F5436A,
'F5419A
'F5437A, 'F5435A,
'F5418A
(A versions only)
0
25.0
PMMCOREVx = 2,
2.2 V ≤ VCC ≤ 3.6 V
(1)
V
MHz
It is recommended to power AVCC and DVCC from the same source. A maximum difference of 0.3 V between AVCC and DVCC can be
tolerated during power up and operation.
The MSP430 CPU is clocked directly with MCLK. Both the high and low phase of MCLK must not exceed the pulse width of the
specified maximum frequency.
Modules may have a different maximum input clock specification. Refer to the specification of the respective module in this data sheet.
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MSP430F543x, MSP430F541x
MSP430F543xA, MSP430F541xA
www.ti.com.......................................................................................................................................................................................... SLAS612 – SEPTEMBER 2008
System Frequency – MHz
Legend
25 MHz
}
18 MHz
A versions only
16 MHz
PMMCOREVx = 2
All versions.
PMMCOREVx = 1
A versions only.
12 MHz
PMMCOREVx = 0
A versions only.
1.8 V 2.0 V 2.2 V
3.6 V
Supply Voltage – V
Figure 1. Frequency vs Supply Voltage
Copyright © 2008, Texas Instruments Incorporated
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MSP430F543x, MSP430F541x
MSP430F543xA, MSP430F541xA
SLAS612 – SEPTEMBER 2008.......................................................................................................................................................................................... www.ti.com
Electrical Characteristics
Active Mode Supply Current Into VCC Excluding External Current
over recommended operating free-air temperature (unless otherwise noted) (1) (2) (3)
PARAMETER
TEST CONDITIONS
TA
PMMCOREVx = 0,
VCC = 3 V
A versions only
PMMCOREVx = 1,
fDCO = fMCLK = fSMCLK = 1 MHz,
VCC = 3 V
fACLK = 32768 Hz
A versions only
Program executes in flash,
XTS = 0, CPUOFF = 0, SCG0 = 0, SCG1 = 0, PMMCOREVx = 2,
OSCOFF = 0
VCC = 3 V
A versions only
IAM, 1MHz
IAM, 16MHz
IAM, 25MHz
A versions only
(1)
(2)
(3)
38
mA
0.28
0.70
0.45
0.80
–40°C to 85°C
mA
0.90
PMMCOREVx = 2,
VCC = 3 V
1.27
PMMCOREVx = 0,
VCC = 3 V
A versions only
1.32
1.47
1.55
–40°C to 85°C
mA
1.75
PMMCOREVx = 2,
VCC = 3 V
2.50
PMMCOREVx = 1,
VCC = 3 V
A versions only
3.00
fDCO = fMCLK = fSMCLK = 25 MHz,
fACLK = 32768 Hz
PMMCOREVx = 2,
Program executes in flash,
VCC = 3 V
XTS = 0, CPUOFF = 0, SCG0 = 0, SCG1 = 0, A versions only
OSCOFF = 0
UNIT
0.25
–40°C to 85°C
PMMCOREVx = 0,
VCC = 3 V
A versions only
fDCO = fMCLK = fSMCLK = 16 MHz,
fACLK = 32768 Hz
PMMCOREVx = 2,
Program executes in flash,
VCC = 3 V
XTS = 0, CPUOFF = 0, SCG0 = 0, SCG1 = 0,
A versions only
OSCOFF = 0
PMMCOREVx = 2,
VCC = 3 V
MAX
0.22
0.37
PMMCOREVx = 1,
fDCO = fMCLK = fSMCLK = 8 MHz,
VCC = 3 V
fACLK = 32768 Hz
A versions only
Program executes in flash,
XTS = 0, CPUOFF = 0, SCG0 = 0, SCG1 = 0, PMMCOREVx = 2,
OSCOFF = 0
VCC = 3 V
A versions only
IAM, 8MHz
TYP
PMMCOREVx = 2,
VCC = 3 V
PMMCOREVx = 1,
fDCO = fMCLK = fSMCLK = 4 MHz,
VCC = 3 V
fACLK = 32768 Hz
A versions only
Program executes in flash,
XTS = 0, CPUOFF = 0, SCG0 = 0, SCG1 = 0, PMMCOREVx = 2,
OSCOFF = 0
VCC = 3 V
A versions only
IAM, 4MHz
MIN
–40°C to 85°C
mA
3.40
5.00
–40°C to 85°C
2.84
5.65
5.56
mA
All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF. The internal and external
load capacitance are chosen to closely match the required 9 pF.
Non-A versions characterized with program executing worst case JMP $. A-versions characterized with program executing typical data
processing.
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MSP430F543x, MSP430F541x
MSP430F543xA, MSP430F541xA
www.ti.com.......................................................................................................................................................................................... SLAS612 – SEPTEMBER 2008
Active Mode Supply Current Into VCC Excluding External Current (continued)
over recommended operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
PMMCOREVx = 0,
VCC = 3 V
A versions only
IAM, 1MHz
fDCO = fMCLK = fSMCLK = 1 MHz,
fACLK = 32768 Hz
PMMCOREVx = 1,
Program executes in RAM,
VCC = 3 V
XTS = 0, CPUOFF = 0, SCG0 = 0, SCG1 = 0, A versions only
OSCOFF = 0
PMMCOREVx = 2,
VCC = 3 V
All versions
IAM, 4MHz
–40°C to 85°C
IAM, 8MHz
IAM, 16MHz
IAM, 25MHz
A versions only
UNIT
mA
0.29
0.49
–40°C to 85°C
0.56
0.60
mA
0.72
0.95
–40°C to 85°C
1.10
1.12
PMMCOREVx = 1,
fDCO = fMCLK = fSMCLK = 16 MHz,
VCC = 3 V
fACLK = 32768 Hz
A versions only
Program executes in RAM,
XTS = 0, CPUOFF = 0, SCG0 = 0, SCG1 = 0, PMMCOREVx = 2,
VCC = 3 V
OSCOFF = 0
All versions
–40°C to 85°C
fDCO = fMCLK = fSMCLK = 25 MHz,
fACLK = 32768 Hz
PMMCOREVx = 2,
Program executes in RAM,
VCC = 3 V
XTS = 0, CPUOFF = 0, SCG0 = 0, SCG1 = 0, A versions only
OSCOFF = 0
–40°C to 85°C
Copyright © 2008, Texas Instruments Incorporated
MAX
0.19
0.20
PMMCOREVx = 0,
VCC = 3 V
A versions only
fDCO = fMCLK = fSMCLK = 8 MHz,
fACLK = 32768 Hz
PMMCOREVx = 1,
Program executes in RAM,
VCC = 3 V
XTS = 0, CPUOFF = 0, SCG0 = 0, SCG1 = 0, A versions only
OSCOFF = 0
PMMCOREVx = 2,
VCC = 3 V
All versions
TYP
0.17
PMMCOREVx = 0,
VCC = 3 V
A versions only
fDCO = fMCLK = fSMCLK = 4 MHz,
fACLK = 32768 Hz
PMMCOREVx = 1,
Program executes in RAM,
VCC = 3 V
XTS = 0, CPUOFF = 0, SCG0 = 0, SCG1 = 0, A versions only
OSCOFF = 0
PMMCOREVx = 2,
VCC = 3 V
All versions
MIN
mA
1.27
2.10
mA
2.20
2.60
3.95
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mA
39
MSP430F543x, MSP430F541x
MSP430F543xA, MSP430F541xA
SLAS612 – SEPTEMBER 2008.......................................................................................................................................................................................... www.ti.com
Low-Power Mode Supply Currents (Into VCC) Excluding External Current
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) (2)
PARAMETER
ILPM0,1MHz
ILPM2
TEST CONDITIONS
Low-power
mode 0 (LPM0)
current (3)
fMCLK = 0 MHz,
fSMCLK = fDCO = 1 MHz,
fACLK = 32768 Hz,
CPUOFF = 1, SCG0 = 0, SCG1 = 0,
OSCOFF = 0
VCC = 2.2 V,
PMMCOREVx = 0
A versions only
Low-power
mode 2 (LPM2)
current (4)
fMCLK = fSMCLK = 0 MHz,
fDCO = 1 MHz,
fACLK = 32768 Hz,
CPUOFF = 1, SCG0 = 0, SCG1 = 1,
OSCOFF = 0, XTS = 0
VCC = 2.2 V,
PMMCOREVx = 0
A versions only
VCC = 3 V,
PMMCOREVx = 2
VCC = 3 V,
PMMCOREVx = 2
VCC = 3 V,
PMMCOREVx = 0
A versions only
ILPM3,XT1LF
Low-power
mode 3 (LPM3)
current,
XT1 LF mode (4)
fDCO = fMCLK = fSMCLK = 0 MHz,
fACLK = 32768 Hz,
OSOCOFF = 0,
CPUOFF = 1,
SCG0 = 1, SCG1 = 1,
XTS = 0, XT1DRIVEx = 0,
SELAx = 0,
SVMH, SVSH off,
SVML, SVSL off,
RAM retention enabled
VCC = 3 V,
PMMCOREVx = 1
A versions only
VCC = 3 V,
PMMCOREVx = 2
A versions only
VCC = 3 V,
PMMCOREVx = 2
VCC = 3 V,
PMMCOREVx = 0
A versions only
ILPM3,VLO
Low-power
mode 3 (LPM3)
current,
VLO mode (5)
fDCO = fMCLK = fSMCLK = 0 MHz,
fACLK = VLO, OSOCOFF = 0,
CPUOFF = 1,
SCG0 = 1, SCG1 = 1,
SELAx = 1,
SVMH, SVSH off,
SVML, SVSL off,
RAM retention enabled
VCC = 3 V,
PMMCOREVx = 1
A versions only
VCC = 3 V,
PMMCOREVx = 2
A versions only
VCC = 3 V,
PMMCOREVx = 2
(1)
(2)
(3)
(4)
(5)
40
TA
–40°C to
85°C
MIN
TYP
UNIT
81
µA
86
–40°C to
85°C
MAX
98
7.2
µA
8.0
–40°C
1.4
25°C
1.6
55°C
2.6
85°C
4.6
–40°C
1.5
25°C
1.8
55°C
2.9
85°C
5.1
–40°C
1.7
25°C
2.0
55°C
3.3
85°C
5.8
–40°C
2.31
25°C
2.60
55°C
4.5
85°C
7.9
–40°C
1.0
25°C
1.1
55°C
1.8
85°C
3.2
–40°C
1.1
25°C
1.3
55°C
2.1
85°C
3.7
–40°C
1.3
25°C
1.5
55°C
2.5
85°C
4.4
–40°C
1.39
25°C
1.80
55°C
2.95
85°C
6.9
15.6
µA
3.37
15.6
µA
2.30
14.6
All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF. The internal and external
load capacitance are chosen to closely match the required 9 pF.
Current for brownout and WDT clocked by SMCLK included.
Current for brownout, WDT and RTC clocked by ACLK included.
For this condition, the VLO must be selected as the source for ACLK, MCLK, and SMCLK otherwise additional current will be drawn due
to the REFO oscillator. Current for brownout, WDT and RTC clocked by ACLK included.
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MSP430F543x, MSP430F541x
MSP430F543xA, MSP430F541xA
www.ti.com.......................................................................................................................................................................................... SLAS612 – SEPTEMBER 2008
Low-Power Mode Supply Currents (Into VCC) Excluding External Current (continued)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC = 3 V,
PMMCOREVx = 0
A versions only
ILPM4
Low-power
mode 4 (LPM4)
current (6)
VCC = 3 V,
PMMCOREVx = 1
A versions only
fDCO = fMCLK = fSMCLK = 0 MHz,
fACLK = 0 Hz,
OSOCOFF = 1,
CPUOFF = 1,
SCG0 = 1, SCG1 = 1,
SVMH, SVSH off,
SVML, SVSL off,
RAM retention enabled
VCC = 3 V,
PMMCOREVx = 2
A versions only
VCC = 3 V,
PMMCOREVx = 2
ILPM5
(6)
(7)
Low-power
mode 5 (LPM5)
current (7)
fDCO = fMCLK = fSMCLK = 0 MHz,
fACLK = 0 Hz,
PMMREGOFF = 1
VCC = 3 V
A versions only
TA
MIN
TYP
–40°C
0.9
25°C
1.0
55°C
1.7
85°C
3.1
–40°C
1.0
25°C
1.2
55°C
2.0
85°C
3.6
–40°C
1.2
25°C
1.4
55°C
2.4
85°C
4.3
–40°C
1.26
25°C
1.69
55°C
3.6
85°C
6.8
–40°C
0.1
25°C
0.1
55°C
0.2
85°C
0.5
MAX
UNIT
µA
2.2
µA
14.5
µA
Current for brownout included.
Internal regulator disabled. No data retention.
Schmitt-Trigger Inputs – General Purpose I/O
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VIT+
Positive-going input threshold voltage
VIT–
Negative-going input threshold voltage
Vhys
Input voltage hysteresis (VIT+ – VIT–)
RPull
Pullup/pulldown resistor
For pullup: VIN = VSS
For pulldown: VIN = VCC
CI
Input capacitance
VIN = VSS or VCC
VCC
MIN
1.8 V
0.80
1.40
3V
1.50
2.10
1.8 V
0.45
1.00
3V
0.75
1.65
1.8 V
0.3
0.8
3V
0.4
1.0
20
TYP
35
MAX
50
5
UNIT
V
V
V
kΩ
pF
Inputs – Ports P1 and P2 (1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
t(int)
(1)
(2)
External interrupt timing
(2)
TEST CONDITIONS
VCC
Port P1, P2: P1.x to P2.x, External trigger pulse width to
set interrupt flag
2.2 V/3 V
MIN
MAX
20
UNIT
ns
Some devices may contain additional ports with interrupts. See the block diagram and terminal function descriptions.
An external signal sets the interrupt flag every time the minimum interrupt pulse width t(int) is met. It may be set by trigger signals shorter
than t(int).
Copyright © 2008, Texas Instruments Incorporated
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41
MSP430F543x, MSP430F541x
MSP430F543xA, MSP430F541xA
SLAS612 – SEPTEMBER 2008.......................................................................................................................................................................................... www.ti.com
Leakage Current – General Purpose I/O
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
Ilkg(Px.x)
(1)
(2)
TEST CONDITIONS
VCC
(1) (2)
High-impedance leakage current
MIN
1.8 V/3 V
MAX
UNIT
±50
nA
The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted.
The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup/pulldown resistor is
disabled.
Outputs – General Purpose I/O (Full Drive Strength)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
I(OHmax) = –3 mA (1)
VOH
High-level output voltage
I(OHmax) = –10 mA (2)
I(OHmax) = –5 mA
I(OLmax) = 3 mA (1)
Low-level output voltage
I(OLmax) = 10 mA (2)
I(OLmax) = 5 mA (1)
I(OLmax) = 15 mA (2)
(1)
(2)
1.8 V
(1)
I(OHmax) = –15 mA (2)
VOL
VCC
3V
1.8 V
3V
MIN
MAX
VCC – 0.25
VCC
VCC – 0.60
VCC
VCC – 0.25
VCC
VCC – 0.60
VCC
UNIT
V
VSS VSS + 0.25
VSS VSS + 0.60
VSS VSS + 0.25
V
VSS VSS + 0.60
The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed ±48 mA to hold the maximum voltage drop
specified.
The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed ±100 mA to hold the maximum voltage
drop specified.
Outputs – General Purpose I/O (Reduced Drive Strength)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
PARAMETER
TEST CONDITIONS
I(OHmax) = –1 mA (2)
VOH
High-level output voltage
I(OHmax) = –3 mA (3)
I(OHmax) = –2 mA (2)
I(OHmax) = –6 mA (3)
I(OLmax) = 1 mA
VOL
Low-level output voltage
(3)
42
1.8 V
3.0 V
(2)
I(OLmax) = 3 mA (3)
I(OLmax) = 2 mA (2)
I(OLmax) = 6 mA (3)
(1)
(2)
VCC
1.8 V
3.0 V
MIN
MAX
VCC – 0.25
VCC
VCC – 0.60
VCC
VCC – 0.25
VCC
VCC – 0.60
VCC
UNIT
V
VSS VSS + 0.25
VSS VSS + 0.60
VSS VSS + 0.25
V
VSS VSS + 0.60
Selecting reduced drive strength may reduce EMI.
The maximum total current, I(OHmax) and I(OLmax), for all outputs combined, should not exceed ±48 mA to hold the maximum voltage drop
specified.
The maximum total current, I(OHmax) and I(OLmax), for all outputs combined, should not exceed ±100 mA to hold the maximum voltage
drop specified.
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MSP430F543x, MSP430F541x
MSP430F543xA, MSP430F541xA
www.ti.com.......................................................................................................................................................................................... SLAS612 – SEPTEMBER 2008
Output Frequency – General Purpose I/O
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
Port output frequency
(with load)
fPx.y
fPort_CLK
(1)
(2)
Clock output frequency
TEST CONDITIONS
P1.6/SMCLK
(1) (2)
P1.0/TA0CLK/ACLK
P1.6/SMCLK
P2.0/TA1CLK/MCLK
CL = 20 pF (2)
MIN
MAX
VCC = 1.8 V
PMMCOREVx = 0
16
VCC = 3 V
PMMCOREVx = 2
25
VCC = 1.8 V
PMMCOREVx = 0
16
VCC = 3 V
PMMCOREVx = 2
25
UNIT
MHz
MHz
A resistive divider with 2 × R1 between VCC and VSS is used as load. The output is connected to the center tap of the divider. For full
drive strength, R1 = 550 Ω. For reduced drive strength, R1 = 1.6 kΩ. CL = 20 pF is connected to the output to VSS.
The output voltage reaches at least 10% and 90% VCC at the specified toggle frequency.
Copyright © 2008, Texas Instruments Incorporated
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MSP430F543x, MSP430F541x
MSP430F543xA, MSP430F541xA
SLAS612 – SEPTEMBER 2008.......................................................................................................................................................................................... www.ti.com
Typical Characteristics – Outputs, Reduced Drive Strength (PxDS.y = 0)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
TYPICAL LOW-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
TYPICAL LOW-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
8.0
VCC = 3.0 V
Px.y
IOL – Typical Low-Level Output Current – mA
IOL – Typical Low-Level Output Current – mA
25.0
TA = 25°C
20.0
TA = 85°C
15.0
10.0
5.0
0.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
TA = 85°C
6.0
5.0
4.0
3.0
2.0
1.0
0.0
0.0
3.5
TYPICAL HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
TYPICAL HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
2.0
0.0
VCC = 3.0 V
Px.y
IOH – Typical High-Level Output Current – mA
IOH – Typical High-Level Output Current – mA
1.5
Figure 3.
-5.0
-10.0
TA = 85°C
TA = 25°C
VCC = 1.8 V
Px.y
-1.0
-2.0
-3.0
-4.0
TA = 85°C
-5.0
-6.0
TA = 25°C
-7.0
-8.0
-25.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
VOH – High-Level Output Voltage – V
Figure 4.
44
1.0
Figure 2.
0.0
-20.0
0.5
VOL – Low-Level Output Voltage – V
VOL – Low-Level Output Voltage – V
-15.0
TA = 25°C
VCC = 1.8 V
Px.y
7.0
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3.5
0.0
0.5
1.0
1.5
VOH – High-Level Output Voltage – V
2.0
Figure 5.
Copyright © 2008, Texas Instruments Incorporated
MSP430F543x, MSP430F541x
MSP430F543xA, MSP430F541xA
www.ti.com.......................................................................................................................................................................................... SLAS612 – SEPTEMBER 2008
Typical Characteristics – Outputs, Full Drive Strength (PxDS.y = 1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
TYPICAL LOW-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
TA = 25°C
VCC = 3.0 V
Px.y
55.0
50.0
IOL – Typical Low-Level Output Current – mA
IOL – Typical Low-Level Output Current – mA
60.0
TYPICAL LOW-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
TA = 85°C
45.0
40.0
35.0
30.0
25.0
20.0
15.0
10.0
5.0
0.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
24
VCC = 1.8 V
Px.y
TA = 85°C
16
12
8
4
0
0.0
3.5
TYPICAL HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
TYPICAL HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
IOH – Typical High-Level Output Current – mA
IOH – Typical High-Level Output Current – mA
2.0
0
-10.0
-15.0
-20.0
-25.0
-30.0
-35.0
-40.0
-45.0
TA = 85°C
-55.0
TA = 25°C
0.0
1.5
Figure 7.
VCC = 3.0 V
Px.y
-60.0
1.0
Figure 6.
0.0
-50.0
0.5
VOL – Low-Level Output Voltage – V
VOL – Low-Level Output Voltage – V
-5.0
TA = 25°C
20
0.5
VCC = 1.8 V
Px.y
-4
-8
-12
TA = 85°C
-16
TA = 25°C
-20
1.0
1.5
2.0
2.5
3.0
VOH – High-Level Output Voltage – V
Figure 8.
Copyright © 2008, Texas Instruments Incorporated
3.5
0.0
0.5
1.0
1.5
2.0
VOH – High-Level Output Voltage – V
Figure 9.
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45
MSP430F543x, MSP430F541x
MSP430F543xA, MSP430F541xA
SLAS612 – SEPTEMBER 2008.......................................................................................................................................................................................... www.ti.com
Crystal Oscillator, XT1, Low-Frequency Mode (1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
fOSC = 32768 Hz, XTS = 0,
XT1BYPASS = 0, XT1DRIVEx = 1,
TA = 25°C
ΔIDVCC.LF
Differential XT1 oscillator crystal
current consumption from lowest
drive setting, LF mode
fOSC = 32768 Hz, XTS = 0,
XT1BYPASS = 0, XT1DRIVEx = 2,
TA = 25°C
fXT1,LF,SW
XT1 oscillator logic-level
square-wave input frequency,
LF mode
XTS = 0, XT1BYPASS = 1 (2) (3)
10
Integrated effective load
capacitance, LF mode (5)
32.768
XTS = 0,
XT1BYPASS = 0, XT1DRIVEx = 0,
fXT1,LF = 32768 Hz, CL,eff = 6 pF
210
XTS = 0,
XT1BYPASS = 0, XT1DRIVEx = 1,
fXT1,LF = 32768 Hz, CL,eff = 12 pF
300
Hz
50
kHz
kΩ
XTS = 0, XCAPx = 0 (6)
CL,eff
UNIT
µA
0.170
32768
XTS = 0, XT1BYPASS = 0
OALF
3.0 V
0.290
XT1 oscillator crystal frequency,
LF mode
MAX
0.075
fOSC = 32768 Hz, XTS = 0,
XT1BYPASS = 0, XT1DRIVEx = 3,
TA = 25°C
fXT1,LF0
Oscillation allowance for
LF crystals (4)
TYP
2
XTS = 0, XCAPx = 1
5.5
XTS = 0, XCAPx = 2
8.5
XTS = 0, XCAPx = 3
12.0
pF
Duty cycle
LF mode
XTS = 0, Measured at ACLK,
fXT1,LF = 32768 Hz
30
70
%
fFault,LF
Oscillator fault frequency,
LF mode (7)
XTS = 0 (8)
10
10000
Hz
tSTART,LF
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
46
Startup time, LF mode
fOSC = 32768 Hz, XTS = 0,
XT1BYPASS = 0, XT1DRIVEx = 0,
TA = 25°C,
CL,eff = 12 pF
fOSC = 32768 Hz, XTS = 0,
XT1BYPASS = 0, XT1DRIVEx = 3,
TA = 25°C,
CL,eff = 12 pF
1000
3.0 V
ms
500
To improve EMI on the XT1 oscillator, the following guidelines should be observed.
a. Keep the trace between the device and the crystal as short as possible.
b. Design a good ground plane around the oscillator pins.
c. Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
d. Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
e. Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins.
f. If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins.
When XT1BYPASS is set, XT1 circuits are automatically powered down.
Maximum frequency of operation of the entire device cannot be exceeded.
Oscillation allowance is based on a safety factor of 5 for recommended crystals. The oscillation allowance is a function of the
XT1DRIVEx settings and the effective load. In general, comparable oscillator allowance can be achieved based on the following
guidelines, but should be evaluated based on the actual crystal selected for the application:
a. For XT1DRIVEx = 0, CL,eff ≤ 6 pF.
b. For XT1DRIVEx = 1, 6 pF ≤ CL,eff ≤ 9 pF.
c. For XT1DRIVEx = 2, 6 pF ≤ CL,eff ≤ 10 pF.
d. For XT1DRIVEx = 3, CL,eff ≥ 6 pF.
Includes parasitic bond and package capacitance (approximately 2 pF per pin).
Since the PCB adds additional capacitance, it is recommended to verify the correct load by measuring the ACLK frequency. For a
correct setup, the effective load capacitance should always match the specification of the used crystal.
Requires external capacitors at both terminals. Values are specified by crystal manufacturers.
Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag.
Frequencies in between might set the flag.
Measured with logic-level input frequency but also applies to operation with crystals.
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MSP430F543x, MSP430F541x
MSP430F543xA, MSP430F541xA
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Crystal Oscillator, XT1, High-Frequency Mode (1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
IDVCC.HF
XT1 oscillator crystal current HF
mode
TEST CONDITIONS
VCC
MIN
TYP
fOSC = 4 MHz,
XTS = 1, XOSCOFF = 0,
XT1BYPASS = 0, XT1DRIVEx = 0,
TA = 25°C
200
fOSC = 12 MHz,
XTS = 1, XOSCOFF = 0,
XT1BYPASS = 0, XT1DRIVEx = 1,
TA = 25°C
260
fOSC = 20 MHz,
XTS = 1, XOSCOFF = 0,
XT1BYPASS = 0, XT1DRIVEx = 2,
TA = 25°C
MAX
UNIT
µA
3.0 V
325
fOSC = 32 MHz,
XTS = 1, XOSCOFF = 0,
XT1BYPASS = 0, XT1DRIVEx = 3,
TA = 25°C
450
fXT1,HF0
XT1 oscillator crystal frequency,
HF mode 0
XTS = 1,
XT1BYPASS = 0, XT1DRIVEx = 0 (2)
4
8
MHz
fXT1,HF1
XT1 oscillator crystal frequency,
HF mode 1
XTS = 1,
XT1BYPASS = 0, XT1DRIVEx = 1 (2)
8
16
MHz
fXT1,HF2
XT1 oscillator crystal frequency,
HF mode 2
XTS = 1,
XT1BYPASS = 0, XT1DRIVEx = 2 (2)
16
24
MHz
fXT1,HF3
XT1 oscillator crystal frequency,
HF mode 3
XTS = 1,
XT1BYPASS = 0, XT1DRIVEx = 3 (2)
24
32
MHz
fXT1,HF,SW
XT1 oscillator logic-level
square-wave input frequency,
HF mode
XTS = 1,
XT1BYPASS = 1 (3) (2)
4
32
MHz
OAHF
tSTART,HF
(1)
(2)
(3)
(4)
Oscillation allowance for
HF crystals (4)
Startup time, HF mode
XTS = 1,
XT1BYPASS = 0, XT1DRIVEx = 0,
fXT1,HF = 6 MHz, CL,eff = 15 pF
450
XTS = 1,
XT1BYPASS = 0, XT1DRIVEx = 1,
fXT1,HF = 12 MHz, CL,eff = 15 pF
320
XTS = 1,
XT1BYPASS = 0, XT1DRIVEx = 2,
fXT1,HF = 20 MHz, CL,eff = 15 pF
200
XTS = 1,
XT1BYPASS = 0, XT1DRIVEx = 3,
fXT1,HF = 32 MHz, CL,eff = 15 pF
200
fOSC = 6 MHz, XTS = 1,
XT1BYPASS = 0, XT1DRIVEx = 0,
TA = 25°C,
CL,eff = 15 pF
0.5
fOSC = 20 MHz, XTS = 1,
XT1BYPASS = 0, XT1DRIVEx = 3,
TA = 25°C,
CL,eff = 15 pF
Ω
3.0 V
ms
0.3
To improve EMI on the XT1 oscillator the following guidelines should be observed.
a. Keep the traces between the device and the crystal as short as possible.
b. Design a good ground plane around the oscillator pins.
c. Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
d. Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
e. Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins.
f. If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins.
Maximum frequency of operation of the entire device cannot be exceeded.
When XT1BYPASS is set, XT1 circuits are automatically powered down.
Oscillation allowance is based on a safety factor of 5 for recommended crystals.
Copyright © 2008, Texas Instruments Incorporated
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MSP430F543x, MSP430F541x
MSP430F543xA, MSP430F541xA
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Crystal Oscillator, XT1, High-Frequency Mode (continued)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
CL,eff
Integrated effective load
capacitance, HF mode (5) (6)
XTS = 1
Duty cycle
HF mode
XTS = 1, Measured at ACLK,
fXT1,HF2 = 20 MHz
40
fFault,HF
Oscillator fault frequency,
HF mode (7)
XTS = 1 (8)
30
(5)
(6)
(7)
(8)
TYP
MAX
1
50
UNIT
pF
60
%
300
kHz
Includes parasitic bond and package capacitance (approximately 2 pF per pin).
Since the PCB adds additional capacitance, it is recommended to verify the correct load by measuring the ACLK frequency. For a
correct setup, the effective load capacitance should always match the specification of the used crystal.
Requires external capacitors at both terminals. Values are specified by crystal manufacturers.
Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag.
Frequencies in between might set the flag.
Measured with logic-level input frequency but also applies to operation with crystals.
Crystal Oscillator, XT2
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) (2)
PARAMETER
XT2 oscillator crystal current
consumption
IDVCC.XT2
TEST CONDITIONS
VCC
MIN
TYP
fOSC = 4 MHz, XT2OFF = 0,
XT2BYPASS = 0, XT2DRIVEx = 0,
TA = 25°C
200
fOSC = 12 MHz, XT2OFF = 0,
XT2BYPASS = 0, XT2DRIVEx = 1,
TA = 25°C
260
fOSC = 20 MHz, XT2OFF = 0,
XT2BYPASS = 0, XT2DRIVEx = 2,
TA = 25°C
MAX
UNIT
µA
3.0 V
325
fOSC = 32 MHz, XT2OFF = 0,
XT2BYPASS = 0, XT2DRIVEx = 3,
TA = 25°C
450
fXT2,HF0
XT2 oscillator crystal frequency,
mode 0
XT2DRIVEx = 0, XT2BYPASS = 0 (3)
4
8
MHz
fXT2,HF1
XT2 oscillator crystal frequency,
mode 1
XT2DRIVEx = 1, XT2BYPASS = 0 (3)
8
16
MHz
fXT2,HF2
XT2 oscillator crystal frequency,
mode 2
XT2DRIVEx = 2, XT2BYPASS = 0 (3)
16
24
MHz
fXT2,HF3
XT2 oscillator crystal frequency,
mode 3
XT2DRIVEx = 3, XT2BYPASS = 0 (3)
24
32
MHz
fXT2,HF,SW
XT2 oscillator logic-level
square-wave input frequency
XT2BYPASS = 1 (4) (3)
4
32
MHz
(1)
(2)
(3)
(4)
48
Requires external capacitors at both terminals. Values are specified by crystal manufacturers.
To improve EMI on the XT2 oscillator the following guidelines should be observed.
a. Keep the traces between the device and the crystal as short as possible.
b. Design a good ground plane around the oscillator pins.
c. Prevent crosstalk from other clock or data lines into oscillator pins XT2IN and XT2OUT.
d. Avoid running PCB traces underneath or adjacent to the XT2IN and XT2OUT pins.
e. Use assembly materials and praxis to avoid any parasitic load on the oscillator XT2IN and XT2OUT pins.
f. If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins.
Maximum frequency of operation of the entire device cannot be exceeded.
When XT2BYPASS is set, the XT2 circuit is automatically powered down.
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MSP430F543x, MSP430F541x
MSP430F543xA, MSP430F541xA
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Crystal Oscillator, XT2 (continued)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
OAHF
tSTART,HF
CL,eff
Oscillation allowance for
HF crystals (5)
Startup time
(5)
(6)
(7)
(8)
VCC
MIN
TYP
450
XT2DRIVEx = 1, XT2BYPASS = 0,
fXT2,HF1 = 12 MHz, CL,eff = 15 pF
320
XT2DRIVEx = 2, XT2BYPASS = 0,
fXT2,HF2 = 20 MHz, CL,eff = 15 pF
200
XT2DRIVEx = 3, XT2BYPASS = 0,
fXT2,HF3 = 32 MHz, CL,eff = 15 pF
200
fOSC = 6 MHz
XT2BYPASS = 0, XT2DRIVEx = 0,
TA = 25°C,
CL,eff = 15 pF
0.5
fOSC = 20 MHz
XT2BYPASS = 0, XT2DRIVEx = 3,
TA = 25°C,
CL,eff = 15 pF
Oscillator fault frequency (7)
MAX
UNIT
Ω
3.0 V
ms
0.3
Integrated effective load
capacitance, HF mode (6) (1)
Duty cycle
fFault,HF
TEST CONDITIONS
XT2DRIVEx = 0, XT2BYPASS = 0,
fXT2,HF0 = 6 MHz, CL,eff = 15 pF
1
Measured at ACLK, fXT2,HF2 = 20 MHz
40
XT2BYPASS = 1 (8)
30
50
pF
60
%
300
kHz
Oscillation allowance is based on a safety factor of 5 for recommended crystals.
Includes parasitic bond and package capacitance (approximately 2 pF per pin).
Since the PCB adds additional capacitance, it is recommended to verify the correct load by measuring the ACLK frequency. For a
correct setup, the effective load capacitance should always match the specification of the used crystal.
Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag.
Frequencies in between might set the flag.
Measured with logic-level input frequency but also applies to operation with crystals.
Internal Very-Low-Power Low-Frequency Oscillator (VLO)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
fVLO
VLO frequency
Measured at ACLK
1.8 V to 3.6 V
dfVLO/dT
VLO frequency temperature drift
Measured at ACLK (1)
1.8 V to 3.6 V
Measured at ACLK (2)
1.8 V to 3.6 V
Measured at ACLK
1.8 V to 3.6 V
dfVLO/dVCC VLO frequency supply voltage drift
Duty cycle
(1)
(2)
MIN
TYP
MAX
6
9.4
14
0.5
kHz
%/°C
4
40
UNIT
%/V
50
60
TYP
MAX
%
Calculated using the box method: (MAX(-40 to 85°C) – MIN(-40 to 85°C)) / MIN(-40 to 85°C) / (85°C – (–40°C))
Calculated using the box method: (MAX(1.8 to 3.6 V) – MIN(1.8 to 3.6 V)) / MIN(1.8 to 3.6 V) / (3.6 V – 1.8 V)
Internal Reference, Low-Frequency Oscillator (REFO)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
UNIT
IREFO
REFO oscillator current consumption TA = 25°C
1.8 V to 3.6 V
3
µA
fREFO
REFO frequency calibrated
Measured at ACLK
1.8 V to 3.6 V
32768
Hz
Full temperature range
1.8 V to 3.6 V
±3.5
3V
±1.5
REFO absolute tolerance calibrated
TA = 25°C
dfREFO/dT
REFO frequency temperature drift
Measured at ACLK (1)
1.8 V to 3.6 V
dfREFO/dVCC
REFO frequency supply voltage drift
Measured at ACLK (2)
1.8 V to 3.6 V
Measured at ACLK
1.8 V to 3.6 V
40%/60% duty cycle
1.8 V to 3.6 V
Duty cycle
tSTART
(1)
(2)
REFO startup time
0.01
50
%
%/°C
1.0
40
%
%/V
60
25
%
µs
Calculated using the box method: (MAX(-40 to 85°C) – MIN(-40 to 85°C)) / MIN(-40 to 85°C) / (85°C – (–40°C))
Calculated using the box method: (MAX(1.8 to 3.6 V) – MIN(1.8 to 3.6 V)) / MIN(1.8 to 3.6 V) / (3.6 V – 1.8 V)
Copyright © 2008, Texas Instruments Incorporated
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MSP430F543x, MSP430F541x
MSP430F543xA, MSP430F541xA
SLAS612 – SEPTEMBER 2008.......................................................................................................................................................................................... www.ti.com
DCO Frequency
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
MAX
UNIT
fDCO(0,0)
DCO frequency (0, 0)
PARAMETER
DCORSELx = 0, DCOx = 0, MODx = 0
TEST CONDITIONS
0.07
0.20
MHz
fDCO(0,31)
DCO frequency (0, 31)
DCORSELx = 0, DCOx = 31, MODx = 0
0.70
1.70
MHz
fDCO(1,0)
DCO frequency (1, 0)
DCORSELx = 1, DCOx = 0, MODx = 0
0.15
0.36
MHz
fDCO(1,31)
DCO frequency (1, 31)
DCORSELx = 1, DCOx = 31, MODx = 0
1.47
3.45
MHz
fDCO(2,0)
DCO frequency (2, 0)
DCORSELx = 2, DCOx = 0, MODx = 0
0.32
0.75
MHz
fDCO(2,31)
DCO frequency (2, 31)
DCORSELx = 2, DCOx = 31, MODx = 0
3.17
7.38
MHz
fDCO(3,0)
DCO frequency (3, 0)
DCORSELx = 3, DCOx = 0, MODx = 0
0.64
1.51
MHz
fDCO(3,31)
DCO frequency (3, 31)
DCORSELx = 3, DCOx = 31, MODx = 0
6.07
14.0
MHz
fDCO(4,0)
DCO frequency (4, 0)
DCORSELx = 4, DCOx = 0, MODx = 0
1.3
3.2
MHz
fDCO(4,31)
DCO frequency (4, 31)
DCORSELx = 4, DCOx = 31, MODx = 0
12.3
28.2
MHz
fDCO(5,0)
DCO frequency (5, 0)
DCORSELx = 5, DCOx = 0, MODx = 0
2.5
6.0
MHz
fDCO(5,31)
DCO frequency (5, 31)
DCORSELx = 5, DCOx = 31, MODx = 0
23.7
54.1
MHz
fDCO(6,0)
DCO frequency (6, 0)
DCORSELx = 6, DCOx = 0, MODx = 0
4.6
10.7
MHz
fDCO(6,31)
DCO frequency (6, 31)
DCORSELx = 6, DCOx = 31, MODx = 0
39.0
88.0
MHz
fDCO(7,0)
DCO frequency (7, 0)
DCORSELx = 7, DCOx = 0, MODx = 0
8.5
19.6
MHz
fDCO(7,31)
DCO frequency (7, 31)
DCORSELx = 7, DCOx = 31, MODx = 0
60
135
MHz
SDCORSEL
Frequency step between range
DCORSEL and DCORSEL + 1
SRSEL = fDCO(DCORSEL+1,DCO)/fDCO(DCORSEL,DCO)
1.2
2.3
ratio
SDCO
Frequency step between tap
DCO and DCO + 1
SDCO = fDCO(DCORSEL,DCO+1)/fDCO(DCORSEL,DCO)
1.02
1.12
ratio
Duty cycle
MIN
Measured at SMCLK
40
TYP
50
60
%
dfDCO/dT
DCO frequency temperature drift
fDCO = 1 MHz,
0.1
%/°C
dfDCO/dVCC
DCO frequency voltage drift
fDCO = 1 MHz
1.9
%/V
Typical DCO Frequency, VCC = 3.0 V, TA = 25°C
100
fDCO – MHz
10
DCOx = 31
1
0.1
DCOx = 0
0
1
2
3
4
5
6
7
DCORSEL
Figure 10. Typical DCO frequency
50
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MSP430F543x, MSP430F541x
MSP430F543xA, MSP430F541xA
www.ti.com.......................................................................................................................................................................................... SLAS612 – SEPTEMBER 2008
PMM, Brown-Out Reset (BOR)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MAX
UNIT
1.55
V
1.65
V
100
250
mV
DVCC = 1.8 V to 3.6 V
0.69
0.83
V
DVCC = 1.8 V to 3.6 V
0.83
1.05
V
70
200
mV
V(DVCC_BOR_IT–)
BORH on voltage,
DVCC falling level
| dDVCC/dt | < 3 V/s
V(DVCC_BOR_IT+)
BORH off voltage,
DVCC rising level
| dDVCC/dt | < 3 V/s
V(DVCC_BOR_hys)
BORH hysteresis
V(VCORE_BOR_IT–)
BORL on voltage,
VCORE falling level
V(VCORE_BOR_IT+)
BORL off voltage,
VCORE rising level
V(VCORE_BOR_hys)
BORL hysteresis
tRESET
Pulse length required at
RST/NMI pin to accept a
reset
MIN
0.80
TYP
1.30
µs
2
PMM, Core Voltage
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VCORE2(AM)
Core voltage, active
mode, PMMCOREV = 2
2.2 V ≤ DVCC ≤ 3.6 V, 0 mA ≤ I(VCORE) ≤ 21 mA
1.60
1.81
1.89
V
VCORE1(AM)
Core voltage, active
mode, PMMCOREV = 1
2.0 V ≤ DVCC ≤ 3.6 V, 0 mA ≤ I(VCORE) ≤ 17 mA
A versions only
1.40
1.61
1.82
V
VCORE0(AM)
Core voltage, active
mode, PMMCOREV = 0
1.8 V ≤ DVCC ≤ 3.6 V, 0 mA ≤ I(VCORE) ≤ 13 mA
A versions only
1.20
1.41
1.56
V
VCORE2(LPM)
Core voltage, low-current
2.2 V ≤ DVCC ≤ 3.6 V, 0 µA ≤ I(VCORE) ≤ 30 µA
mode, PMMCOREV = 2
1.68
1.89
2.10
V
VCORE1(LPM)
Core voltage, low-current 2.0 V ≤ DVCC ≤ 3.6 V, 0 µA ≤ I(VCORE) ≤ 30 µA
mode, PMMCOREV = 1 A versions only
1.46
1.69
1.90
V
VCORE0(LPM)
Core voltage, low-current 1.8 V ≤ DVCC ≤ 3.6 V, 0 µA ≤ I(VCORE) ≤ 30 µA
mode, PMMCOREV = 0 A versions only
1.26
1.47
1.70
V
PSRR(DC,AM)
Power-supply rejection
ratio, active mode
PSRR(DC,LPM)
Power-supply rejection
ratio, low-current mode
Copyright © 2008, Texas Instruments Incorporated
DVCC = 2.2 V/3.6 V, I(VCORE) = 0 mA,
PMMCOREV = 2
60
DVCC = 2.2 V/3.6 V, I(VCORE) = 21 mA,
PMMCOREV = 2
60
DVCC = 2.2 V/3.6 V, I(VCORE) = 0 mA,
PMMCOREV = 2
50
DVCC = 2.4 V/3.6 V, I(VCORE) = 30 µA,
PMMCOREV = 2
50
dB
dB
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MSP430F543x, MSP430F541x
MSP430F543xA, MSP430F541xA
SLAS612 – SEPTEMBER 2008.......................................................................................................................................................................................... www.ti.com
PMM, SVS High Side
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
SVSHE = 0, DVCC = 3.6 V
I(SVSH)
SVS current consumption
SVSHE = 1, DVCC = 3.6 V, SVSHFP = 0
SVSHE = 1, DVCC = 3.6 V, SVSHFP = 1
V(SVSH_IT–)
V(SVSH_IT+)
tpd(SVSH)
SVSH on voltage level
SVSH off voltage level
SVSH propagation delay
dVDVCC/dt
TYP
MAX
nA
200
nA
µA
2.0
SVSHE = 1, SVSHRVL = 0
1.59
1.64
1.69
SVSHE = 1, SVSHRVL = 1
1.79
1.84
1.91
SVSHE = 1, SVSHRVL = 2
1.98
2.04
2.11
SVSHE = 1, SVSHRVL = 3
2.10
2.16
2.23
SVSHE = 1, SVSMHRRL = 0
1.62
1.74
1.81
SVSHE = 1, SVSMHRRL = 1
1.88
1.94
2.01
SVSHE = 1, SVSMHRRL = 2
2.07
2.14
2.21
SVSHE = 1, SVSMHRRL = 3
2.20
2.26
2.33
SVSHE = 1, SVSMHRRL = 4
2.40
SVSHE = 1, SVSMHRRL = 5
2.70
SVSHE = 1, SVSMHRRL = 6
3.00
SVSHE = 1, SVSMHRRL = 7
3.00
SVSHE = 1, DVCC = V(SVMH_IT+) + 10 mV,
SVSHFP = 1
1
SVSHE = 1, DVCC = V(SVMH_IT–) – 10 mV,
SVSHFP = 1
1
SVSHE = 1, DVCC = V(SVMH_IT+) + 10 mV,
SVSHFP = 0
150
SVSHE = 1, DVCC = V(SVMH_IT–) – 10 mV,
SVSHFP = 0
150
DVCC rise time
UNIT
0
V
V
µs
0
1000
V/s
MAX
UNIT
PMM, SVM High Side
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
SVMHE = 0, DVCC = 3.6 V
I(SVMH)
SVMH current consumption
SVMHE= 1, DVCC = 3.6 V, SVMHFP = 0
SVMHE = 1, DVCC = 3.6 V, SVMHFP = 1
V(SVMH)
tpd(SVMH)
52
SVMH on/off voltage level
SVMH propagation delay
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TYP
0
nA
200
nA
µA
2.0
SVMHE = 1, SVSMHRRL = 0
1.65
1.74
1.86
SVMHE = 1, SVSMHRRL = 1
1.85
1.94
2.02
SVMHE = 1, SVSMHRRL = 2
2.02
2.14
2.22
SVMHE = 1, SVSMHRRL = 3
2.18
2.26
2.35
SVMHE = 1, SVSMHRRL = 4
2.40
SVMHE = 1, SVSMHRRL = 5
2.70
SVMHE = 1, SVSMHRRL = 6
3.00
SVMHE = 1, SVSMHRRL = 7
3.00
SVMHE = 1, SVMHOVPE = 1
3.75
V
SVMHE = 1, DVCC = V(SVMH_IT) ± 10 mV,
SVMHFP = 1
1
µs
SVMHE = 1, DVCC = V(SVMH_IT) ± 10 mV,
SVMHFP = 0
150
µs
Copyright © 2008, Texas Instruments Incorporated
MSP430F543x, MSP430F541x
MSP430F543xA, MSP430F541xA
www.ti.com.......................................................................................................................................................................................... SLAS612 – SEPTEMBER 2008
PMM, SVS Low Side
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
SVSLE = 0, PMMCOREV = 2
I(SVSL)
SVSL current consumption
SVSLE = 1, PMMCOREV = 2, SVSLFP = 0
SVSLE = 1, PMMCOREV = 2, SVSLFP = 1
V(SVSL_IT–)
V(SVSL_IT+)
V(SVSL_HYS)
t(SVSL)
tpd(SVSL)
SVSL on voltage level
SVSL off voltage level
SVSL hystersis
SVSL on/off delay time
SVSL propagation delay
TYP
MAX
UNIT
0
nA
200
nA
µA
2.0
SVSLE = 1, SVSLRVL = 0
1.20
1.27
1.32
SVSLE = 1, SVSLRVL = 1
1.39
1.47
1.52
SVSLE = 1, SVSLRVL = 2
1.60
1.67
1.72
SVSLE = 1, SVSLRVL = 3
1.70
1.77
1.82
SVSLE = 1, SVSMLRRL = 0
1.29
1.34
1.39
SVSLE = 1, SVSMLRRL = 1
1.49
1.54
1.59
SVSLE = 1, SVSMLRRL = 2
1.69
1.74
1.79
SVSLE = 1, SVSMLRRL = 3, 4, 5, 6, 7
1.79
1.84
1.89
SVSLE = 1, SVSMLRRL = 0
70
SVSLE = 1, SVSMLRRL = 1
70
SVSLE = 1, SVSMLRRL = 2
70
SVSLE = 1, SVSMLRRL = 3
70
SVSLE = 1, DVCC = V(SVML_IT+) ± 10 mV,
SVSLFP = 1
1
SVSLE = 1, DVCC = V(SVML_IT+) ± 10 mV,
SVSLFP = 0
200
SVSLE = 1, DVCC = V(SVML_IT+) + 10 mV,
SVSLFP = 1
1
SVSLE = 1, DVCC = V(SVML_IT–) – 10mV,
SVSLFP = 1
1
V
V
mV
µs
µs
SVSLE = 1, DVCC = V(SVML_IT+) + 10 mV,
SVSLFP = 0
150
SVSLE = 1, DVCC = V(SVML_IT–) – 10 mV,
SVSLFP = 0
150
PMM, SVM Low Side
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
SVMLE = 0, PMMCOREV = 2
I(SVML)
V(SVML)
SVML current consumption
SVML on/off voltage level
SVML propagation delay
Copyright © 2008, Texas Instruments Incorporated
MAX
UNIT
0
nA
SVMLE= 1, PMMCOREV = 2, SVMLFP = 0
200
nA
SVMLE= 1, PMMCOREV = 2, SVMLFP = 1
2.0
µA
SVMLE = 1, SVSMLRRL = 0
1.28
1.34
1.40
SVMLE = 1, SVSMLRRL = 1
1.49
1.54
1.60
SVMLE = 1, SVSMLRRL = 2
1.68
1.74
1.79
SVMLE = 1, SVSMLRRL = 3, 4, 5, 6, 7
1.76
1.84
1.90
SVMLE = 1, SVSMLOVPL = 1
tpd(SVML)
TYP
V
2.02
SVMLE = 1, DVCC = V(SVML_IT) 10 mV,
SVMLFP = 1
1
SVMLE = 1, DVCC = V(SVML_IT) 10 mV,
SVMLFP = 0
150
µs
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Wake-up from Low Power Modes
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP MAX UNIT
PMMCOREV = 0
SVSLE = 1, SVSMLRRL = 0, SVSLFP = 1
A versions only
tFAST-WAKEUP
Wake-up time from LPM2,
LPM3, or LPM4 to active
mode
PMMCOREV = 1
SVSLE = 1, SVSMLRRL = 1, SVSLFP = 1
A versions only
5
2.2/3.0 V
PMMCOREV = 2
SVSLE = 1, SVSMLRRL = 2, SVSLFP = 1
tWAKE-UP
Wake-up time from LPM5
to active mode
LPM5
A versions only
5
2.2/3.0 V
2
PMMCOREV = 0
SVSLE = 1, SVSMLRRL = 0, SVSLFP = 0
A versions only
tSLOW-WAKEUP
Wake-up time from LPM2,
LPM3, or LPM4 to active
mode
PMMCOREV = 1
SVSLE = 1, SVSMLRRL = 1, SVSLFP = 0
A versions only
µs
5
3
ms
150
2.2/3.0 V
µs
150
PMMCOREV = 2
SVSLE = 1, SVSMLRRL = 2, SVSLFP = 0
150
Timer_A
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
fTA
Timer_A input clock frequency
Internal: SMCLK, ACLK
External: TACLK
Duty cycle = 50% ± 10%
tTA,cap
Timer_A capture timing
All capture inputs.
Minimum pulse width required for
capture.
VCC
1.8 V/
3.0 V
1.8 V/
3.0 V
MIN
TYP
MAX
UNIT
25
MHz
20
ns
Timer_B
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
fTB
Timer_B input clock frequency
Internal: SMCLK, ACLK
External: TBCLK
Duty cycle = 50% ± 10%
tTB,cap
Timer_B capture timing
All capture inputs.
Minimum pulse width required for
capture.
VCC
1.8 V/
3.0 V
1.8 V/
3.0 V
MIN
TYP
MAX
UNIT
25
MHz
20
ns
USCI (UART Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
fUSCI
USCI input clock frequency
fBITCLK
BITCLK clock frequency
(equals baud rate in MBaud)
tτ
UART receive deglitch time (1)
(1)
54
TEST CONDITIONS
VCC
MIN
Internal: SMCLK, ACLK
External: UCLK
Duty cycle = 50% ± 10%
TYP
MAX
UNIT
fSYSTEM
MHz
1
MHz
2.2 V
50
600
3V
50
600
ns
Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To ensure that pulses are
correctly recognized their width should exceed the maximum specification of the deglitch time.
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USCI (SPI Master Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 11 and
Figure 12)
PARAMETER
fUSCI
USCI input clock frequency
tSU,MI
SOMI input data setup time
tHD,MI
SOMI input data hold time
tVALID,MO
SIMO output data valid time
TEST CONDITIONS
VCC
MIN
TYP
SMCLK, ACLK
Duty cycle = 50% ± 10%
UCLK edge to SIMO valid,
CL = 20 pF
2.2 V
65
3V
50
2.2 V
0
3V
0
MAX
UNIT
fSYSTEM
MHz
ns
ns
2.2 V
25
3V
20
ns
USCI (SPI Slave Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 13 and
Figure 14)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
STE lead time, STE low to clock
2.2 V/3 V
tSTE,LAG
STE lag time, Last clock to STE high
2.2 V/3 V
tSTE,ACC
STE access time, STE low to SOMI data out
2.2 V/3 V
40
ns
tSTE,DIS
STE disable time, STE high to SOMI high
impedance
2.2 V/3 V
40
ns
tSU,SI
SIMO input data setup time
tHD,SI
SIMO input data hold time
tVALID,SO
SOMI output data valid time
UCLK edge to SOMI valid,
CL = 20 pF
40
UNIT
tSTE,LEAD
ns
10
2.2 V
20
3V
15
2.2 V
10
3V
10
ns
ns
ns
2.2 V
62
3V
50
ns
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLOW/HIGH
tLOW/HIGH
tSU,MI
tHD,MI
SOMI
tVALID,MO
SIMO
Figure 11. SPI Master Mode, CKPH = 0
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1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLOW/HIGH
tLOW/HIGH
tSU,MI
tHD,MI
SOMI
tVALID,MO
SIMO
Figure 12. SPI Master Mode, CKPH = 1
tSTE,LAG
tSTE,LEAD
STE
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLOW/HIGH
tSU,SIMO
tLOW/HIGH
tHD,SIMO
SIMO
tACC
tVALID,SOMI
tDIS
SOMI
Figure 13. SPI Slave Mode, CKPH = 0
56
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tSTE,LAG
tSTE,LEAD
STE
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLOW/HIGH
tLOW/HIGH
tHD,SI
tSU,SI
SIMO
tACC
tDIS
tVALID,SO
SOMI
Figure 14. SPI Slave Mode, CKPH = 1
USCI (I2C Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 15)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
Internal: SMCLK, ACLK
External: UCLK
Duty cycle = 50% ± 10%
MAX
UNIT
fSYSTEM
MHz
400
kHz
fUSCI
USCI input clock frequency
fSCL
SCL clock frequency
tHD,STA
Hold time (repeated) START
tSU,STA
Setup time for a repeated START
tHD,DAT
Data hold time
2.2 V/3 V
0
ns
tSU,DAT
Data setup time
2.2 V/3 V
250
ns
tSU,STO
Setup time for STOP
tSP
Pulse width of spikes suppressed by input filter
2.2 V/3 V
fSCL ≤ 100 kHz
fSCL > 100 kHz
fSCL ≤ 100 kHz
fSCL > 100 kHz
fSCL ≤ 100 kHz
fSCL > 100 kHz
tSU,STA
tHD,STA
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
0
4.0
µs
0.6
4.7
µs
0.6
4.0
µs
0.6
2.2 V
50
600
3V
50
600
tHD,STA
ns
tBUF
SDA
tLOW
tHIGH
tSP
SCL
tSU,DAT
tSU,STO
tHD,DAT
Figure 15. I2C Mode Timing
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12-Bit ADC, Power Supply and Input Range Conditions
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
PARAMETER
TEST CONDITIONS
VCC
AVCC
Analog supply voltage
AVCC and DVCC are connected together,
AVSS and DVSS are connected together,
V(AVSS) = V(DVSS) = 0 V
V(Ax)
Analog input voltage range (2)
All ADC12 pins: P6.0 to P6.7, P7.4 to P7.7,
P5.0, and P5.1 terminals
IADC12_A
Operating supply current into
AVCC terminal (3)
fADC12CLK = 5.0 MHz, ADC12ON = 1,
REFON = 0, SHT0 = 0, SHT1 = 0,
ADC12DIV = 0
IREF+
Operating supply current into
AVCC terminal (4)
TYP
MAX
UNIT
2.2
3.6
V
0
AVCC
V
2.2 V
125
155
3V
150
220
ADC12ON = 0,
REFON = 1, REF2_5V = 1
3V
150
190
ADC12ON = 0,
REFON = 1, REF2_5V = 0
2.2 V/3 V
150
180
2.2 V
20
25
pF
200
1900
Ω
µA
µA
CI
Input capacitance
Only one terminal Ax can be selected at one
time
RI
Input MUX ON resistance
0 V ≤ VAx ≤ AVCC
(1)
(2)
(3)
(4)
MIN
10
The leakage current is specified by the digital I/O input leakage.
The analog input voltage range must be within the selected reference voltage range VR+ to VR– for valid conversion results.
The internal reference supply current is not included in current consumption parameter IADC12.
The internal reference current is supplied via terminal AVCC. Consumption is independent of the ADC12ON control bit, unless a
conversion is active. The REFON bit enables to settle the built-in reference before starting an A/D conversion. No external load.
12-Bit ADC, External Reference
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
PARAMETER
VeREF+
TEST CONDITIONS
Positive external reference voltage input
MAX
UNIT
VeREF+ > VREF–/VeREF– (2)
VCC
MIN
1.4
TYP
AVCC
V
0
1.2
V
1.4
AVCC
V
VREF–/VeREF–
Negative external reference voltage input
VeREF+ > VREF–/VeREF–
(3)
(VeREF+ –
VREF–/VeREF–)
Differential external reference voltage
input
VeREF+ > VREF–/VeREF–
(4)
IVeREF+
Static input current
0 V ≤ VeREF+ ≤ VAVCC
2.2 V/3 V
±1
µA
IVREF–/VeREF–
Static input current
0 V ≤ VeREF– ≤ VAVCC
2.2 V/3 V
±1
µA
(1)
(2)
(3)
(4)
The external reference is used during conversion to charge and discharge the capacitance array. The input capacitance, Ci, is also the
dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the
recommendations on analog-source impedance to allow the charge to settle for 12-bit accuracy.
The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced
accuracy requirements.
The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with reduced
accuracy requirements.
The accuracy limits minimum external differential reference voltage. Lower differential reference voltage levels may be applied with
reduced accuracy requirements.
12-Bit ADC, Built-In Reference
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VREF+
Positive built-in reference
voltage output
AVCC(min)
AVCC minimum voltage,
Positive built-in reference
active
IVREF+
Load current out of VREF+
terminal
58
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TEST CONDITIONS
VCC
MIN
TYP
MAX
REF2_5V = 1 for 2.5 V,
IVREF+(max) ≤ IVREF+ ≤ IVREF+(min)
3V
2.35
2.45
2.53
REF2_5V = 0 for 1.5 V,
IVREF+(max) ≤ IVREF+ ≤ IVREF+(min)
2.2 V/3 V
1.41
1.47
1.53
UNIT
V
REF2_5V = 0
2.2
REF2_5V = 1
2.8
V
2.2 V
–1
3V
–1
mA
Copyright © 2008, Texas Instruments Incorporated
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MSP430F543xA, MSP430F541xA
www.ti.com.......................................................................................................................................................................................... SLAS612 – SEPTEMBER 2008
12-Bit ADC, Built-In Reference (continued)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
IL(VREF)+
CVREF+
TREF+
tSETTLE
(1)
(2)
TEST CONDITIONS
IVREF+ = +10 µA/–1000 µA,
Analog input voltage ~0.75 V, REF2_5V = 0
Load-current regulation,
VREF+ terminal
IVREF+ = +10 µA/–1000 µA,
Analog input voltage ~1.25 V, REF2_5V = 1
Capacitance at VREF+
terminal
Temperature coefficient of
built-in reference (1)
Settling time of reference
voltage (2)
VCC
MIN
TYP
MAX
2.2 V
±2
3V
±2
3V
±2
REFON = REFOUT = 1,
0 mA ≤ IVREF+ ≤ IVREF+(max)
2.2 V/3 V
REF2_5V = 0
IVREF+ is a constant in the range of
0 mA ≤ IVREF+ ≤ –1 mA
2.2 V/3 V
30
REF2_5V = 1
IVREF+ is a constant in the range of
0 mA ≤ IVREF+ ≤ –1 mA
3V
375
REF2_5V = 1
IVREF+ is a constant in the range of
0 mA ≤ IVREF+ ≤ –1 mA
A version only
3V
30
20
UNIT
LSB
100
VREF+ = 1.5 V, VAVCC = 2.2 V,
REFOUT = 0, REFON = 0 → 1
20
VREF+ = 1.5 V, VAVCC = 2.2 V
CVREF = CVREF(max)
REFOUT = 1, REFON = 0 → 1
35
VREF+ = 2.5 V, VAVCC = 2.8 V
CVREF = CVREF(max)
REFOUT = 1, REFON = 0 → 1
35
pF
ppm/
°C
µs
Calculated using the box method: (MAX(-40 to 85°C) – MIN(-40 to 85°C)) / MIN(-40 to 85°C)/(85°C – (–40°C))
The condition is that the error in a conversion started after tREFON is less than ±0.5 LSB. The settling time depends on the external
capacitive load.
12-Bit ADC, Timing Parameters
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
fADC12CLK
fADC12OSC
tCONVERT
Internal ADC12
oscillator (1)
Conversion time
VCC
MIN
TYP
MAX
UNIT
For specified performance of ADC12 linearity
parameters
TEST CONDITIONS
2.2 V/3 V
0.45
4.8
5.4
MHz
ADC12DIV = 0, fADC12CLK = fADC12OSC
2.2 V/3 V
4.2
4.65
5.0
MHz
REFON = 0, Internal oscillator,
fADC12OSC = 4.2 MHz to 5.4 MHz
2.2 V/3 V
2.4
Turn on settling time of
the ADC
See
tSample
Sampling time
RS = 400 Ω, RI = 1000 Ω, CI = 30 pF,
τ = [RS + RI] × CI (4)
(1)
(2)
(3)
(4)
µs
External fADC12CLK from ACLK, MCLK or SMCLK,
ADC12SSEL ≠ 0
tADC12ON
3.1
(2)
(3)
100
2.2 V/3 V
1000
ns
ns
The ADC12OSC is sourced directly from MODOSC inside the UCS.
13 × ADC12DIV × 1/fADC12CLK
The condition is that the error in a conversion started after tADC12ON is less than ±0.5 LSB. The reference and input signal are already
settled.
Approximately ten Tau (τ) are needed to get an error of less than ±0.5 LSB:
tSample = ln(2n+1) x (RS + RI) × CI + 800 ns, where n = ADC resolution = 12, RS = external source resistance
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12-Bit ADC, Linearity Parameters
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
EI
Integral
linearity error
1.4 V ≤ (VeREF+ – VREF–/VeREF–)min ≤ 1.6 V
ED
Differential
linearity error
(VeREF+ – VREF–/VeREF–)min ≤ (VeREF+ – VREF–/VeREF–),
CVREF+ = 20 pF
2.2 V/3 V
EO
Offset error
(VeREF+ – VREF–/VeREF–)min ≤ (VeREF+ – VREF–/VeREF–),
Internal impedance of source RS < 100 Ω, CVREF+ = 20 pF
2.2 V/3 V
EG
Gain error
(VeREF+ – VREF–/VeREF–)min ≤ (VeREF+ – VREF–/VeREF–),
CVREF+ = 20 pF
ET
Total unadjusted
error
(VeREF+ – VREF–/VeREF–)min ≤ (VeREF+ – VREF–/VeREF–),
CVREF+ = 20 pF
MIN
TYP
±2
2.2 V/3 V
1.6 V < (VeREF+ – VREF–/VeREF–)min ≤ VAVCC
MAX
±1.7
UNIT
LSB
±1
LSB
±1
±3.5
LSB
2.2 V/3 V
±1.1
±2
LSB
2.2 V/3 V
±2
±5
LSB
TYP
MAX
UNIT
12-Bit ADC, Temperature Sensor and Built-In VMID
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
ISENSOR
Operating supply current into
AVCC terminal (1)
VSENSOR
See
(2)
TCSENSOR
VCC
MIN
REFON = 0, INCH = 0Ah,
ADC12ON = N A, TA = 25°C
2.2 V
150
3V
150
ADC12ON = 1, INCH = 0Ah,
TA = 0°C
2.2 V
894
3V
894
2.2 V
3.66
3V
3.66
ADC12ON = 1, INCH = 0Ah
tSENSOR(sample)
Sample time required if
channel 10 is selected (3)
ADC12ON = 1, INCH = 0Ah,
Error of conversion result ≤ 1 LSB
2.2 V
30
3V
30
VMID
AVCC divider at channel 11
ADC12ON = 1, INCH = 0Bh,
VMID is ~0.5 × VAVCC
2.2 V
1.1
3V
1.5
tVMID(sample)
Sample time required if
channel 11 is selected (4)
ADC12ON = 1, INCH = 0Bh,
Error of conversion result ≤ 1 LSB
(1)
(2)
1000
mV
mV/°C
µs
V
ns
The sensor current ISENSOR is consumed if (ADC12ON = 1 and REFON = 1) or (ADC12ON = 1 and INCH = 0Ah and sample signal is
high). When REFON = 1, ISENSOR is already included in IREF+.
The temperature sensor offset can be as much as ±20°C. A single-point calibration is recommended in order to minimize the offset error
of the built-in temperature sensor.
The typical equivalent impedance of the sensor is 51 kΩ. The sample time required includes the sensor-on time tSENSOR(on).
The on-time tVMID(on) is included in the sampling time tVMID(sample); no additional on time is needed.
Typical Temperature Sensor Voltage, V
(3)
(4)
2.2 V/3 V
µA
1.400
1.300
1.200
1.100
1.000
0.900
VTEMP = 0.00366(TEMP°C) + 0.894
0.800
0.700
−40
−20
0
20
40
60
80
100
Ambient Temperature – °C
Figure 16. Typical Temperature Sensor Voltage
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Flash Memory
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST
CONDITIONS
DVCC(PGM/ERASE) Program and erase supply voltage
tREADMARGIN
Read access time during margin mode
IPGM
Supply current from DVCC during program
IERASE
Supply current from DVCC during erase
IMERASE, IBANK
Supply current from DVCC during mass erase or bank erase
tCPT
Cumulative program time
tCMErase
Cumulative mass erase time
MIN
TYP
1.8
3.6
3
See
MAX
(1)
104
V
200
ns
5
mA
2
mA
2
mA
16
ms
10
Program/erase endurance
UNIT
ms
105
cycles
tRetention
Data retention duration
TJ = 25°C
tWord
Word or byte program time
See
(2)
64
85
µs
tBlock, 0
Block program time for first byte or word
See
(3)
49
65
µs
tBlock, 1–(N–1)
Block program time for each additional byte or word, except for last
byte or word
See
(3)
37
49
µs
See
(3)
55
73
µs
Mass erase time
See
(3)
23
32
ms
Segment erase time
See
(3)
23
32
ms
tBlock, N
tMass
Erase
tSeg Erase
(1)
(2)
(3)
Block program time for last byte or word
100
years
The cumulative program time must not be exceeded when writing to a 128-byte flash block. This parameter applies to all programming
methods: individual word/byte write and block write modes.
These values are hardwired into the flash controller's state machine.
These values are hardwired into the flash controller's state machine.
JTAG and Spy-Bi-Wire Interface
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST
CONDITIONS
MIN
TYP
MAX
UNIT
fSBW
Spy-Bi-Wire input frequency
2.2 V/3 V
0
20
MHz
tSBW,Low
Spy-Bi-Wire low clock pulse length
2.2 V/3 V
0.025
15
µs
tSBW, En
Spy-Bi-Wire enable time (TEST high to acceptance of first clock
edge) (1)
2.2 V/3 V
1
µs
tSBW,Rst
Spy-Bi-Wire return to normal operation time
100
µs
fTCK
TCK input frequency - 4-wire JTAG (2)
Rinternal
Internal pull-down resistance on TEST
(1)
(2)
15
2.2 V
0
5
MHz
3V
0
10
MHz
2.2 V/3 V
45
80
kΩ
60
Tools accessing the Spy-Bi-Wire interface need to wait for the tSBW,En time after pulling the TEST/SBWTCK pin high before applying the
first SBWTCK clock edge.
fTCK may be restricted to meet the timing requirements of the module selected.
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INPUT/OUTPUT SCHEMATICS
Port P1, P1.0 to P1.7, Input/Output With Schmitt Trigger
Pad Logic
P1REN.x
P1DIR.x
0
0
Module X OUT
1
DVCC
1
P1DS.x
0: Low drive
1: High drive
P1SEL.x
P1IN.x
EN
Module X IN
0
1
Direction
0: Input
1: Output
1
P1OUT.x
DVSS
P1.0/TA0CLK/ACLK
P1.1/TA0.0
P1.2/TA0.1
P1.3/TA0.2
P1.4/TA0.3
P1.5/TA0.4
P1.6/SMCLK
P1.7
D
P1IE.x
EN
P1IRQ.x
Q
P1IFG.x
P1SEL.x
P1IES.x
62
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Interrupt
Edge
Select
Copyright © 2008, Texas Instruments Incorporated
MSP430F543x, MSP430F541x
MSP430F543xA, MSP430F541xA
www.ti.com.......................................................................................................................................................................................... SLAS612 – SEPTEMBER 2008
Port P1 (P1.0 to P1.7) Pin Functions
PIN NAME (P1.x)
P1.0/TA0CLK/ACLK
P1.1/TA0.0
P1.2/TA0.1
P1.3/TA0.2
P1.4/TA0.3
P1.5/TA0.4
x
0
1
2
3
4
5
P1.6/SMCLK
6
P1.7
7
FUNCTION
CONTROL BITS/SIGNALS
P1DIR.x
P1SEL.x
I: 0; O: 1
0
Timer0_A5.TA0CLK
0
1
ACLK
1
1
P1.0 (I/O)
P1.1 (I/O)
I: 0; O: 1
0
Timer0_A5.CCI0A
0
1
Timer0_A5.TA0
1
1
P1.2 (I/O)
I: 0; O: 1
0
Timer0_A5.CCI1A
0
1
Timer0_A5.TA1
1
1
P1.3 (I/O)
I: 0; O: 1
0
Timer0_A5.CCI2A
0
1
Timer0_A5.TA2
1
1
I: 0; O: 1
0
Timer0_A5.CCI3A
0
1
Timer0_A5.TA3
1
1
I: 0; O: 1
0
Timer0_A5.CCI4A
0
1
Timer0_A5.TA4
1
1
I: 0; O: 1
0
1
1
I: 0; O: 1
0
P1.4 (I/O)
P1.5 (I/O)
P1.6 (I/O)
SMCLK
P1.7 (I/O)
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MSP430F543x, MSP430F541x
MSP430F543xA, MSP430F541xA
SLAS612 – SEPTEMBER 2008.......................................................................................................................................................................................... www.ti.com
Port P2, P2.0 to P2.7, Input/Output With Schmitt Trigger
Pad Logic
P2REN.x
P2DIR.x
0
0
Module X OUT
1
DVCC
1
1
P2DS.x
0: Low drive
1: High drive
P2SEL.x
P2IN.x
EN
Module X IN
0
Direction
0: Input
1: Output
1
P2OUT.x
DVSS
P2.0/TA1CLK/MCLK
P2.1/TA1.0
P2.2/TA1.1
P2.3/TA1.2
P2.4/RTCCLK
P2.5
P2.6/ACLK
P2.7/ADC12CLK/DMAE0
D
P2IE.x
EN
P2IRQ.x
Q
P2IFG.x
P2SEL.x
P2IES.x
64
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Interrupt
Edge
Select
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MSP430F543x, MSP430F541x
MSP430F543xA, MSP430F541xA
www.ti.com.......................................................................................................................................................................................... SLAS612 – SEPTEMBER 2008
Port P2 (P2.0 to P2.7) Pin Functions
PIN NAME (P2.x)
P2.0/TA1CLK/MCLK
P2.1/TA1.0
P2.2/TA1.1
P2.3/TA1.2
x
0
1
2
3
FUNCTION
CONTROL BITS/SIGNALS
P2DIR.x
P2SEL.x
I: 0; O: 1
0
Timer1_A3.TA1CLK
0
1
MCLK
1
1
P2.0 (I/O)
P2.1 (I/O)
I: 0; O: 1
0
Timer1_A3.CCI0A
0
1
Timer1_A3.TA0
1
1
P2.2 (I/O)
I: 0; O: 1
0
Timer1_A3.CCI1A
0
1
Timer1_A3.TA1
1
1
P2.3 (I/O)
I: 0; O: 1
0
Timer1_A3.CCI2A
0
1
Timer1_A3.TA2
1
1
I: 0; O: 1
0
P2.4/RTCCLK
4
P2.4 (I/O)
RTCCLK
1
1
P2.5
5
P2.5 (I/O
I: 0; O: 1
0
P2.6/ACLK
6
P2.6 (I/O)
I: 0; O: 1
0
P2.7/ADC12CLK/DMAE0
7
ACLK
1
1
I: 0; O: 1
0
DMAE0
0
1
ADC12CLK
1
1
P2.7 (I/O)
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MSP430F543x, MSP430F541x
MSP430F543xA, MSP430F541xA
SLAS612 – SEPTEMBER 2008.......................................................................................................................................................................................... www.ti.com
Port P3, P3.0 to P3.7, Input/Output With Schmitt Trigger
Pad Logic
P3REN.x
P3DIR.x
0
0
Module X OUT
1
0
DVCC
1
P3DS.x
0: Low drive
1: High drive
P3SEL.x
P3IN.x
EN
Module X IN
1
Direction
0: Input
1: Output
1
P3OUT.x
DVSS
P3.0/UB0STE/UCA0CLK
P3.1/UCB0SIMO/UCB0SDA
P3.2/UCB0SOMI/UCB0SCL
P3.3/USC0CLK/UCA0STE
P3.4/UCA0TXD/UCA0SIMO
P3.5/UCA0RXD/UCA0SOMI
P3.6/UCB1STE/UCA1CLK
P3.7/UCB1SIMO/UCB1SDA
D
Port P3 (P3.0 to P3.7) Pin Functions
PIN NAME (P3.x)
P3.0/UCB0STE/UCA0CLK
x
0
FUNCTION
P3.0 (I/O)
UCB0STE/UCA0CLK
P3.1/UCB0SIMO/UCB0SDA
1
(2) (3)
P3.1 (I/O)
UCB0SIMO/UCB0SDA (2) (4)
P3.2/UCB0SOMI/UCB0SCL
2
P3.2 (I/O)
UCB0SOMI/UCB0SCL (2) (4)
P3.3/UCB0CLK/UCA0STE
3
P3.3 (I/O)
UCB0CLK/UCA0STE (2)
P3.4/UCA0TXD/UCA0SIMO
4
P3.4 (I/O)
UCA0TXD/UCA0SIMO (2)
P3.5/UCA0RXD/UCA0SOMI
5
P3.5 (I/O)
UCA0RXD/UCA0SOMI
P3.6/UCB1STE/UCA1CLK
6
(2)
P3.6 (I/O)
UCB1STE/UCA1CLK (2) (5)
P3.7/UCB1SIMO/UCB1SDA
7
P3.7 (I/O)
UCB1SIMO/UCB1SDA (2) (4)
(1)
(2)
(3)
(4)
(5)
66
CONTROL BITS/SIGNALS (1)
P3DIR.x
P3SEL.x
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
X = Don't care
The pin direction is controlled by the USCI module.
UCA0CLK function takes precedence over UCB0STE function. If the pin is required as UCA0CLK input or output, USCI A0/B0 is forced
to 3-wire SPI mode if 4-wire SPI mode is selected.
If the I2C functionality is selected, the output drives only the logical 0 to VSS level.
UCA1CLK function takes precedence over UCB1STE function. If the pin is required as UCA1CLK input or output, USCI A1/B1 is forced
to 3-wire SPI mode if 4-wire SPI mode is selected.
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MSP430F543xA, MSP430F541xA
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Port P4, P4.0 to P4.7, Input/Output With Schmitt Trigger
Pad Logic
P4REN.x
P4DIR.x
0
0
Module X OUT
1
DVCC
1
1
P4DS.x
0: Low drive
1: High drive
P4SEL.x
P4IN.x
EN
Module X IN
0
Direction
0: Input
1: Output
1
P4OUT.x
DVSS
P4.0/TB0
P4.1/TB1
P4.2/TB2
P4.3/TB3
P4.4/TB4
P4.5/TB5
P4.6/TB6
P4.7/TBCLK/SMCLK
D
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MSP430F543x, MSP430F541x
MSP430F543xA, MSP430F541xA
SLAS612 – SEPTEMBER 2008.......................................................................................................................................................................................... www.ti.com
Port P4 (P4.0 to P4.7) Pin Functions
PIN NAME (P4.x)
P4.0/TB0
P4.1/TB1
P4.2/TB2
P4.3/TB3
P4.4/TB4
P4.5/TB5
P4.6/TB6
P4.7/TBCLK/SMCLK
(1)
68
x
0
1
2
3
4
5
6
7
FUNCTION
CONTROL BITS/SIGNALS
P4DIR.x
P4SEL.x
I: 0; O: 1
0
Timer_B7.CCI0A and Timer_B7.CCI0B
0
1
Timer_B7.TB0 (1)
1
1
4.0 (I/O)
4.1 (I/O)
I: 0; O: 1
0
Timer_B7.CCI1A and Timer_B7.CCI1B
0
1
Timer_B7.TB1 (1)
1
1
4.2 (I/O)
I: 0; O: 1
0
Timer_B7.CCI2A and Timer_B7.CCI2B
0
1
Timer_B7.TB2 (1)
1
1
4.3 (I/O)
I: 0; O: 1
0
Timer_B7.CCI3A and Timer_B7.CCI3B
0
1
Timer_B7.TB3 (1)
1
1
I: 0; O: 1
0
Timer_B7.CCI4A and Timer_B7.CCI4B
0
1
Timer_B7.TB4 (1)
1
1
I: 0; O: 1
0
Timer_B7.CCI5A and Timer_B7.CCI5B
0
1
Timer_B7.TB5 (1)
1
1
I: 0; O: 1
0
Timer_B7.CCI6A and Timer_B7.CCI6B
0
1
Timer_B7.TB6 (1)
1
1
I: 0; O: 1
0
Timer_B7.TBCLK
0
1
SMCLK
1
1
4.4 (I/O)
4.5 (I/O)
4.6 (I/O)
4.7 (I/O)
Setting TBOUTH causes all Timer_B configured outputs to be set to high impedance.
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MSP430F543xA, MSP430F541xA
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Port P5, P5.0 and P5.1, Input/Output With Schmitt Trigger
Pad Logic
To/From
ADC12 Reference
P5REN.x
P5DIR.x
DVSS
0
DVCC
1
1
0
1
P5OUT.x
0
Module X OUT
1
P5.0/VREF+/VeREF+
P5.1/VREF–/VeREF–
P5DS.x
0: Low drive
1: High drive
P5SEL.x
P5IN.x
Bus
Keeper
EN
Module X IN
D
Port P5 (P5.0 and P5.1) Pin Functions
PIN NAME (P5.x)
P5.0/VREF+/VeREF+
P5.1/VREF–/VeREF–
(1)
(2)
(3)
(4)
(5)
(6)
x
0
1
FUNCTION
CONTROL BITS/SIGNALS (1)
P5DIR.x
P5SEL.x
REFOUT
P5.0 (I/O) (2)
I: 0; O: 1
0
X
VeREF+ (3)
X
1
0
VREF+ (4)
X
1
1
P5.1 (I/O)
(2)
I: 0; O: 1
0
X
VeREF– (5)
X
1
0
VREF– (6)
X
1
1
X = Don't care
Default condition
Setting the P5SEL.0 bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross
analog signals. An external voltage can be applied to VeREF+ and used as the reference for the ADC12_A.
Setting the P5SEL.0 bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross
analog signals. The ADC12_A, VREF+ reference is available at the pin.
Setting the P5SEL.1 bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross
analog signals. An external voltage can be applied to VeREF- and used as the reference for the ADC12_A.
Setting the P5SEL.1 bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross
analog signals. The ADC12_A, VREF– reference is available at the pin.
Copyright © 2008, Texas Instruments Incorporated
currents when applying
currents when applying
currents when applying
currents when applying
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MSP430F543x, MSP430F541x
MSP430F543xA, MSP430F541xA
SLAS612 – SEPTEMBER 2008.......................................................................................................................................................................................... www.ti.com
Port P5, P5.2, Input/Output With Schmitt Trigger
Pad Logic
To XT2
P5REN.2
P5DIR.2
DVSS
0
DVCC
1
1
0
1
P5OUT.2
0
Module X OUT
1
P5DS.2
0: Low drive
1: High drive
P5SEL.2
P5.2/XT2IN
P5IN.2
EN
Module X IN
70
Bus
Keeper
D
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MSP430F543xA, MSP430F541xA
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Port P5, P5.3, Input/Output With Schmitt Trigger
Pad Logic
To XT2
P5REN.3
P5DIR.3
DVSS
0
DVCC
1
1
0
1
P5OUT.3
0
Module X OUT
1
P5.3/XT2OUT
P5DS.3
0: Low drive
1: High drive
P5SEL.3
P5IN.3
Bus
Keeper
EN
Module X IN
D
Port P5 (P5.2) Pin Functions
PIN NAME (P5.x)
P5.2/XT2IN
P5.3/XT2OUT
(1)
(2)
(3)
x
2
3
FUNCTION
CONTROL BITS/SIGNALS (1)
P5DIR.x
P5SEL.2
P5SEL.3
XT2BYPASS
I: 0; O: 1
0
X
X
XT2IN crystal mode (2)
X
1
X
0
XT2IN bypass mode (2)
X
1
X
1
P5.2 (I/O)
P5.3 (I/O)
I: 0; O: 1
0
X
X
XT2OUT crystal mode (3)
X
1
X
0
P5.3 (I/O) (3)
X
1
X
1
X = Don't care
Setting P5SEL.2 causes the general-purpose I/O to be disabled. Pending the setting of XT2BYPASS, P5.2 is configured for crystal
mode or bypass mode.
Setting P5SEL.2 causes the general-purpose I/O to be disabled in crystal mode. When using bypass mode, P5.3 can be used as
general-purpose I/O.
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MSP430F543x, MSP430F541x
MSP430F543xA, MSP430F541xA
SLAS612 – SEPTEMBER 2008.......................................................................................................................................................................................... www.ti.com
Port P5, P5.4 to P5.7, Input/Output With Schmitt Trigger
Pad Logic
P5REN.x
P5DIR.x
0
0
Module X OUT
1
0
DVCC
1
1
Direction
0: Input
1: Output
1
P5OUT.x
DVSS
P5DS.x
0: Low drive
1: High drive
P5SEL.x
P5.4/UCB1SOMI/UCB1SCL
P5.5/UCB1CLK/UCA1STE
P5.6/UCA1TXD/UCA1SIMO
P5.7/UCA1RXD/UCA1SOMI
P5IN.x
EN
Module X IN
D
Port P5 (P5.4 to P5.7) Pin Functions
PIN NAME (P5.x)
x
P5.4/UCB1SOMI/UCB1SCL
4
FUNCTION
P5.4 (I/O)
UCB1SOMI/UCB1SCL
P5.5/UCB1CLK/UCA1STE
5
(2) (3)
P5.5 (I/O)
UCB1CLK/UCA1STE (2)
P5.6/UCA1TXD/UCA1SIMO
6
P5.6 (I/O)
UCA1TXD/UCA1SIMO (2)
P5.7/UCA1RXD/UCA1SOMI
7
P5.7 (I/O)
UCA1RXD/UCA1SOMI (2)
(1)
(2)
(3)
72
CONTROL BITS/SIGNALS (1)
P5DIR.x
P5SEL.x
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
X = Don't care
The pin direction is controlled by the USCI module.
If the I2C functionality is selected, the output drives only the logical 0 to VSS level.
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MSP430F543xA, MSP430F541xA
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Port P6, P6.0 to P6.7, Input/Output With Schmitt Trigger
Pad Logic
To ADC12
INCHx = y
P6REN.x
P6DIR.x
DVSS
0
DVCC
1
1
0
1
P6OUT.x
0
Module X OUT
1
P6DS.x
0: Low drive
1: High drive
P6SEL.x
P6IN.x
EN
Module X IN
Bus
Keeper
P6.0/A0
P6.1/A1
P6.2/A2
P6.3/A3
P6.4/A4
P6.5/A5
P6.6/A6
P6.7/A7
D
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MSP430F543x, MSP430F541x
MSP430F543xA, MSP430F541xA
SLAS612 – SEPTEMBER 2008.......................................................................................................................................................................................... www.ti.com
Port P6 (P6.0 to P6.7) Pin Functions
PIN NAME (P6.x)
P6.0/A0
x
0
FUNCTION
P6.0 (I/O)
A0 (2) (3)
P6.1/A1
1
P6.1 (I/O)
A1 (2) (3)
P6.2/A2
2
P6.2 (I/O)
A2 (2) (3)
P6.3/A3
3
P6.3 (I/O)
A3 (2) (3)
P6.4/A4
4
P6.4 (I/O)
A4 (2) (3)
P6.5/A5
P6.6/A6
5
6
7
(3)
74
P6SEL.x
INCHx
0
X
X
X
0
I: 0; O: 1
0
X
X
X
1
I: 0; O: 1
0
X
X
X
2
I: 0; O: 1
0
X
X
X
3
I: 0; O: 1
0
X
X
X
4
0
X
A5 (1) (2) (3)
X
X
5
P6.6 (I/O)
I: 0; O: 1
0
X
P6.7 (I/O)
A7 (2) (3)
(1)
(2)
P6DIR.x
I: 0; O: 1
I: 0; O: 1
P6.5 (I/O)
A6 (2) (3)
P6.7/A7
CONTROL BITS/SIGNALS (1)
X
X
6
I: 0; O: 1
0
X
X
X
7
X = Don't care
Setting the P6SEL.x bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when applying
analog signals.
The ADC12_A channel Ax is connected internally to AVSS if not selected via the respective INCHx bits.
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MSP430F543xA, MSP430F541xA
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Port P7, P7.0, Input/Output With Schmitt Trigger
Pad Logic
To XT1
P7REN.0
P7DIR.0
DVSS
0
DVCC
1
1
0
1
P7OUT.0
0
Module X OUT
1
P7DS.0
0: Low drive
1: High drive
P7SEL.0
P7.0/XIN
P7IN.0
EN
Module X IN
Bus
Keeper
D
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MSP430F543x, MSP430F541x
MSP430F543xA, MSP430F541xA
SLAS612 – SEPTEMBER 2008.......................................................................................................................................................................................... www.ti.com
Port P7, P7.1, Input/Output With Schmitt Trigger
Pad Logic
To XT1
P7REN.1
P7DIR.1
DVSS
0
DVCC
1
1
0
1
P7OUT.1
0
Module X OUT
1
P7.1/XOUT
P7DS.1
0: Low drive
1: High drive
P7SEL.0
XT1BYPASS
P7IN.1
Bus
Keeper
EN
Module X IN
D
Port P7 (P7.0 and P7.1) Pin Functions
PIN NAME (P7.x)
P7.0/XIN
x
0
FUNCTION
P7DIR.x
P7SEL.0
P7SEL.1
XT1BYPASS
I: 0; O: 1
0
X
X
X
1
X
0
X
1
X
1
I: 0; O: 1
0
X
X
XOUT crystal mode (3)
X
1
X
0
P7.1 (I/O) (3)
X
1
X
1
P7.0 (I/O)
XIN crystal mode
(2)
XIN bypass mode (2)
P7.1/XOUT
(1)
(2)
(3)
76
1
CONTROL BITS/SIGNALS (1)
P7.1 (I/O)
X = Don't care
Setting P7SEL.0 causes the general-purpose I/O to be disabled. Pending the setting of XT1BYPASS, P7.0 is configured for crystal
mode or bypass mode.
Setting P7SEL.0 causes the general-purpose I/O to be disabled in crystal mode. When using bypass mode, P7.1 can be used as
general-purpose I/O.
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MSP430F543xA, MSP430F541xA
www.ti.com.......................................................................................................................................................................................... SLAS612 – SEPTEMBER 2008
Port P7, P7.2 and P7.3, Input/Output With Schmitt Trigger
Pad Logic
P7REN.x
P7DIR.x
0
0
Module X OUT
1
0
DVCC
1
1
Direction
0: Input
1: Output
1
P7OUT.x
DVSS
P7.2/TBOUTH/SVMOUT
P7.3/TA1.2
P7DS.x
0: Low drive
1: High drive
P7SEL.x
P7IN.x
EN
Module X IN
D
Port P7 (P7.2 and P7.3) Pin Functions
PIN NAME (P7.x)
P7.2/TBOUTH/SVMOUT
P7.3/TA1.2
x
2
3
FUNCTION
CONTROL BITS/SIGNALS
P7DIR.x
P7SEL.x
P7.2 (I/O)
I: 0; O: 1
0
TBOUTH
0
1
SVMOUT
1
1
P7.3 (I/O)
I: 0; O: 1
0
Timer1_A3.CCI2B
0
1
Timer1_A3.TA2
1
1
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MSP430F543x, MSP430F541x
MSP430F543xA, MSP430F541xA
SLAS612 – SEPTEMBER 2008.......................................................................................................................................................................................... www.ti.com
Port P7, P7.4 to P7.7, Input/Output With Schmitt Trigger
Pad Logic
To ADC12
INCHx = y
P7REN.x
P7DIR.x
DVSS
0
DVCC
1
1
0
1
P7OUT.x
0
Module X OUT
1
P7.4/A12
P7.5/A13
P7.6/A14
P7.7/A15
P7DS.x
0: Low drive
1: High drive
P7SEL.x
P7IN.x
Bus
Keeper
EN
Module X IN
D
Port P7 (P7.4 to P7.7) Pin Functions
PIN NAME (P7.x)
P7.4/A12
P7.5/A13
x
4
5
FUNCTION
P7DIR.x
P7SEL.x
P7.4 (I/O)
I: 0; O: 1
0
X
A12 (2) (3)
X
X
12
P7.5 (I/O)
I: 0; O: 1
0
X
13
A13
P7.6/A14
P7.7/A15
(1)
(2)
(3)
(4)
(5)
78
6
7
CONTROL BITS/SIGNALS (1)
(4) (5)
INCHx
X
X
P7.6 (I/O)
I: 0; O: 1
0
X
A14 (4) (5)
X
X
14
P7.7 (I/O)
I: 0; O: 1
0
X
A15 (4) (5)
X
X
15
X = Don't care
Setting the P7SEL.x bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when applying
analog signals.
The ADC12_A channel Ax is connected internally to AVSS if not selected via the respective INCHx bits.
Setting the P7SEL.x bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when applying
analog signals.
The ADC12_A channel Ax is connected internally to AVSS if not selected via the respective INCHx bits.
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MSP430F543x, MSP430F541x
MSP430F543xA, MSP430F541xA
www.ti.com.......................................................................................................................................................................................... SLAS612 – SEPTEMBER 2008
Port P8, P8.0 to P8.7, Input/Output With Schmitt Trigger
Pad Logic
P8REN.x
P8DIR.x
0
0
Module X OUT
1
0
DVCC
1
1
Direction
0: Input
1: Output
1
P8OUT.x
DVSS
P8.0/TA0.0
P8.1/TA0.1
P8.2/TA0.2
P8.3/TA0.3
P8.4/TA0.4
P8.5/TA1.0
P8.6/TA1.1
P8.7
P8DS.x
0: Low drive
1: High drive
P8SEL.x
P8IN.x
EN
Module X IN
D
Port P8 (P8.0 to P8.7) Pin Functions
PIN NAME (P8.x)
P8.0/TA0.0
x
0
FUNCTION
P8.0 (I/O)
Timer0_A5.CCI0B
Timer0_A5.TA0
P8.1/TA0.1
1
P8.1 (I/O)
Timer0_A5.CCI1B
Timer0_A5.TA1
P8.2/TA0.2
P8.3/TA0.3
P8.4/TA0.4
P8.5/TA1.0
P8.6/TA1.1
P8.7
2
3
4
5
6
7
CONTROL BITS/SIGNALS
P8DIR.x
P8SEL.x
I: 0; O: 1
0
0
1
1
1
I: 0; O: 1
0
0
1
1
1
I: 0; O: 1
0
Timer0_A5.CCI2B
0
1
Timer0_A5.TA2
1
1
P8.2 (I/O)
P8.3 (I/O)
I: 0; O: 1
0
Timer0_A5.CCI3B
0
1
Timer0_A5.TA3
1
1
P8.4 (I/O)
I: 0; O: 1
0
Timer0_A5.CCI4B
0
1
Timer0_A5.TA4
1
1
P8.5 (I/O)
I: 0; O: 1
0
Timer1_A3.CCI0B
0
1
Timer1_A3.TA0
1
1
I: 0; O: 1
0
Timer1_A3.CCI1B
0
1
Timer1_A3.TA1
1
1
I: 0; O: 1
0
P8.6 (I/O)
P8.7 (I/O)
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MSP430F543x, MSP430F541x
MSP430F543xA, MSP430F541xA
SLAS612 – SEPTEMBER 2008.......................................................................................................................................................................................... www.ti.com
Port P9, P9.0 to P9.7, Input/Output With Schmitt Trigger
Pad Logic
P9REN.x
P9DIR.x
0
0
Module X OUT
1
0
DVCC
1
P9DS.x
0: Low drive
1: High drive
P9SEL.x
P9IN.x
EN
Module X IN
1
Direction
0: Input
1: Output
1
P9OUT.x
DVSS
P9.0/UCB2STE/UCA2CLK
P9.1/UCB2SIMO/UCB2SDA
P9.2/UCB2SOMI/UCB2SCL
P9.3/UCB2CLK/UCA2STE
P9.4/UCA2TXD/UCA2SIMO
P9.5/UCA2RXD/UCA2SOMI
P9.6
P9.7
D
Port P9 (P9.0 to P9.7) Pin Functions
PIN NAME (P9.x)
P9.0/UCB2STE/UCA2CLK
x
0
FUNCTION
P9.0 (I/O)
UCB2STE/UCA2CLK
P9.1/UCB2SIMO/UCB2SDA
1
(2) (3)
P9.1 (I/O)
UCB2SIMO/UCB2SDA (2) (4)
P9.2/UCB2SOMI/UCB2SCL
2
P9.2 (I/O)
UCB2SOMI/UCB2SCL (2) (4)
P9.3/UCB2CLK/UCA2STE
3
P9.3 (I/O)
UCB2CLK/UCA2STE (2)
P9.4/UCA2TXD/UCA2SIMO
4
P9.4 (I/O)
UCA2TXD/UCA2SIMO (2)
P9.5/UCA2RXD/UCA2SOMI
5
P9.5 (I/O)
UCA2RXD/UCA2SOMI
(2)
CONTROL BITS/SIGNALS (1)
P9DIR.x
P9SEL.x
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
P9.6
6
P9.6 (I/O)
I: 0; O: 1
0
P9.7
7
P9.7 (I/O)
I: 0; O: 1
0
(1)
(2)
(3)
(4)
80
X = Don't care
The pin direction is controlled by the USCI module.
UCA2CLK function takes precedence over UCB2STE function. If the pin is required as UCA2CLK input or output, USCI A2/B2 is forced
to 3-wire SPI mode if 4-wire SPI mode is selected.
If the I2C functionality is selected, the output drives only the logical 0 to VSS level.
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MSP430F543x, MSP430F541x
MSP430F543xA, MSP430F541xA
www.ti.com.......................................................................................................................................................................................... SLAS612 – SEPTEMBER 2008
Port P10, P10.0 to P10.7, Input/Output With Schmitt Trigger
Pad Logic
P10REN.x
P10DIR.x
0
0
Module X OUT
1
0
DVCC
1
1
Direction
0: Input
1: Output
1
P10OUT.x
DVSS
P10DS.x
0: Low drive
1: High drive
P10SEL.x
P10IN.x
EN
Module X IN
P10.0/UCB3STE/UCA3CLK
P10.1/UCB3SIMO/UCB3SDA
P10.2/UCB3SOMI/UCB3SCL
P10.3/UCB3CLK/UCA3STE
P10.4/UCA3TXD/UCA3SIMO
P10.5/UCA3RXD/UCA3SOMI
P10.6
P10.7
D
Port P10 (P10.0 to P10.7) Pin Functions
PIN NAME (P10.x)
P10.0/UCB3STE/UCA3CLK
x
0
FUNCTION
P10.0 (I/O)
UCB3STE/UCA3CLK (2) (3)
P10.1/UCB3SIMO/UCB3SDA
1
P10.1 (I/O)
UCB3SIMO/UCB3SDA
P10.2/UCB3SOMI/UCB3SCL
2
(2) (4)
P10.2 (I/O)
UCB3SOMI/UCB3SCL (2) (4)
P10.3/UCB3CLK/UCA3STE
3
P10.3 (I/O)
UCB3CLK/UCA3STE (2)
P10.4/UCA3TXD/UCA3SIMO
4
P10.4 (I/O)
UCA3TXD/UCA3SIMO (2)
P10.5/UCA3RXD/UCA3SOMI
5
P10.5 (I/O)
UCA3RXD/UCA3SOMI (2)
P10.6
6
P10.6 (I/O)
Reserved
P10.7
(1)
(2)
(3)
(4)
(5)
7
(5)
CONTROL BITS/SIGNALS (1)
P10DIR.x
P10SEL.x
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
P10.7 (I/O)
I: 0; O: 1
0
Reserved (5)
x
1
X = Don't care
The pin direction is controlled by the USCI module.
UCA3CLK function takes precedence over UCB3STE function. If the pin is required as UCA3CLK input or output, USCI A3/B3 is forced
to 3-wire SPI mode if 4-wire SPI mode is selected.
If the I2C functionality is selected, the output drives only the logical 0 to VSS level.
The secondary function on these pins are reserved for factory test purposes. Application should keep the P10SEL.x of these ports
cleared to prevent potential conflicts with the application.
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MSP430F543x, MSP430F541x
MSP430F543xA, MSP430F541xA
SLAS612 – SEPTEMBER 2008.......................................................................................................................................................................................... www.ti.com
Port P11, P11.0 to P11.2, Input/Output With Schmitt Trigger
Pad Logic
P11REN.x
P11DIR.x
0
0
Module X OUT
1
0
DVCC
1
1
Direction
0: Input
1: Output
1
P11OUT.x
DVSS
P11.0/ACLK
P11.1/MCLK
P11.2/SMCLK
P11DS.x
0: Low drive
1: High drive
P11SEL.x
P11IN.x
EN
Module X IN
D
Port P11 (P11.0 to P11.2) Pin Functions
PIN NAME (P11.x)
P11.0/ACLK
x
0
FUNCTION
P11.0 (I/O)
ACLK
P11.1/MCLK
1
P11.1 (I/O)
MCLK
P11.2/SMCLK
2
P11.2 (I/O)
SMCLK
82
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CONTROL BITS/SIGNALS
P11DIR.x
P11SEL.x
I: 0; O: 1
0
1
1
I: 0; O: 1
0
1
1
I: 0; O: 1
0
1
1
Copyright © 2008, Texas Instruments Incorporated
MSP430F543x, MSP430F541x
MSP430F543xA, MSP430F541xA
www.ti.com.......................................................................................................................................................................................... SLAS612 – SEPTEMBER 2008
Port J, J.0 JTAG pin TDO, Input/Output With Schmitt Trigger or Output
Pad Logic
PJREN.0
PJDIR.0
0
DVCC
1
PJOUT.0
0
From JTAG
1
DVSS
0
DVCC
1
1
PJ.0/TDO
PJDS.0
0: Low drive
1: High drive
From JTAG
PJIN.0
EN
D
Port J, J.1 to J.3 JTAG pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger or Output
Pad Logic
PJREN.x
PJDIR.x
0
DVSS
1
PJOUT.x
0
From JTAG
1
DVSS
0
DVCC
1
PJDS.x
0: Low drive
1: High drive
From JTAG
1
PJ.1/TDI/TCLK
PJ.2/TMS
PJ.3/TCK
PJIN.x
EN
To JTAG
D
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MSP430F543x, MSP430F541x
MSP430F543xA, MSP430F541xA
SLAS612 – SEPTEMBER 2008.......................................................................................................................................................................................... www.ti.com
Port PJ (PJ.0 to PJ.3) Pin Functions
PIN NAME (PJ.x)
x
CONTROL BITS/
SIGNALS (1)
FUNCTION
PJDIR.x
PJ.0/TDO
0
PJ.0 (I/O) (2)
I: 0; O: 1
TDO (3)
PJ.1/TDI/TCLK
1
PJ.1 (I/O)
X
(2)
I: 0; O: 1
TDI/TCLK (3) (4)
PJ.2/TMS
2
X
PJ.2 (I/O) (2)
I: 0; O: 1
TMS (3) (4)
PJ.3/TCK
3
X
PJ.3 (I/O) (2)
I: 0; O: 1
TCK (3) (4)
(1)
(2)
(3)
(4)
84
X
X = Don't care
Default condition
The pin direction is controlled by the JTAG module.
In JTAG mode, pullups are activated automatically on TMS, TCK, and TDI/TCLK. PJREN.x are do not care.
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MSP430F543x, MSP430F541x
MSP430F543xA, MSP430F541xA
www.ti.com.......................................................................................................................................................................................... SLAS612 – SEPTEMBER 2008
Data Sheet Revision History
REVISION
DESCRIPTION
SLAS612
Initial release
Copyright © 2008, Texas Instruments Incorporated
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PACKAGE OPTION ADDENDUM
www.ti.com
26-Sep-2008
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
MSP430F5418IPN
ACTIVE
LQFP
PN
80
119
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
MSP430F5418IPNR
ACTIVE
LQFP
PN
80
1000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
MSP430F5419IPZ
ACTIVE
LQFP
PZ
100
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
MSP430F5419IPZR
ACTIVE
LQFP
PZ
100
1000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
MSP430F5435IPN
ACTIVE
LQFP
PN
80
119
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
MSP430F5435IPNR
ACTIVE
LQFP
PN
80
1000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
MSP430F5436IPZ
ACTIVE
LQFP
PZ
100
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
MSP430F5436IPZR
ACTIVE
LQFP
PZ
100
1000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
MSP430F5437IPN
ACTIVE
LQFP
PN
80
119
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
MSP430F5437IPNR
ACTIVE
LQFP
PN
80
1000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
MSP430F5438IPZ
ACTIVE
LQFP
PZ
100
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
MSP430F5438IPZR
ACTIVE
LQFP
PZ
100
1000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
XMS430F5438IPZ
PREVIEW
LQFP
PZ
100
90
90
90
90
TBD
Lead/Ball Finish
Call TI
MSL Peak Temp (3)
Call TI
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
26-Sep-2008
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
MECHANICAL DATA
MTQF010A – JANUARY 1995 – REVISED DECEMBER 1996
PN (S-PQFP-G80)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
0,08 M
41
60
61
40
80
21
0,13 NOM
1
20
Gage Plane
9,50 TYP
12,20
SQ
11,80
14,20
SQ
13,80
0,25
0,05 MIN
0°– 7°
0,75
0,45
1,45
1,35
Seating Plane
0,08
1,60 MAX
4040135 / B 11/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
MECHANICAL DATA
MTQF013A – OCTOBER 1994 – REVISED DECEMBER 1996
PZ (S-PQFP-G100)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
75
0,08 M
51
76
50
100
26
1
0,13 NOM
25
12,00 TYP
Gage Plane
14,20
SQ
13,80
16,20
SQ
15,80
0,05 MIN
1,45
1,35
0,25
0°– 7°
0,75
0,45
Seating Plane
0,08
1,60 MAX
4040149 /B 11/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
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products in automotive applications, TI will not be responsible for any failure to meet such requirements.
Following are URLs where you can obtain information on other Texas Instruments products and application solutions:
Products
Amplifiers
Data Converters
DSP
Clocks and Timers
Interface
Logic
Power Mgmt
Microcontrollers
RFID
RF/IF and ZigBee® Solutions
amplifier.ti.com
dataconverter.ti.com
dsp.ti.com
www.ti.com/clocks
interface.ti.com
logic.ti.com
power.ti.com
microcontroller.ti.com
www.ti-rfid.com
www.ti.com/lprf
Applications
Audio
Automotive
Broadband
Digital Control
Medical
Military
Optical Networking
Security
Telephony
Video & Imaging
Wireless
www.ti.com/audio
www.ti.com/automotive
www.ti.com/broadband
www.ti.com/digitalcontrol
www.ti.com/medical
www.ti.com/military
www.ti.com/opticalnetwork
www.ti.com/security
www.ti.com/telephony
www.ti.com/video
www.ti.com/wireless
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