[ /Title (CD74 HC174 , CD74 HCT17 4) /Subject (High Speed CMOS Logic Hex DType FlipFlop CD54HC174, CD74HC174, CD54HCT174, CD74HCT174 Data sheet acquired from Harris Semiconductor SCHS159C High-Speed CMOS Logic Hex D-Type Flip-Flop with Reset August 1997 - Revised October 2003 Features times is transferred to the Q output on the low to high transition of the CLOCK input. The MR input, when low, sets all outputs to a low state. • Buffered Positive Edge Triggered Clock • Asynchronous Common Reset Each output can drive ten low power Schottky TTL equivalent loads. The ’HCT174 is functional as well as, pin compatible to the ’LS174. • Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads Ordering Information • Wide Operating Temperature Range . . . -55oC to 125oC • Balanced Propagation Delay and Transition Times PART NUMBER • Significant Power Reduction Compared to LSTTL Logic ICs • HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V • HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH Description The ’HC174 and ’HCT174 are edge triggered flip-flops which utilize silicon gate CMOS circuitry to implement D-type flipflops. They possess low power and speeds comparable to low power Schottky TTL circuits. The devices contain six masterslave flip-flops with a common clock and common reset. Data on the D input having the specified setup and hold TEMP. RANGE (oC) CD54HC174F3A -55 to 125 16 Ld CERDIP CD54HCT174F3A -55 to 125 16 Ld CERDIP CD74HC174E -55 to 125 16 Ld PDIP CD74HC174M -55 to 125 16 Ld SOIC CD74HC174MT -55 to 125 16 Ld SOIC CD74HC174M96 -55 to 125 16 Ld SOIC CD74HCT174E -55 to 125 16 Ld PDIP CD74HCT174M -55 to 125 16 Ld SOIC CD74HCT174MT -55 to 125 16 Ld SOIC CD74HCT174M96 -55 to 125 16 Ld SOIC NOTE: When ordering, use the entire part number. The suffix 96 denotes tape and reel. The suffix T denotes a small-quantity reel of 250. Pinout CD54HC174, CD54HCT174 (CERDIP) CD74HC174, CD74HCT174 (PDIP, SOIC) TOP VIEW MR 1 16 VCC Q0 2 15 Q5 D0 3 14 D5 D1 4 13 D4 Q1 5 12 Q4 D2 6 11 D3 Q2 7 10 Q3 GND 8 9 CP CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © 2003, Texas Instruments Incorporated PACKAGE 1 CD54HC174, CD74HC174, CD54HCT174, CD74HCT174 Functional Diagram CP CP D R D0 Q0 D1 Q1 D2 Q2 D3 Q3 D4 Q4 D5 Q5 MR TRUTH TABLE INPUTS OUTPUT RESET (MR) CLOCK CP DATA Dn Qn L X X L H ↑ H H H ↑ L L H L X Q0 H = High Voltage Level, L = Low Voltage Level, X = Irrelevant, ↑ = Transition from Low to High Level, Q0 = Level Before the Indicated Steady-State Input Conditions Were Established Logic Diagram 3 (4, 6, 11, 13, 14) Dn D CL CL p p n n CL CL CL CL p p n n CL CL R ONE OF SIX F/F CL CL Q 2 (5, 7, 10, 12, 15) Qn CP 8 16 1 MR TO OTHER FIVE F/F VCC 9 CP TO OTHER FIVE F/F 2 CD54HC174, CD74HC174, CD54HCT174, CD74HCT174 Absolute Maximum Ratings Thermal Information DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, IIK For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA DC Output Diode Current, IOK For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA DC Output Source or Sink Current per Output Pin, IO For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA DC VCC or Ground Current, ICC or IGND . . . . . . . . . . . . . . . . . .±50mA Thermal Resistance (Typical, Note 1) θJA (oC/W) E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . 67 M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . 73 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only) Operating Conditions Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Supply Voltage Range, VCC HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Time 2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max) 4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max) 6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. The package thermal impedance is calculated in accordance with JESD 51-7. DC Electrical Specifications TEST CONDITIONS PARAMETER SYMBOL VI (V) High Level Input Voltage VIH - Low Level Input Voltage VIL 25oC IO (mA) VCC (V) -40oC TO +85oC -55oC TO 125oC MIN TYP MAX MIN MAX MIN MAX UNITS 2 1.5 - - 1.5 - 1.5 - V 4.5 3.15 - - 3.15 - 3.15 - V 6 4.2 - - 4.2 - 4.2 - V 2 - - 0.5 - 0.5 - 0.5 V 4.5 - - 1.35 - 1.35 - 1.35 V 6 - - 1.8 - 1.8 - 1.8 V -0.02 2 1.9 - - 1.9 - 1.9 - V -0.02 4.5 4.4 - - 4.4 - 4.4 - V -0.02 6 5.9 - - 5.9 - 5.9 - V -4 4.5 3.98 - - 3.84 - 3.7 - V -5.2 6 5.48 - - 5.34 - 5.2 - V HC TYPES High Level Output Voltage CMOS Loads VOH - VIH or VIL High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads VOL VIH or VIL Low Level Output Voltage TTL Loads Input Leakage Current Quiescent Device Current - - 0.02 2 - - 0.1 - 0.1 - 0.1 V 0.02 4.5 - - 0.1 - 0.1 - 0.1 V 0.02 6 - - 0.1 - 0.1 - 0.1 V 4 4.5 - - 0.26 - 0.33 - 0.4 V 5.2 6 - - 0.26 - 0.33 - 0.4 V II VCC or GND - 6 - - ±0.1 - ±1 - ±1 µA ICC VCC or GND 0 6 - - 8 - 80 - 160 µA 3 CD54HC174, CD74HC174, CD54HCT174, CD74HCT174 DC Electrical Specifications (Continued) TEST CONDITIONS SYMBOL VI (V) High Level Input Voltage VIH - - Low Level Input Voltage VIL - High Level Output Voltage CMOS Loads VOH VIH or VIL PARAMETER 25oC IO (mA) VCC (V) -40oC TO +85oC -55oC TO 125oC MIN TYP MAX MIN MAX MIN MAX UNITS 4.5 to 5.5 2 - - 2 - 2 - V - 4.5 to 5.5 - - 0.8 - 0.8 - 0.8 V -0.02 4.5 4.4 - - 4.4 - 4.4 - V -4 4.5 3.98 - - 3.84 - 3.7 - V 0.02 4.5 - - 0.1 - 0.1 - 0.1 V 4 4.5 - - 0.26 - 0.33 - 0.4 V HCT TYPES High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads VOL VIH or VIL Low Level Output Voltage TTL Loads Input Leakage Current Quiescent Device Current Additional Quiescent Device Current Per Input Pin: 1 Unit Load II VCC to GND 0 5.5 - - ±0.1 - ±1 - ±1 µA ICC VCC or GND 0 5.5 - - 8 - 80 - 160 µA ∆ICC (Note 2) VCC -2.1 - 4.5 to 5.5 - 100 360 - 450 - 490 µA NOTE: 2. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA. HCT Input Loading Table INPUT UNIT LOADS CP 0.80 MR 0.55 D 0.15 NOTE: Unit Load is ∆ICC limit specified in DC Electrical Specifications table, e.g. 360µA max at 25oC. Prerequisite For Switching Function PARAMETER SYMBOL TEST CONDITIONS VCC (V) 25oC -40oC TO 85oC -55oC TO 125oC MIN MAX MIN MAX MIN MAX UNITS 2 80 - 100 - 120 - ns 4.5 16 - 20 - 24 - ns 6 14 - 17 - 20 - ns 2 80 - 100 - 120 - ns 4.5 16 - 20 - 24 - ns 6 14 - 17 - 20 - ns HC TYPES Clock Pulse Width MR Pulse Width tw tw - - 4 CD54HC174, CD74HC174, CD54HCT174, CD74HCT174 Prerequisite For Switching Function PARAMETER SYMBOL Setup Time, Data to Clock (Continued) TEST CONDITIONS VCC (V) tSU Hold Time, Data to Clock Removal Time, MR to Clock Clock Frequency MAX MIN MAX MIN MAX UNITS 2 60 - 75 - 90 - ns 4.5 12 - 15 - 18 - ns 6 10 - 13 - 15 - ns 2 5 - 5 - 5 - ns 4.5 5 - 5 - 5 - ns 6 5 - 5 - 5 - ns 2 5 - 5 - 5 - ns 4.5 5 - 5 - 5 - ns 6 5 - 5 - 5 - ns 2 6 - 5 - 4 - MHz 4.5 30 - 24 - 20 - MHz 6 35 - 28 - 24 - MHz - tREM - fMAX -40oC TO 85oC -55oC TO 125oC MIN - tH 25oC - HCT TYPES Clock Pulse Width tw - 4.5 20 - 25 - 30 - ns MR Pulse Width tw - 6 25 - 31 - 38 - ns Setup Time, Data to Clock tSU - 4.5 16 - 20 - 24 - ns Hold Time, Data to Clock tH - 6 5 - 5 - 5 - ns Removal Time, MR to Clock tREM - 4.5 12 - 15 - 18 - ns Clock Frequency fMAX - 6 25 - 20 - 17 - MHz Switching Specifications PARAMETER Input tr, tf = 6ns SYMBOL TEST CONDITIONS tPLH, tPHL CL = 50pF 25oC -40oC TO 85oC -55oC TO 125oC VCC (V) TYP MAX MAX MAX UNITS 2 - 165 205 250 ns 4.5 - 33 41 50 ns 6 - 28 35 43 ns CL = 15pF 5 13 - - - ns CL = 50pF 2 - 150 190 225 ns 4.5 - 30 38 45 ns 6 - 26 33 38 ns CL = 15pF 5 12 - - - ns CL = 50pF 2 - 75 95 110 ns 4.5 - 15 19 22 ns 6 - 13 16 19 ns HC TYPES Propagation Delay, Clock to Q Propagation Delay, MR to Q Output Transition Times tPLH, tPHL tTLH, tTHL Input Capacitance CIN - - - 10 10 10 pF Power Dissipation Capacitance (Notes 3, 4) CPD - 5 38 - - - pF 5 CD54HC174, CD74HC174, CD54HCT174, CD74HCT174 Switching Specifications PARAMETER Input tr, tf = 6ns (Continued) SYMBOL TEST CONDITIONS tPLH, tPHL 25oC -40oC TO 85oC -55oC TO 125oC VCC (V) TYP MAX MAX MAX UNITS CL = 50pF 4.5 - 40 50 60 ns CL = 15pF 5 17 - - - ns CL = 50pF 4.5 - 44 55 66 ns CL = 15pF 5 18 - - - ns CL = 50pF 4.5 - 15 19 22 ns HCT TYPES Propagation Delay, Clock to Q Propagation Delay, MR to Q tPLH, tPHL Output Transition Times tTLH, tTHL Input Capacitance CIN - - - 10 10 10 pF Power Dissipation Capacitance (Notes 3, 4) CPD - 5 44 - - - pF NOTES: 3. CPD is used to determine the dynamic power consumption, per flip-flop. 4. PD = VCC2 fi + ∑ (CL VCC2 + fO) where fi = Input Frequency, fO = Input Frequency, CL = Output Load Capacitance, VCC = Supply Voltage. Test Circuits and Waveforms CLOCK INPUT trCL tfCL trCL VCC 90% GND tH(H) GND tH(H) VCC DATA INPUT 50% tH(L) 3V 1.3V 1.3V 1.3V GND tSU(H) tSU(H) tSU(L) tTLH 90% OUTPUT tTHL 90% 50% 10% tTLH 90% 1.3V OUTPUT tREM 3V SET, RESET OR PRESET GND tTHL 1.3V 10% FIGURE 1. HC SETUP TIMES, HOLD TIMES, REMOVAL TIME, AND PROPAGATION DELAY TIMES FOR EDGE TRIGGERED SEQUENTIAL LOGIC CIRCUITS tPHL 1.3V GND IC CL 50pF GND 90% tPLH 50% IC tSU(L) tPHL tPLH tREM VCC SET, RESET OR PRESET 1.3V 0.3V tH(L) DATA INPUT 3V 2.7V CLOCK INPUT 50% 10% tfCL CL 50pF FIGURE 2. HCT SETUP TIMES, HOLD TIMES, REMOVAL TIME, AND PROPAGATION DELAY TIMES FOR EDGE TRIGGERED SEQUENTIAL LOGIC CIRCUITS 6 PACKAGE OPTION ADDENDUM www.ti.com 26-Sep-2005 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty 5962-8974301EA ACTIVE CDIP J 16 1 TBD Call TI Level-NC-NC-NC CD54HC174F ACTIVE CDIP J 16 1 TBD Call TI Level-NC-NC-NC CD54HC174F3A ACTIVE CDIP J 16 1 TBD Call TI Level-NC-NC-NC CD54HCT174F ACTIVE CDIP J 16 1 TBD Call TI Level-NC-NC-NC CD54HCT174F3A ACTIVE CDIP J 16 1 TBD Call TI Level-NC-NC-NC CD74HC174E ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU Level-NC-NC-NC CD74HC174M ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC174M96 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC174M96E4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC174ME4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC174MT ACTIVE SOIC D 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC174MTE4 ACTIVE SOIC D 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HCT174E ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU Level-NC-NC-NC CD74HCT174EE4 ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU Level-NC-NC-NC CD74HCT174M ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HCT174M96 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HCT174M96E4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HCT174ME4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HCT174MT ACTIVE SOIC D 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HCT174MTE4 ACTIVE SOIC D 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 26-Sep-2005 retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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