MITSUBISHI LSIs SGRAM (Rev. 0.0) M5M4V16G50DFP -8, -10, -12 Jan'97 Preliminary 16M (2-BANK x 262144-WORD x 32-BIT) Synchronous Graphics RAM PRELIMINARY Some of contents are described for general products and are subject to change without notice. DESCRIPTION The M5M4V16G50DFP is a 2-bank x 262,144-word x 32-bit Synchronous GRAM, with LVTTL interface. All inputs and outputs are referenced to the rising edge of CLK. The M5M4V16G50DFP can operate at frequencies of 100+ MHz. The BLOCK WRITE and WRITE-PER-BIT functions provide improved performance in graphic memory systems. FEATURES - Single 3.3v±0.3v power supply - Clock frequencies of 125 MHz - Fully synchronous operation referenced to clock rising edge - Dual bank operation controlled by A10(Bank Address) - Internal pipelined operation: column address can be changed every clock cycle - Programmable /CAS Latency (LVTTL: 2 and 3) - Programmable Burst Length (1/2/4/8 and Full Page) - Programmable Burst Type (Sequential / Interleave) - Byte control using DQM0 - DQM3 signals in both read and write cycles - Persistent Write-Per-Bit (WPB) function - 8 Column Block Write (BW) function - Auto Precharge / All bank precharge controlled by A9 - Auto Refresh and Self Refresh Capability - 2048 refresh cycles /32ms - LVTTL Interface - 100 pin QFP package with 0.65mm lead pitch Max. Frequency CLK Access Time M5M4V16G50DFP - 8 125MHz 7ns M5M4V16G50DFP- 10 100MHz 8ns M5M4V16G50DFP- 12 83MHz 10ns MITSUBISHI ELECTRIC MITSUBISHI LSIs SGRAM (Rev. 0.0) M5M4V16G50DFP -8, -10, -12 Jan'97 Preliminary 80 DQ28 VDDQ 79 DQ27 78 DQ26 77 VSSQ 76 DQ25 75 DQ24 74 VDDQ 73 DQ15 72 71 DQ14 70 VSSQ 69 DQ13 68 DQ12 67 VDDQ 66 VSS 65 VDD 64 DQ11 63 DQ10 62 VSSQ 61 DQ9 60 DQ8 59 VDDQ 58 NC 57 DQM3 56 DQM1 55 CLK 54 CKE 53 DSF 52 NC 51 A9 16M (2-BANK x 262144-WORD x 32-BIT) Synchronous Graphics RAM 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 100 Pin QFP 14.0 x 20.0 mm2 CLK CKE /CS /RAS /CAS /WE DSF A0-10 A0-9 A0-7 A10 DQ0-31 DQM0-3 Vdd VddQ Vss VssQ 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 14 VDD 15 VSS 16 DQ20 17 DQ21 18 VSSQ 19 DQ22 20 DQ23 21 VDDQ 22 DQM0 23 DQM2 24 /WE 25 /CAS 26 /RAS 27 /CS 28 A10 29 A8 30 12 13 10 11 1 2 3 4 5 6 7 8 9 0.65 mm pitch DQ3 VDDQ DQ4 DQ5 VSSQ DQ6 DQ7 VDDQ DQ16 DQ17 VSSQ DQ18 DQ19 VDDQ DQ29 VSSQ DQ30 DQ31 VSS NC NC NC NC NC NC NC NC NC NC VDD DQ0 DQ1 VSSQ DQ2 : Master Clock : Clock Enable : Chip Select : Row Address Strobe : Column Address Strobe : Write Enable : Special Function Enable : Address Input : Row Address inputs : Column Address inputs : Bank Address : Data I/O : Output Disable/ Write Mask : Power Supply : Power Supply for Output : Ground : Ground for Output MITSUBISHI ELECTRIC A7 A6 A5 A4 VSS NC NC NC NC NC NC NC NC NC NC VDD A3 A2 A1 A0 MITSUBISHI LSIs SGRAM (Rev. 0.0) M5M4V16G50DFP -8, -10, -12 Jan'97 Preliminary 16M (2-BANK x 262144-WORD x 32-BIT) Synchronous Graphics RAM DQ0-31 BLOCK DIAGRAM DQM0-3 Color Register I/O Buffer Mask Register Memory Array Memory Array Bank #0 Bank #1 Mode Register Control Circuitry Address Buffer A0-9 A10 Control Signal Buffer Clock Buffer CLK /CS /RAS /CAS /WE DSF CKE Type Designation Code This rule is applied only to Synchronous DRAM family. M 5M 4 V 16 G 5 0 D FP - 8 Cycle Time (min.) 8: 8ns, 10: 10ns, 12: 12ns Package Type FP: QFP Process Generation Function 0: Random Column, 1: 2N-rule Organization 2 n 5: x32 Synchronous Graphics RAM Density 16:16M bits Interface V:LVTTL Memory Style (DRAM) Use, Recommended Operating Conditions, etc Mitsubishi Main Designation MITSUBISHI ELECTRIC MITSUBISHI LSIs SGRAM (Rev. 0.0) M5M4V16G50DFP -8, -10, -12 Jan'97 Preliminary 16M (2-BANK x 262144-WORD x 32-BIT) Synchronous Graphics RAM PIN FUNCTION CLK Input Master Clock: All other inputs are referenced to the rising edge of CLK. CKE Input Clock Enable: CKE controls internal clock. When CKE is low, internal clock for the following cycle is stopped. CKE is also used to select auto / self refresh. After self refresh mode is started, CKE becomes asynchronous input. Self refresh is maintained as long as CKE is low. /CS Input Chip Select: When /CS is high, any command means No Operation. /RAS, /CAS, / WE, and DSF Input Combination of /RAS, /CAS, /WE, and DSF defines basic commands. A0-9 Input A0-9 specify the Row / Column Address in conjunction with BA. The Row Address is specified by A0-9. The Column Address is specified by A0-7. A9 is also used to indicate precharge option. When A9 is high at a read / write command, an auto precharge is performed. When A9 is high at a precharge command, both banks are precharged. A10 Input Bank Address: A10 (BA) specifies the bank to which a command is applied. A10 (BA) must be set with ACT, PRE, READ, WRITE commands. DQ0-31 DQM0 DQM3 Input / Output Input Data In/Data out are referenced to the rising edge of CLK. These pins are used for input mask pins for Write-Per-Bit and column/byte mask inputs for Block Writes. Input/Output Byte Mask: When DQM0-3 are high during a write, data for the current cycle is masked. When DQM0-3 are high during a read, output data is disabled at the next cycle. DQM0 controls byte 0 (DQ7-0), DQM1 controls byte 1 (DQ15-8), DQM2 controls byte 2 (DQ23-16), and DQM3 controls byte 3 (DQ31-24). VREF Input Reference voltage for all inputs. Vdd, Vss Power Supply Power Supply for the memory array and peripheral circuitry. VddQ, VssQ Power Supply VddQ and VssQ are supplied to the Output Buffers only. MITSUBISHI ELECTRIC MITSUBISHI LSIs SGRAM (Rev. 0.0) Jan'97 Preliminary M5M4V16G50DFP -8, -10, -12 16M (2-BANK x 262144-WORD x 32-BIT) Synchronous Graphics RAM BASIC FUNCTIONS The M5M4V16G50DFP provides basic functions, bank (row) activate, burst read / write, bank (row) precharge, and auto / self refresh. Each command is defined by control signals of /RAS, /CAS, /WE, and DSF at CLK rising edge. In addition to 3 signals, /CS ,CKE and A9 are used as chip select, refresh option, and precharge option, respectively. For a more detailed definition of commands, please see the command truth table. CLK /CS Chip Select : L=select, H=deselect /RAS Command /CAS Command /WE Command DSF Command CKE Refresh Option @refresh command A9 Precharge Option @precharge or read/write command define basic commands Activate (ACT) [/CS, /RAS, DSF = L, /CAS, /WE = H] ACT command activates a row in an idle bank indicated by A10 (BA) and row address selected by A0 - A9. Activate with WPB enable (ACTWPB) [/CS, /RAS = L, /CAS, /WE, DSF = H] This command is the same as Activate except that Write-Per-Bit (WPB) is enabled. The Mask Register’s contents are used as the WPB data. Read (READ) [/CS, /CAS, DSF = L, /RAS, /WE = H] READ command starts burst read from the active bank indicated by A10 (BA). First output data appears after /CAS latency. When A9 = H at this command, the bank is deactivated after the burst read (auto-precharge, READA). Write (WRITE) [/CS, /CAS, /WE, DSF = L, /RAS = H] WRITE command starts burst write to the active bank indicated by A10 (BA). Total data length to be written is set by burst length. When A9 = H at this command, the bank is deactivated after the burst write (auto-precharge, WRITEA). Precharge (PRE) [/CS, /RAS, /WE, DSF = L, /CAS = H] PRE command deactivates the active bank indicated by A10 (BA). This command also terminates burst read /write operation. When A9 = H at this command, both banks are deactivated (precharge all, PREA). MITSUBISHI ELECTRIC MITSUBISHI LSIs SGRAM (Rev. 0.0) M5M4V16G50DFP -8, -10, -12 Jan'97 Preliminary 16M (2-BANK x 262144-WORD x 32-BIT) Synchronous Graphics RAM BASIC FUNCTIONS (continued) Auto-Refresh (REFA) [/CS, /RAS, /CAS, DSF = L, /WE, CKE = H] REFA command starts auto-refresh cycle. Refresh address including bank address are generated internally. After this command, the banks are precharged automatically. Both banks must be precharged before this command can begin. Self-Refresh (REFS) [/CS, /RAS, /CAS, DSF, CKE = L, /WE = H] REFS command starts self-refresh cycle. The self-refresh cycle will continue while CKE remains low. When CKE goes high, self-refresh is exited. Refresh address including bank address are generated internally. After this command, the banks are precharged automatically. Both banks must be precharged before this command can begin. Burst Terminate (TERM) [/CS, /WE, DSF = L, /RAS, /CAS = H] TERM command stops the current burst operation. During read cycles, burst data stops after CAS latency is met. No Operation (NOP) [/CS, DSF = L, /RAS, /CAS, /WE = H] NOP command does not perform any operation on the SGRAM. Mode Register Set (MRS) [/CS, /WE, /RAS, /CAS, DSF = L] MRS command loads the mode register that defines how the device operates. The address pins, A0 A10, are used as input pins for the mode register data. This command must be issued after power-on to initialize the SGRAM. The mode register can only be set when both banks are idle. During the two cycles following this command, the SGRAM cannot accept any other commands. Special Register Set (SRS) [/CS, /WE, /RAS, /CAS = L, DSF = H] SRS command sets the color and mask registers. During the two cycles following this command, the SGRAM cannot accept any other commands. Masked Block Write (BW) [/CS, /CAS, /WE = L, /RAS, DSF = H] BW command starts the 8 column Block Write function. Burst Length = 1 is assumed. Write data comes from the color register and column address mask data is applied on the DQs. When A9 = H at this command, the bank is deactivated after the burst write (auto-precharge, BWA). MITSUBISHI ELECTRIC MITSUBISHI LSIs SGRAM (Rev. 0.0) M5M4V16G50DFP -8, -10, -12 Jan'97 Preliminary 16M (2-BANK x 262144-WORD x 32-BIT) Synchronous Graphics RAM COMMAND TRUTH TABLE CKE CKE n-1 n DESEL H X H X X X X No Operation NOP H X L H H H Row Address Entry & Bank Activate ACT H X L L H Row Address Entry & Bank Activate ACTWPB H X L L Single Bank Precharge PRE H X L L COMMAND MNEMONIC Deselect /CS /RAS /CAS /WE DSF A10 A9 A0-8 X X X L X X X H L BA Row Add. H H H BA Row Add. H L L BA L X X H X Precharge All Banks PREA H X L L H L L Column Address Entry & Write WRITE H X L H L L L BA L Col. Column Address Entry & Write with AutoPrecharge WRITEA H X L H L L L BA H Col. Column Address Entry & Masked Block Write BW H X L H L L H BA L Col. Masked Block Write with Auto-Precharge BWA H X L H L L H BA H Col. Column Address Entry & Read READ H X L H L H L BA L Col. Column Address Entry & Read with AutoPrecharge READA H X L H L H L BA H Col. Auto-Refresh REFA H H L L L H L X X X Self-Refresh Entry REFS H L L L L H L X X X Self-Refresh Exit REFSX L H H X X X X X X X L H L H H H L X X X H X L H H L L X X X L L OPCODE L H OPCODE Burst Terminate TERM Mode Register Set MRS Special Register Set SRS H H X X L L L L L L H=High Level, L=Low Level, BA=Bank Address, Col.=Column Address (A0-A7) Row Add.=Row Address (A0-A9), X=Don't Care, n=CLK cycle number MITSUBISHI ELECTRIC MITSUBISHI LSIs SGRAM (Rev. 0.0) M5M4V16G50DFP -8, -10, -12 Jan'97 Preliminary 16M (2-BANK x 262144-WORD x 32-BIT) Synchronous Graphics RAM FUNCTION TRUTH TABLE Current State /CS /RAS /CAS /WE DSF IDLE ROW ACTIVE Address Command Action H X X X X X DESEL NOP L H H H L X NOP NOP L H H L H X Undefined L H H L L X TERM L H L H H X Undefined L H L H L BA, CA, A9 READ / READA L H L L L BA, CA, A9 WRITE / WRITEA ILLEGAL*2 L H L L H BA, CA, A9 L L H H L BA, RA L L H H H BA, RA L L H L H X L L H L L BA, A9 L L L H H X Undefined L L L H L X REFA Auto-Refresh*5 L L L L H Op-Code, Mode-Add SRS Special Register Set*5 L L L L L Op-Code, Mode-Add MRS Mode Register Set*5 H X X X X X DESEL NOP L H H H L X NOP NOP L H H L L BA TERM NOP L H L H L BA, CA, A9 READ / READA Begin Read; Latch CA; Determine Auto-Precharge L H L L L BA, CA, A9 WRITE / WRITEA Begin Write; Latch CA; Determine Auto-Precharge L H L L H BA, CA, A9 BW / BWA Block Write; Latch CA; Determine Auto-Precharge L L H H L BA, RA BW / BWA ACT ACTWPB Undefined PRE / PREA ACT ILLEGAL ILLEGAL*2 ILLEGAL ILLEGAL*2 ILLEGAL*2 Bank Active; Latch RA; No Mask Bank Active; Latch RA; Use Mask ILLEGAL NOP*4 ILLEGAL Bank Active / ILLEGAL*2 L L H H H BA, RA ACTWPB Bank Active / ILLEGAL*2 L L H L L BA, A9 PRE / PREA Precharge / Precharge All L L L H L X REFA ILLEGAL L L L L H Op-Code, Mode-Add SRS Special RegisteSet *5 L L L L L Op-Code, Mode-Add MRS ILLEGAL MITSUBISHI ELECTRIC MITSUBISHI LSIs SGRAM (Rev. 0.0) M5M4V16G50DFP -8, -10, -12 Jan'97 Preliminary 16M (2-BANK x 262144-WORD x 32-BIT) Synchronous Graphics RAM FUNCTION TRUTH TABLE(continued) Current State /CS /RAS /CAS /WE DSF READ WRITE Address Command Action H X X X X X DESEL NOP (Continue Burst to END) L H H H L X NOP NOP (Continue Burst to END) L H H L L BA TERM Terminate Burst Terminate Burst, Latch CA, READ / READA Begin New Read, Determine Auto-Precharge*3 L H L H L BA, CA, A9 L H L L L BA, CA, A9 WRITE / WRITEA L H L L H BA, CA, A9 BW / BWA L L H H L BA, RA ACT L L H H L BA, RA ACTWPB L L H L L BA, A9 PRE / PREA L L L H L X REFA ILLEGAL L L L L H Op-Code, Mode-Add SRS ILLEGAL L L L L L Op-Code, Mode-Add MRS ILLEGAL H X X X X X DESEL NOP (Continue Burst to END) L H H H L X NOP NOP (Continue Burst to END) L H H L L BA TERM Terminate Burst BA, CA, A9 BA, CA, A89 WRITE / WRITEA L H L H L H L L L L L BA, CA, A9 BW / BWA H L L L H H ACTWPB L H H L L BA, RA L BA, RA ACT L L H L L BA, A9 PRE / PREA L L L H L X L L L L H L L L L L Op-Code, Mode-Add Op-Code, Mode-Add Terminate Burst, Latch CA, Block Write, Determine AutoPrecharge*3 Bank Active / ILLEGAL*2 Bank Active / ILLEGAL*2 Terminate Burst, Precharge Terminate Burst, Latch CA, READ / READA Begin Read, Determine AutoPrecharge*3 L L Terminate Burst, Latch CA, Begin Write, Determine AutoPrecharge*3 Terminate Burst, Latch CA, Begin Write, Determine AutoPrecharge*3 Terminate Burst, Latch CA, Block Write, Determine AutoPrecharge*3 Bank Active / ILLEGAL*2 Bank Active / ILLEGAL*2 Terminate Burst, Precharge REFA ILLEGAL SRS ILLEGAL MRS ILLEGAL MITSUBISHI ELECTRIC MITSUBISHI LSIs SGRAM (Rev. 0.0) M5M4V16G50DFP -8, -10, -12 Jan'97 Preliminary 16M (2-BANK x 262144-WORD x 32-BIT) Synchronous Graphics RAM FUNCTION TRUTH TABLE (continued) Current State /CS /RAS /CAS /WE READ with AUTO PRECHARGE WRITE with AUTO PRECHARGE DSF Address Command Action H X X X X X DESEL NOP (Continue Burst to END) L H H H L X NOP NOP (Continue Burst to END) L H H L L BA TERM ILLEGAL BA, CA, A9 L H L H L L H L L L BA, CA, A9 WRITE / WRITEA ILLEGAL L H L L H BA, CA, A9 BW / BWA ILLEGAL L L H H L BA, RA ACT Bank Active / ILLEGAL*2 L L H H H BA, RA ACTWPB Bank Active / ILLEGAL*2 L L H L L BA, A9 PRE / PREA L L L H L X REFA ILLEGAL SRS ILLEGAL MRS ILLEGAL READ / READA ILLEGAL ILLEGAL*2 L L L L H Op-Code, Mode-Add L L L L L Op-Code, Mode-Add H X X X X X DESEL NOP (Continue Burst to END) L H H H L X NOP NOP (Continue Burst to END) L H H L L BA TERM ILLEGAL L H L H L BA, CA, A9 L H L L L BA, CA, A9 WRITE / WRITEA ILLEGAL L H L L H BA, CA, A9 BW / BWA ILLEGAL L L H H L BA, RA ACT Bank Active / ILLEGAL*2 L L H H H BA, RA ACTWPB Bank Active / ILLEGAL*2 L L H L L BA, A9 PRE / PREA L L L H L X REFA ILLEGAL L L L L H SRS ILLEGAL L L L L L Op-Code, Mode-Add Op-Code, Mode-Add MRS ILLEGAL READ / READA ILLEGAL MITSUBISHI ELECTRIC ILLEGAL*2 MITSUBISHI LSIs SGRAM (Rev. 0.0) M5M4V16G50DFP -8, -10, -12 Jan'97 Preliminary 16M (2-BANK x 262144-WORD x 32-BIT) Synchronous Graphics RAM FUNCTION TRUTH TABLE (continued) Current State /CS PRE CHARGING ROW ACTIVATING /RAS /CAS /WE DSF Address H X X X X X L H H H L L H H L L H L L H L H L Command Action DESEL NOP (Idle after tRP) X NOP NOP (Idle after tRP) L BA TERM ILLEGAL*2 H L BA, CA, A9 READ / READA ILLEGAL*2 L L L BA, CA, A9 WRITE / WRITEA ILLEGAL*2 L L H BA, CA, A9 L H H L L L H H L L H L L L BW / BWA ILLEGAL*2 BA, RA ACT ILLEGAL*2 L BA, RA ACTWPB ILLEGAL*2 L L BA, A9 PRE / PREA L H L X L L L H L L L L L H X X X X Op-Code, Mode-Add Op-Code, Mode-Add X L H H H L L H H L L H L L H L NOP*4 (Idle after tRP) REFA ILLEGAL SRS ILLEGAL MRS ILLEGAL DESEL NOP (Row Active after tRCD) X NOP NOP (Row Active after tRCD) L BA TERM ILLEGAL*2 H L BA, CA, A9 READ / READA ILLEGAL*2 L L L BA, CA, A9 WRITE / WRITEA ILLEGAL*2 H L L H BA, CA, A9 L L H H L L L H H L L H L L L L BW / BWA ILLEGAL*2 BA, RA ACT ILLEGAL*2 H BA, RA ACTWPB ILLEGAL*2 L L BA, A9 PRE / PREA ILLEGAL*2 L H L X REFA ILLEGAL L L L H Op-Code, Mode-Add SRS ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL MITSUBISHI ELECTRIC MITSUBISHI LSIs SGRAM (Rev. 0.0) M5M4V16G50DFP -8, -10, -12 Jan'97 Preliminary 16M (2-BANK x 262144-WORD x 32-BIT) Synchronous Graphics RAM FUNCTION TRUTH TABLE (continued) Current State /CS WRITE RECOVERING REFRESHING /RAS /CAS /WE DSF Address Command Action H X X X X X DESEL NOP L H H H L X NOP NOP L H H L L BA TERM ILLEGAL*2 L H L H L BA, CA, A9 READ / READA ILLEGAL*2 L H L L L BA, CA, A9 WRITE / WRITEA ILLEGAL*2 L H L L H BA, CA, A9 L L H H L L L H H L L H L L L BW / BWA ILLEGAL*2 BA, RA ACT ILLEGAL*2 H BA, RA ACTWPB ILLEGAL*2 L L BA, A9 PRE / PREA ILLEGAL*2 L H L X REFA ILLEGAL L L L H Op-Code, Mode-Add SRS ILLEGAL L L L L L Op-Code, Mode-Add MRS ILLEGAL H X X X X X DESEL NOP (Idle after tRC) L H H H L X NOP NOP (Idle after tRC) L H H L L BA TERM ILLEGAL L H L H L BA, CA, A9 READ / READA ILLEGAL L H L L L BA, CA, A9 WRITE / WRITEA ILLEGAL L H L L H BA, CA, A9 L L H H L L L H H L L H L L L L BW / BWA ILLEGAL BA, RA ACT ILLEGAL L BA, RA ACT ILLEGAL L L BA, A9 PRE / PREA ILLEGAL L H L X REFA ILLEGAL L L L H Op-Code, Mode-Add SRS ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL MITSUBISHI ELECTRIC MITSUBISHI LSIs SGRAM (Rev. 0.0) M5M4V16G50DFP -8, -10, -12 Jan'97 Preliminary 16M (2-BANK x 262144-WORD x 32-BIT) Synchronous Graphics RAM FUNCTION TRUTH TABLE (continued) Current State MODE REGISTER SETTING /CS /RAS /CAS /WE DSF Address Command Action H X X X X X DESEL NOP (Idle after tRSC) L H H H L X NOP NOP (Idle after tRSC) L H H L L BA TERM ILLEGAL L H L H L BA, CA, A9 READ / READA ILLEGAL L H L L L BA, CA, A9 WRITE / WRITEA ILLEGAL L H L L H BA, CA, A9 L L H H L L L H H L L H L L L L BW / BWA ILLEGAL BA, RA ACT ILLEGAL H BA, RA ACTWPB ILLEGAL L L BA, A9 PRE / PREA ILLEGAL L H L X REFA ILLEGAL L L L H Op-Code, Mode-Add SRS ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL ABBREVIATIONS: H=High Level, L=Low Level, X=Don't Care BA=Bank Address, RA=Row Address, CA=Column Address, NOP=No Operation NOTES: 1. All entries assume that CKE was High during the preceding clock cycle and the current clock cycle. 2. ILLEGAL to bank in specified state; function may be legal in the bank indicated by BA, depending on the state of that bank. 3. Must satisfy bus contention, bus turn around, write recovery requirements. 4. NOP to bank precharging or in idle state. May precharge bank indicated by BA. 5. ILLEGAL if any bank is not idle. ILLEGAL = Device operation and/or data-integrity are not guaranteed. MITSUBISHI ELECTRIC MITSUBISHI LSIs SGRAM (Rev. 0.0) M5M4V16G50DFP -8, -10, -12 Jan'97 Preliminary 16M (2-BANK x 262144-WORD x 32-BIT) Synchronous Graphics RAM FUNCTION TRUTH TABLE for CKE Current State SELFREFRESH*1 POWER DOWN ALL BANKS IDLE*2 ANY STATE other than listed above CKE CKE /CS /RAS /CAS /WE DSF Add Action n-1 n H X X X X X X X INVALID L H H X X X X X Exit Self-Refresh (Idle after tRC) L H L H H H X X Exit Self-Refresh (Idle after tRC) L H L H H L X X ILLEGAL L H L H L X X X ILLEGAL L H L L X X X X ILLEGAL L L X X X X X X NOP (Maintain Self-Refresh) X INVALID H X X X X X X L H X X X X X X Exit Power Down to Idle L L X X X X X X NOP (Maintain Self-Refresh) H H X X X X X X Refer to Function Truth Table H L L L L H L X Enter Self-Refresh H L H X X X X X Enter Power Down H L L H H H X X Enter Power Down X ILLEGAL H L L H H L X H L L H L X X X ILLEGAL H L L L X X X X ILLEGAL L X X X X X X X Refer to Current State =Power Down H H X X X X X X Refer to Function Truth Table H L X X X X X X Begin CLK Suspend at Next Cycle*3 L H X X X X X X Exit CLK Suspend at Next Cycle*3 X X X Maintain CLK Suspend L L X X X ABBREVIATIONS: H=High Level, L=Low Level, X=Don't Care NOTES: 1. CKE Low to High transition will re-enable CLK and other inputs asynchronously . A minimum setup time must be satisfied before any command other than EXIT. 2. Power-Down and Self-Refresh can be entered only from the All Banks Idle State. 3. Must be legal command. MITSUBISHI ELECTRIC MITSUBISHI LSIs SGRAM (Rev. 0.0) M5M4V16G50DFP -8, -10, -12 Jan'97 Preliminary 16M (2-BANK x 262144-WORD x 32-BIT) Synchronous Graphics RAM POWER ON SEQUENCE Before starting normal operation, the following power on sequence is necessary to prevent a SGRAM from damaged or malfunctioning. 1. Apply power and start clock. Attempt to maintain CKE high, DQM0-3 high and NOP condition at the inputs. 2. Maintain stable power, stable clock, and NOP input conditions for a minimum of 500µs. 3. Issue precharge commands for all banks. (PRE or PREA) 4. After all banks become idle state (after tRP), issue 8 or more auto-refresh commands. 5. Issue a mode register set command to initialize the mode register. After these sequence, the SGRAM is idle state and ready for normal operation. MODE REGISTER Burst Length, Burst Type and /CAS Latency can be programmed by setting the mode register (MRS). The mode register stores these data until the next MRS command, which may be issued when both banks are in idle state. After tRSC from a MRS command, the SGRAM is ready for new command. CLK /CS /RAS /CAS A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 /WE 0 0 0 0 LTMODE BT DSF BL A10, A9 -A0 CL CAS LATENCY BURST LENGTH BL LVTTL A10 A9 0 0 1 0 - A8 0 0 - A7 0 0 - 000 001 010 011 100 101 Reserved Reserved 110 111 Reserved Reserved 000 001 010 011 100 2 3 Reserved Reserved Operating Mode Normal Operation Burst Read and Single Write All Others are Reserved 101 110 111 BURST TYPE 0 1 MITSUBISHI ELECTRIC V BT= 0 BT= 1 1 2 4 Reserved Reserved 4 8 8 Reserved Reserved Reserved Full Page SEQUENTIAL INTERLEAVED Reserved Reserved Reserved Reserved MITSUBISHI LSIs SGRAM (Rev. 0.0) M5M4V16G50DFP -8, -10, -12 Jan'97 Preliminary 16M (2-BANK x 262144-WORD x 32-BIT) Synchronous Graphics RAM SPECIAL REGISTER The Mask Register and Color Register can be loaded by setting the special register (SRS). If CR and MR are both high, data in the Mask and Color Registers will be unknown.After tRSC from a SRS command, the SGRAM is ready for new command. CLK /CS /RAS /CAS A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 /WE 0 0 0 0 CR MR 0 0 0 0 DSF 0 A10, A9 -A0 Mask Register Color Register MR Operation 0 1 No Load Operation Load Mask CR Operation 0 1 No Load Operation Load Color MITSUBISHI ELECTRIC V MITSUBISHI LSIs SGRAM (Rev. 0.0) M5M4V16G50DFP -8, -10, -12 Jan'97 Preliminary 16M (2-BANK x 262144-WORD x 32-BIT) Synchronous Graphics RAM CLK Command Read Write Y Y Address Q0 DQ CL= 3 BL= 4 /CAS Latency Q1 Q2 D0 Q3 Burst Length D1 D2 D3 Burst Length Burst Type Initial Address BL A2 Column Addressing A1 A0 Sequential Interleaved 0 0 0 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 0 1 1 2 3 4 5 6 7 0 1 0 3 2 5 4 7 6 0 1 0 2 3 4 5 6 7 0 1 2 3 0 1 6 7 4 5 0 1 1 3 4 5 6 7 0 1 2 3 2 1 0 7 6 5 4 8 1 0 0 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 1 0 1 5 6 7 0 1 2 3 4 5 4 7 6 1 0 3 2 1 1 0 6 7 0 1 2 3 4 5 6 7 4 5 2 3 0 1 1 1 1 7 0 1 2 3 4 5 6 7 6 5 4 3 2 1 0 - 0 0 0 1 2 3 0 1 2 3 - 0 1 1 2 3 0 1 0 3 2 4 - 1 0 2 3 0 1 2 3 0 1 - 1 1 3 0 1 2 3 2 1 0 - - 0 0 1 0 1 1 0 1 0 2 - - 1 NOTE: FULL PAGE BURST is an extension of the above tables of Sequential Addressing with the length being 256. MITSUBISHI ELECTRIC MITSUBISHI LSIs SGRAM (Rev. 0.0) M5M4V16G50DFP -8, -10, -12 Jan'97 Preliminary 16M (2-BANK x 262144-WORD x 32-BIT) Synchronous Graphics RAM OPERATIONAL DESCRIPTION BANK ACTIVATE The SGRAM has two independent banks. Each bank is activated by the ACT command with the bank address (A10/BA). A row is indicated by the row address A9-0. The minimum activation interval between one bank and the other bank is tRRD. PRECHARGE The PRE command deactivates the bank indicated by A10/BA. When both banks are active, the precharge all command (PREA, PRE + A9=H) is available to deactivate them at the same time. After tRP from the precharge, an ACT command can be issued. Bank Activation and Precharge All (BL=4, CL=3) CLK Command ACT ACT READ tRRD A0-8 Xa A9 A10 PRE ACT tRAS Xb Y Xa Xb 0 0 1 0 tRP Xb tRCD DQ 1 Xb 1 Qa0 Qa1 Qa2 Qa3 Precharge all READ After tRCD from the bank activation, a READ command can be issued. 1st output data is available after the /CAS Latency from the READ, followed by (BL -1) consecutive data when the Burst Length is BL. The start address is specified by A7-0, and the address sequence of burst data is defined by the Burst Type. A READ command may be applied to any active bank, so the row precharge time (tRP) can be hidden behind continuous output data (in case of BL=4) by interleaving the dual banks. When A9 is high at a READ command, the auto-precharge (READA) is performed. Any command (READ, WRITE, PRE, ACT) to the same bank is inhibited until the internal precharge is complete. The internal precharge start timing depends on /CAS Latency. The next ACT command can be issued after tRP from the internal precharge timing. MITSUBISHI ELECTRIC MITSUBISHI LSIs SGRAM (Rev. 0.0) M5M4V16G50DFP -8, -10, -12 Jan'97 Preliminary 16M (2-BANK x 262144-WORD x 32-BIT) Synchronous Graphics RAM Dual Bank Interleaving READ (BL=4, CL=3) CLK Command ACT READ ACT READ PRE tRCD A0-8 Xa Y Xb Y A9 Xa 0 Xb 0 0 A10 0 0 1 1 0 Qa1 Qa2 DQ Qa0 /CAS latency Qa3 Qb0 Qb1 Burst Length READ with Auto-Precharge (BL=4, CL=3) CLK Command ACT READ ACT tRCD tRP A0-8 Xa Y Xa A9 Xa 1 Xa A10 0 0 0 DQ Qa0 Qa1 Qa2 Qa3 Internal precharge begins READ Auto-Precharge Timing (BL=4) CLK Command ACT CL=3 DQ CL=2 DQ READ Qa0 Qa0 Qa1 Qa2 Qa1 Qa2 Qa3 Qa3 Internal Precharge Start Timing MITSUBISHI ELECTRIC Qb2 MITSUBISHI LSIs SGRAM (Rev. 0.0) M5M4V16G50DFP -8, -10, -12 Jan'97 Preliminary 16M (2-BANK x 262144-WORD x 32-BIT) Synchronous Graphics RAM WRITE After tRCD from the bank activation, a WRITE command can be issued. 1st input data is set in the same cycle as the WRITE. The following (BL -1) data is written into the RAM, when the Burst Length is BL. The start address is specified by A7-0, and the address sequence of burst data is defined by the Burst Type. A WRITE command may be applied to any active bank, so the row precharge time (tRP) can be hidden behind continuous output data (in case of BL=4) by interleaving the dual banks. When A9 is high at a WRITE command, the auto-precharge (WRITEA) is performed. Any command (READ, WRITE, PRE, ACT) to the same bank is inhibited until the internal precharge is complete. The internal precharge begins at tWR after the last input datacycle. The next ACT command can be issued after tRP from the internal precharge timing. Dual Bank Interleaving WRITE (BL=4) CLK Command ACT A0-8 Xa Write ACT tRCD Write PRE tRCD Y Xb Y tWR A9 Xa 0 Xb 0 0 A10 0 0 1 1 0 Da0 Da1 Db0 Db1 DQ Da2 Da3 Db2 Db3 Burst Length WRITE with Auto-Precharge (BL=4) CLK Command ACT A0-8 Xa Y Xa A9 Xa 1 Xa A10 0 0 Write ACT tRCD tRP 0 tWR DQ Da0 Da1 Da2 Da3 Internal precharge begins MITSUBISHI ELECTRIC MITSUBISHI LSIs SGRAM (Rev. 0.0) M5M4V16G50DFP -8, -10, -12 Jan'97 Preliminary 16M (2-BANK x 262144-WORD x 32-BIT) Synchronous Graphics RAM BURST INTERRUPTION [ Read Interrupted by Read ] Burst read operation can be interrupted by new read of the same or the other bank. M5M4V16G50DFP allows random column access. READ to READ interval is minimum 1 CLK. Read Interrupted by Read (BL=4, CL=3) CLK Command READ READ READ READ A0-8 Yi Yj Yk Yl A9 0 0 0 0 A10 0 0 1 0 DQ Qai0 Qaj0 Qaj1 Qbk0 Qbk1 Qbk2 Qal0 Qal1 Qal2 Qal3 [ Read Interrupted by Write ] Burst read operation can be interrupted by write of the same or the other bank. Random column access is allowed. In this case, the DQ should be controlled adequately by using the DQM0 - 3 to prevent bus contention. The output is disabled automatically 2 cycles after WRITE assertion. Read Interrupted by Write (BL=4, CL=3) CLK Command READ Write A0-8 Yi Yj A9 0 0 A10 0 0 DQM0-3 Q D Qai0 Daj0 Daj1 DQM0-3 control MITSUBISHI ELECTRIC Daj2 Daj3 Write control MITSUBISHI LSIs SGRAM (Rev. 0.0) M5M4V16G50DFP -8, -10, -12 Jan'97 Preliminary 16M (2-BANK x 262144-WORD x 32-BIT) Synchronous Graphics RAM [ Read Interrupted by Precharge ] Burst read operation can be interrupted by precharge of the same bank. READ to PRE interval is minimum 1 CLK. A PRE command disables the data output depending on the /CAS Latency. The figure below shows examples of when the dataout is terminated. Read Interrupted by Precharge (BL=4) CLK Command READ PRE DQ Command Q0 READ Q1 Q2 Q1 Q2 PRE CL=3 DQ Command Q0 READ PRE DQ Command Q0 READ PRE DQ Command Q0 READ Q1 Q2 PRE CL=2 DQ Command DQ Q0 READ Q1 PRE Q0 MITSUBISHI ELECTRIC Q2 Q3 Q3 MITSUBISHI LSIs SGRAM (Rev. 0.0) M5M4V16G50DFP -8, -10, -12 Jan'97 Preliminary 16M (2-BANK x 262144-WORD x 32-BIT) Synchronous Graphics RAM [ Read Interrupted by Burst Terminate ] Similarly to the precharge, burst terminate command can interrupt burst read operation and disable the data output. READ to TERM interval is minimum 1 CLK. The figure below shows examples when the dataout is terminated. Read Interrupted by Burst Terminate (BL=4) CLK Command READ TERM DQ Command Q0 READ Q1 Q2 Q1 Q2 TERM CL=3 DQ Command Q0 READ TERM DQ Command Q0 READ TERM DQ Command Q0 READ Q1 Q2 TERM CL=2 DQ Command DQ Q0 READ Q1 TERM Q0 MITSUBISHI ELECTRIC Q2 Q3 Q3 MITSUBISHI LSIs SGRAM (Rev. 0.0) M5M4V16G50DFP -8, -10, -12 Jan'97 Preliminary 16M (2-BANK x 262144-WORD x 32-BIT) Synchronous Graphics RAM [ Write Interrupted by Write ] Burst write operation can be interrupted by new write of the same or the other bank. Random column access is allowed. WRITE to WRITE interval is minimum 1 CLK. Write Interrupted by Write (BL=4) CLK Command Write Write Write Write A0-8 Yi Yj Yk Yl A9 0 0 0 0 A10 0 0 1 0 DQ Dai0 Daj0 Daj1 Dbk0 Dbk1 Dbk2 Dal0 Dal1 Dal2 Dal3 [ Write Interrupted by Read ] Burst write operation can be interrupted by read of the same or the other bank. Random column access is allowed. WRITE to READ interval is minimum 1 CLK. The input data on DQ at the interrupting READ cycle is “don’t care”. Write Interrupted by Read (BL=4, CL=3) CLK Command Write READ Write READ A0-8 Yi Yj Yk Yl A9 0 0 0 0 A10 0 0 0 1 DQM0-3 DQ Dai0 Qaj0 Qaj1 Dak0 Dak1 MITSUBISHI ELECTRIC Qbl0 MITSUBISHI LSIs SGRAM (Rev. 0.0) M5M4V16G50DFP -8, -10, -12 Jan'97 Preliminary 16M (2-BANK x 262144-WORD x 32-BIT) Synchronous Graphics RAM [ Write Interrupted by Precharge ] Burst write operation can be interrupted by precharge of the same bank. Random column access is allowed. Write Interrupted by Precharge (BL=4) CLK Command Write PRE ACT tRP tWR A0-8 Yi A89 0 0 Xb A10 0 0 0 Xb DQM0-3 DQ Dai0 Dai1 [ Write Interrupted by Burst Terminate ] Burst terminate command can terminate burst write operation. In this case, the write recovery time is not required and the bank remains active. The figure below shows the case that 3 words of data are written. Random column access is allowed. WRITE to TERM interval is minimum 1 CLK. Write Interrupted by Burst Terminate (BL=4) CLK Command A0-8 Write TERM Yi A9 0 A10 0 DQM0-3 DQ Dai0 Dai1 Dai2 MITSUBISHI ELECTRIC MITSUBISHI LSIs SGRAM (Rev. 0.0) M5M4V16G50DFP -8, -10, -12 Jan'97 Preliminary 16M (2-BANK x 262144-WORD x 32-BIT) Synchronous Graphics RAM AUTO REFRESH Single cycle of auto-refresh is initiated with REFA (/CS= /RAS= /CAS= DSF= L, /WE= /CKE= H) command. The refresh address is generated internally. 2048 REFA cycles within 32ms refresh 16Mbit memory cells. The auto-refresh is performed on each bank alternately (ping-pong refresh). Before performing an auto-refresh, both banks must be in the idle state. Additional commands must not be supplied to the device before tRC from the REFA command. Auto-Refresh CLK /CS NOP or DESLECT /RAS /CAS /WE DSF CKE minimum tRC A0-9 A10 Auto Refresh on Bank 0 Auto Refresh on Bank 1 MITSUBISHI ELECTRIC MITSUBISHI LSIs SGRAM (Rev. 0.0) Jan'97 Preliminary M5M4V16G50DFP -8, -10, -12 16M (2-BANK x 262144-WORD x 32-BIT) Synchronous Graphics RAM SELF REFRESH Self-refresh mode is entered by issuing a REFS command (/CS= /RAS= /CAS= DSF= L, /WE= H, CKE= L). Once the self-refresh is initiated, it is maintained as long as CKE is kept low. During the selfrefresh mode, CKE is asynchronous and the only enabled input (but asynchronous), all other inputs including CLK are disabled and ignored, and power consumption due to synchronous inputs is saved. To exit the self-refresh, supplying stable CLK inputs, asserting DESEL or NOP command and then asserting CKE (REFSX). After tRC from REFSX both banks are in the idle state and a new command can be issued after tRC, but DESEL or NOP commands must be asserted until then. Self-Refresh CLK Stable CLK /CS NOP /RAS /CAS /WE DSF CKE new command A0-9 X A10 0 Self Refresh Entry Self Refresh Exit MITSUBISHI ELECTRIC minimum tRC for recovery MITSUBISHI LSIs SGRAM (Rev. 0.0) M5M4V16G50DFP -8, -10, -12 Jan'97 Preliminary 16M (2-BANK x 262144-WORD x 32-BIT) Synchronous Graphics RAM CLK SUSPEND CKE controls the internal CLK at the following cycle. Figure below shows how CKE works. By negating CKE, the next internal CLK is suspended. The purpose of CLK suspend is power down, output suspend or input suspend. CKE is a synchronous input except during the self-refresh mode. CLK suspend can be performed either when the banks are active or idle, but a command at the following cycle is ignored. ext.CLK CKE int.CLK Power Down by CKE CLK Standby Power Down CKE Command PRE NOP NOP NOP NOP Active Power Down CKE Command NOP NOP NOP ACT NOP NOP NOP NOP NOP NOP NOP DQ Suspend by CKE CLK CKE Command DQ Write D0 READ D1 D2 D3 MITSUBISHI ELECTRIC Q0 Q1 Q2 Q3 MITSUBISHI LSIs SGRAM (Rev. 0.0) M5M4V16G50DFP -8, -10, -12 Jan'97 Preliminary 16M (2-BANK x 262144-WORD x 32-BIT) Synchronous Graphics RAM DQM0 - 3 CONTROL DQM0 - 3 is a dual function signal defined as the data mask for writes and the output disable for reads. During writes, DQM0 - 3 masks input data. DQM0 - 3 to write mask latency is 0. During reads, DQM0 - 3 forces output to Hi-Z. DQM0 - 3 to output Hi-Z latency is 2. DQM0 masks DQ0-7, DQM1 masks DQ8-15, DQM2 masks DQ16-23, DQM3 masks DQ24-031. DQM0 - 3 Function CLK Command Write READ DQM0 DQ(0-7) D0 D2 D3 Q0 masked by DQM0=High Q1 Q3 disabled by DQM0=High DQM1 DQ(8-15) D0 D1 D3 masked by DQM1=High Q0 Q2 Q3 disabled by DQM1=High DQM2 DQ(16-23) D0 D1 D2 D3 Q0 masked by DQM2=High Q1 Q3 disabled by DQM2=High DQM3 DQ(24-31) D0 D1 D2 D3 masked by DQM3=High Q1 Q2 disabled by DQM3=High MITSUBISHI ELECTRIC Q3 MITSUBISHI LSIs SGRAM (Rev. 0.0) M5M4V16G50DFP -8, -10, -12 Jan'97 Preliminary 16M (2-BANK x 262144-WORD x 32-BIT) Synchronous Graphics RAM ABSOLUTE MAXIMUM RATINGS Symbol Parameter Conditions Ratings Unit Vdd Supply Voltage with respect to Vss -0.5 ~ 4.6 V VddQ Supply Voltage for Output with respect to VssQ -0.5 ~ 4.6 V VI Input Voltage with respect to Vss -0.5 ~ 4.6 V VO Output Voltage with respect to VssQ -0.5 ~ 4.6 V IO Output Current 50 mA Pd Power Dissipation 1000 mW Topr Operating Temperature 0 ~ 70 °C Tstg Storage Temperature -65 ~ 150 °C Ta = 25 °C RECOMMENDED OPERATING CONDITIONS (Ta=0 ~ 70°C, unless otherwise noted) Limits Symbol Parameter Unit Min. Typ. Max. Vdd Supply Voltage 3.0 3.3 3.6 V Vss Supply Voltage 0 0 0 V VddQ Supply Voltage for Output 3.0 3.3 3.6 V VssQ Supply Voltage for Output 0 0 0 V VIH*1 High-Level Input Voltage all inputs 2.0 VddQ+0.3 V VIL*2 Low-Level Input Voltage all inputs -0.3 0.8 V NOTES: 1. VIH (max) = 5.5V for pulse width less than 10ns. 2. VIL (min) = -1.0V for pulse width less than 10ns. CAPACITANCE (Ta=0 ~ 70°C, Vdd = VddQ = 3.3 ± 0.3v, Vss = VssQ = 0v, unless otherwise noted) Symbol Parameter CI(A) Input Capacitance, address pin CI(C) Input Capacitance, control pin CI(K) Input Capacitance, CLK pin CI/O Input Capacitance, I/O pin Test Condition VI=Vss f=1MHz Vi=25mVrms MITSUBISHI ELECTRIC Limits (max.) Unit 5 pF 5 pF 5 pF 7 pF MITSUBISHI LSIs SGRAM (Rev. 0.0) M5M4V16G50DFP -8, -10, -12 Jan'97 Preliminary 16M (2-BANK x 262144-WORD x 32-BIT) Synchronous Graphics RAM AVERAGE SUPPLY CURRENT from Vdd (Ta=0 ~ 70°C, Vdd = VddQ = 3.3 ± 0.3v, Vss = VssQ = 0v, unless otherwise noted) Limits(max) Symbol Parameter Test Conditions Unit -8 tRC=min, tCLK=min, BL=1, CL=3 Icc2h standby current, CKE=H both banks idle, tCLK=min, CKE=H Icc2l standby current, CKE=L both banks idle, tCLK=min, CKE=L Icc3 active standby current both banks active, tCLK=min, CKE=H burst current tCLK=min, BL=4, CL=3, 1 bank idle Icc5 auto-refresh current tRC=min, tCLK=min Icc6 self-refresh current CKE <0.2v Icc7 operating current, block write tCLK=min Icc4*1 -12 TBD TBD TBD TBD TBD TBD TBD TBD TBD Icc1s*1 operating current, single bank tRC=min, tCLK=min, BL=1, CL=3 Icc1d*1 operating current, dual bank -10 mA mA mA mA mA mA mA mA mA NOTES: 1. Icc (max) is specified at the output open condition. AC OPERATING CONDITIONS AND CHARACTERISTICS (Ta=0 ~ 70°C, Vdd = VddQ = 3.3 ± 0.3v, Vss = VssQ = 0v, unless otherwise noted) Limits Symbol Parameter Test Conditions Unit Min. VOH (DC) High-Level Output Voltage (DC) IOH=-2mA VOL (DC) Low-Level Output Voltage (DC) IOL= 2mA Max. 2.4 V 0.4 V IOZ Off-state Output Current Q floating VO=0 ~ VddQ -10 10 µA II Input Current VIH = 0 ~ VddQ+0.3V -10 10 µA MITSUBISHI ELECTRIC MITSUBISHI LSIs SGRAM (Rev. 0.0) M5M4V16G50DFP -8, -10, -12 Jan'97 Preliminary 16M (2-BANK x 262144-WORD x 32-BIT) Synchronous Graphics RAM AC TIMING REQUIREMENTS (Ta=0 ~ 70°C, Vdd = VddQ = 3.3 ± 0.3v, Vss = VssQ = 0v, unless otherwise noted) Input Pulse Levels : 0.8V to 2.0V Input Timing Measurement Level : 1.4V Limits Symbol Parameter -8 Min. tCLK CLK cycle time -10 Max. Min. Unit -12 Max. Min. Max. CL=2 12 15 18 ns CL=3 8 10 12 ns tCH CLK High pulse width 3 3.5 4 ns tCL CLK Low pulse width 3 3.5 4 ns tT Transition time of CLK 1 tIS Input Setup time (all inputs) 2.5 2.5 3 ns tIH Input Hold time (all inputs) 1 1 1.5 ns tRC Row Cycle time 96 100 120 ns tRCD Row to Column Delay 24 30 36 ns tRAS Row Active time 70 tRP Row Precharge time 30 30 36 ns tWR Write Recovery time 8 10 12 ns tRRD Act to Act Delay time 30 30 36 ns tRSC Mode Register Set Cycle time 16 20 24 ns tPDE Power Down Exit time 8 12 15 ns tREF Refresh Interval time tBWC Block Write Cycle time tBPL Block Write to Precharge 10 10000 1 70 32 10 10000 1 84 32 10 10000 32 ns ns ms 16 20 24 ns 8 10 12 ns CLK 1.4V Signal 1.4V MITSUBISHI ELECTRIC Any AC timing is referenced to the input signal crossing through 1.4V. MITSUBISHI LSIs SGRAM (Rev. 0.0) M5M4V16G50DFP -8, -10, -12 Jan'97 Preliminary 16M (2-BANK x 262144-WORD x 32-BIT) Synchronous Graphics RAM SWITCHING CHARACTERISTICS (Ta=0 ~ 70°C, Vdd = VddQ = 3.3 ± 0.3v, Vss = VssQ = 0v, unless otherwise noted) Limits Symbol Parameter -8 Min. tAC -10 Max. Min. Unit -12 Max. Min. Max. CL=2 9 11 14 ns CL=3 7 8 10 ns Access time from CLK tOH Output Hold time from CLK 3 3 3 ns tOLZ Delay time, output low impedance from CLK 0 0 0 ns tOHZ Delay time, output high impedance from CLK 3 7 3 8 3 8 ns Output Load Condition V TT=1.4V 1.4V CLK 50* VREF =1.4V 1.4V DQ VOUT 50pF Output Timing Measurement Reference Point CLK 1.4V DQ 1.4V tAC tOH tOHZ MITSUBISHI ELECTRIC