BSI BS616LV1015AC-55 Very low power/voltage cmos sram 64k x 16 bit Datasheet

BSI
Very Low Power/Voltage CMOS SRAM
64K X 16 bit
BS616LV1015
„ DESCRIPTION
„ FEATURES
The BS616LV1015 is a high performance, very low power CMOS Static
Random Access Memory organized as 65,536 words by 16 bits and
operates from a wide range of 4.5V to 5.5V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current
of 0.4uA and maximum access time of 55ns in 5V operation.
Easy memory expansion is provided by an active LOW chip
enable(CE) and active LOW output enable(OE) and three-state output
drivers.
The BS616LV1015 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS616LV1015 is available in the JEDEC standard 44-pin TSOP
Type II and 48-pin BGA package.
• Vcc operation voltage : 4.5V ~ 5.5V
• Very low power consumption :
Vcc = 5.0V
C-grade : 35mA (Max.) operating current
I- grade : 40mA (Max.) operating current
0.4uA (Typ.) CMOS standby current
• High speed access time :
-55
55ns (Max.) at Vcc = 5.0V
• Automatic power down when chip is deselected
• Three state outputs and TTL compatible
• Fully static operation
• Data retention supply voltage as low as 1.5V
• Easy expansion with CE and OE options
• I/O Configuration x8/x16 selectable by LB and UB pin
„ PRODUCT FAMILY
PRODUCT
FAMILY
OPERATING
TEMPERATURE
BS616LV1015EC
+0 O C to +70 O C
BS616LV1015AC
BS616LV1015EI
-40 O C to +85 O C
BS616LV1015AI
„ PIN CONFIGURATIONS
A4
A3
A2
A1
A0
CE
DQ0
DQ1
DQ2
DQ3
VCC
GND
DQ4
DQ5
DQ6
DQ7
WE
A15
A14
A13
A12
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
1
A
LB
BS616LV1015EC
BS616LV1015EI
2
OE
3
A0
4
A1
5
A2
Vcc
RANGE
4.5V ~ 5.5V
4.5V ~ 5.5V
SPEED
(ns)
POWER DISSIPATION
STANDBY
Operating
Vcc=5.0V
Vcc=5.0V
(ICCSB1, Max)
55
Vcc=5.0V
10uA
55
PKG TYPE
(ICC, Max)
35mA
20uA
40mA
TSOP2-44
BGA-48-0608
TSOP2-44
BGA-48-0608
„ BLOCK DIAGRAM
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A7
OE
UB
LB
DQ15
DQ14
DQ13
DQ12
GND
VCC
DQ11
DQ10
DQ9
DQ8
NC
A8
A9
A10
A11
NC
A8
A13
A15
A14
A12
Address
A7
Buffer
Input
A6
A5
A4
16
DQ0
.
.
.
.
NC
.
.
.
.
UB
A3
A4
CE
IO0
C
IO9
IO10
A5
A6
IO1
IO2
D
VSS
IO11
NC
A7
IO3
VCC
E
VCC
IO12
NC
NC
IO4
VSS
IO14
IO13
A14
A15
IO5
IO6
G
IO15
NC
A12
A13
WE
IO7
H
NC
A8
A9
A10
A11
NC
512 x 2048
Data
Input
Buffer
16
Column I/O
Write Driver
Data
Output
Buffer
16
128
Column Decoder
14
CE
WE
OE
UB
LB
F
Memory Array
Decoder
Sense Amp
16
DQ15
IO8
512
Row
2048
6
B
18
Control
Address Input Buffer
A11 A9 A3 A2 A1 A0 A10
Vcc
Gnd
Brilliance Semiconductor, Inc. reserves the right to modify document contents without notice.
R0201-BS616LV1015
1
Revision 1.1
Jan.
2004
BSI
BS616LV1015
„ PIN DESCRIPTIONS
Name
Function
A0-A15 Address Input
These 16 address inputs select one of the 65,536 x 16-bit words in the RAM.
CE Chip Enable Input
CE is active LOW. Chip enables must be active when data read from or write to the
device. if chip enable is not active, the device is deselected and is in a standby power
mode. The DQ pins will be in the high impedance state when the device is deselected.
WE Write Enable Input
The write enable input is active LOW and controls read and write operations. With the
chip selected, when WE is HIGH and OE is LOW, output data will be present on the
DQ pins; when WE is LOW, the data present on the DQ pins will be written into the
selected memory location.
OE Output Enable Input
The output enable input is active LOW. If the output enable is active while the chip is
selected and the write enable is inactive, data will be present on the DQ pins and they
will be enabled. The DQ pins will be in the high impedance state when OE is inactive.
LB and UB Data Byte Control Input
Lower byte and upper byte data input/output control pins.
DQ0 - DQ15 Data Input/Output
Ports
These 16 bi-directional ports are used to read data from or write data into the RAM.
Vcc
Power Supply
Gnd
Ground
„ TRUTH TABLE
MODE
Not selected
(Power Down)
Output Disabled
Read
Write
R0201-BS616LV1015
CE
WE
OE
LB
UB
DQ0~DQ7
DQ8~DQ15
Vcc CURRENT
H
X
X
X
X
High Z
High Z
ICCSB, ICCSB1
L
H
H
X
X
High Z
High Z
ICC
L
L
Dout
Dout
ICC
H
L
High Z
Dout
ICC
L
H
Dout
High Z
ICC
ICC
L
L
H
L
L
X
L
L
Din
Din
H
L
X
Din
ICC
L
H
Din
X
ICC
2
Revision 1.1
Jan.
2004
BSI
BS616LV1015
„ ABSOLUTE MAXIMUM RATINGS(1)
SYMBOL
PARAMETER
„ OPERATING RANGE
RATING
UNITS
-0.5 to
Vcc+0.5
V
VTERM
Terminal Voltage
Respect to GND
with
TBIAS
Temperature Under Bias
-40 to +85
O
C
TSTG
Storage Temperature
-60 to +150
O
C
PT
Power Dissipation
1.0
W
IOUT
DC Output Current
20
mA
AMBIENT
TEMPERATURE
RANGE
O
Commercial
Vcc
O
0 C to +70 C
O
Industrial
4.5V ~ 5.5V
O
-40 C to +85 C
4.5V ~ 5.5V
„ CAPACITANCE (1) (TA = 25oC, f = 1.0 MHz)
SYMBOL
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
reliability.
CIN
CDQ
PARAMETER
Input
Capacitance
Input/Output
Capacitance
CONDITIONS
MAX.
UNIT
VIN=0V
6
pF
VI/O=0V
8
pF
1. This parameter is guaranteed and not 100% tested.
„ DC ELECTRICAL CHARACTERISTICS ( TA = 0oC to + 70oC )
PARAMETER
NAME
PARAMETER
TEST CONDITIONS
Guaranteed Input Low
(2)
Voltage
Guaranteed Input High
(2)
Voltage
VIL
VIH
MIN.
TYP. (1)
MAX.
UNITS
Vcc=5.0V
-0.5
--
0.8
V
Vcc=5.0V
2.2
--
Vcc+0.2
V
IIL
Input Leakage Current
Vcc = Max, VIN = 0V to Vcc
--
--
1
uA
ILO
Output Leakage Current
Vcc = Max, CE = VIH, or OE = VIH,
VI/O = 0V to Vcc
--
--
1
uA
VOL
Output Low Voltage
Vcc = Max, IOL = 2mA
Vcc=5.0V
--
--
0.4
V
VOH
Output High Voltage
Vcc = Min, IOH = -1mA
Vcc=5.0V
2.4
--
--
V
ICC
Operating Power Supply
Current
CE = VIL, IDQ = 0mA, F = Fmax
Vcc=5.0V
--
--
35
mA
ICCSB
Standby Current-TTL
CE = VIH, IDQ = 0mA
Vcc=5.0V
--
--
2
mA
ICCSB1
Standby Current-CMOS
CE ≧ Vcc-0.2V,
VIN ≧ Vcc - 0.2V or VIN ≦ 0.2V
Vcc=5.0V
--
0.4
10
uA
(3)
1. Typical characteristics are at TA = 25oC.
2. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included.
3. Fmax = 1/tRC .
„ DATA RETENTION CHARACTERISTICS ( TA = 0oC to + 70oC )
SYMBOL
PARAMETER
TEST CONDITIONS
MIN.
TYP. (1)
MAX.
UNITS
VDR
Vcc for Data Retention
CE ≧ Vcc - 0.2V
VIN ≧ Vcc - 0.2V or VIN ≦ 0.2V
1.5
--
--
V
ICCDR
Data Retention Current
CE ≧ Vcc - 0.2V
VIN ≧ Vcc - 0.2V or VIN ≦ 0.2V
--
0.02
0.3
uA
tCDR
Chip Deselect to Data
Retention Time
--
--
ns
--
--
ns
tR
See Retention Waveform
Operation Recovery Time
0
TRC
(2)
1. Vcc = 1.5V, TA = + 25OC
2. tRC = Read Cycle Time
R0201-BS616LV1015
3
Revision 1.1
Jan.
2004
BSI
BS616LV1015
„ LOW VCC DATA RETENTION WAVEFORM ( CE Controlled )
Data Retention Mode
Vcc
VDR ≥ 1.5V
Vcc
Vcc
tR
t CDR
CE ≥ Vcc - 0.2V
VIH
CE
VIH
„ KEY TO SWITCHING WAVEFORMS
„ AC TEST CONDITIONS
Input Pulse Levels
Vcc/0V
Input Rise and Fall Times
WAVEFORM
INPUTS
OUTPUTS
1V/ns
MUST BE
STEADY
MUST BE
STEADY
Input and Output
Timing Reference Level
0.5Vcc
MAY CHANGE
FROM H TO L
WILL BE
CHANGE
FROM H TO L
Output Load
CL=30pF+1TTL
CL=100pF+1TTL
MAY CHANGE
FROM L TO H
WILL BE
CHANGE
FROM L TO H
,
DON T CARE:
ANY CHANGE
PERMITTED
CHANGE :
STATE
UNKNOWN
DOES NOT
APPLY
CENTER
LINE IS HIGH
IMPEDANCE
”OFF ”STATE
„ AC ELECTRICAL CHARACTERISTICS ( TA = 0oC to + 70oC, Vcc = 5.0V )
READ CYCLE
JEDEC
PARAMETER
NAME
PARAMETER
NAME
CYCLE TIME : 55ns
MIN. TYP. MAX.
DESCRIPTION
UNIT
t AVAX
t RC
Read Cycle Time
55
--
--
ns
t AVQV
t AA
Address Access Time
--
--
55
ns
t E1LQV
t ACS
Chip Select Access Time
--
--
55
ns
t BA
t BA
Data Byte Control Access Time
t GLQV
t OE
Output Enable to Output Valid
t E1LQX
t CLZ
Chip Select to Output Low Z
t BE
t BE
Data Byte Control to Output Low Z
t GLQX
t OLZ
Output Enable to Output in Low Z
t E1HQZ
t CHZ
Chip Deselect to Output in High Z
t BDO
t BDO
Data Byte Control to Output High Z
t GHQZ
t OHZ
t AXOX
t OH
R0201-BS616LV1015
(CE)
--
--
35
ns
--
--
35
ns
(CE)
10
--
--
ns
(LB,UB)
10
--
--
ns
10
--
--
ns
(CE)
--
--
35
ns
(LB,UB)
--
--
35
ns
Output Disable to Output in High Z
--
--
30
ns
Data Hold from Address Change
5
--
--
ns
4
(LB,UB)
Revision 1.1
Jan.
2004
BSI
BS616LV1015
„ SWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE1
(1,2,4)
t RC
ADDRESS
t
t
t OH
AA
OH
D OUT
READ CYCLE2
(1,3,4)
CE
t ACS
t BA
LB,UB
t BE
t
D OUT
READ CYCLE3
t BDO
t
CHZ
CLZ
(1,4)
t
RC
ADDRESS
t
AA
OE
t OH
t OE
t OLZ
CE
t CLZ
t
t OHZ
t CHZ(1)
ACS
t BA
LB,UB
t BE
t BDO
D OUT
NOTES:
1. WE is high for read Cycle.
2. Device is continuously selected when CE = VIL.
3. Address valid prior to or coincident with CE transition low.
4. OE = VIL .
R0201-BS616LV1015
5
Revision 1.1
Jan.
2004
BSI
BS616LV1015
„ AC ELECTRICAL CHARACTERISTICS ( TA = 0oC to + 70oC, Vcc = 5.0V )
WRITE CYCLE
JEDEC
PARAMETER
NAME
PARAMETER
NAME
t AVAX
t E1LWH
t AVWL
t AVWH
tWLWH
tWHAX
tBW
tWLQZ
tDVWH
tWHDX
tGHQZ
t WC
t CW
t AS
t AW
t WP
t WR
t BW
t WHZ
t DW
t DH
t OHZ
tWHOX
t OW
CYCLE TIME : 55ns
MIN. TYP. MAX.
DESCRIPTION
UNIT
Write Cycle Time
55
--
--
ns
Chip Select to End of Write
55
--
--
ns
0
--
--
ns
Address Valid to End of Write
55
--
--
ns
Write Pulse Width
35
--
--
ns
(CE,WE)
0
--
--
ns
(LB,UB)
55
--
--
ns
--
--
25
ns
Data to Write Time Overlap
25
--
--
ns
Data Hold from Write Time
0
--
--
ns
Output Disable to Output in High Z
--
--
25
ns
End of Write to Output Active
5
--
--
ns
Address Setup Time
Write recovery Time
Date Byte Control to End of Write
Write to Output in High Z
„ SWITCHING WAVEFORMS (WRITE CYCLE)
WRITE CYCLE1 (1)
t WC
ADDRESS
(3)
t WR
OE
(10)
t CW
(5)
CE
t BW
LB,UB
t AW
WE
(3)
t WP
t AS
(2)
(4)
t OHZ
D OUT
t
DH
t DW
D IN
R0201-BS616LV1015
6
Revision 1.1
Jan.
2004
BSI
BS616LV1015
WRITE CYCLE2 (1,6)
t WC
ADDRESS
(10)
t CW
(5)
CE
t BW
LB,UB
t AW
WE
t WR
t WP
(3)
(2)
t AS
(4)
t WHZ
D OUT
(7)
t
OW
t
DH
(8)
t DW
(8,9)
D IN
NOTES:
1. WE must be high during address transitions.
2. The internal write time of the memory is defined by the overlap of CE and WE low. All signals
must be active to initiate a write and any one signal can terminate a write by going inactive.
The data input setup and hold timing should be referenced to the second transition edge of
the signal that terminates the write.
3. TWR is measured from the earlier of CE or WE going high at the end of write cycle.
4. During this period, DQ pins are in the output state so that the input signals of opposite phase
to the outputs must not be applied.
5. If the CE low transition occurs simultaneously with the WE low transitions or after the WE
transition, output remain in a high impedance state.
6. OE is continuously low (OE = VIL ).
7. DOUT is the same phase of write data of this write cycle.
8. DOUT is the read data of next address.
9. If CE goes low during this period, DQ pins are in the output state. Then the data input signals of
opposite phase to the outputs must not be applied to them.
10. TCW is measured from the later of CE going low to the end of write.
R0201-BS616LV1015
7
Revision 1.1
Jan.
2004
BSI
BS616LV1015
„ ORDERING INFORMATION
BS616LV1015 X X
Z
YY
SPEED
55: 55ns
PKG MATERIAL
-: Normal
G: Green
P: Pb free
GRADE
C: +0oC ~ +70oC
I: -40oC ~ +85oC
PACKAGE
E: TSOP2-44
A: BGA-48-0608
Note:
BSI (Brilliance Semiconductor Inc.) assumes no responsibility for the application or use of any product or circuit described herein. BSI does not authorize its products
for use as critical components in any application in which the failure of the BSI product may be expected to result in significant injury or death, including life-support
systems and critical medical instruments.
„ PACKAGE DIMENSIONS
TSOP2-44
R0201-BS616LV1015
8
Revision 1.1
Jan.
2004
BSI
BS616LV1015
„ PACKAGE DIMENSIONS (continued)
NOTES:
1: CONTROLLING DIMENSIONS ARE IN MILLIMETERS.
2: PIN#1 DOT MARKING BY LASER OR PAD PRINT.
1.4 Max.
3: SYMBOL "N" IS THE NUMBER OF SOLDER BALLS.
BALL PITCH e = 0.75
D
E
N
D1
E1
8.0
6.0
48
5.25
3.75
E1
e
D1
VIEW A
48 mini-BGA (6 x 8)
R0201-BS616LV1015
9
Revision 1.1
Jan.
2004
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