Microchip MCP2025T-330E/MD Lin transceiver with voltage regulator Datasheet

MCP2025
LIN Transceiver with Voltage Regulator
Features
Description
• The MCP2025 is compliant with:
- LIN Bus Specifications Version 1.3, and 2.x
- SAE J2602-2
• Supports Baud Rates up to 20 kBaud
• 43V Load Dump Protected
• Maximum Continuous Input Voltage of 30V
• Wide LIN Compliant Supply Voltage: 6.0-18.0V
• Extended Temperature Range: -40 to +125°C
• Interface to PIC® EUSART and Standard USARTs
• Wake-up on LIN Bus Activity or Local Wake Input
• LIN Bus Pin
- Internal Pull-up Termination Resistor and
Diode for Slave Node
- Protected Against VBAT Shorts
- Protected Against Loss of Ground
- High Current Drive
• TXD and LIN Bus Dominant Time-out Function
• Two Low-power Modes
- TRANSMITTER-OFF: 90 µA (typical)
- POWER-DOWN mode: 4.5 µA (typical)
• MCP2025 On-chip Voltage Regulator
- Output Voltage of 5.0V or 3.3V 70 mA
Capability with Tolerances of ±3% Over
Temperature Range.
- Internal Short Circuit Current Limit
- Only External Filter and Load Capacitors
Needed
• Automatic Thermal Shutdown
• High Electromagnetic Immunity (EMI), Low
Electromagnetic Emission (EME)
• Robust ESD Performance: ±15 kV for LBUS and
VBB Pin (IEC61000-4-2)
• Transient Protection for LBUS and VBB pins in
Automotive Environment (ISO7637)
• Meets stringent automotive design requirements
including “OEM Hardware Requirements for LIN,
CAN and FlexRay Interfaces in Automotive
Applications”, Version 1.2, March 2011
• Multiple Package Options Including Small 4x4 mm
DFN
The MCP2025 provides a bidirectional, half-duplex
communication physical interface to meet the LIN bus
specification Revision 2.1 and SAE J2602-2. The
device incorporates a voltage regulator with 5V or 3.3V
70 mA regulated power supply output.
MCP2025 family members include:
- MCP2025-500, 8-pin, LIN driver with 5.0V
regulator
- MCP2025-330, 8-pin, LIN driver with 3.3V
regulator
Package Types (Top View)
PDIP, SOIC
VBB
1
CS/LWAKE
VSS
2
LIN
4
3
MCP2025
 2012 Microchip Technology Inc.
The device has been designed to meet the stringent
quiescent current requirements of the automotive
industry and will survive +43V load dump transients,
and double battery jumps.
8
VREG
7
RESET
6
TXD
5
RXD
4x4 DFN
VBB
1
8
VREG
CS/LWAKE
2
7
RESET
VSS
3
6
TXD
LIN
4
5
RXD
EP
9
DS22306A-page 1
MCP2025
Block Diagram
Short Circuit
Protection
VREG
Internal Circuits 4.2V
VREG
Thermal
Protection
RESET
Voltage
Regulator
VBB
Wake-Up
Logic and
Power Control
Ratiometric
Reference
Bus Wakeup
RXD
CS/LWAKE
Slope Control
~30
k
LBUS
TXD
Bus
Dominant
Timer
VSS
Thermal
and
Short Circuit
Protection
DS22306A-page 2
 2012 Microchip Technology Inc.
MCP2025
1.0
FUNCTION DESCRIPTION
1.1
The MCP2025 provides a physical interface between a
microcontroller and a LIN half-duplex bus. It is intended
for automotive and industrial applications with serial
bus baud rates up to 20 kbaud. This device will
translate the CMOS/TTL logic levels to LIN logic levels,
and vice versa. The device offers optimum EMI and
ESD performance; it can withstand high voltage on the
LIN bus. The device supports two low-power modes to
meet automotive industry power consumption
requirements. The MCP2025 also provides a +5V or
3.3V 70 mA regulated power output.
FIGURE 1-1:
Modes of Operation
The MCP2025 works in five modes: POWER-ONRESET mode, POWER-DOWN mode, READY mode,
OPERATION mode, and TRANSMITTER-OFF mode.
For an overview of all operational modes, please refer
to Table 1-1. For the operational mode transition,
please refer to Figure 1-1.
STATE DIAGRAM
CS/LWAKE=0
POR(2)
READY
VREG OFF
RX OFF
TX OFF
VREG ON
RX ON
TX OFF
VBB>VON
CS/LWAKE=1 &TXD=1
VREG_OK=1(1)
CS=1 &TXD=0&
VREG_OK=1(1)
CS/LWAKE=1&
TXD=1&
No Fault(3)
CS/LWAKE=1 OR
Voltage Rising Edge on LBUS
TX OFF
VREG ON
RX ON
TX OFF
CS/LWAKE=0 or
Fault detected(3)
CS/LWAKE=0
&TXD=0
OPERATION
VREG ON
RX ON
TX ON
POWER-DOWN
VREG OFF
RX OFF
TX OFF
Note 1: VREG_OK : Regulator Output Voltage > 0.8VREG_NOM.
2: If the voltage on pin VBB falls below VOFF, the device will enter POWER-ON RESET mode from all other
modes, which is not shown in the figure.
3: Faults include TXD/LBUS permanent dominant, LBUS short to VBB, thermal protection, and VREG_OK
is false.
1.1.1
POWER-ON-RESET MODE
Upon application of VBB, or whenever the voltage on
VBB is below the threshold of regulator turn off voltage
VOFF (typically 4.50V), the device enters POWER-ONRESET mode (POR). During this mode, the device
maintains the digital section in a reset mode and waits
until the voltage on pin VBB rises above the threshold
of regulator turn on voltage VON (typically 5.75V) to
 2012 Microchip Technology Inc.
enter READY mode. In POWER-ON-RESET mode,
the LIN physical layer and voltage regulator are
disabled, and the RESET pin is switched to ground.
DS22306A-page 3
MCP2025
1.1.2
READY MODE
1.1.4
The device enters READY mode from POR mode after
the voltage on VBB rises above the threshold of
regulator turn on voltage VON or from POWER-DOWN
mode when a remote or local wake-up event happens.
Upon entering READY mode, the voltage regulator and
receiver section of the transceiver are powered up. The
transmitter remains in an off state. The device is ready
to receive data but not to transmit. In order to minimize
the power consumption, the regulator operates in a
reduced power mode. It has a lower GBW product and
thus is slower. However, the 70 mA drive capability is
unchanged.
The device stays in READY mode until the output of the
voltage regulator has stabilized and CS/LWAKE pin is
HIGH (‘1’).
1.1.3
OPERATION MODE
If the CS/LWAKE pin changes to high while VREG is OK
(VREG > 0.8*VREG_NOM) and TXD pin is HIGH, the part
enters OPERATION mode from either READY or
TRANSMITTER-OFF mode.
In this mode, all internal modules are operational. The
internal pull-up resistor between LBUS and VBB is connected only in this mode.
The device goes to TRANSMITTER-OFF mode at the
falling edge on the CS/LWAKE pin or when a fault is
detected.
Note:
The TXD pin needs to be set high before
setting the CS/LWAKE pin to low in order
to jump and stay in TRANSMITTER-OFF
mode. If the TXD pin is set or maintained
low before setting the CS/LWAKE pin to
low, the part will transit to TRANSMITTEROFF mode and then jump to POWERDOWN mode after a deglitch delay of
about 20 µs.
TABLE 1-1:
State
TRANSMITTER OFF MODE
If VREG is OK (VREG > 0.8*VREG_NOM), the TRANSMITTER-OFF mode can be reached by setting CS/LWAKE
to HIGH when TXD pin is LOW from READY mode; or
by pulling down CS/LWAKE to low from OPERATION
mode.
In TRANSMITTER-OFF mode, the receiver is enabled
but the LBUS transmitter is off. It is a lower power mode.
In order to minimize the power consumption, the regulator operates in a reduced power mode. It has a lower
GBW product and thus is slower. However, the 70 mA
drive capability is unchanged.
The transmitter is also turned off whenever the voltage
regulator is unstable or recovering from a fault. This
prevents unwanted disruption on the bus during times
of uncertain operation.
1.1.5
POWER-DOWN MODE
POWER-DOWN mode is entered by pulling down both
the CS/LWAKE pin and TXD to low from TRANSMITTER-OFF mode. In POWER-DOWN mode, the transceiver and the voltage regulator are both off. Only the
Bus Wake-up section and the CS/LWAKE pin wake-up
circuits are in operation. This is the lowest power mode.
If any bus activity (e.g. a BREAK character) occurs or
CS/LWAKE is set to HIGH during POWER-DOWN
mode, the device will immediately enter READY mode
and enable the voltage regulator. Then, once the regulator output has stabilized (approximately 0.3 ms to
1.2 ms) it can go to either the OPERATION mode or
TRANSMITTER-OFF mode. Refer to Section 1.1.6
“Remote Wake-up” for more details.
1.1.6
REMOTE WAKE-UP
The remote wake-up sub module observes the LBUS in
order to detect bus activity. In POWER-DOWN mode,
the normal LIN recessive/dominant threshold is
disabled, and the LIN bus Wake-Up Voltage Threshold
VWK(LBUS) is used to detect bus activities. Bus activity
is detected when the voltage on the LBUS falls below
the LIN bus Wake-Up Voltage Threshold VWK(LBUS)
(approximately 3.4V) for at least tBDB (a typical duration
of 80 µs ) followed by a rising edge. Such a condition
causes the device to leave POWER-DOWN mode.
OVERVIEW OF OPERATIONAL MODES
Transmitter Receiver
Internal
Voltage
Wake Module Regulator
Operation
Comments
POWER-ONRESET
OFF
OFF
OFF
OFF
Transfer to READYmode after VBB > VON
READY
OFF
ON
OFF
ON
If CS/LWAKE is high, then proceed to OPERATION
or TRANSMITTER-OFF mode
Bus Off state
OPERATION
ON
ON
OFF
ON
If CS/LWAKE is low level, then TRANSMITTEROFF mode
Normal operation
mode
POWER-DOWN
OFF
OFF
ON
Activity Detect
OFF
On LIN bus rising edge or CS/LWAKE high level, go
to READY mode
Lowest power mode
TRANSMITTEROFF
OFF
ON
OFF
ON
If TXD and CS/LWAKE low level, then POWERDOWN
If TXD and CS/LWAKE high level, then OPERATION
Bus Off state, lower
power mode
 2012 Microchip Technology Inc.
DS22306A-page 4
MCP2025
1.2
Pin Descriptions
Please refer to Table 1-2 for the pinout overview.
ElectroMagnetic Emission, the slopes during signal
changes are controlled, and the LBUS pin has cornerrounding control for both falling and rising edges.
Battery Positive Supply Voltage pin. An external diode
is connected in series to prevent the device from being
reversely powered (refer to Figure 1-9).
The internal LIN receiver observes the activities on the
LIN bus, and generates the output signal RXD that
follows the state of the LBUS. A first degree 160 KHz,
low-pass input filter optimizes ElectroMagnetic
immunity.
1.2.2
1.2.7
1.2.1
VBB
VREG
CS/LWAKE
Positive Supply Voltage Regulator Output pin. An onchip Low Dropout Regulator (LDO) gives +5.0 or +3.3V
70 mA regulated voltage on this pin.
Chip Select and Local Wake-up Input pin (TTL level,
high voltage tolerant). This pin controls the device state
transition. Refer to Figure 1-1.
1.2.3
An internal pull-down resistor will keep the CS/LWAKE
pin low to ensure that no disruptive data will be present
on the bus while the microcontroller is executing a
POWER-ON RESET and I/O initialization sequence.
When CS/LWAKE is ‘1’, a weak pull-down (~600 KΩ) is
used to reduce current. When CS/LWAKE is ‘0’ a
stronger pull-down (~300 KΩ) is used to maintain the
logic level.
VSS
Ground pin.
1.2.4
TXD
Transmit data input pin (TTL level, HV compliant,
adaptive pull-up). The transmitter reads the data
stream on the TXD pin and sends it to the LIN bus. The
LBUS pin is low (dominant) when TXD is low, and high
(recessive) when TXD is high.
The Transmit Data Input pin has an internal adaptive
pull-up
to
an
internally-generated
4.2V
(approximately). When TXD is ‘0’, a weak pull-up
(~900 kΩ) is used to reduce current. When TXD is ‘1’
a stronger pull-up (~300 kΩ) is used to maintain the
logic level. A series reverse-blocking diode allows
applying TXD input voltages greater than the internally
generated 4.2V and renders the TXD pin HV compliant
up to 30V (see Block Diagram).
1.2.5
RXD
Receive Data Output pin. The RXD pin is a standard
CMOS output pin and it follows the state of the LBUS
pin.
1.2.6
This pin may also be used as a local wake-up input
(See Figure 1-9). The microcontroller will set the I/O pin
to control the CS/LWAKE. An external switch, or other
source, can then wake-up both the transceiver and the
microcontroller.
Note:
1.2.8
CS/LWAKE should NOT be tied directly to
pin VREG as this could force the
MCP2025 into OPERATION mode before
the microcontroller is initialized.
RESET
RESET OUTPUT pin. This is an open drain output pin.
It indicates the internal voltage has reached a valid,
stable level. As long as the internal voltage is valid
(above 0.8VREG), this pin will present high impedance;
otherwise the RESET pin switches to ground.
LBUS
LIN Bus pin. LBUS is a bidirectional LIN bus Interface
pin and is controlled by the signal TXD. It has an open
collector output with a current limitation. To reduce
TABLE 1-2:
PINOUT OVERVIEW
PIN Name
PIN Number
PIN Type
Function
VREG
8
Output
Voltage regulator output
VSS
3
Power
Ground
VBB
1
Power
Battery
TXD
6
Input, HV-tolerant
Transmit data input
Receive data output
RXD
5
Output
LBUS
4
I/O, HV
LIN Bus
CS/LWAKE
2
TTL Input, HV-tolerant
Chip Select and Local Wake-up input
RESET
7
Open Drain Output, HVtolerant
Reset output
 2012 Microchip Technology Inc.
DS22306A-page 5
MCP2025
1.3
1.3.1
Fail-Safe Features
GENERAL FAIL-SAFE FEATURES
• An internal pull-down resistor on the CS/LWAKE
pin disables the transmitter if the pin is floating.
• An internal pull-up resistor on the TXD pin places
TXD in HIGH, thus the LBUS is recessive if the
TXD pin is floating.
• High-impedance and low leakage current on
LBUS during loss of power or ground.
• The current limit on LBUS protects the transceiver
from being damaged if the pin is shorted to VBB.
1.3.2
THERMAL PROTECTION
The thermal protection circuit monitors the die
temperature and is able to shut down the LIN
transmitter and voltage regulator.
There are three causes for a thermal overload. A
thermal shut down can be triggered by any one, or a
combination of, the following thermal overload
conditions:
• Voltage regulator overload
• LIN bus output overload
• Increase in die temperature due to increase in
environment temperature
The recovery time from the thermal shutdown is equal
to adequate cooling time.
Driving the TXD and checking the RXD pin makes it
possible to determine whether there is a bus contention
(TXD = high, RXD = low) or a thermal overload condition (TXD = low, RXD = high).
FIGURE 1-2:
THERMAL SHUTDOWN
STATE DIAGRAMS
LIN bus
shorted
to VBB
Output
Overload
Voltage
Regulator
Shutdown
Operation
Mode
Transmitter
Shutdown
Temp < SHUTDOWNTEMP Temp < SHUTDOWNTEMP
1.3.3
TXD/LBUS TIME-OUT TIMER
The LIN bus can be driven to a dominant level either
from the TXD pin or externally. An internal timer deactivates the LBUS transmitter if a dominant status
(LOW) on the LIN bus lasts longer than Bus Dominant
Time-out Time tTO(LIN) (approximately 20 milliseconds);
at the same time, RXD output is put in recessive
(HIGH) and the internal pull-up resistor between LBUS
and VBB is disconnected. The timer is reset on any
recessive LBUS status or POR mode. The recessive
 2012 Microchip Technology Inc.
status on LBUS can be caused either by the bus being
externally pulled up or by the TXD pin being returned
high.
1.4
Internal Voltage Regulator
The MCP2025 has a positive regulator capable of supplying +5.00 or +3.30 VDC ±3% at up to 70mA of load
current over the entire operating temperature range of
-40°C to +125°C. The regulator uses an LDO design, is
short-circuit-protected and will turn the regulator output
off if its output falls below the Shutdown Voltage
Threshold VSD.
With a load current of 70mA, the minimum input to output voltage differential required for the output to remain
in regulation is typically +0.5V (+1V maximum over the
full operating temperature range). Quiescent current is
less than 100 µA with a full 70mA load current when the
input to output voltage differential is greater than
+3.00V.
Regarding the correlation between VBB, VREG and IDD,
please refer to Figure 1-6 and Figure 1-7. When the
input voltage (VBB) drops below the differential needed
to provide stable regulation, the voltage regulator
output VREG will track the input down to approximately
VOFF. The regulator will turn off the output at this point.
This will allow PIC microcontrollers, with internal POR
circuits, to generate a clean arming of the POWER-ON
RESET trip point. The MCP2025 will then monitor VBB
and turn on the regulator when VBB is above the threshold of regulator turn on voltage VON.
Under specific ambient temperature and battery voltage range, the voltage regulator can output as high as
150 mA current. For current load capability of the voltage regulator, refer to Figure 1-4 and Figure 1-5.
In POWER-DOWN mode, the VBB monitor is turned off
(see Section 1.1.5 “Power-down Mode” for details).
Note:
The regulator overload current limit is
approximately 250 mA. The regulator output voltage VREG is monitored. If output
voltage VREG is lower than VSD, the voltage regulator will turn off. After a recovery
time of about 3mS, the VREG will be
checked again. If there is no short circuit,
(VREG > VSD) then the voltage regulator
remains on.
The regulator requires an external output bypass
capacitor for stability. See FIGURE 2-1: “ESR Curves
For Load Capacitor Selection” for correct capacity
and ESR for stable operation.
DS22306A-page 6
MCP2025
FIGURE 1-3:
VOLTAGE REGULATOR BLOCK DIAGRAM
Pass
Element
VREG
Sampling
Network
VBB
Fast
Transient
Loop
Buffer
VSS
VREF
5.0V VREG VS. IREG AT
VBB = 12V
FIGURE 1-5:
6
3.5
3.5
3.5
3.5
3.5
3.5
3.5
3.5
3.5
3.5
3.5
3.5
3.5
3.5
3.5
3.5
3.5
3.5
3.5
3.5
3.5
3.5
5
3333333333333
4
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
VREG (V)
VREG (V)
FIGURE 1-4:
-45
3
25
90
2
125
1
2222222222222
0
0
100
IREG (mA)
 2012 Microchip Technology Inc.
200
300
-45
-45
-45
-45
-45
-45
-45
-45
-45
-45
-45
-45
-45
-45
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
25
25
25
25
25
25
25
25
25
25
25
25
25
1111111111111
90
90
90
90
90
90
90
90
90
90
90
90
90
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
000000000000
0000000000000
3.3V VREG VS. IREG AT
VBB = 12V
125
125
125
125
125
125
125
125
125
125
125
125
125
100
100
100
100
100
100
100
100
100
100
100
100
100
100
200
200
200
200
200
200
200
200
200
200
200
200
100
100
100
200
200
200
200
200
200
200
200
200
REG
REG
REG
IIREG
IREG
IREG
IREG
IREG
IREG
IREG
IREG
IREG
(mA)
(mA)
(mA)
(mA)
(mA)
(mA)
(mA)
(mA)
(mA)
(mA)
(mA)
REG
REG
REG
REG
REG
REG
REG
REG
IREG
IREG
IREG
(mA)
(mA)
(mA)
(mA)
(mA)
(mA)
(mA)
300
300
300
300
300
300
300
300
300
300
300
300
300
300
300
300
300
300
300
300
300
30
30
DS22306A-page 7
MCP2025
FIGURE 1-6:
VOLTAGE REGULATOR OUTPUT ON POWER-ON RESET
8
6
VBB
V
Minimum VBB to maintain regulation
VON
VOFF
4
2
0
t
VREG
V
5
VREG-NOM
4
3
2
1
0
Note 1:
2:
3:
4:
 2012 Microchip Technology Inc.
t
(4)
(1)
(2)
(3)
Start-up, VBB < VON, regulator off
VBB > VON, regulator on .
VBB  Minimum VBB to maintain regulation
VBB < VOFF, regulator will turn off
DS22306A-page 8
MCP2025
FIGURE 1-7:
VOLTAGE REGULATOR OUTPUT ON OVER CURRENT SITUATION
IREG
mA
ILIM
0
6
5
t
VREG
V
VREG-NOM
4
VSD
3
2
1
0
t
(1)
Note 1:
2:
1.5
1.5.1
IREG less than ILIM, regulator on
After IREG exceeds ILIM, voltage regulator output will be reduced until
voltage regulator shutdown voltage VSD is reached.
Optional External Protection
REVERSE BATTERY PROTECTION
An external reverse-battery-blocking diode should be
used to provide polarity protection (see Figure 1-9).
1.5.2
(2)
TRANSIENT VOLTAGE
PROTECTION (LOAD DUMP)
An external 43V transient suppressor (TVS) diode,
between VBB and ground, with a transient protection
resistor (RTP) in series with the battery supply and the
VBB pin protects the device from power transients and
ESD events greater than 43V (see Figure 1-9). The
maximum value for the RTP protection resistor depends
upon two parameters: the minimum voltage the part will
start at, and the impacts of this RTP resistor on the VBB
value, thus on the Bus recessive level and slopes.
This leads to a set of three equations to fulfill.
Equation 1-1 provides a max RTP value, according to
the minimum battery voltage the user wants the part to
start with.
 2012 Microchip Technology Inc.
Equation 1-2 provides a max RTP value according to
the maximum error on the recessive level, thus VBB,
since the part uses VBB as the reference value for the
recessive level.
Equation 1-3 provides a max RTP value according to
the maximum relative variation the user can accept on
the slope when IREG varies.
Since both Equation 1-1 and Equation 1-2 must be fulfilled, the maximum allowed value for RTP is the
smaller of the two values found when solving
Equation 1-1 and Equation 1-2.
Usually, Equation 1-1 gives the higher constraint
(smaller value) for RTP as shown in the example where
VBATmin is 8V.
However, the user needs to verify that the value found
in Equation 1-1 also satisfies Equation 1-2 and
Equation 1-3.
While this protection is optional, it should be
considered as good engineering practice.
DS22306A-page 9
MCP2025
EQUATION 1-1:
EQUATION 1-4:
V BATmin – 5.5V
R TP  ------------------------------------250mA
C BAT
------------- =
C REG
5.5V = V OFF + 1.0V
250 mA is the peak current at power-on when
VBB = 5.5V
Assume that VBATmin = 8V. Equation 1-1 gives 10.
EQUATION 1-2:
RTP <= ∆VRECCESSIVE / IREGMAX.
∆VRECCESSIVE is the maximum variation tolerated on
the recessive level
Assume that ∆VRECCESSIVE = 1V and IREGMAX=50 mA.
Equation 1-2 gives 20.
EQUATION 1-3:
where L is in mH and RTOT in .
RTOT = RLINE + RTP
Equation 1-4 allows lower CBAT/CREG values than the
10* ratio we recommend.
Assumee that we have a good quality connection with
RTOT = 0.1 and L = 0.1 mH.
Solving the equation results in CBAT/CREG = 1.
If RTOT is increased to 1, the result becomes CBAT/
CREG = 1.4
But if the connection is highly resistive or highly inductive (poor connection), the CBAT/CREG ratio greatly
increases.
For a highly resistive connection: RTOT = 10 and
L = 0.1 mH: again, the CBAT/CREG ratio increases to 7.
∆Slope is the maximum variation tolerated on the
slope level and Iregmax is the maximum current the
regulator will provide to the load.
VBATmin>VOFF + 1.0V,
1.5.3
2
For a highly inductive connection: RTOT = 0.1 and L =
1 mH; the CBAT/CREG ratio increases to 7.
Slope   V BATmin – 1V 
R TP  -------------------------------------------------------------I regmax
Assume that ∆Slope =15%, VBATmin=8V
IREGMAX = 50 mA. Equation 1-3 gives 20.
2
100L + Rtot
-----------------------------2
R
2
tot
1 + L + -------100
Figure 1-8 shows the minimum recommended CBAT/
CREG ratio as a function of the impedance of the VBAT
connection.
and
CBAT CAP
Selecting CBAT = 10* CREG is recommended, however
this leads to a high value cap. Lower values for CBAT
cap can be used, but certain rules must be followed. In
any case, the voltage at the VBB pin should remain
above VOFF when the device is turned on.
The current peak at start-up (due to the fast charge of
the CREG and CBAT capacitor) may induce a significant
drop on the VBB pin. This drop is proportional to the
impedance of the VBAT connection (see Figure 1-9).
Let’s assume that the VBAT connection is mainly inductive and resistive, and that the customer knows the
resistive and inductive values of the connection.
The following formula gives an indication of the
minimum value the customer should use for CBAT:
 2012 Microchip Technology Inc.
DS22306A-page 10
MCP2025
Minimum Recommended CBAT/CREG Ratio
FIGURE 1-8:
Cbat/Creg ratio as function of the Vbat line impedance
CBAT/CREG
10
Rbat=0.1
Rbat=0.3
Rbat=1
Rbat=2
CBAT/CREG
Rbat=4
Rbat=10
1
0.1
1
Vbat line inductance [mH]
 2012 Microchip Technology Inc.
DS22306A-page 11
MCP2025
1.6
Typical Applications
FIGURE 1-9:
TYPICAL APPLICATION CIRCUIT
VBAT
VBAT
Rtp
10 K
43V(5)
WAKE-UP
µC
VDD
VREG
TXD
TXD
RXD
I/O
CBAT
CREG
Master Node Only
VBB
VBB
1 K
RXD
(3)
RESET
43V
RESET
VSS
LIN Bus
LBUS
CS/LWAKE
(4)
VSS
Note 1: CREG, the load capacitor, should be ceramic or tantalum-rated for extended temperatures, 1.022 µF. See Figure 2-1 for selecting correct ESR.
2: CBAT is the filter capacitor for the external voltage supply. Typically 10 * CREG with no ESR
restriction. See Figure 1-8 to select the minimum recommended value for CBAT. The RTP value is
added to the line resistance.
3: This diode is only needed if CS/LWAKE is connected to VBAT supply.
4: Transient suppressor diode. Vclamp L = 43V.
5: This component is for additional load dump protection.
FIGURE 1-10:
TYPICAL LIN NETWORK CONFIGURATION
40m
+ Return
LIN bus
VBB
1 k
LIN bus
MCP2025
LIN bus
MCP205X
Slave 1
µC
LIN bus
MCP202XA
LIN bus
MCP2003
Slave 2
µC
Slave n <16
µC
Master
µC
 2012 Microchip Technology Inc.
DS22306A-page 12
MCP2025
2.0
ELECTRICAL
CHARACTERISTICS
2.1
Absolute Maximum Ratings†
VIN DC Voltage on RXD, and RESET ................................................................................................. -0.3V to VREG+0.3
VIN DC Voltage on TXD, CS/LWAKE .............................................................................................................-0.3 to +40V
VBB Battery Voltage, continuous, non-operating (Note 1)..............................................................................-0.3 to +40V
VBB Battery Voltage, non-operating (LIN bus recessive, no regulator load, t < 60s) (Note 2) .......................-0.3 to +43V
VBB Battery Voltage, transient ISO 7637 Test 1 ......................................................................................................-100V
VBB Battery Voltage, transient ISO 7637 Test 2a .....................................................................................................+75V
VBB Battery Voltage, transient ISO 7637 Test 3a ....................................................................................................-150V
VBB Battery Voltage, transient ISO 7637 Test 3b ...................................................................................................+100V
VLBUS Bus Voltage, continuous.......................................................................................................................-18 to +30V
VLBUS Bus Voltage, transient (Note 3)............................................................................................................-27 to +43V
ILBUS Bus Short Circuit Current Limit ....................................................................................................................200 mA
ESD protection on LIN, VBB (IEC 61000-4-2) (Note 4) .......................................................................................... ±15 kV
ESD protection on LIN, VBB (Human Body Model) (Note 5).................................................................................... ±8 kV
ESD protection on all other pins (Human Body Model) (Note 5) ............................................................................. ±4 kV
ESD protection on all pins (Charge Device Model) (Note 6) ................................................................................±1500V
ESD protection on all pins (Machine Model) (Note 7).............................................................................................±200V
Maximum Junction Temperature ............................................................................................................................. 150C
Storage Temperature .................................................................................................................................. -65 to +150C
Note 1: LIN 2.x compliant specification.
2: SAE J2602 compliant specification.
3: ISO 7637 immunity against transients (t < 500 ms).
4: According to IEC 61000-4-2, 330Ω, 150 pF and Transceiver EMC Test Specifications [2] to [4].
5: According to AEC-Q100-002 / JESD22-A114.
6: According to AEC-Q100-011B.
7: According to AEC-Q100-003 / JESD22-A115.
† NOTICE: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This
is a stress rating only and functional operation of the device at those or any other conditions above those indicated in
the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods
may affect device reliability.
2.2
Nomenclature Used in this Document
Some terms and names used in this data sheet deviate from those referred to in the LIN specifications. Equivalent
values are shown below.
LIN 2.1 Name
Term used in the following tables
VBAT
not used
ECU operating voltage
VSUP
VBB
Supply voltage at device pin
VBUS_LIM
ISC
Current limit of driver
VBUSREC
VIH(LBUS)
Recessive state
VBUSDOM
VIL(LBUS)
Dominant state
 2012 Microchip Technology Inc.
DS22306A-page 13
MCP2025
2.3
DC Specifications
DC Specifications
Electrical Characteristics:
Unless otherwise indicated, all limits are specified for:
VBB = 6.0V to 18.0V
TA = -40°C to +125°C
Parameter
Sym.
Min.
Typ.
Max.
Units
Conditions
VBB Quiescent Operating Current
IBBQ
—
—
200
µA
IOUT = 0 mA, LBUS recessive
VREG = 5.0V
—
—
200
µA
IOUT = 0 mA, LBUS recessive
VREG = 3.3V
—
—
100
µA
IOUT = 0 mA, LBUS recessive
VREG = 5.0V
—
—
100
µA
IOUT = 0 mA, LBUS recessive
VREG = 3.3V
—
—
100
µA
With voltage regulator on,
transmitter off, receiver on,
CS = VIH,VREG = 5.0V
—
—
100
µA
With voltage regulator on,
transmitter off, receiver on,
CS = VIH,VREG = 3.3V
IBBPD
—
4.5
8
µA
With voltage regulator powered
off, receiver on and transmitter
off, CS = VIL.
IBBNOGND
-1
—
1
mA
VBB = 12V, GND to VBB,
VLIN = 0-18V
High-level Input Voltage
(TXD)
VIH
2.0
—
30
V
Low-level Input Voltage
(TXD)
VIL
-0.3
—
0.8
V
High-level Input Current (TXD)
IIH
-2.5
—
0.4
µA
Input voltage = 4.0V. ~800 k
internal adaptive pull-up
Low-level Input Current (TXD)
IIL
-10
—
—
µA
Input voltage = 0.5V. ~800 k
internal adaptive pull-up
High-level Input Voltage
(CS/LWAKE)
VIH
2
—
30
V
Through a current-limiting
resistor
Low-level Input Voltage
(CS/LWAKE)
VIL
-0.3
—
0.8
V
High-level Input Current (CS/
LWAKE)
IIH
—
—
8.0
µA
Input voltage = 0.8VREG
~1.3 M internal pull-down to
VSS
Low-level Input Current (CS/
LWAKE)
IIL
—
—
5.0
µA
Input voltage = 0.2VREG
~1.3 M internal pull-down to
VSS
Power
VBB Ready Current
VBB Transmitter-off Current with
Watchdog Disabled
VBB Power-down Current
VBB Current with VSS Floating
IBBRD
IBBTO
Microcontroller Interface
Low-level Output Voltage (RXD)
VOLRXD
—
—
0.2VREG
V
IOL = 2 mA
High-level Output Voltage
(RXD)
VOHRXD
0.8
VREG
—
—
V
IOH = 2 mA
Note 1:
2:
3:
Internal current limited. 2.0 ms maximum recovery time (RLBUS = 0, TX = 0, VLBUS = VBB).
For design guidance only, not tested.
In POWER-DOWN mode, normal LIN recessive/dominant threshold is disabled; VWK(LBUS) is used to
detect bus activities.
DS22306A-page 14
 2012 Microchip Technology Inc.
MCP2025
2.3
DC Specifications (Continued)
DC Specifications
Parameter
Electrical Characteristics:
Unless otherwise indicated, all limits are specified for:
VBB = 6.0V to 18.0V
TA = -40°C to +125°C
Sym.
Min.
Typ.
Max.
Units
Conditions
Bus Interface (DC specifications are for a VBB range of 6.0 to 18.0V)
High-level Input Voltage
VIH(LBUS)
0.6 VBB
—
—
V
Recessive state
Low-level Input Voltage
VIL(LBUS)
-8
—
0.4 VBB
V
Dominant state
Input Hysteresis
VHYS
—
—
0.175 VBB
V
Low-level Output Current
IOL(LBUS)
40
—
200
mA
Output voltage = 0.1 VBB,
VBB = 12V
Pull-up Current on Input
IPU(LBUS)
-180
—
-72
µA
~30 k internal pull-up
@ VIH (LBUS) = 0.7 VBB,
VBB=12V
ISC
50
—
200
mA
(Note 1)
Short Circuit Current Limit
—
VBB
V
Driver Dominant Voltage
V_LOSUP
—
—
1.1
V
VBB = 7.3V, RLOAD = 1000
Driver Dominant Voltage
V_HISUP
—
—
1.2
V
VBB = 18V,
RLOAD = 1000
Input Leakage Current
(at the receiver during dominant
bus level)
IBUS_PAS_
-1
—
—
mA
Driver off,
VBUS = 0V,
VBB = 12V
Input Leakage Current
(at the receiver during recessive
bus level)
IBUS_PAS_
-20
—
20
µA
Driver off,
8V < VBB < 18V
8V < VBUs < 18V
VBUS  VBB
Leakage Current (disconnected
from ground)
IBUS_NO_G
-10
—
+10
µA
GNDDEVICE = VBB,
0V < VBUS < 18V,
VBB = 12V
Leakage Current
(disconnected from VBB)
IBUS_NO_P
-10
—
+10
µA
VBB = GND,
0 < VBUS < 18V
Receiver Center Voltage
VBUS_CNT
0.475
VBB
0.5
VBB
0.525 VBB
V
VBUS_CNT = (VIL (LBUS) + VIH
(LBUS))/2
RSLAVE
20
30
47
k
50
pF
(Note 2)
—
—
3.4
V
Wake up from POWER-DOWN
mode (Note 3)
High-level Output Voltage
Slave Termination
Capacitance of slave node
Wake-Up Voltage Threshold on
LIN Bus
Note 1:
2:
3:
VOH(LBUS) 0.8 VBB
VIH(LBUS) – VIL(LBUS)
DOM
REC
ND
WR
CSLAVE
VWK(LBUS)
(Note 2)
Internal current limited. 2.0 ms maximum recovery time (RLBUS = 0, TX = 0, VLBUS = VBB).
For design guidance only, not tested.
In POWER-DOWN mode, normal LIN recessive/dominant threshold is disabled; VWK(LBUS) is used to
detect bus activities.
 2012 Microchip Technology Inc.
DS22306A-page 15
MCP2025
2.3
DC Specification (Continued)
DC Specifications
Parameter
Electrical Characteristics:
Unless otherwise indicated, all limits are specified for:
VBB = 6.0V to 18.0V
TA = -40°C to +125°C
CLOADREG = 10 µF
Sym.
Min.
Typ.
Max.
Units
Conditions
VREG
4.85
5.00
5.15
V
Line Regulation
VOUT1
—
10
50
mV
IOUT = 1 mA,
6.0V < VBB < 18V
Load Regulation
VOUT2
—
10
50
mV
5 mA < IOUT <70 mA
6.0V < VBB < 12V
Power Supply Ripple
Reject
PSRR
—
—
50
dB
1 VPP @10-20 kHz
ILOAD = 20 mA
Output Noise Voltage
eN
—
—
100
Shutdown Voltage
Threshold
VSD
3.5
—
4.0
V
Input Voltage to Turn-off
Output
VOFF
3.9
—
4.5
V
Input Voltage to Turn-on
Output
VON
5.25
—
6.0
V
Output Voltage
VREG
3.20
3.30
3.40
V
Line Regulation
VOUT1
—
10
50
mV
IOUT = 1 mA,
6.0V < VBB < 18V
Load Regulation
VOUT2
—
10
50
mV
5 mA < IOUT < 70 mA,
6.0V < VBB < 12V
Power Supply Ripple
Reject
PSRR
—
50
—
dB
1 VPP @10-20 kHz ,
ILOAD = 20 mA
Output Noise Voltage
eN
—
—
100
Shutdown Voltage
VSD
2.5
—
2.7
V
Input Voltage to Turn-off
Output
VOFF
3.9
—
4.5
V
Input Voltage to Turn-on
Output
VON
5.25
—
6
V
Voltage Regulator - 5.0V
Output Voltage Range
0 mA < IOUT < 70 mA
µVRMS 10 Hz – 40 MHz
CFILTER = 10 µf,
CBP = 0.1 µf, ILOAD = 20 mA
See Figure 1-7 (Note 1)
Voltage Regulator - 3.3V
DS22306A-page 16
0 mA < IOUT < 70 mA
µVRMS 10 Hz – 40 MHz
/Hz CFILTER = 10 µF,
CBP = 0.1 µF, ILOAD= 20 mA
See Figure 1-7 (Note 2)
 2012 Microchip Technology Inc.
MCP2025
FIGURE 2-1:
ESR CURVES FOR LOAD CAPACITOR SELECTION
ESR Curves
10
Unstable
Instable
Stable only
ESR [ohm]
1
with Tantalum or
Electrolytic cap.
Stable with
Tantalum,
Electrolytic and
Ceramic cap.
Unstable
Instable
0.1
0.01
Unstable
Instable
0.001
0.1
1
10
100
1000
Load Capacitor [uF]
 2012 Microchip Technology Inc.
DS22306A-page 17
MCP2025
2.4
AC Specification
AC CHARACTERISTICS
Parameter
VBB = 6.0V to 18.0V; TA = -40°C to +125°C
Sym.
Min.
Typ.
Max.
Units
Test Conditions
Bus Interface - Constant Slope Time Parameters (DC specifications are for a VBB range of 6.0 to 18.0V)
tSLOPE
3.5
—
22.5
µs
7.3V <= VBB <= 18V
Propagation Delay of
Transmitter
tTRANSPD
—
—
6.0
µs
tTRANSPD = max (tTRANSPDR
or tTRANSPDF)
Propagation Delay of
Receiver
tRECPD
—
—
6.0
µs
tRECPD = max (tRECPDR or
tRECPDF)
Symmetry of Propagation
Delay of Receiver rising
edge w.r.t. falling edge
tRECSYM
-2.0
—
2.0
µs
trecsym = max (trecpdf –
trecpdr)
RRXD 2.4Kto VCC, CRXD
20pF
Symmetry of Propagation
Delay of Transmitter rising
edge w.r.t. falling edge
tTRANSSYM
-2.0
—
2.0
µs
tTRANSSYM = max (tTRANSPDF
- tTRANSPDR)
Bus dominant time-out time
tTO(LIN)
Slope rising and falling
edges
—
25
—
mS
Duty Cycle 1 @20.0 kbit/sec
.396
—
—
%tBIT
CBUS;RBUS conditions:
1 nF; 1 k | 6.8 nF; 660 |
10 nF; 500
THREC(MAX) = 0.744 x VBB,
THDOM(MAX) = 0.581 x VBB,
VBB =7.0V - 18V; tBIT = 50 µs.
D1 = tBUS_REC(MIN) / 2 x tBIT)
Duty Cycle 2 @20.0 kbit/sec
—
—
.581
%tBIT
CBUS;RBUS conditions:
1 nF; 1 k | 6.8 nF; 660 |
10 nF; 500
THREC(MAX) = 0.284 x VBB,
THDOM(MAX) = 0.422 x VBB,
VBB =7.6V - 18V; tBIT = 50 µs.
D2 = tBUS_REC(MAX) / 2 x tBIT)
Duty Cycle 3 @10.4 kbit/sec
.417
—
—
%tBIT
CBUS;RBUS conditions:
1 nF; 1 k | 6.8 nF; 660 |
10 nF; 500
THREC(MAX) = 0.778 x VBB,
THDOM(MAX) = 0.616 x VBB,
VBB =7.0V - 18V; tBIT = 96 µs.
D3 = tBUS_REC(MIN) / 2 x tBIT)
Duty Cycle 4 @10.4 kbit/sec
—
—
.590
%tBIT
CBUS;RBUS conditions:
1 nF; 1 k | 6.8 nF; 660 |
10 nF; 500
THREC(MAX) = 0.251 x VBB,
THDOM(MAX) = 0.389 x VBB,
VBB =7.6V - 18V; tBIT = 96 µs.
D4 = tBUS_REC(MAX) / 2 x tBIT)
Note 1:
2:
Time depends on external capacitance and load. Test condition: CREG = 4.7uF, no resistor load.
For design guidance only, not tested.
DS22306A-page 18
 2012 Microchip Technology Inc.
MCP2025
2.4
AC Specification (Continued)
AC CHARACTERISTICS
VBB = 6.0V to 18.0V; TA = -40°C to +125°C
Parameter
Sym.
Min.
Typ.
Max.
Units
Test Conditions
Voltage Regulator
Bus Activity Debounce time
tBDB
30
80
250
µs
tBACTIVE
35
—
200
µs
Voltage Regulator Enabled
to Ready
tVEVR
300
—
1200
µs
(Note 1)
Chip Select to Ready Mode
tCSR
—
—
230
µs
(Note 2)
(Note 2)
Bus Activity to Voltage
Regulator Enabled
Chip Select to Power-down
tCSPD
—
—
300
µs
tSHUTDOWN
20
—
100
µs
VREG OK detect to RESET
inactive
tRPU
—
—
60.0
µs
(Note 2)
VREG not OK detect to
RESET active
tRPD
—
—
60.0
µs
(Note 2)
Short circuit to shut-down
RESET Timing
Note 1:
2:
2.5
Time depends on external capacitance and load. Test condition: CREG = 4.7uF, no resistor load.
For design guidance only, not tested.
Thermal Specifications
THERMAL CHARACTERISTICS
Parameter
Symbol
Typ.
Max.
Units
Recovery Temperature
RECOVERY
+140
—
C
Shutdown Temperature
SHUTDOWN
+150
—
C
tTHERM
1.5
5.0
ms
Short Circuit Recovery Time
Test Conditions
Thermal Package Resistances
Thermal Resistance, 8-PDIP
JA
89.3
—
C/W
Thermal Resistance, 8-SOIC
JA
149.5
—
C/W
Thermal Resistance, 8-QFN
JA
48.0
—
C/W
Note 1:
The maximum power dissipation is a function of TJMAX, JA and ambient temperature TA. The maximum
allowable power dissipation at an ambient temperature is PD = (TJMAX - TA)JA. If this dissipation is
exceeded, the die temperature will rise above 150C and the MCP2025 will go into thermal shutdown.
 2012 Microchip Technology Inc.
DS22306A-page 19
MCP2025
2.6
Timing Diagrams and Specifications
FIGURE 2-2:
BUS TIMING DIAGRAM
TXD
50%
50%
LBUS
.95VLBUS
.50VBB
.05VLBUS
tTRANSPDR
tTRANSPDF
tRECPDF
0.0V
tRECPDR
RXD
50%
FIGURE 2-3:
50%
REGULATOR BUS WAKE TIMING DIAGRAM
LBUS
VWK(LBUS)
tVEVR
tBDB
tBACTIVE
VREG-NOM
VREG
DS22306A-page 20
 2012 Microchip Technology Inc.
MCP2025
FIGURE 2-4:
CS/LWAKE, REGULATOR AND RESET TIMING DIAGRAM
CS/LWAKE
tCSR
tVEVR
VREG-NOM
VREG
tRPD
tRPU
tCSPD
RESET
FIGURE 2-5:
TYPICAL IBBQ VS.
TEMPERATURE - 5.0V
FIGURE 2-7:
180
IBBQ POWER-DOWN VS.
TEMPERATURE - 5.0V
6
160
5
120
4
IBBQ (μA)
IBBQ (μA)
140
100
80
6V
12V
18V
60
40
3
6V
12V
2
18V
1
20
0
0
-45
FIGURE 2-6:
-10
25
90
Temperature(⁰C)
130
-45
-10
25
Temperature(⁰C)
90
130
IBBQ TRANS-OFF VS.
TEMPERATURE - 5.0V
80
70
IBBQ (μA)
60
50
40
6V
12V
18V
30
20
10
0
-45
-10
25
90
Temperature(⁰C)
 2012 Microchip Technology Inc.
130
DS22306A-page 21
MCP2025
TYPICAL IBBQVS.
TEMPERATURE - 3.3V
200
180
160
140
120
100
80
60
40
20
0
FIGURE 2-10:
IBBQ POWER-DOWN VS.
TEMPERATURE - 3.3V
6
5
IBBQ (μA)
IBBQ (μA)
FIGURE 2-8:
6V
4
3
6V
12V
18V
2
12V
18V
1
0
-45
FIGURE 2-9:
-10
25
90
Temperature(⁰C)
130
-45
-10
25
90
130
Temperature(⁰C)
IBBQ TRANS-OFF VS.
TEMPERATURE - 3.3V
90
80
IBBQ (μA)
70
60
50
6V
40
12V
30
18V
20
10
0
-45
DS22306A-page 22
-10
25
Temperature(⁰C)
90
130
 2012 Microchip Technology Inc.
MCP2025
3.0
PACKAGING INFORMATION
3.1
Package Marking Information
8-Lead DFN (4x4x0.9 mm)
XXXXXX
XXXXXX
YYWW
NNN
PIN 1
Example
202550
e3
E/MD^^
1220
256
PIN 1
8-Lead SOIC (150 mil)
NNN
8-Lead PDIP (300 mil)
XXXXXXXX
XXXXXNNN
Example:
2025-500
E/SN1220
256
Example
2025500
3
E/P e^^256
1220
YYWW
Legend: XX...X
Y
YY
WW
NNN
e3
*
Note:
Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
 2012 Microchip Technology Inc.
DS22306A-page 23
MCP2025
8-Lead Plastic Dual Flat, No Lead Package (MD) – 4x4x0.9 mm Body [DFN]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Microchip Technology Drawing C04-131E Sheet 1 of 2
DS22306A-page 24
 2012 Microchip Technology Inc.
MCP2025
8-Lead Plastic Dual Flat, No Lead Package (MD) – 4x4x0.9 mm Body [DFN]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Microchip Technology Drawing C04-131E Sheet 2 of 2
 2012 Microchip Technology Inc.
DS22306A-page 25
MCP2025
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS22306A-page 26
 2012 Microchip Technology Inc.
MCP2025
3 & ' !&" & 4# *!( !!& 4 %& &#&
&& 255***' '5 4
N
NOTE 1
E1
1
3
2
D
E
A2
A
L
A1
c
e
eB
b1
b
6&!
'! 9'&!
7"') %!
7,8.
7
7
&
;
<
& &
7:
1,
=
=
-
1!& &
=
=
.
-
-
##4
"# & 4!!
"# >#&
##4>#&
.
<
: 9&
-<
-?
9
-
<
)
?
)
<
1
=
=
& &
9#
6
4!!
9#>#&
9 * 9#>#&
: * +
-
!"#$%&" ' ()"&'"!&) &#*& & & # +%&, & !&
- '! !#.# &"#' #%! & "! ! #%! & "! !! &$#/ !#
'! #& .0
1,21!'! &$& "! **& "&& !
 2012 Microchip Technology Inc.
* ,<1
DS22306A-page 27
MCP2025
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS22306A-page 28
 2012 Microchip Technology Inc.
MCP2025
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
 2012 Microchip Technology Inc.
DS22306A-page 29
MCP2025
! ""#$%& !'
3 & ' !&" & 4# *!( !!& 4 %& &#&
&& 255***' '5 4
DS22306A-page 30
 2012 Microchip Technology Inc.
MCP2025
APPENDIX A:
REVISION HISTORY
Revision A (June 2012)
• Original Release of this Document.
 2012 Microchip Technology Inc.
DS22306A-page 31
MCP2025
NOTES:
DS22306A-page 32
 2012 Microchip Technology Inc.
MCP2025
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
–X
/XX
Examples:
Device:
MCP2025: LIN Transceiver with Voltage Regulator
MCP2025T: LIN Transceiver with Voltage Regulator
(Tape and Reel) (SOIC and DFN only)
a)
b)
c)
d)
e)
f)
g)
Temperature Range:
E
h)
Package:
P
= Plastic DIP (300 mil Body), 8-lead
SN = Plastic Small Outline SOIC, 8-lead
MD = Plastic Dual Flat DFN, 8-lead
Device
Temperature
Range
Package
= -40°C to +125°C
 2012 Microchip Technology Inc.
i)
j)
MCP2025-330E/SN:
MCP2025-330E/P:
MCP2025-330E/MD:
MCP2025-500E/SN:
MCP2025-500E/P:
MCP2025-500E/MD:
MCP2025T-330E/SN:
3.3V, 8L-SOIC package
3.3V, 8L-PDIP package
3.3V, 8L-DFN package
5.0V, 8L-SOIC package
5.0V, 8L-PDIP package
5.0V, 8L-DFN package
Tape and Reel,
3.3V, 8L-SOIC package
MCP2025T-500E/SN: Tape and Reel,
5.0V, 8L-SOIC package
MCP2025T-330E/MD: Tape and Reel,
3.3V, 8L-DFN package
MCP2025T-500E/MD: Tape and Reel,
5.0V, 8L-DFN package
DS22306A-page 33
MCP2025
NOTES:
DS22306A-page 34
 2012 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Trademarks
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
The Microchip name and logo, the Microchip logo, dsPIC,
KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,
PIC32 logo, rfPIC and UNI/O are registered trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MXDEV, MXLAB, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip
Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, chipKIT,
chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net,
dsPICworks, dsSPEAK, ECAN, ECONOMONITOR,
FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP,
Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB,
MPLINK, mTouch, Omniscient Code Generation, PICC,
PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE,
rfLAB, Select Mode, Total Endurance, TSHARC,
UniWinDriver, WiperLock and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2012, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 978-1-62076-393-3
QUALITY MANAGEMENT SYSTEM
CERTIFIED BY DNV
== ISO/TS 16949 ==
 2012 Microchip Technology Inc.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
DS22306A-page 35
Worldwide Sales and Service
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://www.microchip.com/
support
Web Address:
www.microchip.com
Asia Pacific Office
Suites 3707-14, 37th Floor
Tower 6, The Gateway
Harbour City, Kowloon
Hong Kong
Tel: 852-2401-1200
Fax: 852-2401-3431
India - Bangalore
Tel: 91-80-3090-4444
Fax: 91-80-3090-4123
India - New Delhi
Tel: 91-11-4160-8631
Fax: 91-11-4160-8632
Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
Denmark - Copenhagen
Tel: 45-4450-2828
Fax: 45-4485-2829
India - Pune
Tel: 91-20-2566-1512
Fax: 91-20-2566-1513
France - Paris
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
Japan - Osaka
Tel: 81-66-152-7160
Fax: 81-66-152-9310
Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Atlanta
Duluth, GA
Tel: 678-957-9614
Fax: 678-957-1455
Boston
Westborough, MA
Tel: 774-760-0087
Fax: 774-760-0088
Chicago
Itasca, IL
Tel: 630-285-0071
Fax: 630-285-0075
Cleveland
Independence, OH
Tel: 216-447-0464
Fax: 216-447-0643
Dallas
Addison, TX
Tel: 972-818-7423
Fax: 972-818-2924
Detroit
Farmington Hills, MI
Tel: 248-538-2250
Fax: 248-538-2260
Indianapolis
Noblesville, IN
Tel: 317-773-8323
Fax: 317-773-5453
Los Angeles
Mission Viejo, CA
Tel: 949-462-9523
Fax: 949-462-9608
Santa Clara
Santa Clara, CA
Tel: 408-961-6444
Fax: 408-961-6445
Toronto
Mississauga, Ontario,
Canada
Tel: 905-673-0699
Fax: 905-673-6509
Australia - Sydney
Tel: 61-2-9868-6733
Fax: 61-2-9868-6755
China - Beijing
Tel: 86-10-8569-7000
Fax: 86-10-8528-2104
China - Chengdu
Tel: 86-28-8665-5511
Fax: 86-28-8665-7889
China - Chongqing
Tel: 86-23-8980-9588
Fax: 86-23-8980-9500
Korea - Daegu
Tel: 82-53-744-4301
Fax: 82-53-744-4302
China - Hangzhou
Tel: 86-571-2819-3187
Fax: 86-571-2819-3189
Korea - Seoul
Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
82-2-558-5934
China - Hong Kong SAR
Tel: 852-2401-1200
Fax: 852-2401-3431
Malaysia - Kuala Lumpur
Tel: 60-3-6201-9857
Fax: 60-3-6201-9859
China - Nanjing
Tel: 86-25-8473-2460
Fax: 86-25-8473-2470
Malaysia - Penang
Tel: 60-4-227-8870
Fax: 60-4-227-4068
China - Qingdao
Tel: 86-532-8502-7355
Fax: 86-532-8502-7205
Philippines - Manila
Tel: 63-2-634-9065
Fax: 63-2-634-9069
China - Shanghai
Tel: 86-21-5407-5533
Fax: 86-21-5407-5066
Singapore
Tel: 65-6334-8870
Fax: 65-6334-8850
China - Shenyang
Tel: 86-24-2334-2829
Fax: 86-24-2334-2393
Taiwan - Hsin Chu
Tel: 886-3-5778-366
Fax: 886-3-5770-955
China - Shenzhen
Tel: 86-755-8203-2660
Fax: 86-755-8203-1760
Taiwan - Kaohsiung
Tel: 886-7-536-4818
Fax: 886-7-330-9305
China - Wuhan
Tel: 86-27-5980-5300
Fax: 86-27-5980-5118
Taiwan - Taipei
Tel: 886-2-2500-6610
Fax: 886-2-2508-0102
China - Xian
Tel: 86-29-8833-7252
Fax: 86-29-8833-7256
Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
UK - Wokingham
Tel: 44-118-921-5869
Fax: 44-118-921-5820
China - Xiamen
Tel: 86-592-2388138
Fax: 86-592-2388130
China - Zhuhai
Tel: 86-756-3210040
Fax: 86-756-3210049
DS22306A-page 36
Japan - Yokohama
Tel: 81-45-471- 6166
Fax: 81-45-471-6122
11/29/11
 2012 Microchip Technology Inc.