Samsung K4F641612E 4m x 16bit cmos dynamic ram with fast page mode Datasheet

Industrial Temperature
K4F661612E, K4F641612E
CMOS DRAM
4M x 16bit CMOS Dynamic RAM with Fast Page Mode
DESCRIPTION
This is a family of 4,194,304 x 16 bit Fast Page Mode CMOS DRAMs. Fast Page Mode offers high speed random access of memory
cells within the same row. Refresh cycle(4K Ref. or 8K Ref.), access time (-45, -50 or -60), power consumption(Normal or Low pow er)
are optional features of this family. All of this family have CAS-before-RAS refresh, RAS -only refresh and Hidden refresh capabilities.
Furthermore, Self-refresh operation is available in L-version. This 4Mx16 Fast Page Mode DRAM family is fabricated using Samsung ′s
advanced CMOS process to realize high band-width, low power consumption and high reliability.
FEATURES
• Fast Page Mode operation
• Part Identification
• 2CAS Byte/Word Read/Write operation
- K4F661612E-TI/P(3.3V, 8K Ref.)
- K4F641612E-TI/P(3.3V, 4K Ref.)
• CAS-before-RAS refresh capability
• RAS-only and Hidden refresh capability
• Self-refresh capability (L-ver only)
• Fast parallel test mode capability
• LVTTL(3.3V) compatible inputs and outputs
• Active Power Dissipation
Unit : mW
• Early Write or output enable controlled write
Speed
8K
4K
• JEDEC Standard pinout
-45
324
468
• Available in Plastic TSOP(II) packages
-50
288
432
-60
252
396
• +3.3V ±0.3V power supply
• Industrial Temperature operating ( -40~85°C )
• Refresh Cycles
Refresh
cycle
Normal
L-ver
K4F661612E*
8K
64ms
128ms
K4F641612E
4K
FUNCTIONAL BLOCK DIAGRAM
Refresh time
* Access mode & RAS only refresh mode
: 8K cycle/64ms(Normal), 8K cycle/128ms(L-ver.)
CAS -before-RAS & Hidden refresh mode
: 4K cycle/64ms(Normal), 4K cycle/128ms(L-ver.)
RAS
UCAS
LCAS
W
Control
Clocks
Refresh Timer
• Performance Range
Speed
t RAC
t CAC
t RC
t PC
-45
45ns
12ns
80ns
31ns
-50
50ns
13ns
90ns
35ns
-60
60ns
15ns
110ns
40ns
A0~A12
(A0~A11)*1
Row Address Buffer
A0~A8
(A0~A9)*1
Col. Address Buffer
Lower
Data in
Buffer
Row Decoder
Refresh Control
Refresh Counter
Vcc
Vss
VBB Generator
Memory Array
4,194,304 x 16
Cells
Column Decoder
Note) *1 : 4K Refresh
SAMSUNG ELECTRONICS CO., LTD. reserves the right to
change products and specifications without notice.
Sens e Am ps & I/O
Part
NO.
Lower
Data out
Buffer
Upper
Data in
Buffer
Upper
Data out
Buffer
DQ0
to
DQ7
OE
D Q8
to
DQ15
Industrial Temperature
K4F661612E, K4F641612E
CMOS DRAM
PIN CONFIGURATION (Top Views)
• K4F661612E-T
• K4F641612E-T
VCC
DQ0
DQ1
DQ2
DQ3
VCC
DQ4
DQ5
DQ6
DQ7
N.C
VCC
W
RAS
N.C
N.C
N.C
N.C
A0
A1
A2
A3
A4
A5
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
V SS
DQ15
DQ14
DQ13
DQ12
V SS
DQ11
DQ10
DQ9
DQ8
N.C
V SS
LCAS
UCAS
OE
N.C
N.C
A12(N.C)*
A11
A10
A9
A8
A7
A6
V SS
(400mil TSOP(II))
*(N.C) : N.C for 4K Refresh Product
Pin Name
Pin function
A0 - A12
Address Inputs(8K Product)
A0 - A11
Address Inputs(4K Product)
DQ0 - 15
Data In/Out
VSS
Ground
RAS
Row Address Strobe
UCAS
Upper Column Address Strobe
LCAS
Lower Column Address Strobe
W
Read/Write Input
OE
Data Output Enable
VCC
Power(+3.3V)
N.C
No Connection
Industrial Temperature
K4F661612E, K4F641612E
CMOS DRAM
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Rating
Units
VIN, VO U T
-0.5 to +4.6
V
Voltage on VCC supply relative to V SS
V CC
-0.5 to +4.6
V
Storage Temperature
Tstg
-55 to +150
°C
Power Dissipation
PD
1
W
IOS Address
50
mA
Voltage on any pin relative to VSS
Short Circuit Output Current
* Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to
the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
Parameter
(Voltage referenced to Vss, TA= -40 to 85°C)
Symbol
Min
Typ
Max
Units
Supply Voltage
VC C
3.0
3.3
3.6
V
Ground
VSS
0
0
0
V
*1
Input High Voltage
VI H
2.0
-
Vcc+0.3
V
Input Low Voltage
V IL
-0.3 *2
-
0.8
V
*1 : Vcc+1.3V at pulse width ≤15ns which is measured at VCC
*2 : -1.3 at pulse width ≤15ns which is measured at VSS
DC AND OPERATING CHARACTERISTICS
Parameter
(Recommended operating conditions unless otherwise noted.)
Symbol
Min
Max
Units
Input Leakage Current (Any input 0≤V I N≤V CC+0.3V,
all other pins not under test=0 Volt)
II(L)
-5
5
uA
Output Leakage Current
(Data out is disabled, 0V≤V OUT ≤VCC )
IO(L)
-5
5
uA
Output High Voltage Level(IO H=-2mA)
VO H
2.4
-
V
Output Low Voltage Level(IOL=2mA)
VOL
-
0.4
V
Industrial Temperature
K4F661612E, K4F641612E
CMOS DRAM
DC AND OPERATING CHARACTERISTICS
Symbol
Power
Speed
IC C 1
Don′t care
IC C 2
(Continued)
Max
Units
K4F661612E
K4F641612E
-45
-50
-60
90
80
70
130
120
110
mA
mA
mA
Normal
L
Don′t care
1
1
1
1
mA
mA
IC C 3
Don′t care
-45
-50
-60
90
80
70
130
120
110
mA
mA
mA
IC C 4
Don′t care
-45
-50
-60
70
60
50
70
60
50
mA
mA
mA
IC C 5
Normal
L
Don′t care
0.5
200
0.5
200
mA
uA
IC C 6
Don′t care
-45
-50
-60
130
120
110
130
120
110
mA
mA
mA
IC C 7
L
Don′t care
350
350
uA
ICCS
L
Don′t care
350
350
uA
IC C 1* : Operating Current (RAS and UCAS, LCAS, Address cycling @t R C=min.)
IC C 2 : Standby Current (RAS=UCAS=LCAS=W=VIH )
IC C 3* : RAS-only Refresh Current (UCAS=LCAS=V IH , RAS, Address cycling @tRC =min.)
IC C 4* : Fast Page Mode Current (RAS=VIL , UCAS or LCAS, Address cycling @ tPC =min.)
IC C 5 : Standby Current (RAS=UCAS=LCAS=W=VCC -0.2V)
IC C 6* : CAS-Before- RAS Refresh Current (RAS and UCAS or LCAS cycling @t R C=min)
IC C 7 : Battery back-up current, Average power supply current, Battery back-up mode
Input high voltage(VIH )=VC C-0.2V, Input low voltage(VIL )=0.2V, UCAS, LCAS=CAS -before-RAS cycling or 0.2V,
W, OE=VI H, Address=Don′t care, DQ=Open, T R C=31.25us
IC C S : Self Refresh Current
RAS=UCAS =LCAS=0.2V, W=OE=A0 ~ A12(A11)=VCC -0.2V or 0.2V, DQ0 ~ DQ15=V CC-0.2V, 0.2V or Open
*Note :
ICC1 , I CC3, I CC4 and ICC6 are dependent on output loading and cycle rates. Specified values are obtained with the output open.
ICC is specified as an average current. In IC C 1, I CC3 and ICC6, address can be changed maximum once while RAS =VIL. In I CC4 ,
address can be changed maximum once within one fast page mode cycle time, t PC .
Industrial Temperature
K4F661612E, K4F641612E
CAPACITANCE
CMOS DRAM
(TA=25°C, VCC=3.3V, f=1MHz)
Parameter
Symbol
Min
Max
Units
Input capacitance [A0 ~ A12]
CI N 1
-
5
pF
Input capacitance [RAS, UCAS, LCAS, W, OE]
CI N 2
-
7
pF
Output capacitance [DQ0 - DQ15]
C DQ
-
7
pF
AC CHARACTERISTICS
(-40°C≤TA≤85°C, See note 2)
Test condition : V C C=3.3V±0.3V, Vih/Vil=2.2/0.7V, Voh/Vol=2.0/0.8V
Parameter
-45
Symbol
Min
-50
Max
Min
-60
Max
Min
Units
Note
Max
Random read or write cycle time
tR C
80
90
110
ns
Read-modify-write cycle time
tRWC
115
133
153
ns
Access time from RAS
tRAC
45
50
60
ns
3,4,10
Access time from CAS
tCAC
12
13
15
ns
3,4,5
Access time from column address
tAA
23
25
30
ns
3,10
CAS to output in Low-Z
tCLZ
0
ns
3
Output buffer turn-off delay
tO F F
0
13
0
13
0
13
ns
6
Transition time (rise and fall)
tT
1
50
1
50
1
50
ns
2
RAS precharge time
tR P
25
RAS pulse width
0
0
30
10K
50
40
10K
60
ns
tR A S
45
RAS hold time
tRSH
12
13
15
10K
ns
ns
CAS hold time
tCSH
45
50
60
ns
CAS pulse width
tC A S
12
10K
13
10K
15
10K
ns
RAS to CAS delay time
tRCD
18
33
20
37
20
45
ns
4
RAS to column address delay time
tRAD
13
22
15
25
15
30
ns
10
CAS to RAS precharge time
tCRP
5
5
5
ns
Row address set-up time
tASR
0
0
0
ns
Row address hold time
tRAH
8
10
10
ns
Column address set-up time
tASC
0
0
0
ns
13
Column address hold time
13
tCAH
8
10
10
ns
Column address to RAS lead time
tR A L
23
25
30
ns
Read command set-up time
tRCS
0
0
0
ns
Read command hold time referenced to CAS
tRCH
0
0
0
ns
8
Read command hold time referenced to RAS
tRRH
0
0
0
ns
8
Write command hold time
tWCH
8
10
10
ns
Write command pulse width
tW P
8
10
10
ns
Write command to RAS lead time
tRWL
13
15
15
ns
Write command to CAS lead time
tCWL
12
13
15
ns
16
Data set-up time
tD S
0
0
0
ns
9,19
Data hold time
tD H
10
10
10
ns
9,19
Industrial Temperature
K4F661612E, K4F641612E
AC CHARACTERISTICS
CMOS DRAM
(Continued)
Parameter
-45
Symbol
Min
Refresh period (Normal)
-50
Max
Min
-60
Max
Min
Units
Note
Max
t REF
64
64
64
ms
Refresh period (L-ver)
t REF
128
128
128
ms
Write command set-up time
t WCS
0
0
0
ns
7
CAS to W delay time
t CWD
32
36
38
ns
7,15
RAS to W delay time
tR W D
67
73
83
ns
7
Column address to W delay time
t AWD
43
48
53
ns
7
CAS precharge W delay time
tC P W D
48
53
60
ns
CAS set-up time (CAS -before-RAS refresh)
t CSR
5
5
5
ns
17
CAS hold time (CAS -before-RAS refresh)
t CHR
10
10
10
ns
18
RAS to CAS precharge time
t RPC
5
Access time from CAS precharge
t CPA
Fast Page mode cycle time
5
26
5
30
ns
35
ns
t PC
31
35
40
ns
Fast Page mode read-modify-write cycle time
tP R W C
70
76
85
ns
CAS precharge time (Fast page cycle)
tC P
9
10
10
ns
RAS pulse width (Fast page cycle)
3
14
t RASP
45
RAS hold time from CAS precharge
t RHCP
28
OE access time
t OEA
OE to data delay
t OED
12
Output buffer turn off delay time from OE
tOEZ
0
OE command hold time
t OEH
12
13
15
ns
Write command set-up time (Test mode in)
t WTS
10
10
10
ns
11
Write command hold time (Test mode in)
t WTH
15
15
15
ns
11
W to RAS precharge time (C-B-R refresh)
200K
50
200
30
12
13
0
200
35
13
13
60
ns
15
13
13
0
ns
ns
3
ns
13
ns
6
t WRP
10
10
10
ns
W to RAS hold time (C-B-R refresh)
t WRH
10
10
10
ns
RAS pulse width (C-B-R self refresh)
t RASS
100
100
100
us
20,21,22
RAS precharge time (C-B-R self refresh)
t RPS
80
90
110
ns
20,21,22
CAS hold time (C-B-R self refresh)
t CHS
-50
-50
-50
ns
20,21,22
Industrial Temperature
K4F661612E, K4F641612E
CMOS DRAM
TEST MODE CYCLE
Parameter
( Note 11 )
-45
Symbol
Min
-50
Max
Min
-60
Max
Min
Units
Note
Max
Random read or write cycle time
tR C
85
95
115
ns
Read-modify-write cycle time
tR W C
120
138
160
ns
Access time from RAS
t RAC
50
55
65
ns
3,4,10,12
Access time from CAS
t CAC
17
18
20
ns
3,4,5,12
Access time from column address
t AA
28
30
35
ns
3,10,12
RAS pulse width
tRAS
50
10K
55
10K
65
10K
ns
CAS pulse width
tCAS
17
10K
18
10K
20
10K
ns
RAS hold time
t RSH
17
18
20
ns
CAS hold time
t CSH
50
55
65
ns
Column Address to RAS lead time
tRAL
28
30
35
ns
CAS to W delay time
t CWD
37
41
43
ns
7
RAS to W delay time
tR W D
72
78
88
ns
7
Column Address to W delay time
t AWD
48
53
58
ns
7
Fast Page mode cycle time
t PC
36
40
45
ns
Fast Page mode read-modify-write cycle time
tP R W C
75
81
90
ns
RAS pulse width (Fast page cycle)
t RASP
50
Access time from CAS precharge
t CPA
31
OE access time
t OEA
17
OE to data delay
t OED
17
18
18
ns
OE command hold time
t OEH
17
18
20
ns
200K
55
200K
65
200K
ns
35
40
ns
18
20
ns
3
Industrial Temperature
K4F661612E, K4F641612E
CMOS DRAM
NOTES
1. An initial pause of 200§Á is required after power-up followed by any 8 ROR or CBR cycles before proper device operation is
achieved.
2. V IH(min) and VIL (max) are reference levels for measuring timing of input signals. Transition times are measured between
V IH(min) and V IL (max) and are assumed to be 5ns for all inputs.
3. Measured with a load equivalent to 1 TTL load and 100pF.
4. Operation within the t RCD (max) limit insures that tRAC (max) can be met. tRCD (max) is specified as a reference point only.
If t RCD is greater than the specified t RCD (max) limit, then access time is controlled exclusively by tCAC .
5. Assumes that t R C D≥t R C D(max).
6. t OFF (min)and t O E Z(max) define the time at which the output achieves the open circuit condition and are not referenced Voh or
Vol .
7. t W C S, tRWD , tCWD and tAWD are non restrictive operating parameters. They are included in the data sheet as electric characteristics only. If t WCS ≥tW C S(min), the cycles is an early write cycle and the data output will remain high impedance for the
duration of the cycle. If t C W D≥t C W D(min), tRWD ≥ tRWD (min) and t AWD ≥t AWD (min), then the cycle is a read-modify-write cycle
and the data output will contain the data read from the selected address. If neither of the above conditions is satisfied, the
condition of the data out is indeterminate.
8. Either tRCH or t RRH must be satisfied for a read cycle.
9. These parameters are referenced to the CAS leading edge in early write cycles and to the W falling edge in read-modifywrite cycles.
10. Operation within the t RAD (max) limit insures that t RAC (max) can be met. tRAD (max) is specified as a reference point only. If
t RAD is greater than the specified t RAD (max) limit, then access time is controlled by t AA.
11. These specifications are applied in the test mode.
12. In test mode read cycle, the value of tRAC , t AA, tCAC is delayed by 2ns to 5ns for the specified values. These parameters
should be specified in test mode cycles by adding the above value to the specified value in this data sheet.
K4F64(6)1612E Truth Table
RAS
LCAS
UCAS
W
OE
DQ0 - DQ7
DQ8-DQ15
STATE
H
X
X
X
X
Hi-Z
Hi-Z
Standby
L
H
H
X
X
Hi-Z
Hi-Z
Refresh
L
L
H
H
L
DQ-OUT
Hi-Z
Byte Read
L
H
L
H
L
Hi-Z
DQ-OUT
Byte Read
L
L
L
H
L
DQ-OUT
DQ-OUT
Word Read
L
L
H
L
H
DQ-IN
-
Byte Write
L
H
L
L
H
-
DQ-IN
Byte Write
L
L
L
L
H
DQ-IN
DQ-IN
Word Write
L
L
L
H
H
Hi-Z
Hi-Z
-
Industrial Temperature
K4F661612E, K4F641612E
CMOS DRAM
13. tASC , tCAH are referenced to the earlier CAS falling edge.
14. tCP is specified from the last CAS rising edge in the previous cycle to the first CAS falling edge in the next cycle.
15. tC W D is referenced to the later CAS falling edge at word read-modify-write cycle.
16. tC W L is specified from W falling edge to the earlier CAS rising edge.
17. tCSR is referenced to earlier CAS falling before RAS transition low.
18. tC H R is referenced to the later CAS rising high after RAS transition low.
RAS
LCAS
UCAS
t CSR
tC H R
19. tDS is specified for the earlier CAS falling edge and tDH is specified by the later CAS falling edge.
LCAS
UCAS
tD S
DQ0 ~ DQ15
tDH
Din
20. If t RASS ≥100us, then RAS precharge time must use tRPS instead of t R P.
21. For RAS -only-Refresh and Burst CAS -before-RAS refresh mode, 4096 cycles(4K/8K) of burst refresh must be executed within
64ms before and after self refresh, in order to meet refresh specification.
22. For distributed CAS-before-RAS with 15.6us interval, CBR refresh should be executed with in 15.6us immediately before and
after self refresh in order to meet refresh specification.
Industrial Temperature
K4F661612E, K4F641612E
CMOS DRAM
WORD READ CYCLE
tRC
tRAS
tR P
VIH -
RAS
VIL -
tCSH
t CRP
t RCD
UCAS
t CRP
tRSH
V IH -
tCAS
V IL -
tCSH
tC R P
LCAS
tRCD
tCRP
tRSH
V IH -
tCAS
V IL -
tRAD
t ASR
V IH -
A
V IL -
t RAH
tRAL
tASC
t CAH
COLUMN
ADDRESS
ROW
ADDRESS
t RCH
tRCS
tR R H
V IH -
W
V IL -
tAA
OE
VIH -
t OEA
VIL -
DQ0 ~ DQ7
VO H V OL -
tRAC
t CAC
tCLZ
OPEN
tO F F
tOEZ
DATA-OUT
tOFF
t CAC
DQ8 ~ DQ15
VO H V OL -
tRAC
OPEN
tCLZ
tO E Z
DATA-OUT
Don′t care
Undefined
Industrial Temperature
K4F661612E, K4F641612E
CMOS DRAM
LOWER BYTE READ CYCLE
NOTE : DIN = OPEN
tR C
tRAS
RAS
t RP
VIH VIL -
tCRP
UCAS
t RPC
VIH VIL -
t CSH
t CRP
LCAS
t RCD
tRSH
t CAS
VIH VIL -
tRAD
t ASR
A
VIH VIL -
t RAH
t ASC
ROW
ADDRESS
tRAL
tCAH
COLUMN
ADDRESS
t RCH
tR C S
W
tRRH
V IH V IL -
t OFF
tAA
OE
VIH -
t OEA
VIL -
DQ0 ~ DQ7
VO H V OL -
tOEZ
tRAC
t CAC
tCLZ
OPEN
DATA-OUT
DQ8 ~ DQ15
VOH VOL -
OPEN
Don′t care
Undefined
Industrial Temperature
K4F661612E, K4F641612E
CMOS DRAM
UPPER BYTE READ CYCLE
NOTE : DIN = OPEN
tRC
tRAS
RAS
V IL -
tCSH
tCRP
UCAS
tRP
V IH -
tRCD
tCRP
tRSH
tCAS
V IH V IL -
tRPC
tCRP
LCAS
V IH V IL -
tRAD
tRAL
tASR
A
V IH V IL -
t RAH
tASC
ROW
ADDRESS
t CAH
COLUMN
ADDRESS
t RCH
tR C S
W
tR R H
V IH V IL -
t OFF
t AA
OE
V IH -
tOEZ
tOEA
V IL -
DQ0 ~ DQ7
V OH -
OPEN
V OL DQ8 ~ DQ15
V OH V OL -
tCAC
tRAC
OPEN
tCLZ
DATA-OUT
Don′t care
Undefined
Industrial Temperature
K4F661612E, K4F641612E
CMOS DRAM
WORD WRITE CYCLE ( EARLY WRITE )
NOTE : DOUT = OPEN
tR C
tR A S
RAS
VIL -
t CSH
tC R P
UCAS
tR C D
tRSH
VIH -
tC R P
t CAS
VIL -
tCSH
tC R P
LCAS
t RP
VIH -
tRCD
tRSH
V IH -
tCRP
tCAS
V IL -
tRAD
t ASR
A
V IH V IL -
t RAH
tRAL
tASC
ROW
ADDRESS
t CAH
COLUMN
ADDRESS
t WCS
W
OE
tW C H
V IH -
tW P
V IL -
VIH VIL -
DQ0 ~ DQ7
V IH -
tDS
DATA-IN
V IL -
DQ8 ~ DQ15
V IH -
tD H
tDS
tD H
DATA-IN
V IL -
Don′t care
Undefined
Industrial Temperature
K4F661612E, K4F641612E
CMOS DRAM
LOWER BYTE WRITE CYCLE ( EARLY WRITE )
NOTE : DOUT = OPEN
tR C
t RAS
RAS
t RP
V IH V IL -
t CRP
UCAS
t RPC
VIH VIL -
tCSH
t CRP
LCAS
tRCD
tRSH
VIH -
tCRP
tCAS
VIL -
t RAD
t ASR
A
V IH V IL -
t RAH
t ASC
tRAL
t CAH
COLUMN
ADDRESS
ROW
ADDRESS
t WCS
W
OE
V IH -
tW C H
tW P
V IL -
VIH VIL -
DQ0 ~ DQ7
VIH -
tDS
tD H
DATA-IN
VIL -
DQ8 ~ DQ15
V IH V IL -
Don′t care
Undefined
Industrial Temperature
K4F661612E, K4F641612E
CMOS DRAM
UPPER BYTE WRITE CYCLE ( EARLY WRITE )
NOTE : DOUT = OPEN
t RC
tRAS
RAS
V IL -
tCSH
tC R P
UCAS
tR P
V IH -
t RCD
tC A S
V IL -
tC R P
LCAS
tC R P
t RSH
V IH -
t RPC
VIH VIL -
t RAD
tASR
A
V IH V IL -
tRAH
t RAL
tASC
ROW
ADDRESS
t CAH
COLUMN
ADDRESS
t WCS
W
OE
tWCH
VIH -
tWP
VIL -
V IH V IL -
DQ0 ~ DQ7
V IH V IL -
DQ8 ~ DQ15
V IH -
tDS
tD H
DATA-IN
V IL -
Don′t care
Undefined
Industrial Temperature
K4F661612E, K4F641612E
CMOS DRAM
WORD WRITE CYCLE ( OE CONTROLLED WRITE )
NOTE : DOUT = OPEN
tR C
t RAS
RAS
VIL -
t CSH
tC R P
UCAS
tR C D
t RSH
VIH -
tC R P
t CAS
VIL -
tCSH
tC R P
LCAS
t RP
VIH -
tRCD
t RSH
VIH -
tCRP
tCAS
VIL -
tRAD
t ASR
A
V IH V IL -
t RAH
tRAL
tASC
ROW
ADDRESS
tCAH
COLUMN
ADDRESS
tC W L
tR W L
W
OE
V IH -
tWP
V IL -
VIH VIL -
DQ0 ~ DQ7
VIH -
t OEH
t OED
tDS
DATA-IN
VIL -
DQ8 ~ DQ15
V IH -
t DH
tDS
t DH
DATA-IN
V IL -
Don′t care
Undefined
Industrial Temperature
K4F661612E, K4F641612E
CMOS DRAM
LOWER BYTE WRITE CYCLE ( OE CONTROLLED WRITE )
NOTE : DOUT = OPEN
tR C
tRAS
RAS
V IL -
t CRP
UCAS
t RPC
V IH V IL -
t CSH
tC R P
LCAS
tR P
V IH -
tR C D
t RSH
V IH -
tC R P
t CAS
V IL -
t RAD
tASR
A
VIH VIL -
tRAH
t RAL
tASC
ROW
ADDRESS
tCAH
COLUMN
ADDRESS
tC W L
tR W L
W
OE
VIH -
t WP
VIL -
V IH V IL -
DQ0 ~ DQ7
V IH V IL -
tOEH
t OED
tDS
tDH
DATA-IN
DQ8 ~ DQ15
V IH V IL -
Don′t care
Undefined
Industrial Temperature
K4F661612E, K4F641612E
CMOS DRAM
UPPER BYTE WRITE CYCLE ( OE CONTROLLED WRITE )
NOTE : DOUT = OPEN
t RC
tRAS
RAS
V IL -
tCSH
t CRP
UCAS
tRP
V IH -
tRCD
tC A S
V IL -
t CRP
LCAS
tC R P
t RSH
V IH -
t RPC
V IH V IL -
t RAD
tASR
A
V IH V IL -
tRAH
t RAL
tASC
ROW
ADDRESS
t CAH
COLUMN
ADDRESS
tC W L
W
OE
t RWL
VIH -
tWP
VIL -
V IH V IL -
t OEH
t OED
DQ0 ~ DQ7
VIH VIL -
DQ8 ~ DQ15
V IH V IL -
tDS
tDH
DATA-IN
Don′t care
Undefined
Industrial Temperature
K4F661612E, K4F641612E
CMOS DRAM
WORD READ - MODIFY - WRITE CYCLE
tRWC
tR A S
RAS
VIL -
tCRP
UCAS
tR C D
tRSH
V IH -
t CAS
V IL -
tCRP
LCAS
tR P
VIH -
tR C D
tRSH
VIH -
t CAS
VIL -
t RAD
t CSH
tASR
A
VIH VIL -
t RAH
ROW
ADDR
t ASC
tCAH
COLUMN
ADDRESS
tRWL
tAWD
t CWL
tCWD
W
OE
VIH -
tWP
VIL -
tRWD
tOEA
V IH V IL -
t CLZ
tCAC
t AA
DQ0 ~ DQ7
VI/OH -
tOED
tO E Z
t RAC
t DS
VALID
DATA-OUT
VI/OL -
t DH
VALID
DATA-IN
t CLZ
tCAC
t AA
DQ8 ~ DQ15
V I/OH V I/OL -
tOED
tO E Z
t RAC
VALID
DATA-OUT
tDS
t DH
VALID
DATA-IN
Don′t care
Undefined
Industrial Temperature
K4F661612E, K4F641612E
CMOS DRAM
LOWER-BYTE READ - MODIFY - WRITE CYCLE
tRWC
tR A S
RAS
tR P
VIH VIL -
t RPC
t CRP
UCAS
V IH V IL -
tC R P
LCAS
tR C D
tRSH
VIH -
t CAS
VIL -
tRAD
t CSH
tASR
A
VIH VIL -
t RAH
ROW
ADDR
t ASC
t CAH
COLUMN
ADDRESS
t RWL
t AWD
t CWD
W
OE
tCWL
VIH -
tWP
VIL -
tRWD
tOEA
V IH V IL -
t CLZ
tCAC
t AA
DQ0 ~ DQ7
VI/OH VI/OL DQ8 ~ DQ15
VI/OH VI/OL -
t RAC
tOED
tO E Z
VALID
DATA-OUT
tD S
tD H
VALID
DATA-IN
OPEN
Don′t care
Undefined
Industrial Temperature
K4F661612E, K4F641612E
CMOS DRAM
UPPER-BYTE READ - MODIFY - WRITE CYCLE
tRWC
tR P
tRAS
RAS
VIH VIL -
t CRP
UCAS
tR C D
tRSH
VIH -
tCAS
VIL -
t CRP
LCAS
tRPC
VIH VIL -
t RAD
tCSH
t ASR
A
VIH VIL -
t RAH
ROW
ADDR
t ASC
t CAH
COLUMN
ADDRESS
tRWL
tAWD
tCWL
t CWD
W
OE
V IH -
tWP
V IL -
tRWD
tOEA
V IH V IL -
DQ0 ~ DQ7
V I/OH -
OPEN
V I/OL -
t CLZ
t CAC
DQ8 ~ DQ15
VI/OH VI/OL -
t AA
t OED
tRAC
tOEZ
VALID
DATA-OUT
t DS
tD H
VALID
DATA-IN
Don′t care
Undefined
Industrial Temperature
K4F661612E, K4F641612E
CMOS DRAM
FAST PAGE MODE WORD READ CYCLE
tRP
t RASP
RAS
V IH V IL -
¡ó
tRHCP
tCSH
tPC
tCRP
UCAS
tR C D
tPC
tC P
tC A S
VIH -
t PC
tC P
tCAS
tC P
t RPC
tC A S
tC A S
VIL -
t RAL
tC R P
LCAS
tR C D
t CAS
tC P
V IH V IL -
t RAD
t RAH t ASC
ROW
ADDR
t CAH
tASC
COLUMN
ADDRESS
tCAH
t ASC
tC A S
COLUMN
ADDRESS
t RCH
tCAH
t ASC
COLUMN
ADDR
t RCS
tRCH
tCAH
COLUMN
ADDRESS
tRCS
t RCH
tR C S
tRRH
t RCH
V IH V IL -
t CAC
t AA
OE
tRPC
tC A S
V IL -
tR C S
W
t CP
tC A S
V IH -
tASR
A
tC P
t OEA
VIH -
t CAC
tAA
tAA
t CPA
t CPA
tOEA
tCAC
t AA
t CPA
t OEA
tOEA
VIL -
t CAC
DQ0 ~ DQ7
V OH -
tO F F
tRAC
tOEZ
VALID
V OL -
tO F F
tRAC
VOL -
tOEZ
VALID
DATA-OUT
tOFF
tOEZ
VALID
DATA-OUT
tOFF
tOEZ
VALID
DATA-OUT
tO F F
tOEZ
VALID
DATA-OUT
tOFF
tOEZ
VALID
DATA-OUT
DATA-OUT
t CLZ
tCAC
DQ8 ~ DQ15
VOH -
tO F F
tOFF
tOEZ
VALID
DATA-OUT
tOEZ
VALID
DATA-OUT
t CLZ
Don′t care
Undefined
Industrial Temperature
K4F661612E, K4F641612E
CMOS DRAM
FAST PAGE MODE LOWER BYTE READ CYCLE
tR A S P
tR P
VIH -
RAS
VIL -
¡ó
tR H C P
t CRP
t RPC
V IH -
UCAS
V IL -
t PC
tC R P
LCAS
tPC
tCP
tCAS
tC P
tCAS
tCAS
VIH VIL -
tRAD
t RAH
t ASC t CAH
ROW
ADDR
t ASC t CAH
COLUMN
ADDRESS
tASC
COLUMN
ADDRESS
tCAH
tR C S
t RCH
tASC
COLUMN
ADDR
tCAH
COLUMN
ADDRESS
tR C S
tR C H
tR C H
t RCS
t RRH
tR C H
VIH VIL -
tCAC
tCAC
tAA
OE
t RPC
tCAS
VIL -
tRCS
W
t PC
tCP
tRCD
VIH -
t ASR
A
t RAL
t CSH
t AA
tOEA
V IH -
t CAC
tAA
tAA
tC P A
t OEA
tC P A
tOEA
tC P A
tOEA
tOFF
tOEZ
tOFF
tOEZ
V IL -
DQ0 ~ DQ7
VO H -
t CAC
t RAC
VALID
DATA-OUT
VOL -
VALID
DATA-OUT
t OFF
tOEZ
VALID
DATA-OUT
t OFF
tOEZ
VALID
DATA-OUT
tCLZ
DQ8 ~ DQ15
V OH V OL -
OPEN
Don′t care
Undefined
Industrial Temperature
K4F661612E, K4F641612E
CMOS DRAM
FAST PAGE MODE UPPER BYTE READ CYCLE
tR P
tR A S P
RAS
VIH VIL -
¡ó
t CSH
tC R P
UCAS
tR H C P
t PC
tRCD
t PC
tCP
tCAS
VIH -
tPC
tCP
tC A S
tC P
tCAS
t RPC
tCAS
VIL -
tCRP
LCAS
t RAL
VIL -
t RAD
t ASR
A
t RPC
VIH -
VIH VIL -
tRAH
ROW
ADDR
t ASC
tCAH
COLUMN
ADDRESS
t CAH
t ASC
COLUMN
ADDRESS
t CAH
tRCH
tCAH
COLUMN
ADDRESS
t RCS
tR C H
tRCH
tR C S
t RRH
tR C H
VIH VIL -
tCAC
tCAC
t AA
OE
t ASC
COLUMN
ADDR
tR C S
tR C S
W
t ASC
t AA
tOEA
V IH -
tCPA
t OEA
t CAC
tAA
tAA
tCPA
tOEA
tC P A
tOEA
V IL -
DQ0 ~ DQ7
V OH -
OPEN
V OL -
DQ8 ~ DQ15
VOH -
tCAC
t RAC
tOFF
tOEZ
VALID
DATA-OUT
VOL -
tOFF
tOEZ
VALID
DATA-OUT
t OFF
tOEZ
VALID
DATA-OUT
tOFF
tO E Z
VALID
DATA-OUT
t CLZ
Don′t care
Undefined
Industrial Temperature
K4F661612E, K4F641612E
CMOS DRAM
FAST PAGE MODE WORD WRITE CYCLE ( EARLY WRITE )
NOTE : DOUT = OPEN
t RASP
RAS
t RHCP
V IL -
¡ó
tPC
tCRP
UCAS
t RCD
t PC
tC P
V IH -
t RSH
t CP
tCAS
tC R P
tCAS
V IL -
tCAS
¡ó
tPC
tC R P
LCAS
tRP
V IH -
V IH -
t RSH
t PC
tC P
t RCD
tC P
tCAS
tCAS
V IL -
tCAS
¡ó
t RAD
t RAL
t CSH
tASR
A
V IH V IL -
tRAH
t ASC
t CAH
OE
V IH -
t CAH
tASC
t CAH
¡ó
ROW
ADDR
COLUMN
ADDRESS
tWCS
W
t ASC
tW C H
COLUMN
ADDRESS
tW C S
tWP
¡ó
t WCH
tW P
COLUMN
ADDRESS
tW C S
¡ó
t WCH
t WP
V IL -
¡ó
VIH VIL -
DQ0 ~ DQ7
VIH -
¡ó
tDS
V IL -
tD S
tDH
tDS
tDH
¡ó
VALID
DATA-IN
VIL -
DQ8 ~ DQ15
V IH -
t DH
tDS
t DH
VALID
DATA-IN
tD S
¡ó
tDH
VALID
DATA-IN
tDS
tDH
¡ó
VALID
DATA-IN
VALID
VALID
DATA-IN
DATA-IN
¡ó
Don′t care
Undefined
Industrial Temperature
K4F661612E, K4F641612E
CMOS DRAM
FAST PAGE MODE LOWER BYTE WRITE CYCLE ( EARLY WRITE )
NOTE : DOUT = OPEN
t RASP
RAS
t RP
V IH -
tR H C P
V IL -
¡ó
t RPC
tCRP
UCAS
¡ó
VIH VIL -
tPC
tCRP
LCAS
t RCD
tPC
t CP
V IH -
t RSH
tCP
tC A S
tCAS
V IL -
t CAS
¡ó
t RAD
tRAL
tCSH
t ASR
A
V IH V IL -
tRAH
t ASC
tCAH
OE
V IH -
t CAH
tASC
t CAH
¡ó
ROW
ADDR
COLUMN
ADDRESS
COLUMN
ADDRESS
COLUMN
ADDRESS
¡ó
t WCS
W
tASC
t WCH
t WCS
t WP
tWCH
tWP
tWCS
¡ó
tWCH
tW P
V IL -
¡ó
VIH VIL -
DQ0 ~ DQ7
V IH V IL -
¡ó
t DS
tDH
VALID
DATA-IN
t DS
t DH
VALID
DATA-IN
t DS
¡ó
tD H
VALID
DATA-IN
¡ó
DQ8 ~ DQ15
V IH V IL -
Don′t care
Undefined
Industrial Temperature
K4F661612E, K4F641612E
CMOS DRAM
FAST PAGE MODE UPPER BYTE WRITE CYCLE ( EARLY WRITE )
NOTE : DOUT = OPEN
t RASP
RAS
t RHCP
VIL -
¡ó
tPC
t CRP
UCAS
t RP
VIH -
tRCD
tPC
t CP
VIH -
t RSH
t CP
tCAS
t CAS
VIL -
t CAS
¡ó
tRPC
tCRP
LCAS
V IH V IL -
tRAD
t RAL
tCSH
tASR
A
VIH VIL -
t RAH
t ASC
t CAH
OE
V IH -
t CAH
tASC
t CAH
¡ó
ROW
ADDR.
COLUMN
ADDRESS
tW C S
W
t ASC
t WCH
COLUMN
ADDRESS
t WCS
tW P
¡ó
tWCH
tWP
COLUMN
ADDRESS
tW C S
¡ó
tWCH
tW P
V IL -
¡ó
VIH VIL -
¡ó
DQ0 ~ DQ7
V IH -
¡ó
V IL -
DQ8 ~ DQ15
V IH V IL -
¡ó
tDS
t DH
t DS
tD H
t DS
tD H
¡ó
VALID
DATA-IN
VALID
DATA-IN
VALID
DATA-IN
¡ó
Don′t care
Undefined
Industrial Temperature
K4F661612E, K4F641612E
CMOS DRAM
FAST PAGE MODE WORD READ-MODIFY-WRITE CYCLE
tR P
tRASP
RAS
VIH -
tCSH
VIL -
tC R P
UCAS
tRSH
tC R P
tC P
V IH -
t CAS
tCAS
V IL -
tC R P
LCAS
tPRWC
tRCD
tRCD
tC R P
tC P
VIH -
tCAS
tCAS
VIL -
t RAD
t RAH
t ASR
A
VIH VIL -
t RAL
t CAH
t CAH
tASC
t ASC
ROW
ADDR
COL.
ADDR
COL.
ADDR
tRWL
tCWL
tR C S
tC W L
W
OE
t RCS
VIH -
t WP
VIL -
tW P
tC W D
t AWD
tR W D
V IH -
t CWD
tA W D
t CPWD
t OEA
tOEA
V IL -
tOED
t CAC
tCAC
t AA
DQ0 ~ DQ7
V I/OH V I/OL -
tD S
t RAC
t CLZ
VALID
DATA-IN
t OED
tAA
VI/OL -
tOEZ
VALID
DATA-OUT
t CAC
tCAC
tRAC
tDS
tOEZ
tCLZ
VALID
DATA-OUT
DQ8 ~ DQ15
VI/OH -
t DH
t AA
tD H
tO E Z
t OED
tDH
t CLZ
t OED
tD H
tAA
tD S
VALID
DATA-IN
t DS
tO E Z
t CLZ
VALID
DATA-OUT
VALID
DATA-IN
VALID
DATA-OUT
VALID
DATA-IN
Don′t care
Undefined
Industrial Temperature
K4F661612E, K4F641612E
CMOS DRAM
FAST PAGE MODE LOWER BYTE READ - MODIFY - WRITE CYCLE
tR P
t RASP
RAS
t CSH
V IH V IL -
tC R P
tRPC
V IH -
UCAS
V IL -
tC R P
LCAS
tP R W C
t RCD
t RSH
V IH -
tCAS
tCAS
V IL -
tRAD
tRAH
t ASR
A
V IH V IL -
tR A L
tCAH
tASC
OE
t CAH
t ASC
ROW
ADDR
COL.
ADDR
COL.
ADDR
t RCS
W
tCRP
t CP
t CWL
VIH -
tWP
VIL -
tW P
t CWD
tA W D
t RWD
V IH -
tCWD
tAWD
tCPWD
tOEA
V IL -
t OEA
tOED
tCAC
tCAC
t AA
DQ0 ~ DQ7
VI/OH VI/OL -
t RAC
tOEZ
tD H
t CLZ
VI/OL -
t OED
tD H
tAA
tD S
t DS
tOEZ
t CLZ
VALID
DATA-OUT
DQ8 ~ DQ15
VI/OH -
tR W L
tC W L
t RCS
VALID
DATA-IN
VALID
DATA-OUT
VALID
DATA-IN
OPEN
Don′t care
Undefined
Industrial Temperature
K4F661612E, K4F641612E
CMOS DRAM
FAST PAGE MODE UPPER BYTE READ - MODIFY - WRITE CYCLE
t RP
tRASP
RAS
tCSH
VIH VIL -
tC R P
tPRWC
tR C D
V IH -
UCAS
t RSH
tC P
t CAS
tC R P
t CAS
V IL -
t RPC
tC R P
LCAS
VIH VIL -
t RAD
t RAH
t ASR
A
VIH VIL -
t RAL
tCAH
t ASC
t ASC
ROW
ADDR
COL.
ADDR
COL.
ADDR
tR C S
W
OE
t CAH
t CWL
tRWL
tCWL
t RCS
t WP
VIH VIL -
t WP
tC W D
t AWD
tR W D
V IH -
t CWD
tA W D
t CPWD
tOEA
tOEA
V IL -
DQ0 ~ DQ7
V I/OH -
OPEN
V I/OL -
t OED
t OED
t CAC
tAA
DQ8 ~ DQ15
VI/OH VI/OL -
t RAC
t CAC
t DH
tOEZ
tAA
tDS
tDH
tOEZ
tD S
t CLZ
t CLZ
VALID
DATA-OUT
VALID
DATA-IN
VALID
DATA-OUT
VALID
DATA-IN
Don′t care
Undefined
Industrial Temperature
K4F661612E, K4F641612E
CMOS DRAM
RAS - ONLY REFRESH CYCLE
NOTE : W, OE , DIN = Don′t care
DOUT = OPEN
t RC
V IH -
RAS
tRP
t RAS
V IL -
t RPC
t CRP
V IH -
UCAS
V IL -
t CRP
V IH -
LCAS
V IL -
tASR
V IH -
A
V IL -
t RAH
ROW
ADDR
CAS - BEFORE - RAS REFRESH CYCLE
NOTE : OE , A = Don′t care
tRC
tRP
VIH -
RAS
VIL -
tR P
t RAS
tC R P
tRPC
tC P
t CSR
VIH -
UCAS
tC H R
VIL -
tC P
LCAS
t CSR
VIH -
tC H R
VIL -
DQ0 ~ DQ7
VO H -
t OFF
OPEN
V OL DQ8 ~ DQ15
VOH VOL -
W
OPEN
tWRP
tW R H
VIH VIL Don′t care
Undefined
Industrial Temperature
K4F661612E, K4F641612E
CMOS DRAM
HIDDEN REFRESH CYCLE ( READ )
t RC
RAS
UCAS
LCAS
t RAS
V IH -
tCRP
t RCD
t RSH
tC H R
tC R P
tR C D
t RSH
tC H R
V IH V IL -
V IH V IL -
tASR
V IH V IL -
t RAH
tRAL
tASC
tCAH
ROW
ADDRESS
COLUMN
ADDRESS
tW R H
tRCS
W
t RP
t RAS
V IL -
tRAD
A
t RC
tRP
VIH VIL -
tAA
OE
V IH -
tOEA
V IL -
tOFF
t CAC
tCLZ
DQ0 ~ DQ7
VO H V OL -
DQ8 ~ DQ15
V OH V OL -
tRAC
tOEZ
OPEN
DATA-OUT
OPEN
DATA-IN
DATA-OUT
Don′t care
Undefined
Industrial Temperature
K4F661612E, K4F641612E
CMOS DRAM
HIDDEN REFRESH CYCLE ( WRITE )
NOTE : DOUT = OPEN
t RC
RAS
V IL -
tRCD
t RSH
t CHR
tRCD
tRSH
t CHR
VIH VIL -
tCRP
LCAS
tR P
tRAS
t RAS
V IH -
tC R P
UCAS
tR C
tR P
V IH V IL -
tRAD
t ASR
A
V IH V IL -
t RAH
tASC
ROW
ADDRESS
tR A L
tCAH
COLUMN
ADDRESS
tWRH
W
OE
V IH -
tWRP
t WCS
t WCH
tWP
V IL -
VIH VIL -
DQ0 ~ DQ7
VIH -
t DS
t DH
DATA-IN
VIL DQ8 ~ DQ15
V IH V IL -
tD S
tDH
DATA-IN
Don′t care
Undefined
Industrial Temperature
K4F661612E, K4F641612E
CMOS DRAM
CAS - BEFORE - RAS SELF REFRESH CYCLE
NOTE : OE , A = Don′t care
tRP
RAS
t RASS
tRPS
V IH VIL -
t RPC
tRPC
tC P
UCAS
V IH -
t CSR
tCHS
t CSR
tCHS
VIL -
tC P
LCAS
V IH VIL -
DQ0 ~ DQ7
VO H -
tOFF
OPEN
VOL DQ8 ~ DQ15
VOH -
OPEN
VOL -
W
tWRP
t WRH
VIH VIL -
TEST MODE IN CYCLE
NOTE : OE , A = Don′t care
tR C
tR P
RAS
tRP
tRAS
V IH VIL -
tC R P
t RPC
tCP
UCAS
tCSR
V IH -
tCP
LCAS
W
tC H R
VIL V IH -
tCSR
tC H R
VIL -
tWTS
VIH -
tW T H
V IL -
DQ0 ~ DQ15
VOH VOL -
t OFF
OPEN
Don′t care
Undefined
Industrial Temperature
K4F661612E, K4F641612E
CMOS DRAM
PACKAGE DIMENSION
50 TSOP(II) 400mil
0.400 (10.16)
0.455 (11.56)
0.471 (11.96)
Units : Inches (millimeters)
0.004 (0.10)
0.010 (0.25)
0.841 (21.35)
MAX
0.821 (20.85)
0.829 (21.05)
0.034 (0.875)
0.0315 (0.80)
0.047 (1.20)
MAX
0.002 (0.05)
MIN
0.010 (0.25)
0.018 (0.45)
0.010 (0.25)
TYP
0.018 (0.45)
0.030 (0.75)
0~8
O
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