Product Folder Sample & Buy Support & Community Tools & Software Technical Documents ADS1013-Q1, ADS1014-Q1, ADS1015-Q1 SBAS511B – JULY 2010 – REVISED DECEMBER 2016 2 ADS101x-Q1 Automotive, Low-Power, I C-Compatible, 3.3-kSPS, 12-Bit ADCs With Internal Reference, Oscillator, and Programmable Comparator 1 Features 3 Description • • The ADS1013-Q1, ADS1014-Q1, and ADS1015-Q1 devices (ADS101x-Q1) are precision, low-power, 12bit, I2C-compatible, analog-to-digital converters (ADCs) offered in a VSSOP-10 package. The ADS101x-Q1 devices incorporate a low-drift voltage reference and an oscillator. The ADS1014-Q1 and ADS1015-Q1 also incorporate a programmable gain amplifier (PGA) and a digital comparator. These features, along with a wide operating supply range, make the ADS101x-Q1 well suited for power- and space-constrained, sensor measurement applications. 1 • • • • • • • • • • Qualified for Automotive Applications AEC-Q100 Qualified With the Following Results: – Temperature Grade 1: –40°C to +125°C – HBM ESD Classification 2 – CDM ESD Classification C4B 12-Bit Noise-Free Resolution Wide Supply Range: 2.0 V to 5.5 V Low Current Consumption: 150 μA (Continuous-Conversion Mode) Programmable Data Rate: 128 SPS to 3.3 kSPS Single-Cycle Settling Internal Low-Drift Voltage Reference Internal Oscillator I2C Interface: Four Pin-Selectable Addresses Four Single-Ended or Two Differential Inputs (ADS1015-Q1) Programmable Comparator (ADS1014-Q1 and ADS1015-Q1) The ADS101x-Q1 perform conversions at data rates up to 3300 samples per second (SPS). The PGA offers input ranges from ±256 mV to ±6.144 V, allowing precise largeand small-signal measurements. The ADS1015-Q1 features an input multiplexer (MUX) that allows two differential or four single-ended input measurements. Use the digital comparator in the ADS1014-Q1 and ADS1015-Q1 for under- and overvoltage detection. The ADS101x-Q1 operate in either continuousconversion mode or single-shot mode. The devices are automatically powered down after one conversion in single-shot mode; therefore, power consumption is significantly reduced during idle periods. 2 Applications • • • • • Battery Management Systems (BMS) Infotainment Systems On-board Chargers (OBC) General Purpose Voltage and Current Monitoring Powertrain Sensors Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) ADS101x-Q1 VSSOP (10) 3.00 mm × 3.00 mm (1) For all available packages, see the package option addendum at the end of the data sheet. Simplified Block Diagrams VDD VDD VDD Comparator Voltage Reference AIN0 AIN1 12-Bit û¯ ADC Oscillator ADDR I2C Interface SDA ADS1013-Q1 GND AIN0 PGA SCL AIN1 12-Bit û¯ ADC Oscillator GND Comparator ALERT/ RDY Voltage Reference ADDR I2C Interface SCL SDA ADS1014-Q1 ALERT/ RDY Voltage Reference AIN0 AIN1 AIN2 AIN3 MUX PGA 12-Bit û¯ ADC Oscillator ADDR I2C Interface SCL SDA ADS1015-Q1 GND Copyright © 2016, Texas Instruments Incorporated 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. ADS1013-Q1, ADS1014-Q1, ADS1015-Q1 SBAS511B – JULY 2010 – REVISED DECEMBER 2016 www.ti.com Table of Contents 1 2 3 4 5 6 7 8 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Device Comparison Table..................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 4 4 5 7.1 7.2 7.3 7.4 7.5 7.6 7.7 5 5 5 5 6 7 8 Absolute Maximum Ratings ...................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics.......................................... Timing Requirements: I2C......................................... Typical Characteristics .............................................. Detailed Description .............................................. 9 8.1 8.2 8.3 8.4 8.5 Overview ................................................................... 9 Functional Block Diagrams ....................................... 9 Feature Description................................................. 10 Device Functional Modes........................................ 15 Programming........................................................... 16 8.6 Register Map........................................................... 21 9 Application and Implementation ........................ 25 9.1 Application Information............................................ 25 9.2 Typical Application ................................................. 30 10 Power Supply Recommendations ..................... 34 10.1 Power-Supply Sequencing.................................... 34 10.2 Power-Supply Decoupling..................................... 34 11 Layout................................................................... 35 11.1 Layout Guidelines ................................................. 35 11.2 Layout Example .................................................... 36 12 Device and Documentation Support ................. 37 12.1 12.2 12.3 12.4 12.5 12.6 12.7 Documentation Support ........................................ Related Links ........................................................ Receiving Notification of Documentation Updates Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 37 37 37 37 37 37 37 13 Mechanical, Packaging, and Orderable Information ........................................................... 38 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision A (March 2016) to Revision B Page • Added ADS1014-Q1 and ADS1013-Q1 to data sheet ........................................................................................................... 1 • Changed Title, and Description, Features, and Applications sections for clarity ................................................................... 1 • Deleted temperature range text from Description section and moved to Features section ................................................... 1 • Changed Device Comparison Table....................................................................................................................................... 4 • Changed Pin Functions table for clarity.................................................................................................................................. 4 • Changed Power-supply voltage max value from 5.5 V to 7 V in Absolute Maximum Ratings table...................................... 5 • Changed Analog input voltage from –0.3 V to GND – 0.3 V in Absolute Maximum Ratings table ........................................ 5 • Changed Digital input voltage min value from –0.5 V to GND – 0.3 V in Absolute Maximum Ratings table......................... 5 • Changed Digital input voltage max value from 5.5 V to VDD + 0.3 V in Absolute Maximum Ratings table .......................... 5 • Deleted Analog input current rows in Absolute Maximum Ratings table................................................................................ 5 • Added Input current row in Absolute Maximum Ratings table ............................................................................................... 5 • Added Operating temperature range of –40°C to +125°C back into Absolute Maximum Ratings table................................ 5 • Added minimum specification of –40°C for TJ in Absolute Maximum Ratings table ............................................................. 5 • Deleted Machine model row from ESD Ratings table ............................................................................................................ 5 • Deleted Supply current and power dissipation rows and moved to Electrical Characteristics table ...................................... 5 • Changed Full-scale input voltage range (FSR) from typical value of ±4.096/PGA V to min value of ±0.256 V and max value of ±6.144 V for clarity in Recommended Operating Conditions table................................................................... 5 • Added Digital input voltage (VDIG) to Recommended Operating Conditions table ................................................................ 5 • Added new note 1 for Recommended Operating Conditions table ........................................................................................ 5 • Changed text in note 2 (previously note 1 in revision A) from "In no event should more than VDD + 0.3 V be applied to this device" to "No more than VDD + 0.3 V or 5.5 V (whichever is smaller) must be applied to this device. See Table 3 for more information." ................................................................................................................................................ 5 • Added values for ADS111xA-Q1 devices in Thermal Information table................................................................................. 5 • Added values for ADS111xB-Q1 devices in Thermal Information table................................................................................. 5 2 Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: ADS1013-Q1 ADS1014-Q1 ADS1015-Q1 ADS1013-Q1, ADS1014-Q1, ADS1015-Q1 www.ti.com SBAS511B – JULY 2010 – REVISED DECEMBER 2016 Revision History (continued) • Changed existing thermal information values for ADS1015-Q1 (RθJA from 175.2 to 182.7, RθJC(top) from 64 to 67.2, RθJB from 96.4 to 103.8, ψJT from 8.8 to 10.2, ψJB from 94.8 to 102.1) .................................................................................. 5 • Changed Electrical Characteristics table conditions line for clarity ........................................................................................ 6 • Changed all instances of "FS" to "FSR" ................................................................................................................................. 6 • Deleted FSR from Electrical Characteristics and moved to Recommended Operating Conditions table .............................. 6 • Added values from Table 1 to Differential input impedance parameter in Electrical Characteristics..................................... 6 • Deleted Output noise parameter from Electrical Characteristics ........................................................................................... 6 • Changed Offset error parameter min value from empty to –3, and max value from ±3 to 3 for clarity in Electrical Characteristics table ............................................................................................................................................................... 6 • Changed VIH parameter max value from 5.5 V to VDD in Electrical Characteristics table .................................................... 6 • Changed VIL parameter min value from GND – 0.5 V to GND in Electrical Characteristics table ......................................... 6 • Changed Input leakage current parameters from two rows to one row, changed test conditions from VIH = 5.5V and VIL = GND to GND < VDIG < VDD, and changed min value from 10 µA to –10 µA in Electrical Characteristics table........... 6 • Added Supply current parameters to Electrical Characteristics table .................................................................................... 6 • Added Power dissipation parameters to Electrical Characteristics table ............................................................................... 6 • Changed text in note 1 of Electrical Characteristics table from "In no event should more than VDD + 0.3 V be applied to this device" to "No more than VDD + 0.3 V or 5.5 V (whichever is smaller) must be applied to this device. See Table 1 for more information."......................................................................................................................................... 6 • Added condition statement in Timing Requirements: I2C....................................................................................................... 7 • Added note 1 to Timing Requirements table .......................................................................................................................... 7 • Deleted Figure 7, Noise Plot................................................................................................................................................... 8 • Changed functional block diagram; deleted "Gain = 2/3, 1, 2, 4, 8, or 16" from figure ......................................................... 9 • Added Functional Block Diagrams for ADS1014-Q1 and ADS1013-Q1 ................................................................................ 9 • Changed Analog Inputs section to provide LSB size information instead of PGA setting ................................................... 11 • Changed Full-Scale Input section title to Full-Scale Range (FSR) and LSB Size, and updated section for clarity ............. 12 • Added Voltage Reference and Oscillator sections ............................................................................................................... 12 • Changed Comparator section title to Digital Comparator, and updated section for clarity. ................................................. 12 • Changed Conversion Ready Pin section for clarity .............................................................................................................. 13 • Changed Register Map section for clarity ............................................................................................................................ 21 • Changed Application Information section for clarity ............................................................................................................. 25 • Added Input Protection section............................................................................................................................................. 26 • Added Unused Inputs and Outputs section.......................................................................................................................... 26 • Changed Aliasing section title to Analog Input Filtering and updated section for clarity...................................................... 27 • Deleted previous Typical Application section and added new, more detailed Typical Application section.......................... 30 • Changed Power Supply Recommendations section for clarity............................................................................................. 34 • Changed Layout section for clarity ....................................................................................................................................... 35 Changes from Original (July 2010) to Revision A Page • Added ADS1015AQDGSRQ1 package option to the data sheet........................................................................................... 1 • Added ESD Ratings table, and Pin Configuration and Functions, Feature Description, Device Functional Modes, Application and Implementation, Power Supply Recommendations, Layout Device and Documentation Support, and Mechanical, Packaging, and Orderable Information sections ................................................................................................ 1 • Deleted Ordering Information table ....................................................................................................................................... 1 • Changed Figure 3; switched VDD = 5 V and VDD = 2 V series labels in Power-Down Current vs Temperature graph....... 8 • Deleted Figure 22, Connecting Multiple Device Types ........................................................................................................ 28 Copyright © 2010–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADS1013-Q1 ADS1014-Q1 ADS1015-Q1 3 ADS1013-Q1, ADS1014-Q1, ADS1015-Q1 SBAS511B – JULY 2010 – REVISED DECEMBER 2016 www.ti.com 5 Device Comparison Table DEVICE RESOLUTION (Bits) MAXIMUM SAMPLE RATE (SPS) INPUT CHANNELS Differential (Single-Ended) PGA INTERFACE SPECIAL FEATURES ADS1015-Q1 12 3300 2 (4) Yes I2C Comparator ADS1014-Q1 12 3300 1 (1) Yes I2C Comparator ADS1013-Q1 12 3300 1 (1) No I2C ADS1115-Q1 16 860 2 (4) Yes IC Comparator ADS1114-Q1 16 860 1 (1) Yes I2C Comparator ADS1113-Q1 16 860 1 (1) No I2C None ADS1018-Q1 12 3300 2 (4) Yes SPI Temperature sensor ADS1118-Q1 16 860 2 (4) Yes SPI Temperature sensor 2 None 6 Pin Configuration and Functions DGS Package 10-Pin VSSOP Top View ADDR 1 10 SCL ALERT/RDY 2 9 SDA GND 3 8 VDD AIN0 4 7 AIN3 AIN1 5 6 AIN2 Not to scale Pin Functions PIN (1) NAME ADS1013-Q1 ADS1014-Q1 ADS1015-Q1 TYPE ADDR 1 1 1 Digital input I2C slave address select AIN0 4 4 4 Analog input Analog input 0 AIN1 5 5 5 Analog input Analog input 1 AIN2 — — 6 Analog input Analog input 2 (ADS1015-Q1 only) AIN3 — — 7 Analog input Analog input 3 (ADS1015-Q1 only) ALERT/RDY — 2 2 Digital output Comparator output or conversion ready (ADS1014-Q1 and ADS1015-Q1 only) GND 3 3 3 Analog NC 2, 6, 7 6, 7 — — SCL 10 10 10 Digital input SDA 9 9 9 Digital I/O VDD 8 8 8 Analog (1) 4 DESCRIPTION Ground Not connected Serial clock input. Clocks data on SDA Serial data. Transmits and receives data Power supply. Connect a 0.1-μF, power-supply decoupling capacitor to GND. See the Unused Inputs and Outputs section for unused pin connections. Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: ADS1013-Q1 ADS1014-Q1 ADS1015-Q1 ADS1013-Q1, ADS1014-Q1, ADS1015-Q1 www.ti.com SBAS511B – JULY 2010 – REVISED DECEMBER 2016 7 Specifications 7.1 Absolute Maximum Ratings (1) MIN MAX UNIT –0.3 7 V AIN0, AIN1, AIN2, AIN3 GND – 0.3 VDD + 0.3 V SDA, SCL, ADDR, ALERT/RDY GND – 0.3 VDD + 0.3 V Any pin except power supply pins –10 10 mA Operating ambient, TA –40 125 Junction, TJ –40 150 Storage, Tstg –60 150 Power-supply voltage VDD to GND Analog input voltage Digital input voltage Input current, continuous Temperature (1) °C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 7.2 ESD Ratings VALUE Human-body mode.45l (HBM), per AEC Q100-002 (1) V(ESD) (1) Electrostatic discharge Charged-device model (CDM), per AEC Q100-01 UNIT ±2000 Corner pins (1, 5, 6, and 10) ±750 All other pins ±500 V AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification. 7.3 Recommended Operating Conditions MIN NOM MAX UNIT POWER SUPPLY Power supply (VDD to GND) 2 5.5 V ±0.256 ±6.144 V GND VDD V GND VDD V –40 125 °C ANALOG INPUTS (1) FSR Full-scale input voltage range (2) (VIN = V(AINP) – V(AINN)) V(AINx) Absolute input voltage DIGITAL INPUTS VDIG Digital input voltage TEMPERATURE TA (1) (2) Operating ambient temperature AINP and AINN denote the selected positive and negative inputs. AINx denotes one of the four available analog inputs. This parameter expresses the full-scale range of the ADC scaling. No more than VDD + 0.3 V or 5.5 V (whichever is smaller) must be applied to this device. See Table 1 more information. 7.4 Thermal Information ADS101xB-Q1 ADS1015A-Q1 THERMAL METRIC (1) ADS1015-Q1 DGS (VSSOP) DGS (VSSOP) DGS (VSSOP) UNIT 10 PINS 10 PINS 10 PINS RθJA Junction-to-ambient thermal resistance 170.9 175.2 182.7 °C/W RθJC(top) Junction-to-case (top) thermal resistance 61.0 64.0 67.2 °C/W RθJB Junction-to-board thermal resistance 91.2 96.4 103.8 °C/W ψJT Junction-to-top characterization parameter 8.5 8.8 10.2 °C/W ψJB Junction-to-board characterization parameter 89.8 94.8 102.1 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A N/A °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Copyright © 2010–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADS1013-Q1 ADS1014-Q1 ADS1015-Q1 5 ADS1013-Q1, ADS1014-Q1, ADS1015-Q1 SBAS511B – JULY 2010 – REVISED DECEMBER 2016 7.5 www.ti.com Electrical Characteristics At VDD = 3.3 V, data rate = 128 SPS, and full-scale input-voltage range (FSR) = ±2.048 V (unless otherwise noted). Maximum and minimum specifications apply from TA = –40°C to +125°C. Typical specifications are at TA = 25°C. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ANALOG INPUT FSR = ±6.144 V (1) Common-mode input impedance 10 FSR = ±4.096 V (1), FSR = ±2.048 V 6 FSR = ±1.024 V 3 FSR = ±0.512 V, FSR = ±0.256 V FSR = ±6.144 V Differential input impedance MΩ 100 (1) 22 FSR = ±4.096 V (1) 15 FSR = ±2.048 V 4.9 FSR = ±1.024 V 2.4 FSR = ±0.512 V, ±0.256 V 710 MΩ kΩ SYSTEM PERFORMANCE Resolution (no missing codes) DR 12 Data rate INL Bits 128, 250, 490, 920, 1600, 2400, 3300 Data rate variation All data rates Integral nonlinearity DR = 128 SPS, FSR = ±2.048 V (2) –10% FSR = ±2.048 V, differential inputs Offset error 10% 0.5 -0.5 0 FSR = ±2.048 V, single-ended inputs ±0.25 Offset drift FSR = ±2.048 V 0.005 Offset channel match Match between any two inputs Gain error (3) FSR = ±2.048 V, TA = 25°C Gain drift (3) SPS 0.5 FSR = ±0.256 V 7 FSR = ±2.048 V 5 FSR = ±6.144 V (1) 5 LSB LSB/°C 0.25 0.05% LSB LSB 0.25% 40 ppm/°C Gain match (3) Match between any two gains 0.02% 0.1% Gain channel match Match between any two inputs 0.05% 0.1% DIGITAL INPUT/OUTPUT VIH High-level input voltage 0.7 VDD VDD V VIL Low-level input voltage GND 0.3 VDD V VOL Low-level output voltage IOL = 3 mA Input leakage current GND < VDIG < VDD GND 0.15 –10 0.4 V 10 µA POWER-SUPPLY Power-down IVDD Supply current Operating PD (1) (2) (3) 6 Power dissipation TA = 25°C 0.5 2 TA = 25°C 150 200 5 µA 300 VDD = 5.0 V 0.9 VDD = 3.3 V 0.5 VDD = 2.0 V 0.3 mW This parameter expresses the full-scale range of the ADC scaling. No more than VDD + 0.3 V or 5.5 V (whichever is smaller) must be applied to this device. See Table 1 more information. Best-fit INL; covers 99% of full-scale. Includes all errors from onboard PGA and voltage reference. Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: ADS1013-Q1 ADS1014-Q1 ADS1015-Q1 ADS1013-Q1, ADS1014-Q1, ADS1015-Q1 www.ti.com SBAS511B – JULY 2010 – REVISED DECEMBER 2016 7.6 Timing Requirements: I2C over operating ambient temperature range and VDD = 2.0 V to 5.5 V (unless otherwise noted) FAST MODE HIGH-SPEED MODE MIN MAX MIN MAX UNIT fSCL SCL Clock Frequency 0.01 0.4 0.01 3.4 MHz tBUF Bus free time between START and STOP condition 600 160 ns tHDSTA Hold time after repeated START condition. After this period, the first clock is generated. 600 160 ns tSUSTA Setup time for a repeated START condition 600 160 ns tSUSTO Setup time for STOP condition 600 160 ns tHDDAT Data hold time 0 0 ns tSUDAT Data setup time 100 10 ns tLOW Low period of the SCL clock pin 1300 160 ns tHIGH High period for the SCL clock pin 600 tF Rise time for both SDA and SCL signals (1) 300 160 ns tR Fall time for both SDA and SCL signals (1) 300 160 ns (1) 60 ns For high-speed mode maximum values, the capacitive load on the bus line must not exceed 400 pF. t LOW tR tF t HDSTA SCL t HIGH t HDSTA t HDDAT SDA t SUSTO t SUSTA t SUDAT t BUF P S S P Figure 1. I2C Interface Timing Copyright © 2010–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADS1013-Q1 ADS1014-Q1 ADS1015-Q1 7 ADS1013-Q1, ADS1014-Q1, ADS1015-Q1 SBAS511B – JULY 2010 – REVISED DECEMBER 2016 www.ti.com 7.7 Typical Characteristics at TA = 25°C, VDD = 3.3 V, FSR = ±2.048 V, DR = 128 SPS (unless otherwise noted) 5.0 300 4.5 Power-Down Current (µA) Operating Current (µA) 250 VDD = 5 V 200 150 VDD = 3.3 V VDD = 2 V 100 50 4.0 3.5 VDD = 5 V 3.0 2.5 2.0 VDD = 3.3 V 1.5 1.0 0.5 0 -40 -20 0 20 40 60 80 100 120 -40 140 -20 0 20 40 60 80 100 120 140 Temperature (°C) Temperature (°C) Figure 2. Operating Current vs Temperature Figure 3. Power-Down Current vs Temperature 150 60 FSR = ±4.096 V FSR = ±2.048 V 100 FSR = ±1.024 V FSR = ±0.512 V 50 VDD = 5 V 50 VDD = 2 V Offset Voltage (µV) Offset Error (µV) VDD = 2 V 0 0 -50 -100 -150 -200 VDD = 5 V 40 30 VDD = 4 V 20 VDD = 3 V 10 0 VDD = 2 V -10 -250 -20 -300 -40 -20 0 20 40 60 80 100 120 140 -40 -20 0 Temperature (°C) 20 40 60 80 100 120 140 Temperature (°C) Figure 4. Single-Ended Offset Error vs Temperature Figure 5. Differential Offset vs Temperature 0.05 FSR = ±0.256 V 0.04 Gain Error (%) 0.03 FSR = ±0.512 V 0.02 0.01 FSR = ±1.024 V, ±2.048 V, ±4.096 V, and ±6.144 V 0 -0.01 -0.02 -0.03 -0.04 -40 -20 0 20 40 60 80 100 120 140 Temperature (°C) Figure 6. Gain Error vs Temperature 8 Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: ADS1013-Q1 ADS1014-Q1 ADS1015-Q1 ADS1013-Q1, ADS1014-Q1, ADS1015-Q1 www.ti.com SBAS511B – JULY 2010 – REVISED DECEMBER 2016 8 Detailed Description 8.1 Overview The ADS101x-Q1 are very small, low-power, noise-free, 12-bit, delta-sigma (ΔΣ) analog-to-digital converters (ADCs). The ADS101x-Q1 consist of a ΔΣ ADC core with an internal voltage reference, a clock oscillator and an I2C interface. The ADS1014-Q1 and ADS1015-Q1 also integrate a programmable gain amplifier (PGA) and a programmable digital comparator. Figure 7, Figure 8, and Figure 9 show the functional block diagrams of ADS1015-Q1, ADS1014-Q1, and ADS1013-Q1, respectively. The ADS1015AQDGSRQ1, ADS1015BQDGSRQ1, ADS1014BQDGSRQ1, and ADS1013BQDGSRQ1 package options are AEC-Q100 qualified; whereas, the ADS1015QDGSRQ1 package option is only automotive qualified. The ADS101x-Q1 ADC core measures a differential signal, VIN, that is the difference of V(AINP) and V(AINN). The converter core consists of a differential, switched-capacitor ΔΣ modulator followed by a digital filter. This architecture results in a very strong attenuation of any common-mode signals. Input signals are compared to the internal voltage reference. The digital filter receives a high-speed bitstream from the modulator and outputs a code proportional to the input voltage. The ADS101x-Q1 have two available conversion modes: single-shot and continuous-conversion. In single-shot mode, the ADC performs one conversion of the input signal upon request, stores the conversion value to an internal conversion register, and then enters a power-down state. This mode is intended to provide significant power savings in systems that only require periodic conversions or when there are long idle periods between conversions. In continuous-conversion mode, the ADC automatically begins a conversion of the input signal as soon as the previous conversion is completed. The rate of continuous conversion is equal to the programmed data rate. Data can be read at any time and always reflect the most recent completed conversion. 8.2 Functional Block Diagrams VDD Comparator ADS1015-Q1 Voltage Reference MUX ALERT/RDY AIN0 ADDR AIN1 PGA 12-Bit û¯ ADC I2C Interface SCL SDA AIN2 Oscillator AIN3 GND Copyright © 2016, Texas Instruments Incorporated Figure 7. ADS1015-Q1 Block Diagram VDD VDD ADS1014-Q1 ADS1013-Q1 Comparator Voltage Reference ADDR AIN0 PGA AIN1 12-Bit û¯ ADC Voltage Reference ALERT/RDY I 2C Interface ADDR AIN0 SCL AIN1 12-Bit û¯ ADC SDA I 2C Interface SCL SDA Oscillator Oscillator GND Copyright © 2016, Texas Instruments Incorporated Figure 8. ADS1014-Q1 Block Diagram Copyright © 2010–2016, Texas Instruments Incorporated GND Copyright © 2016, Texas Instruments Incorporated Figure 9. ADS1013-Q1 Block Diagram Submit Documentation Feedback Product Folder Links: ADS1013-Q1 ADS1014-Q1 ADS1015-Q1 9 ADS1013-Q1, ADS1014-Q1, ADS1015-Q1 SBAS511B – JULY 2010 – REVISED DECEMBER 2016 www.ti.com 8.3 Feature Description 8.3.1 Multiplexer The ADS1015-Q1 contains an input multiplexer (MUX), as shown in Figure 10. Either four single-ended or two differential signals can be measured. Additionally, AIN0 and AIN1 may be measured differentially to AIN3. The multiplexer is configured by bits MUX[2:0] in the Config register. When single-ended signals are measured, the negative input of the ADC is internally connected to GND by a switch within the multiplexer. ADS1015-Q1 VDD AIN0 VDD GND AINP AINN AIN1 VDD GND AIN2 VDD GND AIN3 GND GND Copyright © 2016, Texas Instruments Incorporated Figure 10. Input Multiplexer The ADS1013-Q1 and ADS1014-Q1 do not have an input multiplexer and can measure either one differential signal or one single-ended signal. For single-ended measurements, connect the AIN1 pin to GND externally. In subsequent sections of this data sheet, AINP refers to AIN0 and AINN refers to AIN1 for the ADS1013-Q1 and ADS1014-Q1. When measuring single-ended inputs, the device does not output negative codes. These negative codes indicate negative differential signals; that is, (V(AINP) – V(AINN)) < 0. Electrostatic discharge (ESD) diodes to VDD and GND protect the ADS101x-Q1 inputs. To prevent the ESD diodes from turning on, keep the absolute voltage on any input within the range given in Equation 1. GND – 0.3 V < V(AINX) < VDD + 0.3 V (1) If the voltages on the input pins can possibly violate these conditions, use external Schottky diodes and series resistors to limit the input current to safe values (see the Absolute Maximum Ratings table). 10 Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: ADS1013-Q1 ADS1014-Q1 ADS1015-Q1 ADS1013-Q1, ADS1014-Q1, ADS1015-Q1 www.ti.com SBAS511B – JULY 2010 – REVISED DECEMBER 2016 Feature Description (continued) 8.3.2 Analog Inputs The ADS101x-Q1 use a switched-capacitor input stage where capacitors are continuously charged and then discharged to measure the voltage between AINP and AINN. The frequency at which the input signal is sampled is called the sampling frequency or the modulator frequency (fMOD). ADS101x-Q1 has a 1-MHz internal oscillator that is further divided by a factor of 4 in order to generate fMOD at 250 kHz. The capacitors used in this input stage are small, and to external circuitry, the average loading appears resistive. This structure is shown in Figure 11. The resistance is set by the capacitor values and the rate at which they are switched. Figure 12 shows the setting of the switches illustrated in Figure 11. During the sampling phase, switches S1 are closed. This event charges CA1 to V(AINP), CA2 to V(AINN), and CB to (V(AINP) – V(AINN)). During the discharge phase, S1 is first opened and then S2 is closed. Both CA1 and CA2 then discharge to approximately 0.7 V and CB discharges to 0 V. This charging draws a very small transient current from the source driving the ADS101x-Q1 analog inputs. The average value of this current can be used to calculate the effective impedance (Zeff), where Zeff = VIN / IAVERAGE. 0.7 V CA1 AINP S1 S2 CB Equivalent Circuit 0.7 V ZCM AINP ZDIFF S2 S1 AINN 0.7 V AINN CA2 ZCM fMOD = 250 kHz 0.7 V Figure 11. Simplified Analog Input Circuit tSAMPLE ON S1 OFF ON S2 OFF Figure 12. S1 and S2 Switch Timing The common-mode input impedance is measured by applying a common-mode signal to the shorted AINP and AINN inputs and measuring the average current consumed by each pin. The common-mode input impedance changes depending on the full-scale range, but is approximately 6 MΩ for the default full-scale range. In Figure 11, the common-mode input impedance is ZCM. The differential input impedance is measured by applying a differential signal to AINP and AINN inputs where one input is held at 0.7 V. The current that flows through the pin connected to 0.7 V is the differential current and scales with the full-scale range. In Figure 11, the differential input impedance is ZDIFF. Make sure to consider the typical value of the input impedance. Unless the input source has a low impedance, the ADS101x-Q1 input impedance may affect the measurement accuracy. For sources with high-output impedance, buffering may be necessary. Active buffers introduce noise, and also introduce offset and gain errors. Consider all of these factors in high-accuracy applications. The clock oscillator frequency drifts slightly with temperature; therefore, the input impedances also drift. For most applications, this input impedance drift is negligible, and can be ignored. Copyright © 2010–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADS1013-Q1 ADS1014-Q1 ADS1015-Q1 11 ADS1013-Q1, ADS1014-Q1, ADS1015-Q1 SBAS511B – JULY 2010 – REVISED DECEMBER 2016 www.ti.com Feature Description (continued) 8.3.3 Full-Scale Range (FSR) and LSB Size A programmable gain amplifier (PGA) is implemented before the ΔΣ core of the ADS1014-Q1 and ADS1015-Q1. The full-scale range is configured by bits PGA[2:0] in the Config register and can be set to ±6.144 V, ±4.096 V, ±2.048 V, ±1.024 V, ±0.512 V, ±0.256 V. Table 1 shows the FSR together with the corresponding LSB size. LSB size is calculated from full-scale voltage by the formula shown in Equation 2. However, analog input voltages may never exceed the analog input voltage limits given in the Electrical Characteristics. If a supply voltage of VDD greater than 4 V is used, the ±6.144 V full-scale range allows input voltages to extend up to the supply. Although in this case (or whenever the supply voltage is less than the full-scale range; for example, VDD = 3.3 V and full-scale range = ±4.096 V), a full-scale ADC output code cannot be obtained. This inability means that some dynamic range is lost. LSB = FSR / 212 (2) Table 1. Full-Scale Range and Corresponding LSB Size (1) FSR LSB SIZE ±6.144 V (1) 3 mV ±4.096 V (1) 2 mV ±2.048 V 1 mV ±1.024 V 0.5 mV ±0.512 V 0.25 mV ±0.256 V 0.125 mV This parameter expresses the full-scale range of the ADC scaling. Do not apply more than VDD + 0.3 V to this device. 8.3.4 Voltage Reference The ADS101x-Q1 have an integrated voltage reference. An external reference cannot be used with these devices. Errors associated with the initial voltage reference accuracy and the reference drift with temperature are included in the gain error and gain drift specifications in the Electrical Characteristics table. 8.3.5 Oscillator The ADS101x-Q1 have an integrated oscillator running at 1 MHz. No external clock can be applied to operate these devices. The internal oscillator drifts over temperature and time. The output data rate scales proportionally with the oscillator frequency. 8.3.6 Digital Comparator (ADS1014-Q1 and ADS1015-Q1 Only) The ADS1015-Q1 and ADS1014-Q1 feature a programmable digital comparator that can issue an alert on the ALERT/RDY pin. The COMP_MODE bit in the Config register configures the comparator as either a traditional comparator or a window comparator. In traditional comparator mode, the ALERT/RDY pin asserts (active low by default) when conversion data exceeds the limit set in the high-threshold register (Hi_thresh). The comparator then deasserts only when the conversion data falls below the limit set in the low-threshold register (Lo_thresh). In window comparator mode, the ALERT/RDY pin asserts when the conversion data exceed the Hi_thresh register or fall below the Lo_thresh register value. In either window or traditional comparator mode, the comparator can be configured to latch after being asserted by the COMP_LAT bit in the Config register. This setting causes the assertion to remain even if the input signal is not beyond the bounds of the threshold registers. This latched assertion can only be cleared by issuing an SMBus alert response or by reading the Conversion register. The ALERT/RDY pin can be configured as active high or active low by the COMP_POL bit in the Config register. Operational diagrams for both the comparator modes are shown in Figure 13. The comparator can also be configured to activate the ALERT/RDY pin only after a set number of successive readings exceed the threshold values set in the threshold registers (Hi_thresh and Lo_thresh). The COMP_QUE[1:0] bits in the Config register configures the comparator to wait for one, two, or four readings beyond the threshold before activating the ALERT/RDY pin. The COMP_QUE[1:0] bits can also disable the comparator function, and put the ALERT/RDY pin into a high state. 12 Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: ADS1013-Q1 ADS1014-Q1 ADS1015-Q1 ADS1013-Q1, ADS1014-Q1, ADS1015-Q1 www.ti.com SBAS511B – JULY 2010 – REVISED DECEMBER 2016 8.3.7 Conversion Ready Pin (ADS1014-Q1 and ADS1015-Q1 Only) The ALERT/RDY pin can also be configured as a conversion ready pin. Set the most-significant bit of the Hi_thresh register to 1 and the most-significant bit of Lo_thresh register to 0 to enable the pin as a conversion ready pin. The COMP_POL bit continues to function as expected. Set the COMP_QUE[1:0] bits to any 2-bit value other than 11 to keep the ALERT/RDY pin enabled, and allow the conversion ready signal to appear at the ALERT/RDY pin output. The COMP_MODE and COMP_LAT bits no longer control any function. When configured as a conversion ready pin, ALERT/RDY continues to require a pullup resistor. The ADS101x-Q1 provide an approximately 8-µs conversion ready pulse on the ALERT/RDY pin at the end of each conversion in continuous-conversion mode, as shown in Figure 14. In single-shot mode, the ALERT/RDY pin asserts low at the end of a conversion if the COMP_POL bit is set to 0. TH_H TH_H Input Signal Input Signal TH_L TH_L Time Latching Comparator Output Successful SMBus Alert Response Time Successful SMBus Alert Response Latching Comparator Output Successful SMBus Alert Response Time Time Non-Latching Comparator Output Non-Latching Comparator Output Time Time TRADITIONAL COMPARATOR MODE WINDOW COMPARATOR MODE Figure 13. ALERT Pin Timing Diagram ADS1014/5-Q1 Status Converting Converting Conversion Ready Converting Conversion Ready Converting Conversion Ready 8 µs ALERT/RDY (active high) Figure 14. Conversion Ready Pulse in Continuous-Conversion Mode Copyright © 2010–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADS1013-Q1 ADS1014-Q1 ADS1015-Q1 13 ADS1013-Q1, ADS1014-Q1, ADS1015-Q1 SBAS511B – JULY 2010 – REVISED DECEMBER 2016 www.ti.com 8.3.8 SMbus Alert Response In latching comparator mode (COMP_LAT = 1), the ALERT/RDY pin asserts when the comparator detects a conversion that exceeds the upper or lower threshold value. This assertion is latched and can be cleared only by reading conversion data, or by issuing a successful SMBus alert response and reading the asserting device I2C address. If conversion data exceed the upper or lower threshold values after being cleared, the pin reasserts. This assertion does not affect conversions that are already in progress. The ALERT/RDY pin is an open-drain output. This architecture allows several devices to share the same interface bus. When disabled, the pin holds a high state so that the pin does not interfere with other devices on the same bus line. When the master senses that the ALERT/RDY pin has latched, the master issues an SMBus alert command (00011001) to the I2C bus. Any ADS1014-Q1 and ADS1015-Q1 data converters on the I2C bus with the ALERT/RDY pins asserted respond to the command with the slave address. If more than one ADS101x-Q1 on the I2C bus assert the latched ALERT/RDY pin, arbitration during the address response portion of the SMBus alert determines which device clears assertion. The device with the lowest I2C address always wins arbitration. If a device loses arbitration, the device does not clear the comparator output pin assertion. The master then repeats the SMBus alert response until all devices have the respective assertions cleared. In window comparator mode, the SMBus alert status bit indicates a 1 if signals exceed the high threshold, and a 0 if signals exceed the low threshold. 14 Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: ADS1013-Q1 ADS1014-Q1 ADS1015-Q1 ADS1013-Q1, ADS1014-Q1, ADS1015-Q1 www.ti.com SBAS511B – JULY 2010 – REVISED DECEMBER 2016 8.4 Device Functional Modes 8.4.1 Reset and Power-Up The ADS101x-Q1 reset on power-up and set all the bits in the Config register to the respective default settings. The ADS101x-Q1 enter a power-down state after completion of the reset process. The device interface and digital blocks are active, but no data conversions are performed. The initial power-down state of the ADS101x-Q1 relieves systems with tight power-supply requirements from encountering a surge during power-up. The ADS101x-Q1 respond to the I2C general call commands. When the ADS101x-Q1 receive a general call reset command, an internal reset is performed as if the device had been powered-up. 8.4.2 Operating Modes The ADS101x-Q1 operate in one of two modes: continuous-conversion or single-shot. The MODE bit in the Config register selects the respective operating mode. 8.4.2.1 Single-Shot Mode When the MODE bit in the Config register is set to 1, the ADS101x-Q1 enter a power-down state, and operate in single-shot mode. This power-down state is the default state for the ADS101x-Q1 when power is first applied. Although powered down, the devices still respond to commands. The ADS101x-Q1 remain in this power-down state until a 1 is written to the operational status (OS) bit in the Config register. When the OS bit is asserted, the device powers up in approximately 25 μs, resets the OS bit to 0, and starts a single conversion. When conversion data are ready for retrieval, the device powers down again. Writing a 1 to the OS bit while a conversion is ongoing has no effect. To switch to continuous-conversion mode, write a 0 to the MODE bit in the Config register. 8.4.2.2 Continuous-Conversion Mode In continuous-conversion mode (MODE bit set to 0), the ADS101x-Q1 perform conversions continuously. When a conversion completes, the ADS101x-Q1 place the result in the Conversion register and immediately begin another conversion. To switch to single-shot mode, write a 1 to the MODE bit in the Config register, or reset the device. 8.4.3 Duty Cycling For Low Power The noise performance of a ΔΣ ADC generally improves when lowering the output data rate because more samples of the internal modulator are averaged to yield one conversion result. In applications where power consumption is critical, the improved noise performance at low data rates may not be required. For these applications, the ADS101x-Q1 support duty cycling that yield significant power savings by periodically requesting high data rate readings at an effectively lower data rate. For example, an ADS101x-Q1 in power-down state with a data rate set to 3300 SPS can be operated by a microcontroller that instructs a single-shot conversion every 7.8 ms (128 SPS). A conversion at 3300 SPS only requires approximately 0.3 ms, so the ADS101x-Q1 enter power-down state for the remaining 7.5 ms. In this configuration, the ADS101x-Q1 consume approximately 1/25th the power that is otherwise consumed in continuous-conversion mode. The duty cycling rate is completely arbitrary and is defined by the master controller. The ADS101x-Q1 offer lower data rates that do not implement duty cycling and also offer improved noise performance if required. Copyright © 2010–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADS1013-Q1 ADS1014-Q1 ADS1015-Q1 15 ADS1013-Q1, ADS1014-Q1, ADS1015-Q1 SBAS511B – JULY 2010 – REVISED DECEMBER 2016 www.ti.com 8.5 Programming 8.5.1 I2C Interface The ADS101x-Q1 communicate through an I2C interface. I2C is a two-wire open-drain interface that supports multiple devices and masters on a single bus. Devices on the I2C bus only drive the bus lines low by connecting them to ground; the devices never drive the bus lines high. Instead, the bus wires are pulled high by pullup resistors, so the bus wires are always high when no device is driving them low. As a result of this configuration, two devices cannot conflict. If two devices drive the bus simultaneously, there is no driver contention. Communication on the I2C bus always takes place between two devices, one acting as the master and the other as the slave. Both the master and slave can read and write, but the slave can only do so under the direction of the master. Some I2C devices can act as a master or slave, but the ADS101x-Q1 can only act as a slave device. An I2C bus consists of two lines: SDA and SCL. SDA carries data; SCL provides the clock. All data are transmitted across the I2C bus in groups of eight bits. To send a bit on the I2C bus, drive the SDA line to the appropriate level while SCL is low (a low on SDA indicates the bit is zero; a high indicates the bit is one). After the SDA line settles, the SCL line is brought high, then low. This pulse on SCL clocks the SDA bit into the receiver shift register. If the I2C bus is held idle for more than 25 ms, the bus times out. The I2C bus is bidirectional; that is, the SDA line is used for both transmitting and receiving data. When the master reads from a slave, the slave drives the data line; when the master sends to a slave, the master drives the data line. The master always drives the clock line. The ADS101x-Q1 cannot act as a master, and therefore can never drive SCL. Most of the time the bus is idle; no communication occurs, and both lines are high. When communication takes place, the bus is active. Only a master device can start a communication and initiate a START condition on the bus. Normally, the data line is only allowed to change state while the clock line is low. If the data line changes state while the clock line is high, it is either a START condition or a STOP condition. A START condition occurs when the clock line is high, and the data line goes from high to low. A STOP condition occurs when the clock line is high, and the data line goes from low to high. After the master issues a START condition, the master sends a byte that indicates with which slave device to communicate. This byte is called the address byte. Each device on an I2C bus has a unique 7-bit address to which it responds. The master sends an address in the address byte, together with a bit that indicates whether the master wishes to read from or write to the slave device. Every byte (address and data) transmitted on the I2C bus is acknowledged with an acknowledge bit. When the master finishes sending a byte (eight data bits) to a slave, the master stops driving SDA and waits for the slave to acknowledge the byte. The slave acknowledges the byte by pulling SDA low. The master then sends a clock pulse to clock the acknowledge bit. Similarly, when the master completes reading a byte, the master pulls SDA low to acknowledge this completion to the slave. The master then sends a clock pulse to clock the bit. The master always drives the clock line. If a device is not present on the bus, and the master attempts to address it, it receives a not-acknowledge because no device is present at that address to pull the line low. A not-acknowledge is performed by simply leaving SDA high during an acknowledge cycle. When the master has finished communicating with a slave, it may issue a STOP condition. When a STOP condition is issued, the bus becomes idle again. The master may also issue another START condition. When a START condition is issued while the bus is active, it is called a repeated start condition. The Timing Requirements section shows a timing diagram for the ADS101x-Q1 I2C communication. 16 Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: ADS1013-Q1 ADS1014-Q1 ADS1015-Q1 ADS1013-Q1, ADS1014-Q1, ADS1015-Q1 www.ti.com SBAS511B – JULY 2010 – REVISED DECEMBER 2016 Programming (continued) 8.5.1.1 I2C Address Selection The ADS101x-Q1 have one address pin, ADDR, that configures the I2C address of the device. This pin can be connected to GND, VDD, SDA, or SCL, allowing for four different addresses to be selected with one pin, as shown in Table 2. The state of address pin ADDR is sampled continuously. Use the GND, VDD and SCL addresses first. If SDA is used as the device address, hold the SDA line low for at least 100 ns after the SCL line goes low to make sure the device decodes the address correctly during I2C communication. Table 2. ADDR Pin Connection and Corresponding Slave Address ADDR PIN CONNECTION SLAVE ADDRESS GND 1001000 VDD 1001001 SDA 1001010 SCL 1001011 2 8.5.1.2 I C General Call The ADS101x-Q1 respond to the I2C general call address (0000000) if the eighth bit is 0. The devices acknowledge the general call address and respond to commands in the second byte. If the second byte is 00000110 (06h), the ADS101x-Q1 reset the internal registers and enter a power-down state. 8.5.1.3 I2C Speed Modes The I2C bus operates at one of three speeds. Standard mode allows a clock frequency of up to 100 kHz; fast mode permits a clock frequency of up to 400 kHz; and high-speed mode (also called Hs mode) allows a clock frequency of up to 3.4 MHz. The ADS101x-Q1 are fully compatible with all three modes. No special action is required to use the ADS101x-Q1 in standard or fast mode, but high-speed mode must be activated. To activate high-speed mode, send a special address byte of 00001xxx following the START condition, where xxx are bits unique to the Hs-capable master. This byte is called the Hs master code, and is different from normal address bytes; the eighth bit does not indicate read/write status. The ADS101x-Q1 do not acknowledge this byte; the I2C specification prohibits acknowledgment of the Hs master code. Upon receiving a master code, the ADS101x-Q1 switch on Hs mode filters, and communicate at up to 3.4 MHz. The ADS101x-Q1 switch out of Hs mode with the next STOP condition. For more information on high-speed mode, consult the I2C specification. 8.5.2 Slave Mode Operations The ADS101x-Q1 act as slave receivers or slave transmitters. The ADS101x-Q1 cannot drive the SCL line as slave devices. 8.5.2.1 Receive Mode In slave receive mode, the first byte transmitted from the master to the slave consists of the 7-bit device address followed by a low R/W bit. The next byte transmitted by the master is the Address Pointer register. The ADS101x-Q1 then acknowledge receipt of the Address Pointer register byte. The next two bytes are written to the address given by the register address pointer bits, P[1:0]. The ADS101x-Q1 acknowledge each byte sent. Register bytes are sent with the most significant byte first, followed by the least significant byte. 8.5.2.2 Transmit Mode In slave transmit mode, the first byte transmitted by the master is the 7-bit slave address followed by the high R/W bit. This byte places the slave into transmit mode and indicates that the ADS101x-Q1 are being read from. The next byte transmitted by the slave is the most significant byte of the register that is indicated by the register address pointer bits, P[1:0]. This byte is followed by an acknowledgment from the master. The remaining least significant byte is then sent by the slave and is followed by an acknowledgment from the master. The master may terminate transmission after any byte by not acknowledging or issuing a START or STOP condition. Copyright © 2010–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADS1013-Q1 ADS1014-Q1 ADS1015-Q1 17 ADS1013-Q1, ADS1014-Q1, ADS1015-Q1 SBAS511B – JULY 2010 – REVISED DECEMBER 2016 www.ti.com 8.5.3 Writing To and Reading From the Registers To access a specific register from the ADS101x-Q1, the master must first write an appropriate value to register address pointer bits P[1:0] in the Address Pointer register. The Address Pointer register is written to directly after the slave address byte, low R/W bit, and a successful slave acknowledgment. After the Address Pointer register is written, the slave acknowledges, and the master issues a STOP or a repeated START condition. When reading from the ADS101x-Q1, the previous value written to bits P[1:0] determines the register that is read. To change which register is read, a new value must be written to P[1:0]. To write a new value to P[1:0], the master issues a slave address byte with the R/W bit low, followed by the Address Pointer register byte. No additional data has to be transmitted, and a STOP condition can be issued by the master. The master can now issue a START condition and send the slave address byte with the R/W bit high to begin the read. Figure 22 details this sequence. If repeated reads from the same register are desired, there is no need to continually send the Address Pointer register, because the ADS101x-Q1 store the value of P[1:0] until it is modified by a write operation. However, for every write operation, the Address Pointer register must be written with the appropriate values. 1 9 1 9 SCL ¼ SDA 1 0 0 1 0 A1 (1) (1) A0 Start By Master 0 R/W 0 0 0 0 0 P1 ACK By ADS1013/4/5-Q1 P0 ACK By Stop By ADS1013/4/5-Q1 Master Frame 2: Address Pointer Register Frame 1: Slave Address Byte 1 9 1 9 SCL (Continued) ¼ SDA (Continued) 1 0 0 1 0 A1 (1) (1) A0 Start By Master R/W D15 D14 ACK By ADS1013/4/5-Q1 D13 D12 D11 D10 D9 D8 From ADS1013/4/5-Q1 ¼ ACK By Master (2) Frame 4: Data Byte 1 Read Register Frame 3: Slave Address Byte 1 9 SCL (Continued) SDA (Continued) D7 D6 D5 D4 D3 D2 From ADS1013/4/5-Q1 D1 D0 ACK By Master (3) Stop By Master Frame 5: Data Byte 2 Read Register (1) The values of A0 and A1 are determined by the ADDR pin. (2) Master can leave SDA high to terminate a single-byte read operation. (3) Master can leave SDA high to terminate a two-byte read operation. Figure 15. Timing Diagram for Reading From ADS101x-Q1 18 Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: ADS1013-Q1 ADS1014-Q1 ADS1015-Q1 ADS1013-Q1, ADS1014-Q1, ADS1015-Q1 www.ti.com SBAS511B – JULY 2010 – REVISED DECEMBER 2016 1 9 9 1 SCL ¼ 1 SDA 0 0 1 A1(1) 0 A0(1) R/W Start By Master 0 0 0 0 0 0 P1 ACK By ADS1013/4/5-Q1 P0 ¼ ACK By ADS1013/4/5-Q1 Frame 2: Address Pointer Register Frame 1: Slave Address Byte 9 1 1 9 SCL (Continued) SDA (Continued) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 ACK By ADS1013/4/5-Q1 ACK By ADS1013/4/5-Q1 Stop By Master Frame 4: Data Byte 2 Frame 3: Data Byte 1 (1) D0 The values of A0 and A1 are determined by the ADDR pin. Figure 16. Timing Diagram for Writing to ADS101x-Q1 ALERT 1 9 1 9 SCL SDA 0 0 0 1 1 Start By Master 0 0 R/W ACK By ADS1013/4/5-Q1 Frame 1: SMBus ALERT Response Address Byte (1) 1 0 0 1 A1 A0 Status From ADS1013/4/5-Q1 NACK By Master Stop By Master Frame 2: Slave Address The values of A0 and A1 are determined by the ADDR pin. Figure 17. Timing Diagram for SMBus Alert Response Copyright © 2010–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADS1013-Q1 ADS1014-Q1 ADS1015-Q1 19 ADS1013-Q1, ADS1014-Q1, ADS1015-Q1 SBAS511B – JULY 2010 – REVISED DECEMBER 2016 www.ti.com 8.5.4 Data Format The ADS101x-Q1 provide 12 bits of data in binary two's complement format that is left justified within the 16-bit data word. A positive full-scale (+FS) input produces an output code of 7FF0h and a negative full-scale (–FS) input produces an output code of 8000h. The output clips at these codes for signals that exceed full-scale. Table 3 summarizes the ideal output codes for different input signals. Figure 18 shows code transitions versus input voltage. Table 3. Input Signal Versus Ideal Output Code INPUT SIGNAL VIN = (VAINP – VAINN) ≥ +FS (2 11 IDEAL OUTPUT CODE(1) (1) 11 – 1)/2 7FF0h +FS/211 (1) 0010h 0 0000h –FS/211 FFF0h ≤ –FS 8000h Excludes the effects of noise, INL, offset, and gain errors. 7FF0h 0010h 0000h FFF0h ... Output Code ... 7FE0h 8010h 8000h ... -FS 2 11 -FS 2 0 ... +FS Input Voltage VIN 2 -1 11 11 +FS 2 -1 11 Figure 18. Code Transition Diagram 20 Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: ADS1013-Q1 ADS1014-Q1 ADS1015-Q1 ADS1013-Q1, ADS1014-Q1, ADS1015-Q1 www.ti.com SBAS511B – JULY 2010 – REVISED DECEMBER 2016 8.6 Register Map The ADS101x-Q1 have four registers that are accessible through the I2C interface using the Address Pointer register. The Conversion register contains the result of the last conversion. The Config register is used to change the ADS101x-Q1 operating modes and query the status of the device. The other two registers, Lo_thresh and Hi_thresh, set the threshold values used for the comparator function, and are not available in the ADS1013-Q1. 8.6.1 Address Pointer Register (address = N/A) [reset = N/A] All four registers are accessed by writing to the Address Pointer register; see Figure 15. Figure 19. Address Pointer Register 7 0 W-0h 6 0 W-0h 5 0 W-0h 4 0 W-0h 3 0 W-0h 2 0 W-0h 1 0 P[1:0] W-0h LEGEND: R/W = Read/Write; R = Read only; W = Write only; -n = value after reset Table 4. Address Pointer Register Field Descriptions Bit Field Type Reset Description 7:2 Reserved W 0h Always write 0h 1:0 P[1:0] W 0h Register address pointer 00 01 10 11 : : : : Conversion register Config register Lo_thresh register Hi_thresh register 8.6.2 Conversion Register (P[1:0] = 0h) [reset = 0000h] The 16-bit Conversion register contains the result of the last conversion in binary two's complement format. Following power-up, the Conversion register is cleared to 0, and remains 0 until the first conversion is completed. Figure 20. Conversion Register 15 D11 R-0h 7 D3 R-0h 14 D10 R-0h 6 D2 R-0h 13 D9 R-0h 5 D1 R-0h 12 D8 R-0h 4 D0 R-0h 11 D7 R-0h 3 10 D6 R-0h 2 R-0h R-0h 9 D5 R-0h 1 8 D4 R-0h 0 R-0h R-0h Reserved LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 5. Conversion Register Field Descriptions Field Type Reset Description 15:4 Bit D[11:0] R 000h 12-bit conversion result 3:0 Reserved R 0h Always Reads back 0h Copyright © 2010–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADS1013-Q1 ADS1014-Q1 ADS1015-Q1 21 ADS1013-Q1, ADS1014-Q1, ADS1015-Q1 SBAS511B – JULY 2010 – REVISED DECEMBER 2016 www.ti.com 8.6.3 Config Register (P[1:0] = 1h) [reset = 8583h] The 16-bit Config register is used to control the operating mode, input selection, data rate, full-scale range, and comparator modes. Figure 21. Config Register 15 OS R/W-1h 7 14 6 DR[2:0] R/W-4h 13 MUX[2:0] R/W-0h 5 12 11 4 COMP_MODE R/W-0h 3 COMP_POL R/W-0h 10 PGA[2:0] R/W-2h 2 COMP_LAT R/W-0h 9 8 MODE R/W-1h 1 0 COMP_QUE[1:0] R/W-3h LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 6. Config Register Field Descriptions Bit Field Type Reset Description Operational status or single-shot conversion start This bit determines the operational status of the device. OS can only be written when in power-down state and has no effect when a conversion is ongoing. 15 OS R/W 1h When writing: 0 : No effect 1 : Start a single conversion (when in power-down state) When reading: 0 : Device is currently performing a conversion 1 : Device is not currently performing a conversion Input multiplexer configuration (ADS1015-Q1 only) These bits configure the input multiplexer. These bits serve no function on the ADS1013-Q1 and ADS1014-Q1. 14:12 MUX[2:0] R/W 0h 000 : 001 : 010 : 011 : 100 : 101 : 110 : 111 : AINP AINP AINP AINP AINP AINP AINP AINP = AIN0 = AIN0 = AIN1 = AIN2 = AIN0 = AIN1 = AIN2 = AIN3 and AINN = AIN1 (default) and AINN = AIN3 and AINN = AIN3 and AINN = AIN3 and AINN = GND and AINN = GND and AINN = GND and AINN = GND Programmable gain amplifier configuration These bits set the FSR of the programmable gain amplifier. These bits serve no function on the ADS1013-Q1. 11:9 8 PGA[2:0] MODE R/W 2h R/W 1h 000 : 001 : 010 : 011 : 100 : 101 : 110 : 111 : FSR = ±6.144 FSR = ±4.096 FSR = ±2.048 FSR = ±1.024 FSR = ±0.512 FSR = ±0.256 FSR = ±0.256 FSR = ±0.256 V (1) V (1) V (default) V V V V V Device operating mode This bit controls the operating mode. 0 : Continuous-conversion mode 1 : Single-shot mode or power-down state (default) Data rate These bits control the data rate setting. 7:5 (1) 22 DR[2:0] R/W 4h 000 : 001 : 010 : 011 : 100 : 101 : 110 : 111 : 128 SPS 250 SPS 490 SPS 920 SPS 1600 SPS (default) 2400 SPS 3300 SPS 3300 SPS This parameter expresses the full-scale range of the ADC scaling. Do not apply more than VDD + 0.3 V to this device. Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: ADS1013-Q1 ADS1014-Q1 ADS1015-Q1 ADS1013-Q1, ADS1014-Q1, ADS1015-Q1 www.ti.com SBAS511B – JULY 2010 – REVISED DECEMBER 2016 Table 6. Config Register Field Descriptions (continued) Bit 4 Field COMP_MODE Type R/W Reset Description 0h Comparator mode (ADS1014-Q1 and ADS1015-Q1 only) This bit configures the comparator operating mode. This bit serves no function on the ADS1013-Q1. 0 : Traditional comparator (default) 1 : Window comparator 3 COMP_POL R/W 0h Comparator polarity (ADS1014-Q1 and ADS1015-Q1 only) This bit controls the polarity of the ALERT/RDY pin. This bit serves no function on the ADS1013-Q1. 0 : Active low (default) 1 : Active high Latching comparator (ADS1014-Q1 and ADS1015-Q1 only) This bit controls whether the ALERT/RDY pin latches after being asserted or clears after conversions are within the margin of the upper and lower threshold values. This bit serves no function on the ADS1013-Q1. 2 1:0 COMP_LAT COMP_QUE[1:0] R/W R/W 0h 3h 0 : Nonlatching comparator . The ALERT/RDY pin does not latch when asserted (default). 1 : Latching comparator. The asserted ALERT/RDY pin remains latched until conversion data are read by the master or an appropriate SMBus alert response is sent by the master. The device responds with its address, and it is the lowest address currently asserting the ALERT/RDY bus line. Comparator queue and disable (ADS1014-Q1 and ADS1015-Q1 only) These bits perform two functions. When set to 11, the comparator is disabled and the ALERT/RDY pin is set to a high-impedance state. When set to any other value, the ALERT/RDY pin and the comparator function are enabled, and the set value determines the number of successive conversions exceeding the upper or lower threshold required before asserting the ALERT/RDY pin. These bits serve no function on the ADS1013-Q1. 00 : Assert after one conversion 01 : Assert after two conversions 10 : Assert after four conversions 11 : Disable comparator and set ALERT/RDY pin to high-impedance (default) Copyright © 2010–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADS1013-Q1 ADS1014-Q1 ADS1015-Q1 23 ADS1013-Q1, ADS1014-Q1, ADS1015-Q1 SBAS511B – JULY 2010 – REVISED DECEMBER 2016 www.ti.com 8.6.4 Lo_thresh (P[1:0] = 2h) [reset = 8000h] and Hi_thresh (P[1:0] = 3h) [reset = 7FFFh] Registers The upper and lower threshold values used by the comparator are stored in two 16-bit registers in two's complement format. The comparator is implemented as a digital comparator; therefore, the values in these registers must be updated whenever the PGA settings are changed. The conversion-ready function of the ALERT/RDY pin is enabled by setting the Hi_thresh register MSB to 1 and the Lo_thresh register MSB to 0. To use the comparator function of the ALERT/RDY pin, the Hi_thresh register value must always be greater than the Lo_thresh register value. The threshold register formats are shown in Figure 22. When set to RDY mode, the ALERT/RDY pin outputs the OS bit when in single-shot mode, and provides a continuous-conversion ready pulse when in continuous-conversion mode. Figure 22. Lo_thresh Register 15 Lo_thresh11 R/W-1h 7 Lo_thresh3 R/W-0h 14 Lo_thresh10 R/W-0h 6 Lo_thresh2 R/W-0h 13 Lo_thresh9 R/W-0h 5 Lo_thresh1 R/W-0h 12 Lo_thresh8 R/W-0h 4 Lo_thresh0 R/W-0h 11 Lo_thresh7 R/W-0h 3 0 R-0h 10 Lo_thresh6 R/W-0h 2 0 R-0h 9 Lo_thresh5 R/W-0h 1 0 R-0h 8 Lo_thresh4 R/W-0h 0 0 R-0h 10 Hi_thresh6 R/W-1h 2 1 R-1h 9 Hi_thresh5 R/W-1h 1 1 R-1h 8 Hi_thresh4 R/W-1h 0 1 R-1h LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Figure 23. Hi_thresh Register 15 Hi_thresh11 R/W-0h 7 Hi_thresh3 R/W-1h 14 Hi_thresh10 R/W-1h 6 Hi_thresh2 R/W-1h 13 Hi_thresh9 R/W-1h 5 Hi_thresh1 R/W-1h 12 Hi_thresh8 R/W-1h 4 Hi_thresh0 R/W-1h 11 Hi_thresh7 R/W-1h 3 1 R-1h LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 7. Lo_thresh and Hi_thresh Register Field Descriptions Bit 24 Field Type Reset Description 15:4 Lo_thresh[11:0] R/W 800h Low threshold value 15:4 Hi_thresh[11:0] R/W 7FFh High threshold value Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: ADS1013-Q1 ADS1014-Q1 ADS1015-Q1 ADS1013-Q1, ADS1014-Q1, ADS1015-Q1 www.ti.com SBAS511B – JULY 2010 – REVISED DECEMBER 2016 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 9.1 Application Information The following sections give example circuits and suggestions for using the ADS101x-Q1 in various situations. 9.1.1 Basic Connections The principle I2C connections for the ADS1015-Q1 are shown in Figure 24. 10 ADS1015-Q1 1-k to 10-k (typ) Pullup Resistors VDD Microcontroller or Microprocessor with I2C Port VDD SCL 1 ADDR SDA 9 2 ALERT/RDY VDD 8 3 GND AIN3 7 4 AIN0 AIN2 6 0.1 …F (typ) AIN1 5 SCL SDA GPIO Inputs Selected from Configuration Register Copyright © 2016, Texas Instruments Incorporated Figure 24. Typical Connections of the ADS1015-Q1 The fully-differential voltage input of the ADS101x-Q1 is ideal for connection to differential sources with moderately low source impedance, such as thermocouples and thermistors. Although the ADS101x-Q1 can read bipolar differential signals, these devices cannot accept negative voltages on either input. The ADS101x-Q1 draw transient currents during conversion. A 0.1-μF power-supply bypass capacitor supplies the momentary bursts of extra current required from the supply. The ADS101x-Q1 interface directly to standard mode, fast mode, and high-speed mode I2C controllers. Any microcontroller I2C peripheral, including master-only and single-master I2C peripherals, operates with the ADS101x-Q1. The ADS101x-Q1 does not perform clock-stretching (that is, the device never pulls the clock line low), so it is not necessary to provide for this function unless other clock-stretching devices are on the same I2C bus. Pullup resistors are required on both the SDA and SCL lines because I2C bus drivers are open drain. The size of these resistors depends on the bus operating speed and capacitance of the bus lines. Higher-value resistors consume less power, but increase the transition times on the bus, thus limiting the bus speed. Lower-value resistors allow higher speed, but at the expense of higher power consumption. Long bus lines have higher capacitance and require smaller pullup resistors to compensate. Do not use resistors that are too small because the bus drivers may not be able to pull the bus lines low. Copyright © 2010–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADS1013-Q1 ADS1014-Q1 ADS1015-Q1 25 ADS1013-Q1, ADS1014-Q1, ADS1015-Q1 SBAS511B – JULY 2010 – REVISED DECEMBER 2016 www.ti.com Application Information (continued) 9.1.2 Single-Ended Inputs The ADS1013-Q1 and ADS1014-Q1 can measure one, and the ADS1015-Q1 up to four, single-ended signals. The ADS1013-Q1 and ADS1014-Q1 can measure single-ended signals by connecting AIN1 to GND externally. The ADS1015-Q1 measures single-ended signals by appropriate configuration of the MUX[2:0] bits in the Config register. Figure 25 shows a single-ended connection scheme for ADS1015-Q1. The single-ended signal ranges from 0 V up to positive supply or +FS, whichever is lower. Negative voltages cannot be applied to these devices because the ADS101x-Q1 can only accept positive voltages with respect to ground. The ADS101x-Q1 do not lose linearity within the input range. The ADS101x-Q1 offer a differential input voltage range of ±FSR. Single-ended configurations use only one-half of the full-scale input voltage range. Differential configurations maximize the dynamic range of the ADC, and provide better common-mode noise rejection than single-ended configurations. VDD Output Codes 0-2047 10 ADS1015-Q1 SCL 1 ADDR SDA 9 2 ALERT/RDY VDD 8 3 GND AIN3 7 4 AIN0 AIN2 6 0.1 F (typ) AIN1 5 Inputs Selected from Configuration Register Copyright © 2016, Texas Instruments Incorporated NOTE: Digital pin connections omitted for clarity. Figure 25. Measuring Single-Ended Inputs The ADS1015-Q1 also allows AIN3 to serve as a common point for measurements by appropriate setting of the MUX[2:0] bits. AIN0, AIN1, and AIN2 can all be measured with respect to AIN3. In this configuration, the ADS1015-Q1 operates with inputs, where AIN3 serves as the common point. This ability improves the usable range over the single-ended configuration because negative differential voltages are allowed when GND < V(AIN3) < VDD; however, common-mode noise attenuation is not offered. 9.1.3 Input Protection The ADS101x-Q1 are fabricated in a small-geometry, low-voltage process. The analog inputs feature protection diodes to the supply rails. However, the current-handling ability of these diodes is limited, and the ADS101x-Q1 can be permanently damaged by analog input voltages that exceed approximately 300 mV beyond the rails for extended periods. One way to protect against overvoltage is to place current-limiting resistors on the input lines. The ADS101x-Q1 analog inputs can withstand continuous currents as large as 10 mA. 9.1.4 Unused Inputs and Outputs Either float unused analog inputs, or tie the unused analog inputs to midsupply or VDD. Connecting unused analog inputs to GND is possible, but may yield higher leakage currents than the previous options. Either float NC (not-connected) pins, or tie the NC pins to GND. If the ALERT/RDY output pin is not used, leave the pin unconnected or tie the pin to VDD using a weak pullup resistor. 26 Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: ADS1013-Q1 ADS1014-Q1 ADS1015-Q1 ADS1013-Q1, ADS1014-Q1, ADS1015-Q1 www.ti.com SBAS511B – JULY 2010 – REVISED DECEMBER 2016 Application Information (continued) 9.1.5 Analog Input Filtering Analog input filtering serves two purposes: 1. Limits the effect of aliasing during the sampling process 2. Reduces external noise from being a part of the measurement Aliasing occurs when frequency components are present in the input signal that are higher than half the sampling frequency of the ADC (also known as the Nyquist frequency). These frequency components fold back and show up in the actual frequency band of interest below half the sampling frequency. The filter response of the digital filter repeats at multiples of the sampling frequency, also known as the modulator frequency (fMOD), as shown in Figure 26. Signals or noise up to a frequency where the filter response repeats are attenuated to a certain amount by the digital filter depending on the filter architecture. Any frequency components present in the input signal around the modulator frequency, or multiples thereof, are not attenuated and alias back into the band of interest, unless attenuated by an external analog filter. Magnitude Sensor Signal Output Data Rate Magnitude Unwanted Signals Unwanted Signals fMOD / 2 fMOD Frequency fMOD Frequency fMOD Frequency Digital Filter Aliasing of Unwanted Signals Output Data Rate Magnitude fMOD / 2 External Antialiasing Filter Roll-Off Output Data Rate fMOD / 2 Figure 26. Effect of Aliasing Many sensor signals are inherently band-limited; for example, the output of a thermocouple has a limited rate of change. In this case, the sensor signal does not alias back into the pass-band when using a ΔΣ ADC. However, any noise pick-up along the sensor wiring or the application circuitry can potentially alias into the pass-band. Power line-cycle frequency and harmonics are one common noise source. External noise can also be generated from electromagnetic interference (EMI) or radio frequency interference (RFI) sources, such as nearby motors and cellular phones. Another noise source typically exists on the printed-circuit-board (PCB) itself in the form of clocks and other digital signals. Analog input filtering helps remove unwanted signals from affecting the measurement result. A first-order resistor-capacitor (RC) filter is (in most cases) sufficient to either totally eliminate aliasing, or to reduce the effect of aliasing to a level within the noise floor of the sensor. Ideally, any signal beyond fMOD / 2 is attenuated to a level below the noise floor of the ADC. The digital filter of the ADS101x-Q1 attenuate signals to a certain degree. In addition, noise components are usually smaller in magnitude than the actual sensor signal. Therefore, use a first-order RC filter with a cutoff frequency set at the output data rate or 10x higher as a generally good starting point for a system design. Copyright © 2010–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADS1013-Q1 ADS1014-Q1 ADS1015-Q1 27 ADS1013-Q1, ADS1014-Q1, ADS1015-Q1 SBAS511B – JULY 2010 – REVISED DECEMBER 2016 www.ti.com Application Information (continued) 9.1.6 Connecting Multiple Devices It is possible to connect up to four ADS101x-Q1 devices to a single I2C bus using different address pin configurations for each device. Use the address pin to set the ADS101x-Q1 to one of four different I2C addresses. Use the GND, VDD and SCL addresses first. If SDA is used as the device address, hold the SDA line low for at least 100 ns after the SCL line goes low to make sure the device decodes the address correctly during I2C communication. An example showing four ADS101x-Q1 devices on the same I2C bus is shown in Figure 27. One set of pullup resistors is required per bus. The pullup resistor values may need to be lowered to compensate for the additional bus capacitance presented by multiple devices and increased line length. VDD GND 10 ADS1015-Q1 1-k to 10-k (typ) I2C Pullup Resistors Microcontroller or Microprocessor With I2C Port VDD SCL 1 ADDR SDA 9 2 ALERT/RDY VDD 8 3 GND AIN3 7 4 AIN0 AIN2 6 AIN1 5 SCL SDA 10 ADS1015-Q1 SCL 1 ADDR SDA 9 2 ALERT/RDY VDD 8 3 GND AIN3 7 4 AIN0 AIN2 6 AIN1 5 ADS1015-Q1 10 SCL 1 ADDR SDA 9 2 ALERT/RDY VDD 8 3 GND AIN3 7 4 AIN0 AIN2 6 AIN1 5 10 ADS1015-Q1 SCL 1 ADDR SDA 9 2 ALERT/RDY VDD 8 3 GND AIN3 7 4 AIN0 AIN2 6 AIN1 5 Copyright © 2016, Texas Instruments Incorporated NOTE: ADS101x-Q1 power and input connections omitted for clarity. The ADDR pin selects the I2C address. Figure 27. Connecting Multiple ADS101x-Q1 Devices 28 Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: ADS1013-Q1 ADS1014-Q1 ADS1015-Q1 ADS1013-Q1, ADS1014-Q1, ADS1015-Q1 www.ti.com SBAS511B – JULY 2010 – REVISED DECEMBER 2016 Application Information (continued) 9.1.7 Quickstart Guide This section provides a brief example of ADS101x-Q1 communications. See subsequent sections of this data sheet for more detailed explanations. Hardware for this design includes: one ADS101x-Q1 configured with an I2C address of 1001000; a microcontroller with an I2C interface; discrete components such as resistors, capacitors, and serial connectors; and a 2 V to 5 V power supply. Figure 28 shows the basic hardware configuration. The ADS101x-Q1 communicate with the master (microcontroller) through an I2C interface. The master provides a clock signal on the SCL pin and data are transferred using the SDA pin. The ADS101x-Q1 never drive the SCL pin. For information on programming and debugging the microcontroller being used, see the device-specific product data sheet. The first byte sent by the master is the ADS101x-Q1 address, followed by the R/W bit that instructs the ADS101x-Q1 to listen for a subsequent byte. The second byte is the Address Pointer register byte. The third and fourth bytes sent from the master are written to the register indicated in register address pointer bits P[1:0]. See Figure 15 and Figure 16 for read and write operation timing diagrams, respectively. All read and write transactions with the ADS101x-Q1 must be preceded by a START condition, and followed by a STOP condition. For example, to write to the configuration register to set the ADS101x-Q1 to continuous-conversion mode and then read the conversion result, send the following bytes in this order: 1. Write to Config register: – First byte: 0b10010000 (first 7-bit I2C address followed by a low R/W bit) – Second byte: 0b00000001 (points to Config register) – Third byte: 0b10000100 (MSB of the Config register to be written) – Fourth byte: 0b10000011 (LSB of the Config register to be written) 2. Write to Address Pointer register: – First byte: 0b10010000 (first 7-bit I2C address followed by a low R/W bit) – Second byte: 0b00000000 (points to Conversion register) 3. Read Conversion register: – First byte: 0b10010001 (first 7-bit I2C address followed by a high R/W bit) – Second byte: the ADS101x-Q1 response with the MSB of the Conversion register – Third byte: the ADS101x-Q1 response with the LSB of the Conversion register 3.3 V ADS101x-Q1 VDD 0.1 µF GND 2 3.3 V I C-Capable Master (MSP430F2002) AIN0 AIN1 3.3 V ADDR AIN2 (ADS1015-Q1 Only) AIN3 (ADS1015-Q1 Only) 10 10 SCL SCL (P1.6) SDA SDA (P1.7) VDD 0.1 µF GND ALERT (ADS1014/5-Q1 Only) JTAG Serial/UART Copyright © 2016, Texas Instruments Incorporated Figure 28. Basic Hardware Configuration Copyright © 2010–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADS1013-Q1 ADS1014-Q1 ADS1015-Q1 29 ADS1013-Q1, ADS1014-Q1, ADS1015-Q1 SBAS511B – JULY 2010 – REVISED DECEMBER 2016 www.ti.com 9.2 Typical Application Shunt-based, current-measurement solutions are widely used to monitor load currents. Low-side, current-shunt measurements are independent of the bus voltage because the shunt common-mode voltage is near ground. Figure 29 shows an example circuit for a bidirectional, low-side, current-shunt measurement system. The load current is determined by measuring the voltage across the shunt resistor that is amplified and level-shifted by a low-drift operational amplifier, OPA333-Q1. The OPA333-Q1 output voltage is digitized with ADS1015-Q1 and sent to the microcontroller using the I2C interface. This circuit is capable of measuring bidirectional currents flowing through the shunt resistor with great accuracy and precision. High-Voltage Bus VCM VDD VDD CCM2 LOAD R6 AINN ILOAD VINX RSHUNT 4-Wire Kelvin Connection R3 R4 OPA333-Q1 R5 + ADS1015-Q1 I2C AINP VOUT ± VSHUNT CDIFF R1 CCM1 R2 Figure 29. Low-Side Current Shunt Monitoring 9.2.1 Design Requirements Table 8 shows the design parameters for this application. Table 8. Design Parameters DESIGN PARAMETER VALUE Supply voltage (VDD) 5V Voltage across Shunt Resistor (VSHUNT) ±50 mV ≥200 readings per second Output Data Rate (DR) Typical measurement accuracy at TA = 25°C (1) (1) ±0.25% Does not account for inaccuracy of shunt resistor and the precision resistors used in the application. 9.2.2 Detailed Design Procedure The first stage of the application circuit consists of an OPA333-Q1 in a noninverting summing amplifier configuration and serves two purposes: 1. To level-shift the ground-referenced signal to allow bidirectional current measurements while running off a unipolar supply. The voltage across the shunt resistor, VSHUNT, is level-shifted by a common-mode voltage, VCM, as shown in Figure 29. The level-shifted voltage, VINX, at the noninverting input is given by Equation 3. VINX = (VCM · R3 + VSHUNT · R4) / (R3 + R4) (3) 2. To amplify the level-shifted voltage (VINX). The OPA333-Q1 is configured in a noninverting gain configuration with the output voltage, VOUT, given by Equation 4. VOUT = VINX · (1 + R2 / R1) (4) Using Equation 3 and Equation 4, VOUT is given as a function of VSHUNT and VCM by Equation 5. VOUT = (VCM · R3 + VSHUNT · R4) / (R3 + R4) · (1 + R2 / R1) (5) Using Equation 5 the ADC differential input voltage, before the first-order RC filter, is given by Equation 6. VOUT – VCM = VSHUNT · (1 + R2 / R1) / (1 + R4 / R3) + VCM · (R2 / R1 – R3 / R4) / (1 + R3 / R4) (6) If R1 = R3 and R2 = R4, Equation 6 is simplified to Equation 7. VOUT – VCM = VSHUNT · (1 + R2 / R1) / (1 + R4 / R3) 30 Submit Documentation Feedback (7) Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: ADS1013-Q1 ADS1014-Q1 ADS1015-Q1 ADS1013-Q1, ADS1014-Q1, ADS1015-Q1 www.ti.com SBAS511B – JULY 2010 – REVISED DECEMBER 2016 9.2.2.1 Shunt Resistor Considerations A shunt resistor (RSHUNT) is an accurate resistance inserted in series with the load as shown in Figure 29. If the absolute voltage drop across the shunt, |VSHUNT|, is a larger percentage of the bus voltage, the voltage drop may reduce the overall efficiency and system performance. If |VSHUNT| is too low, measuring the small voltage drop requires careful design attention and proper selection of the ADC, operation amplifier, and precision resistors. Make sure that the absolute voltage at the shunt terminals does not result in violation of the input common-mode voltage range requirements of the operational amplifier. The power dissipation on the shunt resistor increases the temperature because of the current flowing through it. To minimize the measurement errors due to variation in temperature, select a low-drift shunt resistor. To minimize the measurement gain error, select a shunt resistor with low tolerance value. To remove the errors due to stray ground resistance, use a four-wire Kelvin-connected shunt resistor, as shown in Figure 29. 9.2.2.2 Operational Amplifier Considerations The operational amplifier used for this design example requires the following features: • Unipolar supply operation (5 V) • Low input offset voltage (< 10 µV) and input offset voltage drift (< 0.5 µV/°C) • Rail-to-rail input and output capability • Low thermal and flicker noise • High common-mode rejection (> 100 dB) OPA333-Q1 offers all these benefits and is selected for this application. 9.2.2.3 ADC Input Common-Mode Considerations VCM sets the VOUT common-mode voltage by appropriate selection of precision resistors R1, R2, R3, and R4. If R1 = R3, R2 = R4, and VSHUNT = 0 V, VOUT is given by Equation 8. VOUT = VCM (8) If VOUT is connected to the ADC positive input (AINP) and VCM is connected to the ADC negative input (AINN), VCM appears as a common-mode voltage to the ADC. This configuration allows pseudo-differential measurements and uses the maximum dynamic range of the ADC if VCM is set at midsupply (VDD/2). A resistor divider from VDD to GND followed by a buffer amplifier can be used to generate VCM. 9.2.2.4 Resistor (R1, R2, R3, R4) Considerations Proper selection of resistors R1, R2, R3 and R4 is critical for meeting the overall accuracy requirements. Using Equation 6, the offset term, VOUT-OS, and the gain term, AOUT, of the differential ADC input are represented by Equation 9 and Equation 10 respectively. The error contributions from the first-order RC filters are ignored. VOUT-OS = VCM · (R2 / R1 - R3 / R4) / (1 + R3 / R4) AOUT = (1 + R2 / R1) / (1 + R4 / R3) (9) (10) The tolerance, drift and linearity performance of these resistors is critical to meeting the overall accuracy requirements. In Equation 9, if R1 = R3 and R2 = R4, VOUT-OS = 0 V and therefore, the common-mode voltage, VCM, only contributes to level-shift VSHUNT and does not introduce any error at the differential ADC inputs. Highprecision resistors provide better common-mode rejection from VCM. 9.2.2.5 Noise and Input Impedance Considerations If vn_res represents the input-referred rms noise from all the resistors, vn_op represents the input-referred rms noise of OPA333-Q1, and vn_ADC represents the input-referred rms noise of ADS1015-Q1, the total input-referred noise of the entire system, vN, can be approximated by Equation 11. vN2 = vn_res2 + vn_op2 + vn_ADC/ (1 + R2 / R1)2 (11) It is important to note that the ADC noise contribution, vn_ADC, is attenuated by the non-inverting gain stage. Copyright © 2010–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADS1013-Q1 ADS1014-Q1 ADS1015-Q1 31 ADS1013-Q1, ADS1014-Q1, ADS1015-Q1 SBAS511B – JULY 2010 – REVISED DECEMBER 2016 www.ti.com If the gain of the noninverting gain stage is high (≥ 5), a good approximation for vn_res2 is given by Equation 12. The noise contribution from resistors R2, R4, R5, and R6 when referred to the input is smaller in comparison to R1 and R3 and can be neglected for approximation purposes. vn_res2 = 4 · k · T · (R1 + R3) · Δf where • • • k = Boltzmann constant T = temperature (in kelvins) Δf = noise bandwidth (12) An approximation for the input impedance, RIN, of the application circuit is given by Equation 13. RIN can be modeled as a resistor in parallel with the shunt resistor, and can contribute to additional gain error. RIN = R3 + R4 (13) From Equation 12 and Equation 13, a trade-off exists between vN and RIN. If R3 increases, vn_res increases, and therefore, the total input-referred rms system noise, vN, increases. If R3 decreases, the input impedance, RIN, drops, and causes additional gain error. 9.2.2.6 First-order RC Filter Considerations Although the device digital filter attenuates high-frequency noise, use a first order low-pass RC filter at the ADC inputs to further reject out-of-bandwidth noise and avoid aliasing. A differential low-pass RC filter formed by R5, R6, and the differential capacitor CDIFF sets the –3-dB cutoff frequency, fC, given by Equation 14. These filter resistors produce a voltage drop because of the input currents flowing into and out of the ADC. This voltage drop could contribute to an additional gain error. Limit the filter resistor values to below 1 kΩ. fC = 1 / [2π · (R5 + R6) · CDIFF] (14) Two common-mode filter capacitors (CCM1 and CCM2) are also added to offer attenuation of high-frequency, common-mode noise components. Select a differential capacitor, CDIFF, that is at least an order of magnitude (10x) larger than these common-mode capacitors because mismatches in these common-mode capacitors can convert common-mode noise into differential noise. 9.2.2.7 Circuit Implementation Table 9 shows the chosen values for this design. Table 9. Parameters PARAMETER (1) VALUE VCM 2.5 V FSR of ADC ±0.256 V Output Data Rate 250 SPS R1, R3 1 kΩ (1) R2, R4 5 kΩ (1) R5, R6 100 Ω (1) CDIFF 0.22 µF CCM1, CCM2 0.022 µF 1% precision resistors used Using Equation 5, if VSHUNT ranges from –50 mV to +50 mV, the application circuit produces a differential voltage ranging from –0.250 V to +0.250 V across the ADC inputs . The ADC is therefore configured at a FSR of ±0.256 V to maximize the dynamic range of the ADC. The –3 dB cutoff frequencies of the differential low-pass filter and the common-mode low-pass filters are set at 3.6 kHz and 0.36 kHz, respectively. RSHUNT typically ranges from 0.01 mΩ to 100 mΩ. Therefore, if R1 = R3 = 1 kΩ, a good trade-off exists between the circuit input impedance and input referred resistor noise as explained in the Noise and Input Impedance Considerations section. A simple resistor divider followed by a buffer amplifier is used to generate VCM of 2.5 V from a 5-V supply. 32 Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: ADS1013-Q1 ADS1014-Q1 ADS1015-Q1 ADS1013-Q1, ADS1014-Q1, ADS1015-Q1 www.ti.com SBAS511B – JULY 2010 – REVISED DECEMBER 2016 9.2.2.8 Results Summary A precision voltage source is used to sweep VSHUNT from -50 mV to +50 mV. The application circuit produces a differential voltage of –250 mV to +250 mV across the ADC inputs. Figure 30 and Figure 31 show the measurement results. The measurements are taken at TA = 25°C. Although 1% tolerance resistors are used, the exact value of these resistors are measured with a Fluke 4.5 digit multimeter to exclude the errors due to inaccuracy of these resistors. In Figure 30, the x-axis represents VSHUNT and the black line represents the measured digital output voltage in mV. In Figure 31, the x-axis represents VSHUNT, the black line represents the total measurement error in %, the blue line represents the total measurement error in % after excluding the errors from precision resistors and the green line represents the total measurement error in % after excluding the errors from precision resistors and performing a system offset calibration with VSHUNT = 0 V. Table 10 shows a results summary. Table 10. Results Summary (1) PARAMETER VALUE Total error, including errors from 1% precision resistors 1.89% Total error, excluding errors from 1% precision resistors 0.17% Total error, after offset calibration, excluding errors from 1% precision resistors 0.11% (1) TA = 25°C, not accounting for inaccuracy of shunt resistor. 9.2.3 Application Curves 250 150 Measurement Error ( ) Measured Output (mV) 200 100 50 0 -50 -100 -150 -200 -250 -60 -50 -40 -30 -20 -10 0 10 20 Shunt Voltage (mV) 30 40 50 60 D004 Figure 30. Measured Output vs Shunt Voltage (VSHUNT) Copyright © 2010–2016, Texas Instruments Incorporated 2 1.75 1.5 1.25 1 0.75 0.5 0.25 0 -0.25 -0.5 -0.75 -1 -1.25 -1.5 -1.75 -2 -50 Including all errors Excluding resistor errors Excluding resistor errors, after offset calibration -40 -30 -20 -10 0 10 20 Shunt Voltage (mV) 30 40 50 D005 Figure 31. Measurement Error vs Shunt Voltage (VSHUNT) Submit Documentation Feedback Product Folder Links: ADS1013-Q1 ADS1014-Q1 ADS1015-Q1 33 ADS1013-Q1, ADS1014-Q1, ADS1015-Q1 SBAS511B – JULY 2010 – REVISED DECEMBER 2016 www.ti.com 10 Power Supply Recommendations The device requires a single unipolar supply, VDD, to power both the analog and digital circuitry of the device. 10.1 Power-Supply Sequencing Wait approximately 50 µs after VDD is stabilized before communicating with the device to allow the power-up reset process to complete. 10.2 Power-Supply Decoupling Good power-supply decoupling is important to achieve optimum performance. VDD must be decoupled with at least a 0.1-µF capacitor, as shown in Figure 32. The 0.1-μF bypass capacitor supplies the momentary bursts of extra current required from the supply when the device is converting. Place the bypass capacitor as close to the power-supply pin of the device as possible using low-impedance connections. Use multilayer ceramic chip capacitors (MLCCs) that offer low equivalent series resistance (ESR) and inductance (ESL) characteristics for power-supply decoupling purposes. For very sensitive systems, or for systems in harsh noise environments, avoid the use of vias for connecting the capacitors to the device pins for better noise immunity. The use of multiple vias in parallel lowers the overall inductance, and is beneficial for connections to ground planes. VDD Device 10 DIN 1 ADDR SDA 9 2 ALERT/RDY VDD 8 3 GND AIN3 7 4 AIN0 AIN2 6 0.1 µF AIN1 5 Figure 32. ADS1015-Q1 Power-Supply Decoupling 34 Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: ADS1013-Q1 ADS1014-Q1 ADS1015-Q1 ADS1013-Q1, ADS1014-Q1, ADS1015-Q1 www.ti.com SBAS511B – JULY 2010 – REVISED DECEMBER 2016 11 Layout 11.1 Layout Guidelines Employ best design practices when laying out a printed-circuit board (PCB) for both analog and digital components. For optimal performance, separate the analog components [such as ADCs, amplifiers, references, digital-to-analog converters (DACs), and analog MUXs] from digital components [such as microcontrollers, complex programmable logic devices (CPLDs), field-programmable gate arrays (FPGAs), radio frequency (RF) transceivers, universal serial bus (USB) transceivers, and switching regulators]. An example of good component placement is shown in Figure 33. Although Figure 33 provides a good example of component placement, the best placement for each application is unique to the geometries, components, and PCB fabrication capabilities employed. That is, there is no single layout that is perfect for every design and careful consideration must always be used when designing with any analog component. Ground Fill or Ground Plane Supply Generation Microcontroller Device Optional: Split Ground Cut Signal Conditioning (RC Filters and Amplifiers) Ground Fill or Ground Plane Optional: Split Ground Cut Ground Fill or Ground Plane Interface Transceiver Connector or Antenna Ground Fill or Ground Plane Figure 33. System Component Placement The following outlines some basic recommendations for the layout of the ADS101x-Q1 to get the best possible performance of the ADC. A good design can be ruined with a bad circuit layout. • • • • • • • Separate analog and digital signals. To start, partition the board into analog and digital sections where the layout permits. Route digital lines away from analog lines. This prevents digital noise from coupling back into analog signals. Fill void areas on signal layers with ground fill. Provide good ground return paths. Signal return currents flow on the path of least impedance. If the ground plane is cut or has other traces that block the current from flowing right next to the signal trace, it has to find another path to return to the source and complete the circuit. If it is forced into a larger path, it increases the chance that the signal radiates. Sensitive signals are more susceptible to EMI interference. Use bypass capacitors on supplies to reduce high-frequency noise. Do not place vias between bypass capacitors and the active device. Placing the bypass capacitors on the same layer as close to the active device yields the best results. Consider the resistance and inductance of the routing. Often, traces for the inputs have resistances that react with the input bias current and cause an added error voltage. Reduce the loop area enclosed by the source signal and the return current in order to reduce the inductance in the path. Reduce the inductance to reduce the EMI pickup, and reduce the high frequency impedance seen by the device. Differential inputs must be matched for both the inputs going to the measurement source. Analog inputs with differential connections must have a capacitor placed differentially across the inputs. Best input combinations for differential measurements use adjacent analog input lines such as AIN0, AIN1 and AIN2, AIN3. The differential capacitors must be of high quality. The best ceramic chip capacitors are C0G (NPO), which have stable properties and low-noise characteristics. Copyright © 2010–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADS1013-Q1 ADS1014-Q1 ADS1015-Q1 35 ADS1013-Q1, ADS1014-Q1, ADS1015-Q1 SBAS511B – JULY 2010 – REVISED DECEMBER 2016 www.ti.com SCL SDA ALERT/RDY ADDR 11.2 Layout Example VDD 1 ADDR 2 ALERT/RDY 3 GND 4 5 SCL 10 SDA 9 VDD 8 AIN0 AIN3 7 AIN1 AIN2 6 AIN3 AIN0 Device AIN2 AIN1 Vias connect to either bottom layer or an internal plane. The bottom layer or internal plane are dedicated GND planes Figure 34. ADS1015-Q1 VSSOP Package 36 Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: ADS1013-Q1 ADS1014-Q1 ADS1015-Q1 ADS1013-Q1, ADS1014-Q1, ADS1015-Q1 www.ti.com SBAS511B – JULY 2010 – REVISED DECEMBER 2016 12 Device and Documentation Support 12.1 Documentation Support 12.1.1 Related Documentation For related documentation see the following: • OPAx333-Q1 1.8-V MICROPOWER CMOS OPERATIONAL AMPLIFIER ZERO-DRIFT SERIES (SBOS522) • MSP430F20x1, MSP430F20x2, MSP430F20x3 Mixed Signal Microcontroller (SLAS491) 12.2 Related Links The following table lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. Table 11. Related Links PARTS PRODUCT FOLDER SAMPLE & BUY TECHNICAL DOCUMENTS TOOLS & SOFTWARE SUPPORT & COMMUNITY ADS1013-Q1 Click here Click here Click here Click here Click here ADS1014-Q1 Click here Click here Click here Click here Click here ADS1015-Q1 Click here Click here Click here Click here Click here 12.3 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 12.4 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 12.5 Trademarks E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 12.6 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 12.7 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. Copyright © 2010–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADS1013-Q1 ADS1014-Q1 ADS1015-Q1 37 ADS1013-Q1, ADS1014-Q1, ADS1015-Q1 SBAS511B – JULY 2010 – REVISED DECEMBER 2016 www.ti.com 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 38 Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: ADS1013-Q1 ADS1014-Q1 ADS1015-Q1 PACKAGE OPTION ADDENDUM www.ti.com 11-Dec-2016 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) ADS1013BQDGSRQ1 ACTIVE VSSOP DGS 10 2500 Green (RoHS & no Sb/Br) CU NIPDAUAG Level-2-260C-1 YEAR -40 to 125 19O6 ADS1014BQDGSRQ1 ACTIVE VSSOP DGS 10 2500 Green (RoHS & no Sb/Br) CU NIPDAUAG Level-2-260C-1 YEAR -40 to 125 19N6 ADS1015AQDGSRQ1 ACTIVE VSSOP DGS 10 2500 Green (RoHS & no Sb/Br) CU NIPDAUAG Level-2-260C-1 YEAR -40 to 125 12WV ADS1015BQDGSRQ1 ACTIVE VSSOP DGS 10 2500 Green (RoHS & no Sb/Br) CU NIPDAUAG Level-2-260C-1 YEAR -40 to 125 19M6 ADS1015QDGSRQ1 ACTIVE VSSOP DGS 10 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 BCMQ (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 11-Dec-2016 (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF ADS1013-Q1, ADS1014-Q1, ADS1015-Q1 : • Catalog: ADS1013, ADS1014, ADS1015 NOTE: Qualified Version Definitions: • Catalog - TI's standard catalog product Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 11-Dec-2016 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant ADS1013BQDGSRQ1 VSSOP DGS 10 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 ADS1014BQDGSRQ1 VSSOP DGS 10 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 ADS1015AQDGSRQ1 VSSOP DGS 10 2500 330.0 12.4 5.3 3.3 1.3 8.0 12.0 Q1 ADS1015BQDGSRQ1 VSSOP DGS 10 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 ADS1015QDGSRQ1 VSSOP DGS 10 2500 330.0 12.4 5.3 3.3 1.3 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 11-Dec-2016 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADS1013BQDGSRQ1 VSSOP DGS 10 2500 366.0 364.0 50.0 ADS1014BQDGSRQ1 VSSOP DGS 10 2500 366.0 364.0 50.0 ADS1015AQDGSRQ1 VSSOP DGS 10 2500 370.0 355.0 55.0 ADS1015BQDGSRQ1 VSSOP DGS 10 2500 366.0 364.0 50.0 ADS1015QDGSRQ1 VSSOP DGS 10 2500 370.0 355.0 55.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily performed. TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional restrictions. Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use of any TI components in safety-critical applications. In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and requirements. Nonetheless, such components are subject to these terms. No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties have executed a special agreement specifically governing such use. Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and regulatory requirements in connection with such use. TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of non-designated products, TI will not be responsible for any failure to meet ISO/TS16949. Products Applications Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers DLP® Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps DSP dsp.ti.com Energy and Lighting www.ti.com/energy Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial Interface interface.ti.com Medical www.ti.com/medical Logic logic.ti.com Security www.ti.com/security Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video RFID www.ti-rfid.com OMAP Applications Processors www.ti.com/omap TI E2E Community e2e.ti.com Wireless Connectivity www.ti.com/wirelessconnectivity Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2016, Texas Instruments Incorporated