DP80C51
Pipelined High Performance
8-bit Microcontroller
ver 4.01
OVERVIEW
DP80C51 is an ultra high performance,
speed optimized soft core of a single-chip 8bit embedded controller dedicated for operation with fast (typically on-chip) and slow (offchip) memories. The core has been designed
with a special concern for performance to
power consumption ratio. This ratio is extended by an advanced power management
unit PMU.
DP80C51 soft core is 100% binary and
pin compatible with the industry standard
8051 8-bit microcontroller. There are two configurations of the DP80C51: Harward, where
external data and program buses are separated, and von Neumann, with common program and external data bus. DP80C51 has
Pipelined RISC architecture up to 10 times
faster compared to standard architecture and
executes 85-200 million instructions per
second. This performance can also be exploited to great advantage in low power applications where the core can be clocked over ten
times more slower than the original implementation for no performance penalty.
DP80C51 is delivered with fully automated testbench and complete set of tests
allowing easy package validation at each stage
of SoC design flow.
All trademarks mentioned in this document
are trademarks of their respective owners.
CPU FEATURES
●
100% pin compatible with industry standard
8051
●
100% software compatible with industry
standard 8051
●
Pipelined RISC architecture enables to
execute instructions up to 10 times faster
compared to standard 8051
●
24 times faster multiplication
●
12 times faster addition
●
Up to 256 bytes of internal (on-chip) Data
Memory
●
Up to 64K bytes of internal (on-chip) or
external (off-chip) Program Memory
●
Up to 64K bytes of external (off-chip) Data
Memory
●
User programmable Program Memory Wait
States solution for wide range of memories
speed
●
User programmable External Data Memory
Wait States solution for wide range of
memories speed
●
Dedicated signal for Program Memory
writes.
●
Interface for additional Special Function
Registers
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●
Fully synthesizable, static synchronous
design with positive edge clocking and no
internal tri-states
●
Scan test ready
●
2.0 GHz virtual clock frequency in a 0.25u
technological process
PERIPHERALS
●
DoCD™ debug unit
○ Processor execution control
Run
Halt
Step into instruction
Skip instruction
○ Read-write all processor contents
Program Counter (PC)
Program Memory
Internal (direct) Data Memory
Special Function Registers (SFRs)
External Data Memory
○ Code execution breakpoints
one real-time PC breakpoint
unlimited number of real-time OPCODE breakpoints
○ Hardware execution watch-point
one at Internal (direct) Data Memory
one at Special Function Registers (SFRs)
one at External Data Memory
○ Hardware watch-points activated at a certain
address by any write into memory
address by any read from memory
address by write into memory a required data
address by read from memory a required data
○ Unlimited number of software watch-points
Internal (direct) Data Memory
Special Function Registers (SFRs)
External Data Memory
○ Unlimited number of software breakpoints
Program Memory(PC)
○ Automatic adjustment of debug data transfer
○
○
○
○
Synchronous mode, fixed baud rate
8-bit asynchronous mode, fixed baud rate
9-bit asynchronous mode, fixed baud rate
9-bit asynchronous mode, variable baud rate
CONFIGURATION
The following parameters of the DP80C51 core
can be easy adjusted to requirements of dedicated application and technology. Configuration of the core can be prepared by effortless
changing appropriate constants in package file.
There is no need to change any parts of the
code.
•
Internal Program Memory
type
- synchronous
- asynchronous
•
Internal Program ROM
Memory size
0 - 64kB
-
•
Internal Program RAM
Memory size
0 - 64kB
subroutines
location
• Interrupts
-
• Power Management Mode
- used
- unused
• Stop mode
- used
- unused
• DoCD™ debug unit
- used
- unused
Besides mentioned above parameters all
available peripherals and external interrupts
can be excluded from the core by changing
appropriate constants in package file.
speed rate between HAD and Silicon
○ JTAG Communication interface
●
Power Management Unit
○ Power management mode
○ Switchback feature
○ Stop mode
●
Interrupt Controller
○ 2 priority levels
○ 2 external interrupt sources
○ 3 interrupt sources from peripherals
●
Four 8-bit I/O Ports
○ Bit addressable data direction for each line
○ Read/write of single line and 8-bit group
●
Two 16-bit timer/counters
○ Timers clocked by internal source
○ Auto reload 8-bit timers
○ Externally gated event counters
●
Full-duplex serial port
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DELIVERABLES
♦ Source code:
◊ VHDL Source Code or/and
◊ VERILOG Source Code or/and
◊ Encrypted, or plain text EDIF netlist
♦ VHDL & VERILOG test bench environment
◊ NCSim automatic simulation macros
◊ ModelSim automatic simulation macros
◊ Active-HDL automatic simulation macros
◊ Tests with reference responses
♦ Technical documentation
◊ Installation notes
◊ HDL core specification
◊ Datasheet
♦ Synthesis scripts
♦ Example application
♦ Technical support
◊ IP Core implementation support
◊ 3 months maintenance
●
●
●
Delivery the IP Core updates, minor and
major versions changes
Delivery the documentation updates
Phone & email support
LICENSING
Comprehensible and clearly defined licensing
methods without royalty fees make using of IP
Core easy and simply.
DESIGN FEATURES
♦
○ ROM located in address range between
0x0000 ÷ (ROMsize-1)
○ RAM located in address range between
(RAMsize-1) ÷ 0xFFFF
External Program Memory can be implemented as ROM or RAM located in address range between ROMsize ÷ RAMsize.
♦
INTERNAL DATA MEMORY:
The DP8C051 can address Internal Data
Memory of up to 256 bytes The Internal
Data Memory can be implemented as Single-Port synchronous RAM.
♦
EXTERNAL DATA MEMORY:
The DP80C51 soft core can address up
to 64 kB of External Data Memory.
♦
USER SPECIAL FUNCTION REGISTERS:
Up to 104 External (user) Special Function Registers (ESFRs) may be added to
the DP80C51 design. ESFRs are memory
mapped into Direct Memory between addresses 0x80 and 0xFF in the same manner as core SFRs and may occupy any address that is not occupied by a core SFR.
♦
WAIT STATES SUPPORT:
The DP80C51 soft core is dedicated for
operation with wide range of Program and
Data memories. Slow Program and External Data memory may assert a memory
WAIT signal to hold up CPU activity for required period of time.
Single Design license allows using IP Core in
single FPGA bitstream and ASIC implementation. It also permits FPGA prototyping before
ASIC production.
Unlimited Designs license allows using IP Core
in unlimited number of FPGA bitstreams and
ASIC implementations.
In all cases number of IP Core instantiations
within a design, and number of manufactured
chips are unlimited. There is no time of use
limitations.
●
PROGRAM MEMORY:
The DP80C51 soft core is dedicated for
operation with Internal and External Program Memory. Internal Program Memory
can be implemented as:
Single Design license for
○ VHDL, Verilog source code called HDL Sour-
ce
○ Encrypted, or plain text EDIF called Netlist
●
Unlimited Designs license for
○ HDL Source
○ Netlist
●
Upgrade from
○ Netlist to HDL Source
○ Single Design to Unlimited Designs
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are trademarks of their respective owners.
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Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved.
SYMBOL
PIN
port0(7:0)
port1(7:0)
port2(7:0)
port3(7:0)
ale
psen
pswr
ea
prgromdatai(7:0)
prgramdatai(7:0)
prgaddr(15:0)
prgdatao(7:0)
prgramwr
ramaddr(7:0)
ramdatao(7:0)
ramwe
ramoe
ramdatai(7:0)
sfraddr(6:0)
sfrdatao(7:0)
sfroe
sfrwe
sfrdatai(7:0)
stop
pmm
tdo
rtck
coderun
debugacs
tdi
tck
tms
reset
clk
rsto
PINS DESCRIPTION
PIN
TYPE
DESCRIPTION
clk
input
Global clock
reset
input
Global reset input
port0[7:0]
bidir
I/O Port 0, multifunctional
Data/LSB address of external memory
port1[7:0]
bidir
I/O Port 1
port2[7:0]
bidir
I/O Port 2, multifunctional
MSB address of external memory
port3[0]
bidir
I/O Port 3.0
Serial receiver input/output port
port3[1]
bidir
I/O Port 3.1
Serial transmitter output port
port3[2]
bidir
I/O Port 3.2, multifunctional
Interrupt 0 input/timer 0 gate
port3[3]
bidir
I/O Port 3.3, multifunctional
Interrupt 1 input/timer 1 gate
port3[4]
bidir
I/O Port 3.4, multifunctional
Timer 0 external clock line
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TYPE
DESCRIPTION
port3[5]
bidir
I/O Port 3.5, multifunctional
Timer 1 external clock line
port3[6]
bidir
I/O Port 3.6
External Data Memory write
port3[7]
bidir
I/O Port 3.7
External Data Memory read
ea
input
Enable all external program memory
prgramdatai[7:0]
input
Data bus from int. RAM prog. memory
prgromdatai[7:0]
input
Data bus from int. ROM prog. memory
ramdatai[7:0]
input
Data bus from internal data memory
sfrdatai[7:0]
input
Data bus from user SFR’s
tdi
input
DoCD™ TAP data input
tck
input
DoCD™ TAP clock input
tms
input
DoCD™ TAP mode select input
rsto
output Reset output
prgaddr[15:0]
output Internal program memory address bus
prgdatao[7:0]
output Data bus for internal program memory
prgramwr
output Internal program memory write
ale
output Address Latch Enable
psen
output Program Store (memory) read Enable
pswr
output Program Store (memory) Write
ramaddr[7:0]
output Internal Data Memory address bus
ramdatao[7:0]
output Data bus for internal data memory
ramoe
output Internal data memory output enable
ramwe
output Internal data memory write enable
sfraddr[6:0]
output Address bus for user SFR’s
sfrdatao[7:0]
output Data bus for user SFR’s
sfroe
output User SFR’s read enable
sfrwe
output User SFR’s write enable
tdo
output DoCD™ TAP data output
rtck
output DoCD™ return clock line
debugacs
output DoCD™ accessing data
coderun
output CPU is executing an instruction
pmm
output Power management mode indicator
stop
output Stop mode indicator
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EEPROM storage via UART, SPI, I2C or
DoCD™ module.
BLOCK DIAGRAM
UART
External Memory Interface - Contains memory access related registers such as Data
Page High (DPH), Data Page Low (DPL). It
performs the external Program and Data
Memory addressing and data transfers. Program fetch cycle length can be programmed by
user. This feature is called Program Memory
Wait States, and allows core to work with different speed program memories.
Interrupt
controller
Internal Data Memory Interface – Internal
Data Memory interface controls access into the
internal 256 bytes memory. It contains 8-bit
Stack Pointer (SP) register and related logic.
Opcode
decoder
I/O Port
registers
prgramdatai(7:0)
prgromdatai(7:0)
prgaddr(15:0)
prgdatao(7:0)
prgramwr
Program
memory
interface
Timers
ea
ale
psen
pswr
External
memory
interface
Control
Unit
ramaddr(7:0)
ramdatao(7:0)
ramdatai(7:0)
ramwe
ramoe
sfraddr(6:0)
sfrdatao(7:0)
sfrdatao(7:0)
sfroe
sfrwe
clk
reset
rsto
Internal
data
memory
interface
Power
Management Unit
DoCD™
Debug Unit
User SFR’s
interface
port0(7:0)
port1(7:0)
port2(7:0)
port3(7:0)
stop
pmm
tdi
tck
tms
tdo
rtck
coderun
debugacs
ALU
UNITS SUMMARY
ALU – Arithmetic Logic Unit performs the
arithmetic and logic operations during execution of an instruction. It contains accumulator
(ACC), Program Status Word (PSW), (B) registers and related logic such as arithmetic unit,
logic unit, multiplier and divider.
Opcode Decoder – Performs an instruction
opcode decoding and the control functions for
all other blocks.
Control Unit – Performs the core synchronization and data flow control. This module is directly connected to Opcode Decoder and
manages execution of all microcontroller tasks.
Program Memory Interface – Contains Program Counter (PC) and related logic. It performs the instructions code fetching. Program
Memory can be also written. This feature allows usage of a small boot loader loading new
program into RAM, EPROM or FLASH
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User SFRs Interface – Special Function Registers interface controls access to the special
registers. It contains standard and used defined registers and related logic. User defined
external devices can be quickly accessed
(read, written, modified) using all direct addressing mode instructions.
Interrupt Controller – Interrupt control module
is responsible for the interrupt manage system
for the external and internal interrupt sources.
It contains interrupt related registers such as
Interrupt Enable (IE), Interrupt Priority (IP) and
(TCON) registers. Note that external pins of
this module are connected to appropriate pins
of P3 port.
Timers – System timers module. Contains two
16 bits configurable timers: Timer 0 (TH0,
TL0), Timer 1 (TH1, TL1) and Timers Mode
(TMOD) registers. In the timer mode, timer
registers are incremented every 12 CLK periods when appropriate timer is enabled. In the
counter mode the timer registers are incremented every falling transition on their corresponding input pins (T0, T1), if gates are
opened (GATE0, GATE1). T0, T1 input pins
are sampled every CLK period. It can be used
as clock sources for UARTs. Note that external
pins of this module are connected to appropriate pins of P3 port.
UART0 – Universal Asynchronous Receiver &
Transmitter module is full duplex, meaning it
can transmit and receive concurrently. Includes
Serial Configuration register (SCON), serial
receiver and transmitter buffer (SBUF) registers. Its receiver is double-buffered, meaning it
can commence reception of a second byte
before a previously received byte has been
read from the receive register. Writing to
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SBUF0 loads the transmit register, and reading
SBUF0 reads a physically separate receive
register. Works in 3 asynchronous and 1 synchronous modes. UART0 can be synchronized
by Timer 1. Note that external pins of this
module are connected to appropriate pins of
P3 port.
Ports - Block contains 8051’s general purpose
I/O ports. Each of port’s pin can be read/write
as a single bit or as a 8-bit bus P0, P1, P2, P3.
The P0, P2, P3 are multifunctional ports. When
used with External memory P0 works as a multiplexed Data/LSB address to memory, and P2
works as a MSB address to external memory,
P3.6 is a write signal and P3.7 is a read signal.
Functionality of port is the same as in legacy
80C51 microcontroller.
Power Management Unit – Block contains
advanced power saving mechanisms with
switchback feature, allowing external clock
control logic to stop clocking (Stop mode) or
run core in lower clock frequency (Power Management Mode) to significantly reduce power
consumption. Switchback feature allows
UARTs, and interrupts to be processed in full
speed mode if enabled. It is very desired when
microcontroller is planned to use in portable
and power critical applications.
DoCD™ Debug Unit – it’s a real-time hardware debugger provides debugging capability
of a whole SoC system. In contrast to other onchip debuggers DoCD™ provides non-intrusive
debugging of running application. It can halt,
run, step into or skip an instruction, read/write
any contents of microcontroller including all
registers, internal, external, program memories, all SFRs including user defined peripherals. Hardware breakpoints can be set and controlled on program memory, internal and external data memories, as well as on SFRs. Hardware breakpoint is executed if any write/read
occurred at particular address with certain data
pattern or without pattern. Two additional pins
CODERUN, DEBUGACS indicate the sate of
the debugger and CPU. CODERUN is active
when CPU is executing an instruction. DEBUGACS pin is active when any access is performed by DoCD™ debugger. The DoCD™
system includes JTAG interface and complete
set of tools to communicate and work with core
in real time debugging. It is built as scalable
unit and some features can be turned off to
save silicon and reduce power consumption. A
special care on power consumption has been
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taken, and when debugger is not used it is
automatically switched in power save mode.
Finally whole debugger is turned off when debug option is no longer used.
PROGRAM CODE SPACE
IMPLEMENTATION
The figure below shows an example Program Memory space implementation in systems with DP80C51 Microcontroller core. The
On-chip Program Memory located in address
space between 0kB and 1kB is typically used
for BOOT code with system initialization functions. This part of the code is typically implemented as ROM. The On-chip Program Memory located in address space between 60kB
and 64kB is typically used for timing critical
part of the code e.g. interrupt subroutines,
arithmetic functions etc. This part of the code is
typically implemented as RAM and can be
loaded by the BOOT code during initialization
phase from Off-chip memory or through RS232
interface from external device. From the two
mentioned above spaces program code is
executed without wait-states and can achieve
a top performance up to 200 million instructions per second (many instructions executed
in one clock cycle). The Off-chip Program
Memory located in address space between
1kB and 60kB is typically used for main code
and constants. This part of the code is usually
implemented as ROM, SRAM or FLASH device. Because of relatively long access time
the program code executed from mentioned
above devices must be fetched with additional
Wait-States. Number of required Wait-States
depends on memory access time and
DP80C51 clock frequency.
0xFFFF
0xF000
On chip Memory
(implemented as RAM)
Off chip Memory
(implemented as ROM,
SRAM or FLASH)
0x0400
0x0000
On-chip Memory
(implemented as ROM)
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In most cases the proper number of WaitStates cycles is between 2-5. The READY pin
can be also dynamically modulated e.g. by
SDRAM controller.
The figure below shows a typical Program
Memories connections in system with
DP80C51 Microcontroller core.
8
prgramdatai
8
prgdatao
prgramwr
On-chip Memory
12
(implemented as RAM)
0 Wait-State access
prgaddr
10
8
prgromdatai
On-chip Memory
(implemented as ROM)
0 Wait-State access
ASIC or FPGA
chip
DP80C51
8
port0
Latch
ale
port2
Off-chip Memory
(implemented as
FLASH, or SRAM)
eg. 2-5 Wait-State
access
8
psen
pswr
The described above implementation should be
treated as an example. All Program Memory
spaces are fully configurable. For timing-critical
applications whole program code can be implemented as on-chip ROM and (or) RAM and
executed without Wait-States, but for some
other applications whole program code can be
implemented as off-chip ROM or FLASH and
executed with required number Wait-State cycles.
PERFORMANCE
The following tables give a survey about the
Core area and performance in Programmable
Logic Devices after Place & Route (CPU features and peripherals have been included):
Device
FLEX10KE
ACEX1K
APEX20K
APEX20KE
APEX20KC
APEX-II
MERCURY
CYCLONE
CYCLONE-II
Speed grade
-1
-1
-1
-1
-7
-7
-5
-6
-6
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STRATIX
STRATIX-II
-5
-3
90 MHz
160 MHz
Core performance in ALTERA® devices
For a user the most important is application
speed improvement. The most commonly used
arithmetic functions and theirs improvement
are shown in table below. Improvement was
computed as {80C51 clock periods} divided by
{DP80C51 clock periods} required to execute
an identical function for code executed from
internal (first column) and external (second
column) program memory. More details are
available in core documentation.
Function
8-bit addition (immediate data)
8-bit addition (direct addressing)
8-bit addition (indirect addressing)
8-bit addition (register addressing)
8-bit subtraction (immediate data)
8-bit subtraction (direct addressing)
8-bit subtraction (indirect addressing)
8-bit subtraction (register addressing)
8-bit multiplication
8-bit division
16-bit addition
16-bit subtraction
16-bit multiplication
32-bit addition
32-bit subtraction
32-bit multiplication
Average speed improvement:
Improvement
9,00
3,00
9,00
3,00
9,00
3,60
12,00
4,00
9,00
3,00
9,00
3,00
9,00
3,60
12,00
4,00
16,00
6,00
9,60
4,80
12,00
4,00
12,00
4,00
13,60
5,47
12,00
4,00
12,00
4,00
12,60
4,89
11,12
4,03
Dhrystone Benchmark Version 2.1 was used to
measure Core performance. The following table gives a survey about the DP80C51 performance in terms of Dhrystone/sec and VAX
MIPS rating for testing code executed from
external (1) and internal (2) program memory.
Device
80C51
80C310
DP80C511
2
DP80C51
Target
STRATIX-II
STRATIX-II
Clock
frequency
12 MHz
33 MHz
150 MHz
150 MHz
Dhry/sec
(VAX MIPS)
268 (0.153)
1550 (0.882)
11525 (6,563)
26220 (14.924)
Core performance in terms of Dhrystones
Fmax
57 MHz
57 MHz
50 MHz
66 MHz
78 MHz
76 MHz
100 MHz
91 MHz
93 MHz
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28000
26000
24000
22000
20000
18000
16000
14000
12000
10000
8000
6000
4000
2000
0
26220
11525
268
1550
80C51 (12MHz)
80C310 (33MHz)
DP80C51 - external program memory (150MHz)
DP80C51 - internal program memory (150MHz)
Area utilized by the each unit of DP80C51 core
in vendor specific technologies is summarized
in table below.
Component
CPU*
Interrupt Controller
Power Management Unit
I/O ports
Timers
UART0
Total area
Area
[LC]
[FFs]
1670
150
10
100
160
210
2300
310
40
5
35
50
60
500
*CPU – consisted of ALU, Opcode Decoder, Control Unit, Program &
Internal & External Memory Interfaces, User SFRs Interface
Core components area utilization in all technologies except
STRATIX-II
Component
CPU*
Interrupt Controller
Power Management Unit
I/O ports
Timers
UART0
Total area
Area
[LC]
[FFs]
1305
115
10
75
125
160
1790
310
40
5
35
50
60
500
*CPU – consisted of ALU, Opcode Decoder, Control Unit, Program &
Internal & External Memory Interfaces, User SFRs Interface
Core components area utilization in STRATIX-II
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1
2
4
4
-
-
-
-
-
Fixed Point
Coprocessor
Floating Point
Coprocessor
2
3
SPI
I\O Ports
1
1
2
Master I2C Bus
Controller
Slave I2C Bus
Controller
UART
2
2
2
Watchdog
Timer/Counters
2
5
15
Compare/Capture
Data Pointers
Interface for
additional SFRs
Power Management Unit
Internal Data Memory
space
External Data Memory
space
External Data / Program
Memory Wait States
Stack space size
off-chip
on-chip ROM
64k 64k 64k 256 256 16M
64k 64k 64k 256 256 16M
64k 64k 64k 256 256 16M
Interrupt levels
10
10
10
Interrupt sources
DP8051CPU
DP8051
DP8051XP
Program
Memory
space
on-chip RAM
Design
Architecture speed grade
The main features of each DP80C51 family member have been summarized in table below. It
gives a briefly member characterization helping user to select the most suitable IP Core for its application. User can specify its own peripheral set (including listed below and the others) and requests
the core modifications.
-
-
DP8051 family of Pipelined High Performance Microcontroller Cores
4
4
-
-
-
-
DP80390 family of Pipelined High Performance Microcontroller Cores
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-
Fixed Point
Coprocessor
Floating Point
Coprocessor
1
2
SPI
I\O Ports
2
3
Master I C Bus
Controller
Slave I2C Bus
Controller
UART
1
1
2
2
Timer/Counters
2
2
2
Watchdog
Data Pointers
2
5
15
Compare/Capture
Interrupt levels
Interface for
additional SFRs
Interrupt sources
64k 64k 8M 256 256 16M
64k 64k 8M 256 256 16M
64k 64k 8M 256 256 16M
Power Management Unit
Internal Data Memory
space
External Data Memory
space
External Data / Program
Memory Wait States
Stack space size
off-chip
10
10
10
on-chip ROM
DP80390CPU
DP80390
DP80390XP
Program
Memory
space
on-chip RAM
Design
Architecture speed grade
The main features of each DP80390 family member have been summarized in table below. It gives
a briefly member characterization helping user to select the most suitable IP Core for its application.
User can specify its own peripheral set (including listed below and the others) and requests the core
modifications.
-
-
CONTACTS
For any modification or special request contact to DCD.
Headquarters:
Wroclawska 94
41-902 Bytom, POLAND
[email protected]
e-mail: [email protected]
tel.
: +48 32 282 82 66
fax
: +48 32 282 74 37
Distributors:
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