TI1 ISO7721-Q1 High-speed, robust emc reinforced dual-channel digital isolator Datasheet

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ISO7720-Q1, ISO7721-Q1
SLLSEU1 – MARCH 2017
ISO772x-Q1 High-Speed, Robust EMC Reinforced Dual-Channel Digital Isolators
1 Features
3 Description
•
•
The ISO772x-Q1 devices are high-performance, dualchannel digital isolators with 5000 VRMS (DW
package) and 3000 VRMS (D package) isolation
ratings per UL 1577. These devices are also certified
by VDE, TUV, CSA, and CQC.
1
•
•
•
•
•
•
•
•
•
•
•
Qualified for Automotive Applications
AEC-Q100 Qualified With the Following Results:
– Device Temperature Grade 1: –40°C to
+125°C Ambient Operating Temperature
Range
– Device HBM ESD Classification Level 3A
– Device CDM ESD Classification Level C6
Signaling Rate: Up to 100 Mbps
Wide Supply Range: 2.25 V to 5.5 V
2.25-V to 5.5-V Level Translation
Default Output High and Low Options
Low Power Consumption, Typical 1.7 mA per
Channel at 1 Mbps
Low Propagation Delay: 11 ns Typical
(5-V Supplies)
High CMTI: ±100 kV/μs Typical
Robust Electromagnetic Compatibility (EMC)
– System-Level ESD, EFT, and Surge Immunity
– Low Emissions
Isolation Barrier Life: >40 Years
Wide-SOIC (DW-16) and Narrow-SOIC (D-8)
Package Options
Safety-Related Certifications:
– VDE Reinforced Insulation according to DIN V
VDE V 0884-10 (VDE V 0884-10):2006-12
– 5000 VRMS (DW) and 3000 VRMS (D) Isolation
Rating per UL 1577
– CSA Component Acceptance Notice 5A, IEC
60950-1 and IEC 60601-1 End Equipment
Standards
– CQC Certification per GB4943.1-2011
– TUV Certification according to EN 60950-1 and
EN 61010-1
– VDE, UL, CSA, and TUV Certifications for DW
Package Complete; All Other Certifications
Planned
2 Applications
•
•
•
•
Hybrid Electric Vehicles
Motor Control
Power Supplies
Solar Inverters
The
ISO772x-Q1
devices
provide
high
electromagnetic immunity and low emissions at low
power consumption, while isolating CMOS or
LVCMOS digital I/Os. Each isolation channel has a
logic input and output buffer separated by a silicon
dioxide (SiO2) insulation barrier. The ISO7720-Q1
device has both channels in the same direction while
the -Q1 device has both channels in the opposite
direction. In the event of input power or signal loss,
the default output is high for devices without suffix F
and low for devices with suffix F. See the Device
Functional Modes section for further details.
Used in conjunction with isolated power supplies,
these devices help prevent noise currents on a data
bus or other circuits from entering the local ground
and interfering with or damaging sensitive circuitry.
Through innovative chip design and layout
techniques, the electromagnetic compatibility of the
ISO772x-Q1 devices has been significantly enhanced
to ease system-level ESD, EFT, surge, and
emissions compliance. The ISO772x-Q1 family of
devices is available in 16-pin SOIC wide-body (DW)
and 8-pin SOIC narrow-body (D) packages.
Device Information(1)
PART NUMBER
ISO7720-Q1
ISO7721-Q1
PACKAGE
BODY SIZE (NOM)
SOIC (D)
4.90 mm × 3.91 mm
SOIC (DW)
10.30 mm × 7.50 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Simplified Schematic
VCCI
Isolation
Capacitor
VCCO
INx
OUTx
GNDI
GNDO
Copyright © 2016, Texas Instruments Incorporated
VCCI and GNDI are supply and ground
connections respectively for the input
channels.
VCCO and GNDO are supply and ground
connections respectively for the output
channels.
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
ISO7720-Q1, ISO7721-Q1
SLLSEU1 – MARCH 2017
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
6.11
6.12
6.13
6.14
6.15
6.16
6.17
6.18
6.19 Typical Characteristics .......................................... 13
1
1
1
2
3
4
7
8
Parameter Measurement Information ................ 15
Detailed Description ............................................ 16
8.1
8.2
8.3
8.4
Absolute Maximum Ratings ..................................... 4
ESD Ratings ............................................................ 4
Recommended Operating Conditions....................... 4
Thermal Information .................................................. 5
Power Ratings........................................................... 5
Insulation Specifications............................................ 6
Safety-Related Certifications..................................... 7
Safety Limiting Values .............................................. 7
Electrical Characteristics—5-V Supply ..................... 8
Supply Current Characteristics—5-V Supply .......... 8
Electrical Characteristics—3.3-V Supply ................ 9
Supply Current Characteristics—3.3-V Supply ....... 9
Electrical Characteristics—2.5-V Supply .............. 10
Supply Current Characteristics—2.5-V Supply ..... 10
Switching Characteristics—5-V Supply................. 11
Switching Characteristics—3.3-V Supply.............. 11
Switching Characteristics—2.5-V Supply.............. 11
Insulation Characteristics Curves ......................... 12
9
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
16
16
17
18
Applications and Implementation ...................... 19
9.1 Application Information............................................ 19
9.2 Typical Application .................................................. 19
10 Power Supply Recommendations ..................... 21
11 Layout................................................................... 21
11.1 Layout Guidelines ................................................. 21
11.2 Layout Example .................................................... 21
12 Device and Documentation Support ................. 22
12.1
12.2
12.3
12.4
12.5
12.6
12.7
Documentation Support ........................................
Related Links ........................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
22
22
22
22
22
22
22
13 Mechanical, Packaging, and Orderable
Information ........................................................... 23
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
2
DATE
REVISION
NOTES
March 2017
*
Initial release.
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5 Pin Configuration and Functions
ISO7720-Q1 DW Package
16-Pin SOIC
Top View
16 GND2
2
15
VCC1
3
INA
4
INB
5
NC
ISOLATION
NC
GND1 1
NC
16 GND2
NC
2
15
14 VCC2
VCC1
3
14 VCC2
13 OUTA
OUTA 4
ISOLATION
GND1 1
ISO7721-Q1 DW Package
16-Pin SOIC
Top View
13
NC
INA
12 OUTB
INB
5
6
11
NC
NC
6
11
NC
GND1 7
10
NC
GND1 7
10
NC
8
9 GND2
NC
8
9 GND2
ISO7720-Q1 D Package
8-Pin SOIC
Top View
1
INA
2
INB
3
ISOLATION
VCC1
ISO7721-Q1 D Package
8-Pin SOIC
Top View
8 VCC2
VCC1
7 OUTA
OUTA 2
6 OUTB
GND1 4
INB
5 GND2
1
3
8 VCC2
ISOLATION
NC
12 OUTB
GND1 4
7
INA
6 OUTB
5 GND2
Pin Functions
PIN
NAME
DW PACKAGE
D PACKAGE
I/O
DESCRIPTION
ISO7720-Q1
ISO7721-Q1
ISO7720-Q1
ISO7721-Q1
1, 7
1, 7
4
4
—
Ground connection for VCC1
9
9
16
16
5
5
—
Ground connection for VCC2
INA
4
13
2
7
I
Input, channel A
INB
5
5
3
3
I
Input, channel B
NC
2, 6, 8, 10, 11,
15
2, 6, 8, 10,
11, 15
—
—
—
Not connected
GND1
GND2
OUTA
13
4
7
2
O
Output, channel A
OUTB
12
12
6
6
O
Output, channel B
VCC1
3
3
1
1
—
Power supply, VCC1
VCC2
14
14
8
8
—
Power supply, VCC2
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6 Specifications
6.1 Absolute Maximum Ratings
See
(1)
.
Supply voltage (2)
VCC1, VCC2
MIN
MAX
–0.5
6
V
Voltage at INx, OUTx
–0.5
IO
Output current
–15
TJ
Junction temperature
Tstg
Storage temperature
(1)
(2)
(3)
VCC + 0.5
–65
UNIT
V
(3)
V
15
mA
150
°C
150
°C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values except differential I/O bus voltages are with respect to the local ground terminal (GND1 or GND2) and are peak
voltage values.
Maximum voltage must not exceed 6 V.
6.2 ESD Ratings
VALUE
Electrostatic
discharge
V(ESD)
(1)
Human-body model (HBM), per AEC Q100-002 (1)
±6000
Charged-device model (CDM), per AEC Q100-011
±1500
UNIT
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
MIN
NOM
UNIT
Supply voltage
VCC(UVLO+)
UVLO threshold when supply voltage is rising
VCC(UVLO-)
UVLO threshold when supply voltage is falling
1.7
1.8
V
VHYS(UVLO)
Supply voltage UVLO hysteresis
100
200
mV
IOH
IOL
High-level output current
Low-level output current
2.25
MAX
VCC1, VCC2
2
VCCO (1) = 5 V
–4
VCCO = 3.3 V
–2
VCCO = 2.5 V
–1
5.5
V
2.25
V
mA
VCCO = 5 V
4
VCCO = 3.3 V
2
VCCO = 2.5 V
1
mA
VIH
High-level input voltage
0.7 × VCCI (1)
VCCI
V
VIL
Low-level input voltage
0
0.3 × VCCI
V
DR
Signaling rate
TA
Ambient temperature
(1)
4
0
–40
25
100
Mbps
125
°C
VCCI = Input-side VCC; VCCO = Output-side VCC.
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6.4 Thermal Information
ISO772x-Q1
THERMAL METRIC (1)
DW (SOIC)
D (SOIC)
16 PINS
8 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
86.5
137.7
°C/W
RθJC(top)
Junction-to-case(top) thermal resistance
49.6
54.9
°C/W
RθJB
Junction-to-board thermal resistance
49.7
71.7
°C/W
ψJT
Junction-to-top characterization parameter
32.3
7.1
°C/W
ψJB
Junction-to-board characterization parameter
49.2
70.7
°C/W
RθJC(bottom)
Junction-to-case(bottom) thermal resistance
n/a
n/a
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Power Ratings
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ISO7720-Q1
PD
Maximum power dissipation
VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF,
input a 50 MHz 50% duty cycle square wave
100
mW
PD1
Maximum power dissipation by side-1
VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF,
input a 50 MHz 50% duty cycle square wave
20
mW
PD2
Maximum power dissipation by side-2
VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF,
input a 50 MHz 50% duty cycle square wave
80
mW
ISO7721-Q1
PD
Maximum power dissipation
VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF,
input a 50 MHz 50% duty cycle square wave
100
mW
PD1
Maximum power dissipation by side-1
VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF,
input a 50 MHz 50% duty cycle square wave
50
mW
PD2
Maximum power dissipation by side-2
VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF,
input a 50 MHz 50% duty cycle square wave
50
mW
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6.6 Insulation Specifications
PARAMETER
CLR
External clearance
VALUE
TEST CONDITIONS
DW-16
D-8
UNIT
(1)
Shortest terminal-to-terminal distance through air
8
4
mm
(1)
Shortest terminal-to-terminal distance across the
package surface
8
4
mm
21
21
μm
>600
>600
V
CPG
External creepage
DTI
Distance through the insulation
Minimum internal gap (internal clearance)
CTI
Comparative tracking index
DIN EN 60112 (VDE 0303-11); IEC 60112; UL 746A
Material group
According to IEC 60664-1
Overvoltage category per IEC 60664-1
I
I
Rated mains voltage ≤ 150 VRMS
I–IV
I–IV
Rated mains voltage ≤ 300 VRMS
I–IV
I–III
Rated mains voltage ≤ 600 VRMS
I–IV
n/a
Rated mains voltage ≤ 1000 VRMS
I–III
n/a
AC voltage (bipolar)
1414
637
VPK
AC voltage; Time dependent dielectric breakdown
(TDDB) test
1000
450
VRMS
DC voltage
1414
637
VDC
8000
4242
VPK
8000
5000
VPK
Method a, After Input/Output safety test subgroup 2/3,
Vini = VIOTM, tini = 60 s; Vpd(m) = 1.2 × VIORM, tm = 10 s
≤5
≤5
Method a, After environmental tests subgroup 1,
Vini = VIOTM, tini = 60 s; Vpd(m) = 1.6 × VIORM, tm = 10 s
≤5
≤5
Method b1; At routine test (100% production) and
preconditioning (type test), Vini = VIOTM, tini = 1 s;
Vpd(m) = 1.875 × VIORM, tm = 1 s
≤5
≤5
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 (2)
VIORM
Maximum repetitive peak isolation
voltage
VIOWM
Maximum working isolation voltage
VIOTM
Maximum transient isolation voltage
VTEST = VIOTM, t = 60 s (qualification);
t = 1 s (100% production)
VIOSM
Maximum surge isolation voltage (3)
Test method per IEC 60065, 1.2/50 µs waveform,
VTEST = 1.6 × VIOSM (qualification)
Apparent charge (4)
qpd
Barrier capacitance, input to output (5)
CIO
Isolation resistance (5)
RIO
pC
VIO = 0.4 × sin (2πft), f = 1 MHz
~0.5
~0.5
VIO = 500 V, TA = 25°C
>1012
>1012
VIO = 500 V, 100°C ≤ TA ≤ 125°C
>1011
>1011
9
9
VIO = 500 V at TS = 150°C
>10
pF
Ω
>10
Pollution degree
2
2
Climatic category
55/125/21
5/125/21
5000
3000
UL 1577
VISO
(1)
(2)
(3)
(4)
(5)
6
Withstanding isolation voltage
VTEST = VISO, t = 60 s(qualification);
VTEST = 1.2 × VISO, t = 1 s (100% production)
VRMS
Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care
should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on
the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in certain cases.
Techniques such as inserting grooves and/or ribs on a printed circuit board are used to help increase these specifications.
This coupler is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured by
means of suitable protective circuits.
Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
Apparent charge is electrical discharge caused by a partial discharge (pd).
All pins on each side of the barrier tied together creating a two-terminal device.
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6.7 Safety-Related Certifications
DW package devices certified according to VDE, CSA, UL, and TUV; All other certifications are planned.
VDE
Certified according to
DIN V VDE V 0884-10
(VDE V 0884-10):200612
CSA
UL
Certified under CSA
Component Acceptance
Notice 5A, IEC 60950-1,
and IEC 60601-1
Reinforced insulation per
CSA 60950-1-07+A1+A2
and IEC 60950-1 2nd Ed.,
Maximum transient
800 VRMS (DW-16) and 400
isolation voltage, 8000
VPK (DW-16, Reinforced) VRMS (D-8) max working
voltage (pollution degree 2,
and 4242 VPK (D-8);
Maximum repetitive peak material group I);
isolation voltage, 1414
VPK (DW-16, Reinforced)
and 637 VPK (D-8);
2 MOPP (Means of Patient
Maximum surge isolation Protection) per CSA 60601voltage, 8000 VPK (DW- 1:14 and IEC 60601-1 Ed.
16, Reinforced) and
3.1, 250 VRMS (DW-16) max
5000 VPK (D-8)
working voltage
Certificate number:
40040142
Master contract number:
220991
Certified according to UL
1577 Component
Recognition Program
CQC
TUV
Certified according to EN
61010-1:2010 (3rd Ed)
Plan to certify according to
and EN 60950GB4943.1-2011
1:2006/A11:2009/A1:2010/
A12:2011/A2:2013
DW-16: Single
protection, 5000 VRMS;
D-8: Single protection,
3000 VRMS
DW-16: Reinforced
Insulation, Altitude ≤ 5000
m, Tropical Climate, 400
VRMS maximum working
voltage;
D-8: Basic Insulation,
Altitude ≤ 5000 m, Tropical
Climate, 250 VRMS
maximum working voltage
File number: E181974
Certification planned
5000 VRMS (DW-16) and
3000 VRMS (D-8)
Reinforced insulation per
EN 61010-1:2010 (3rd Ed)
up to working voltage of
600 VRMS (DW-16) and
300 VRMS (D-8)
5000 VRMS (DW-16) and
3000 VRMS (D-8)
Reinforced insulation per
EN 609501:2006/A11:2009/A1:2010/
A12:2011/A2:2013 up to
working voltage of 800
VRMS (DW-16) and 400
VRMS (D-8)
Client ID number: 77311
6.8 Safety Limiting Values
Safety limiting intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry. A failure of
the I/O can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to overheat
the die and damage the isolation barrier potentially leading to secondary system failures.
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
DW-16 PACKAGE
IS
Safety input, output, or supply
current
PS
Safety input, output, or total
power
TS
Maximum safety temperature
RθJA = 86.5 °C/W, VI = 5.5 V, TJ = 150°C, TA = 25°C, see Figure 1
263
RθJA = 86.5 °C/W, VI = 3.6 V, TJ = 150°C, TA = 25°C, see Figure 1
401
RθJA = 86.5 °C/W, VI = 2.75 V, TJ = 150°C, TA = 25°C, see Figure 1
525
RθJA = 86.5 °C/W, TJ = 150°C, TA = 25°C, see Figure 2
mA
1445
mW
150
°C
D-8 PACKAGE
IS
Safety input, output, or supply
current
PS
Safety input, output, or total
power
TS
Maximum safety temperature
RθJA = 137.7 °C/W, VI = 5.5 V, TJ = 150°C, TA = 25°C, see Figure 3
165
RθJA = 137.7 °C/W, VI = 3.6 V, TJ = 150°C, TA = 25°C, see Figure 3
252
RθJA = 137.7 °C/W, VI = 2.75 V, TJ = 150°C, TA = 25°C, see Figure 3
330
RθJA = 137.7 °C/W, TJ = 150°C, TA = 25°C, see Figure 4
908
mW
150
°C
mA
The maximum safety temperature is the maximum junction temperature specified for the device. The power
dissipation and junction-to-air thermal impedance of the device installed in the application hardware determines
the junction temperature. The assumed junction-to-air thermal resistance in the Thermal Information is that of a
device installed on a high-K test board for leaded surface-mount packages. The power is the recommended
maximum input voltage times the current. The junction temperature is then the ambient temperature plus the
power times the junction-to-air thermal resistance.
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6.9 Electrical Characteristics—5-V Supply
VCC1 = VCC2 = 5 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
VCCO (1) –
0.4
4.8
VOH
High-level output voltage
IOH = –4 mA; see Figure 13
VOL
Low-level output voltage
IOL = 4 mA; see Figure 13
VIT+(IN)
Rising input threshold voltage
VIT-(IN)
Falling input threshold voltage
0.3 x VCCI
0.4 x VCCI
VI(HYS)
Input threshold voltage hysteresis
0.1 × VCCI
0.2 × VCCI
IIH
High-level input current
VIH = VCCI (1) at INx
IIL
Low-level input current
VIL = 0 V at INx
CMTI
Common-mode transient
immunity
VI = VCCI or 0 V, VCM = 1200 V; see Figure 15
CI
Input Capacitance (2)
VI = VCC/ 2 + 0.4×sin(2πft), f = 1 MHz, VCC = 5 V
(1)
(2)
MAX
V
0.2
0.4
V
0.6 x VCCI
0.7 x VCCI
V
V
V
10
–10
85
UNIT
μA
µA
100
kV/μs
2
pF
VCCI = Input-side VCC; VCCO = Output-side VCC.
Measured from input pin to ground.
6.10 Supply Current Characteristics—5-V Supply
VCC1 = VCC2 = 5 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER
SUPPLY
CURRENT
TEST CONDITIONS
MIN
TYP
MAX
ICC1
0.8
1.1
ICC2
1.1
1.7
ICC1
2.9
4.2
ICC2
1.2
1.9
ICC1
1.8
2.7
ICC2
1.3
1.9
ICC1
1.9
2.7
ICC2
2.2
3
ICC1
2.5
3.2
ICC2
11.6
14
UNIT
ISO7720-Q1
VI = VCCI (ISO7720-Q1), VI = 0 V (ISO7720-Q1 with F suffix)
Supply current - DC signal
VI = 0 V (ISO7720-Q1), VI = VCCI (ISO7720-Q1 with F suffix)
1 Mbps
Supply current - AC signal
All channels switching with square
wave clock input; CL = 15 pF
10 Mbps
100 Mbps
mA
ISO7721-Q1
Supply current - DC signal
Supply current - AC signal
8
VI = VCCI (ISO7721-Q1),
VI = 0 V (ISO7721-Q1 with F suffix)
ICC1, ICC2
1
1.6
VI = 0 V (ISO7721-Q1),
VI = VCCI (ISO7721-Q1 with F suffix)
ICC1, ICC2
2.2
3.2
1 Mbps
ICC1, ICC2
1.7
2.4
10 Mbps
ICC1, ICC2
2.2
3
100 Mbps
ICC1, ICC2
7.3
9
All channels switching with square
wave clock input; CL = 15 pF
mA
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6.11 Electrical Characteristics—3.3-V Supply
VCC1 = VCC2 = 3.3 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
VCCO (1) – 0.3
3.2
VOH
High-level output voltage
IOH = –2 mA; see Figure 13
VOL
Low-level output voltage
IOL = 2 mA; see Figure 13
VIT+(IN)
Rising input voltage threshold
VIT-(IN)
Falling input voltage threshold
0.3 x VCCI
0.4 x VCCI
VI(HYS)
Input threshold voltage hysteresis
0.1 × VCCI
0.2 × VCCI
IIH
High-level input current
VIH = VCCI (1) at INx
IIL
Low-level input current
VIL = 0 V at INx
CMTI
Common-mode transient immunity
VI = VCCI or 0 V, VCM = 1200 V; see Figure 15
(1)
MAX
UNIT
V
0.1
0.3
V
0.6 x VCCI
0.7 x VCCI
V
V
V
10
–10
μA
µA
85
100
kV/μs
MIN
TYP
MAX
ICC1
0.8
1.1
ICC2
1.1
1.7
ICC1
2.9
4.2
ICC2
1.2
1.9
ICC1
1.8
2.7
ICC2
1.2
1.9
ICC1
1.9
2.7
ICC2
1.9
2.6
ICC1
2.2
3.1
ICC2
8.6
11
VCCI = Input-side VCC; VCCO = Output-side VCC.
6.12 Supply Current Characteristics—3.3-V Supply
VCC1 = VCC2 = 3.3 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER
SUPPLY
CURRENT
TEST CONDITIONS
UNIT
ISO7720-Q1
VI = VCCI (ISO7720-Q1), VI = 0 V (ISO7720-Q1 with F suffix)
Supply current - DC signal
VI = 0 V (ISO7720-Q1), VI = VCCI (ISO7720-Q1 with F suffix)
1 Mbps
Supply current - AC signal
All channels switching with square wave
clock input; CL = 15 pF
10 Mbps
100 Mbps
mA
ISO7721-Q1
Supply current - DC signal
Supply current - AC signal
VI = VCCI (ISO7721-Q1), VI = 0 V (ISO7721-Q1 with F suffix)
ICC1, ICC2
1
1.6
VI = 0 V (ISO7721-Q1), VI = VCCI (ISO7721-Q1 with F suffix)
ICC1, ICC2
2.2
3.2
1 Mbps
ICC1, ICC2
1.6
2.4
10 Mbps
ICC1, ICC2
2
2.8
100 Mbps
ICC1, ICC2
5.6
7
All channels switching with square wave
clock input; CL = 15 pF
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6.13 Electrical Characteristics—2.5-V Supply
VCC1 = VCC2 = 2.5 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
VCCO (1) – 0.2
2.45
VOH
High-level output voltage
IOH = –1 mA; see Figure 13
VOL
Low-level output voltage
IOL = 1 mA; see Figure 13
VIT+(IN)
Rising input voltage threshold
VIT-(IN)
Falling input voltage threshold
0.3 x VCCI
0.4 x VCCI
VI(HYS)
Input threshold voltage hysteresis
0.1 × VCCI
0.2 × VCCI
IIH
High-level input current
VIH = VCCI (1) at INx
IIL
Low-level input current
VIL = 0 V at INx
CMTI
Common-mode transient immunity
VI = VCCI or 0 V, VCM = 1200 V; see Figure 15
(1)
MAX
V
0.05
0.2
V
0.6 x VCCI
0.7 x VCCI
V
V
V
10
–10
85
UNIT
μA
μA
100
kV/μs
VCCI = Input-side VCC; VCCO = Output-side VCC.
6.14 Supply Current Characteristics—2.5-V Supply
VCC1 = VCC2 = 2.5 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
SUPPLY CURRENT
MIN
TYP
MAX
UNIT
ISO7720-Q1
VI = VCCI (ISO7720-Q1), VI = 0 V (ISO7720-Q1 with F
suffix)
ICC1
0.8
1.1
ICC2
1.1
1.7
VI = 0 V (ISO7720-Q1), VI = VCCI (ISO7720-Q1 with F
suffix)
ICC1
2.9
4.2
ICC2
1.2
1.9
ICC1
1.8
2.7
ICC2
1.3
1.9
ICC1
1.9
2.7
ICC2
1.7
2.4
ICC1
2.2
3
ICC2
6.8
9
Supply current - DC signal
1 Mbps
Supply current - AC signal
All channels switching with square
wave clock input; CL = 15 pF
10 Mbps
100 Mbps
mA
ISO7721-Q1
Supply current - DC signal
Supply current - AC signal
10
VI = VCCI (ISO7721-Q1), VI = 0 V (ISO7721-Q1 with F
suffix)
ICC1, ICC2
1
1.6
VI = 0 V (ISO7721-Q1), VI = VCCI (ISO7721-Q1 with F
suffix)
ICC1, ICC2
2.2
3.2
1 Mbps
ICC1, ICC2
1.6
2.4
10 Mbps
ICC1, ICC2
1.9
2.7
100 Mbps
ICC1, ICC2
4.6
6
All channels switching with square
wave clock input; CL = 15 pF
mA
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6.15 Switching Characteristics—5-V Supply
VCC1 = VCC2 = 5 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
tPLH, tPHL
Propagation delay time
PWD
Pulse width distortion (1) |tPHL – tPLH|
tsk(o)
Channel-to-channel output skew time (2)
tsk(pp)
Part-to-part skew time (3)
tr
Output signal rise time
tf
Output signal fall time
MAX
11
16
ns
0.5
4.9
ns
4
ns
4.5
ns
1.8
3.9
ns
1.9
3.9
ns
0.1
0.3
μs
Same direction channels
See Figure 13
tDO
Default output delay time from input power loss
tie
Time interval error
216 – 1 PRBS data at 100 Mbps
(3)
TYP
6
See Figure 13
Measured from the time VCC goes below 1.7
V. See Figure 14
(1)
(2)
MIN
1
UNIT
ns
Also known as pulse skew.
tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical loads.
tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
6.16 Switching Characteristics—3.3-V Supply
VCC1 = VCC2 = 3.3 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
tPLH, tPHL
Propagation delay time
PWD
Pulse width distortion (1) |tPHL – tPLH|
tsk(o)
Channel-to-channel output skew time (2)
tsk(pp)
Part-to-part skew time (3)
tr
Output signal rise time
tf
Output signal fall time
See Figure 13
MAX
11
16
ns
0.5
5
ns
4.1
ns
4.5
ns
0.7
3
ns
0.7
3
ns
0.1
0.3
μs
See Figure 13
tDO
Default output delay time from input power loss
tie
Time interval error
216 – 1 PRBS data at 100 Mbps
(3)
TYP
6
Same direction channels
Measured from the time VCC goes
below 1.7 V. See Figure 14
(1)
(2)
MIN
1
UNIT
ns
Also known as pulse skew.
tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical loads.
tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
6.17 Switching Characteristics—2.5-V Supply
VCC1 = VCC2 = 2.5 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER
tPLH, tPHL
Propagation delay time
PWD
Pulse width distortion (1) |tPHL – tPLH|
TEST CONDITIONS
See Figure 13
tsk(o)
Channel-to-channel output skew time
tsk(pp)
Part-to-part skew time (3)
tr
Output signal rise time
tf
Output signal fall time
tDO
tie
(1)
(2)
(3)
(2)
Time interval error
TYP
MAX
UNIT
7.5
12
18.5
ns
0.5
5.1
ns
4.1
ns
4.6
ns
1
3.5
ns
1
3.5
ns
0.1
0.3
μs
Same direction channels
See Figure 13
Default output delay time from input power loss
MIN
Measured from the time VCC goes
below 1.7 V. See Figure 14
16
2
– 1 PRBS data at 100 Mbps
1
ns
Also known as pulse skew.
tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical loads.
tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
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6.18 Insulation Characteristics Curves
1600
VCC1 = VCC2 = 2.75 V
VCC1 = VCC2 = 3.6 V
VCC1 = VCC2 = 5.5 V
500
1400
Safety Limiting Current (mA)
Safety Limiting Current (mA)
600
400
300
200
100
800
600
400
0
0
50
100
150
Ambient Temperature (qC)
0
200
50
D001
Figure 1. Thermal Derating Curve for Limiting Current per
VDE for DW-16 Package
100
150
Ambient Temperature (qC)
200
D002
Figure 2. Thermal Derating Curve for Limiting Power per
VDE for DW-16 Package
350
1000
VCC1 = VCC2 = 2.75 V
VCC1 = VCC2 = 3.6 V
VCC1 = VCC2 = 5.5 V
900
Safety Limiting Current (mA)
300
Safety Limiting Current (mA)
1000
200
0
250
200
150
100
50
800
700
600
500
400
300
200
100
0
0
0
50
100
150
Ambient Temperature (qC)
200
0
50
D003
Figure 3. Thermal Derating Curve for Limiting Current per
VDE for D-8 Package
12
1200
100
150
Ambient Temperature (qC)
200
D004
Figure 4. Thermal Derating Curve for Limiting Power per
VDE for D-8 Package
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6.19 Typical Characteristics
5
14
ICC1 at 2.5 V
ICC2 at 2.5 V
ICC1 at 3.3 V
ICC1 at 2.5 V
ICC2 at 2.5 V
ICC1 at 3.3 V
4.5
4
10
Supply Current (mA)
Supply Current (mA)
12
ICC2 at 3.3 V
ICC1 at 5 V
ICC2 at 5 V
8
6
4
ICC2 at 3.3 V
ICC1 at 5 V
ICC2 at 5 V
3.5
3
2.5
2
1.5
1
2
0.5
0
0
0
25
50
Data Rate (Mbps)
TA = 25°C
75
0
100
CL = 15 pF
50
Data Rate (Mbps)
TA = 25°C
Figure 5. ISO7720-Q1 Supply Current vs Data Rate
(With 15-pF Load)
75
100
D006
CL = No Load
Figure 6. ISO7720-Q1 Supply Current vs Data Rate
(With No Load)
4
9
ICC1, ICC2 at 2.5 V
ICC1, ICC2 at 3.3 V
ICC1, ICC2 at 5 V
8
ICC1, ICC2 at 2.5 V
ICC1, ICC2 at 3.3 V
ICC1, ICC2 at 5 V
3.5
Supply Current (mA)
7
Supply Current (mA)
25
D005
6
5
4
3
2
3
2.5
2
1.5
1
0.5
1
0
0
0
25
TA = 25°C
50
Data Rate (Mbps)
75
0
100
25
D007
CL = 15 pF
TA = 25°C
Figure 7. ISO7721-Q1 Supply Current vs Data Rate
(With 15-pF Load)
50
Data Rate (Mbps)
75
100
D008
CL = No Load
Figure 8. ISO7721-Q1 Supply Current vs Data Rate
(With No Load)
6
0.9
Low-Level Output Voltage (V)
High-Level Output Voltage (V)
0.8
5
4
3
2
VCC at 2.5 V
VCC at 3.3 V
VCC at 5 V
1
0
-15
0.7
0.6
0.5
0.4
0.3
0.2
VCC at 2.5 V
VCC at 3.3 V
VCC at 5 V
0.1
0
-10
-5
High-Level Output Current (mA)
0
0
5
10
Low-Level Output Current (mA)
D011
TA = 25°C
15
D012
TA = 25°C
Figure 9. High-Level Output Voltage vs High-level
Output Current
Figure 10. Low-Level Output Voltage vs Low-Level
Output Current
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Typical Characteristics (continued)
14
Propagation Delay Time (ns)
Power Supply UVLO Threshold (V)
2.1
2.05
2
1.95
1.9
1.85
1.8
1.75
1.7
VCC1+
VCC1-
1.65
1.6
-55
-25
5
35
65
Free-Air Temperature (qC)
12
11
10
tPLH at 2.5 V
tPHL at 2.5 V
tPLH at 3.3 V
9
VCC2+
VCC295
125
8
-55
-25
D011
Figure 11. Power Supply Undervoltage Threshold vs
Free-Air Temperature
14
13
5
35
65
Free Air Temperature (qC)
tPHL at 3.3 V
tPLH at 5 V
tPHL at 5 V
95
125
D012
Figure 12. Propagation Delay Time vs Free-Air Temperature
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7 Parameter Measurement Information
Isolation Barrier
IN
Input Generator
(See Note A)
VI
VCCI
VI
OUT
50%
50%
0V
tPLH
CL
See Note B
VO
50
tPHL
VOH
90%
50%
VO
50%
10%
VOL
tf
tr
A.
The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3
ns, tf ≤ 3 ns, ZO = 50 Ω. At the input, 50 Ω resistor is required to terminate Input Generator signal. It is not needed in
actual application.
B.
CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 13. Switching Characteristics Test Circuit and Voltage Waveforms
VI
See Note B
VCC
VCC
Isolation Barrier
IN = 0 V (Devices without suffix F)
IN = VCC (Devices with suffix F)
VI
IN
1.7 V
0V
OUT
VO
tDO
CL
See Note A
default high
VOH
50%
VO
VOL
default low
A.
CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
B.
Power Supply Ramp Rate = 10 mV/ns
Figure 14. Default Output Delay Time Test Circuit and Voltage Waveforms
VCCI
VCCO
S1
Isolation Barrier
C = 0.1 µF ±1%
IN
C = 0.1 µF ±1%
Pass-fail criteria:
The output must
remain stable.
OUT
+
EN
CL
See Note A
GNDI
A.
+
VCM ±
VOH or VOL
±
GNDO
CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 15. Common-Mode Transient Immunity Test Circuit
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8 Detailed Description
8.1 Overview
The ISO772x-Q1 family of devices has an ON-OFF keying (OOK) modulation scheme to transmit the digital data
across a silicon dioxide based isolation barrier. The transmitter sends a high frequency carrier across the barrier
to represent one digital state and sends no signal to represent the other digital state. The receiver demodulates
the signal after advanced signal conditioning and produces the output through a buffer stage. These devices also
incorporate advanced circuit techniques to maximize the CMTI performance and minimize the radiated emissions
due the high frequency carrier and IO buffer switching. The conceptual block diagram of a digital capacitive
isolator, Figure 16, shows a functional block diagram of a typical channel.
8.2 Functional Block Diagram
Transmitter
TX IN
Receiver
OOK
Modulation
TX Signal
Conditioning
Oscillator
SiO2 based
Capacitive
Isolation
Barrier
RX Signal
Conditioning
Envelope
Detection
RX OUT
Emissions
Reduction
Techniques
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Figure 16. Conceptual Block Diagram of a Digital Capacitive Isolator
Figure 17 shows a conceptual detail of how the OOK scheme works.
TX IN
Carrier signal through
isolation barrier
RX OUT
Figure 17. On-Off Keying (OOK) Based Modulation Scheme
16
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8.3 Feature Description
The ISO772x-Q1 family of devices is available in two channel configurations and default output state options to
enable a variety of application uses. Table 1 lists the device features of the ISO772x-Q1 devices.
Table 1. Device Features
PART NUMBER
MAXIMUM DATA
RATE
CHANNEL
DIRECTION
DEFAULT OUTPUT
STATE
ISO7720-Q1
100 Mbps
2 Forward, 0 Reverse
High
ISO7720-Q1 with F
suffix
100 Mbps
2 Forward, 0 Reverse
Low
ISO7721-Q1
ISO7721-Q1 with F
suffix
(1)
100 Mbps
100 Mbps
1 Forward, 1 Reverse
1 Forward, 1 Reverse
High
Low
PACKAGE
RATED ISOLATION (1)
DW-16
5000 VRMS / 8000 VPK
D-8
3000 VRMS / 4242 VPK
DW-16
5000 VRMS / 8000 VPK
D-8
3000 VRMS / 4242 VPK
DW-16
5000 VRMS / 8000 VPK
D-8
3000 VRMS / 4242 VPK
DW-16
5000 VRMS / 8000 VPK
D-8
3000 VRMS / 4242 VPK
See the Safety-Related Certifications section for detailed isolation ratings.
8.3.1 Electromagnetic Compatibility (EMC) Considerations
Many applications in harsh industrial environment are sensitive to disturbances such as electrostatic discharge
(ESD), electrical fast transient (EFT), surge and electromagnetic emissions. These electromagnetic disturbances
are regulated by international standards such as IEC 61000-4-x and CISPR 22. Although system-level
performance and reliability depends, to a large extent, on the application board design and layout, the ISO772xQ1 family of devices incorporates many chip-level design improvements for overall system robustness. Some of
these improvements include:
• Robust ESD protection cells for input and output signal pins and inter-chip bond pads.
• Low-resistance connectivity of ESD cells to supply and ground pins.
• Enhanced performance of high voltage isolation capacitor for better tolerance of ESD, EFT and surge events.
• Bigger on-chip decoupling capacitors to bypass undesirable high energy signals through a low impedance
path.
• PMOS and NMOS devices isolated from each other by using guard rings to avoid triggering of parasitic
SCRs.
• Reduced common mode currents across the isolation barrier by ensuring purely differential internal operation.
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8.4 Device Functional Modes
Table 2 lists the functional modes for the ISO772x-Q1 devices.
Table 2. Function Table (1)
VCCI
VCCO
PU
(1)
(2)
(3)
INPUT
(INx) (2)
OUTPUT
(OUTx)
H
H
L
L
Open
Default
Default mode: When INx is open, the corresponding channel output goes to the
default high logic state. The default is High for ISO772x-Q1 and Low for
ISO772x-Q1 with F suffix.
Default mode: When VCCI is unpowered, a channel output assumes the logic
state based on the selected default option. The default is High for ISO772x-Q1
and Low for ISO772x-Q1 with F suffix.
When VCCI transitions from unpowered to powered-up, a channel output
assumes the logic state of the input.
When VCCI transitions from powered-up to unpowered, channel output assumes
the selected default state.
COMMENTS
Normal Operation:
A channel output assumes the logic state of the input.
PU
PD
PU
X
Default
X
PD
X
Undetermined
When VCCO is unpowered, a channel output is undetermined (3).
When VCCO transitions from unpowered to powered-up, a channel output
assumes the logic state of the input
VCCI = Input-side VCC; VCCO = Output-side VCC; PU = Powered up (VCC ≥ 2.25 V); PD = Powered down (VCC ≤ 1.7 V); X = Irrelevant; H
= High level; L = Low level
A strongly driven input signal can weakly power the floating VCC via an internal protection diode and cause undetermined output.
The outputs are in undetermined state when 1.7 V < VCCI, VCCO < 2.25 V.
8.4.1 Device I/O Schematics
Input (Devices without F suffix)
VCCI
VCCI
VCCI
Input (Devices with F suffix)
VCCI
VCCI
VCCI
VCCI
1.5 M
985
985
INx
INx
1.5 M
Output
VCCO
~20
OUTx
Figure 18. Device I/O Schematics
18
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9 Applications and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant the accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The ISO772x-Q1 devices are high-performance, dual-channel digital isolators. The devices use single-ended
CMOS-logic switching technology. The supply voltage range is from 2.25 V to 5.5 V for both supplies, VCC1 and
VCC2. When designing with digital isolators, keep in mind that because of the single-ended design structure,
digital isolators do not conform to any specific interface standard and are only intended for isolating single-ended
CMOS or TTL digital signal lines. The isolator is typically placed between the data controller (that is, μC or
UART), and a data converter or a line transceiver, regardless of the interface type or standard.
9.2 Typical Application
The ISO7721-Q1 device can be used with Texas Instruments' Piccolo™ microcontroller, CAN transceiver,
transformer driver, and voltage regulator to create an isolated CAN interface.
VS
3.3 V
0.1 F
2
VCC D2 3
1:1.33
MBR0520L
1
SN6501-Q1
GND D1
10 F
0.1 F
IN
OUT
5
10 F
TPS76333-Q1
3
1
EN
GND
3.3VISO
2
10 F
MBR0520L
4, 5
ISO Barrier
0.1 F
0.1 F
0.1 F
1
29,57
VCC1
VDDIO
CANRXA 26
TMS320F28035PAGQ
CANTXA
25
VSS
2
8
GND1
3
VCC2
VCC
INA 7
4
6
1
OUTA
ISO7721-Q1
3
OUTB
INB
4
6,28
0.1 F
GND2
5
RS 8
R
D
CANH
SN65HVD231Q
CANL
10
(optional)
10
(optional)
7
6
Vref 5
GND
SM712
2
4.7 nF /
2 kV
Copyright © 2017, Texas Instruments Incorporated
Figure 19. Isolated 4-mA to 20-mA Current Loop
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Typical Application (continued)
9.2.1 Design Requirements
To design with these devices, use the parameters listed in Table 3.
Table 3. Design Parameters
PARAMETER
VALUE
Supply voltage, VCC1 and VCC2
2.25 V to 5.5 V
Decoupling capacitor between VCC1 and GND1
0.1 µF
Decoupling capacitor from VCC2 and GND2
0.1 µF
9.2.2 Detailed Design Procedure
Unlike optocouplers, which require external components to improve performance, provide bias, or limit current,
the ISO772x-Q1 devices only require two external bypass capacitors to operate.
VCC1
VCC2
GND1 1
GND1
16 GND2
GND2
0.1 µF
0.1 µF
NC
2
15
NC
VCC1
3
14 VCC2
GND2
OUTA
OUTA 4
INB
ISOLATION
GND1
13
INA
INA
INB
5
12 OUTB
NC
6
11
NC
GND1 7
10
NC
OUTB
GND1
NC
8
9 GND2
GND2
Figure 20. Typical ISO7721-Q1 Circuit Hook-up
9.2.3 Application Curve
1 V/ div
1 V/ div
The following typical eye diagrams of the ISO772x-Q1 family of devices indicate low jitter and wide open eye at
the maximum data rate of 100 Mbps.
Time = 3.5 ns / div
Time = 3.5 ns / div
Figure 21. ISO7720-Q1 Eye Diagram at 100 Mbps PRBS,
5-V Supplies and 25°C
20
Figure 22. ISO7721-Q1 Eye Diagram at 100 Mbps PRBS,
5-V Supplies and 25°C
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10 Power Supply Recommendations
To help ensure reliable operation at data rates and supply voltages, a 0.1-μF bypass capacitor is recommended
at the input and output supply pins (VCC1 and VCC2). The capacitors should be placed as close to the supply pins
as possible. If only a single primary-side power supply is available in an application, isolated power can be
generated for the secondary-side with the help of a transformer driver such as Texas Instruments' SN6501-Q1.
For such applications, detailed power supply design and transformer selection recommendations are available in
SN6501-Q1 Transformer Driver for Isolated Power Supplies.
11 Layout
11.1 Layout Guidelines
A minimum of four layers is required to accomplish a low EMI PCB design (see Figure 23). Layer stacking should
be in the following order (top-to-bottom): high-speed signal layer, ground plane, power plane and low-frequency
signal layer.
• Routing the high-speed traces on the top layer avoids the use of vias (and the introduction of their
inductances) and allows for clean interconnects between the isolator and the transmitter and receiver circuits
of the data link.
• Placing a solid ground plane next to the high-speed signal layer establishes controlled impedance for
transmission line interconnects and provides an excellent low-inductance path for the return current flow.
• Placing the power plane next to the ground plane creates additional high-frequency bypass capacitance of
approximately 100 pF/in2.
• Routing the slower speed control signals on the bottom layer allows for greater flexibility as these signal links
usually have margin to tolerate discontinuities such as vias.
If an additional supply voltage plane or signal layer is needed, add a second power or ground plane system to
the stack to keep it symmetrical. This makes the stack mechanically stable and prevents it from warping. Also the
power and ground plane of each power system can be placed closer together, thus increasing the high-frequency
bypass capacitance significantly.
For detailed layout recommendations, refer to the Digital Isolator Design Guide.
11.1.1 PCB Material
For digital circuit boards operating at less than 150 Mbps, (or rise and fall times greater than 1 ns), and trace
lengths of up to 10 inches, use standard FR-4 UL94V-0 printed circuit board. This PCB is preferred over cheaper
alternatives because of lower dielectric losses at high frequencies, less moisture absorption, greater strength and
stiffness, and the self-extinguishing flammability-characteristics.
11.2 Layout Example
High-speed traces
10 mils
Ground plane
40 mils
Keep this
space free
from planes,
traces, pads,
and vias
FR-4
0r ~ 4.5
Power plane
10 mils
Low-speed traces
Figure 23. Layout Example
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation, see the following:
• Digital Isolator Design Guide
• Isolation Glossary
• SN6501-Q1 Transformer Driver for Isolated Power Supplies
• SN65HVD231Q 3.3-V CAN Transceivers
• TPS763xx-Q1 Low-Power, 150-mA, Low-Dropout Linear Regulators
• TMS320F2803x Piccolo™ Microcontrollers
12.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 4. Related Links
PARTS
PRODUCT FOLDER
ORDER NOW
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
ISO7720-Q1
Click here
Click here
Click here
Click here
Click here
ISO7721-Q1
Click here
Click here
Click here
Click here
Click here
12.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.5 Trademarks
Piccolo, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
12.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
22
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13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OUTLINE
D0008B
SOIC - 1.75 mm max height
SCALE 2.800
SOIC
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
A
.004 [0.1] C
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.150
[3.81]
.189-.197
[4.81-5.00]
NOTE 3
4
5
B
.150-.157
[3.81-3.98]
NOTE 4
8X .012-.020
[0.31-0.51]
.010 [0.25]
C A
B
.069 MAX
[1.75]
.005-.010 TYP
[0.13-0.25]
SEE DETAIL A
.010
[0.25]
.004-.010
[ 0.11 -0.25]
0 -8
.016-.050
[0.41-1.27]
DETAIL A
.041
[1.04]
TYPICAL
4221445/B 04/2014
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15], per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
24
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EXAMPLE BOARD LAYOUT
D0008B
SOIC - 1.75 mm max height
SOIC
8X (.061 )
[1.55]
SEE
DETAILS
SYMM
8X (.055)
[1.4]
SEE
DETAILS
SYMM
1
1
8
8X (.024)
[0.6]
8
SYMM
8X (.024)
[0.6]
5
4
6X (.050 )
[1.27]
SYMM
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
(.217)
[5.5]
HV / ISOLATION OPTION
.162 [4.1] CLEARANCE / CREEPAGE
IPC-7351 NOMINAL
.150 [3.85] CLEARANCE / CREEPAGE
LAND PATTERN EXAMPLE
SCALE:6X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL
.0028 MAX
[0.07]
ALL AROUND
.0028 MIN
[0.07]
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4221445/B 04/2014
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
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ISO7720-Q1, ISO7721-Q1
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EXAMPLE STENCIL DESIGN
D0008B
SOIC - 1.75 mm max height
SOIC
8X (.061 )
[1.55]
8X (.055)
[1.4]
SYMM
SYMM
1
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
8
SYMM
8X (.024)
[0.6]
5
4
6X (.050 )
[1.27]
SYMM
5
4
(.217)
[5.5]
(.213)
[5.4]
HV / ISOLATION OPTION
.162 [4.1] CLEARANCE / CREEPAGE
IPC-7351 NOMINAL
.150 [3.85] CLEARANCE / CREEPAGE
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.127 MM] THICK STENCIL
SCALE:6X
4221445/B 04/2014
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
26
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ISO7720-Q1, ISO7721-Q1
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SLLSEU1 – MARCH 2017
PACKAGE OUTLINE
DW0016B
SOIC - 2.65 mm max height
SCALE 1.500
SOIC
C
10.63
TYP
9.97
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
14X 1.27
16
1
2X
8.89
10.5
10.1
NOTE 3
8
9
0.51
0.31
0.25
C A
16X
7.6
7.4
NOTE 4
B
2.65 MAX
B
0.33
TYP
0.10
SEE DETAIL A
0.25
GAGE PLANE
0.3
0.1
0 -8
1.27
0.40
DETAIL A
(1.4)
TYPICAL
4221009/B 07/2016
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.
5. Reference JEDEC registration MS-013.
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EXAMPLE BOARD LAYOUT
DW0016B
SOIC - 2.65 mm max height
SOIC
SYMM
SYMM
16X (2)
16X (1.65)
SEE
DETAILS
1
SEE
DETAILS
1
16
16
16X (0.6)
16X (0.6)
SYMM
SYMM
14X (1.27)
14X (1.27)
9
8
9
8
R0.05 TYP
R0.05 TYP
(9.75)
(9.3)
HV / ISOLATION OPTION
8.1 mm CLEARANCE/CREEPAGE
IPC-7351 NOMINAL
7.3 mm CLEARANCE/CREEPAGE
LAND PATTERN EXAMPLE
SCALE:4X
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4221009/B 07/2016
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
28
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ISO7720-Q1, ISO7721-Q1
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SLLSEU1 – MARCH 2017
EXAMPLE STENCIL DESIGN
DW0016B
SOIC - 2.65 mm max height
SOIC
SYMM
SYMM
16X (1.65)
16X (2)
1
1
16
16
16X (0.6)
16X (0.6)
SYMM
SYMM
14X (1.27)
14X (1.27)
9
8
9
8
R0.05 TYP
R0.05 TYP
(9.3)
(9.75)
IPC-7351 NOMINAL
7.3 mm CLEARANCE/CREEPAGE
HV / ISOLATION OPTION
8.1 mm CLEARANCE/CREEPAGE
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:4X
4221009/B 07/2016
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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29
PACKAGE OPTION ADDENDUM
www.ti.com
6-May-2017
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
ISO7720FQDQ1
PREVIEW
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
7720FQ
ISO7720FQDRQ1
PREVIEW
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
7720FQ
ISO7720FQDWQ1
ACTIVE
SOIC
DW
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ISO7720FQ
ISO7720FQDWRQ1
ACTIVE
SOIC
DW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ISO7720FQ
ISO7720QDQ1
PREVIEW
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
7720Q
ISO7720QDRQ1
PREVIEW
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
7720Q
ISO7720QDWQ1
ACTIVE
SOIC
DW
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ISO7720Q
ISO7720QDWRQ1
ACTIVE
SOIC
DW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ISO7720Q
ISO7721FQDQ1
PREVIEW
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
7721FQ
ISO7721FQDRQ1
PREVIEW
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
7721FQ
ISO7721FQDWQ1
ACTIVE
SOIC
DW
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ISO7721FQ
ISO7721FQDWRQ1
ACTIVE
SOIC
DW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ISO7721FQ
ISO7721QDQ1
PREVIEW
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
7721Q
ISO7721QDRQ1
PREVIEW
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
7721Q
ISO7721QDWQ1
ACTIVE
SOIC
DW
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ISO7721Q
ISO7721QDWRQ1
ACTIVE
SOIC
DW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ISO7721Q
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
6-May-2017
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF ISO7720-Q1, ISO7721-Q1 :
• Catalog: ISO7720, ISO7721
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
31-Mar-2017
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
ISO7720FQDWRQ1
SOIC
DW
16
2000
330.0
16.4
10.75
10.7
2.7
12.0
16.0
Q1
ISO7720QDWRQ1
SOIC
DW
16
2000
330.0
16.4
10.75
10.7
2.7
12.0
16.0
Q1
ISO7721FQDWRQ1
SOIC
DW
16
2000
330.0
16.4
10.75
10.7
2.7
12.0
16.0
Q1
ISO7721QDWRQ1
SOIC
DW
16
2000
330.0
16.4
10.75
10.7
2.7
12.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
31-Mar-2017
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
ISO7720FQDWRQ1
SOIC
DW
16
2000
367.0
367.0
38.0
ISO7720QDWRQ1
SOIC
DW
16
2000
367.0
367.0
38.0
ISO7721FQDWRQ1
SOIC
DW
16
2000
367.0
367.0
38.0
ISO7721QDWRQ1
SOIC
DW
16
2000
367.0
367.0
38.0
Pack Materials-Page 2
IMPORTANT NOTICE
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semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers
should obtain the latest relevant information before placing orders and should verify that such information is current and complete.
TI’s published terms of sale for semiconductor products (http://www.ti.com/sc/docs/stdterms.htm) apply to the sale of packaged integrated
circuit products that TI has qualified and released to market. Additional terms may apply to the use or sale of other types of TI products and
services.
Reproduction of significant portions of TI information in TI data sheets is permissible only if reproduction is without alteration and is
accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such reproduced
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different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the
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Buyers and others who are developing systems that incorporate TI products (collectively, “Designers”) understand and agree that Designers
remain responsible for using their independent analysis, evaluation and judgment in designing their applications and that Designers have
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consequences of failures, (2) monitor failures and their consequences, and (3) lessen the likelihood of failures that might cause harm and
take appropriate actions. Designer agrees that prior to using or distributing any applications that include TI products, Designer will
thoroughly test such applications and the functionality of such TI products as used in such applications.
TI’s provision of technical, application or other design advice, quality characterization, reliability data or other services or information,
including, but not limited to, reference designs and materials relating to evaluation modules, (collectively, “TI Resources”) are intended to
assist designers who are developing applications that incorporate TI products; by downloading, accessing or using TI Resources in any
way, Designer (individually or, if Designer is acting on behalf of a company, Designer’s company) agrees to use any particular TI Resource
solely for this purpose and subject to the terms of this Notice.
TI’s provision of TI Resources does not expand or otherwise alter TI’s applicable published warranties or warranty disclaimers for TI
products, and no additional obligations or liabilities arise from TI providing such TI Resources. TI reserves the right to make corrections,
enhancements, improvements and other changes to its TI Resources. TI has not conducted any testing other than that specifically
described in the published documentation for a particular TI Resource.
Designer is authorized to use, copy and modify any individual TI Resource only in connection with the development of applications that
include the TI product(s) identified in such TI Resource. NO OTHER LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE
TO ANY OTHER TI INTELLECTUAL PROPERTY RIGHT, AND NO LICENSE TO ANY TECHNOLOGY OR INTELLECTUAL PROPERTY
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other intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information
regarding or referencing third-party products or services does not constitute a license to use such products or services, or a warranty or
endorsement thereof. Use of TI Resources may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
TI RESOURCES ARE PROVIDED “AS IS” AND WITH ALL FAULTS. TI DISCLAIMS ALL OTHER WARRANTIES OR
REPRESENTATIONS, EXPRESS OR IMPLIED, REGARDING RESOURCES OR USE THEREOF, INCLUDING BUT NOT LIMITED TO
ACCURACY OR COMPLETENESS, TITLE, ANY EPIDEMIC FAILURE WARRANTY AND ANY IMPLIED WARRANTIES OF
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INCLUDING BUT NOT LIMITED TO ANY INFRINGEMENT CLAIM THAT RELATES TO OR IS BASED ON ANY COMBINATION OF
PRODUCTS EVEN IF DESCRIBED IN TI RESOURCES OR OTHERWISE. IN NO EVENT SHALL TI BE LIABLE FOR ANY ACTUAL,
DIRECT, SPECIAL, COLLATERAL, INDIRECT, PUNITIVE, INCIDENTAL, CONSEQUENTIAL OR EXEMPLARY DAMAGES IN
CONNECTION WITH OR ARISING OUT OF TI RESOURCES OR USE THEREOF, AND REGARDLESS OF WHETHER TI HAS BEEN
ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
Unless TI has explicitly designated an individual product as meeting the requirements of a particular industry standard (e.g., ISO/TS 16949
and ISO 26262), TI is not responsible for any failure to meet such industry standard requirements.
Where TI specifically promotes products as facilitating functional safety or as compliant with industry functional safety standards, such
products are intended to help enable customers to design and create their own applications that meet applicable functional safety standards
and requirements. Using products in an application does not by itself establish any safety features in the application. Designers must
ensure compliance with safety-related requirements and standards applicable to their applications. Designer may not use any TI products in
life-critical medical equipment unless authorized officers of the parties have executed a special contract specifically governing such use.
Life-critical medical equipment is medical equipment where failure of such equipment would cause serious bodily injury or death (e.g., life
support, pacemakers, defibrillators, heart pumps, neurostimulators, and implantables). Such equipment includes, without limitation, all
medical devices identified by the U.S. Food and Drug Administration as Class III devices and equivalent classifications outside the U.S.
TI may expressly designate certain products as completing a particular qualification (e.g., Q100, Military Grade, or Enhanced Product).
Designers agree that it has the necessary expertise to select the product with the appropriate qualification designation for their applications
and that proper product selection is at Designers’ own risk. Designers are solely responsible for compliance with all legal and regulatory
requirements in connection with such selection.
Designer will fully indemnify TI and its representatives against any damages, costs, losses, and/or liabilities arising out of Designer’s noncompliance with the terms and provisions of this Notice.
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