TI1 ADC0817 Adc0816/adc0817 8-bit î¼p compatible a/d converters with16-channel multiplexer Datasheet

ADC0816, ADC0817
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SNAS527C – JUNE 1999 – REVISED MARCH 2013
ADC0816/ADC0817 8-Bit μP Compatible A/D Converters
with16-Channel Multiplexer
Check for Samples: ADC0816, ADC0817
FEATURES
1
•
•
23
•
•
•
•
•
•
•
•
•
•
Easy interface to all microprocessors
Operates ratiometrically or with 5 VDC or
analog span adjusted voltage reference
16-channel multiplexer with latched control
logic
Outputs meet TTL voltage level specifications
0V to 5V analog input voltage range with
single 5V supply
No zero or full-scale adjust required
Standard hermetic or molded 40-pin MDIP
package
Temperature range −40°C to +85°Cor −55°C to
+125°C
Latched TRI-STATE output
Direct access to “comparator in” and
“multiplexer out” for signal conditioning
ADC0816 equivalent to MM74C948
ADC0817 equivalent to MM74C948-1
KEY SPECIFICATIONS
•
•
•
•
•
Resolution ........................8 Bits
Total Unadjusted Error....±½ LSB and ±1
Single Supply....................5 VDC
Low Power........................15 mW
Conversion Time..............100 µs
DESCRIPTION
The ADC0816, ADC0817 data acquisition component
is a monolithic CMOS device with an 8-bit analog-todigital
converter,16-channel
multiplexer
and
microprocessor compatible control logic. The 8-bit
A/D converter uses successive approximation as the
conversion technique. The converter features a high
impedance chopper stabilized comparator, a 256R
voltage divider with analog switch tree and a
successive approximation register. The 16-channel
multiplexer can directly access any one of 16-singleended analog signals, and provides the logic for
additional channel expansion. Signal conditioning of
any analog input signal is eased by direct access to
the multiplexer output, and to the input of the 8-bit
A/D converter.
The device eliminates the need for external zero and
full-scale
adjustments.
Easy
interfacing
to
microprocessors is provided by the latched and
decoded multiplexer address inputs and latched TTL
TRI-STATE®outputs.
The design of the ADC0816, ADC0817 has been
optimized by incorporating the most desirable aspects
of several A/D conversion techniques. The
ADC0816,ADC0817 offers high speed, high
accuracy,
minimal
temperature
dependence,
excellent long-term accuracy and repeatability, and
consumes minima lpower. These features make this
device ideally suited to applications from process and
machine control to consumer and automotive
applications. For similar performance in an 8-channel,
28-pin, 8-bit A/D converter, see the ADC0808,
ADC0809 data sheet. (See AN-258 for more
information.)
1
2
3
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
TRI-STATE is a registered trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1999–2013, Texas Instruments Incorporated
ADC0816, ADC0817
SNAS527C – JUNE 1999 – REVISED MARCH 2013
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Block Diagram
Connection Diagram
Dual-In-Line Package
See Package Number NJF0040A
2
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Absolute Maximum Ratings
Supply Voltage (VCC)
(1) (2)
(3)
6.5V
−0.3V to (VCC+0.3V)
Voltage at Any Pin
Except Control Inputs
−0.3V to 15V
Voltage at Control Inputs
(START, OE, CLOCK, ALE, EXPANSION CONTROL,
ADD A, ADD B, ADD C, ADD D)
−65°C to +150°C
Storage Temperature Range
Package Dissipation at TA = 25°C
875 mW
Lead Temp. (Soldering, 10 seconds)
Dual-In-Line Package (Plastic)
260°C
Molded Chip Carrier Package
Vapor Phase (60seconds)
215°C
Infrared (15 seconds)
220°C
ESD Susceptibility
(1)
(2)
(3)
(4)
(4)
400V
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not
apply when operating the device beyond its specified operating conditions.
All voltages are measured with respect to GND, unless otherwise specified.
A Zener diode exists, internally, from VCC to GND and has a typical breakdown voltage of 7 VDC.
Human body model, 100 pF discharged through a 1.5 kΩ resistor.
Operating Conditions
Temperature Range
(1)
(2)
TMIN≤TA≤TMAX
−40°C≤TA≤+85°C
ADC0816CCN, ADC0817CCN
Range of VCC (2)
4.5 VDC to 6.0VDC
Voltage at Any Pin
0V to VCC
Except Control Inputs
Voltage at Control Inputs
0V to 15V
(START,OE, CLOCK, ALE, EXPANSION CONTROL,
ADD A, ADD B, ADD C, ADDD)
(1)
(2)
All voltages are measured with respect to GND, unless otherwise specified.
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not
apply when operating the device beyond its specified operating conditions.
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Electrical Characteristics
Converter Specifications: VCC = 5 VDC = VREF(+), VREF(−)= GND, VIN = VCOMPARATOR IN,TMIN ≤ TMAX and fCLK = 640 kHz unless
otherwise stated.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
ADC0816
Total Unadjusted Error
25°C
±½
LSB
(1)
TMIN to TMAX
±¾
LSB
Total Unadjusted Error
0°C to 70°C
±1
LSB
(1)
TMIN to TMAX
±1¼
LSB
VCC + 0.1
VDC
VCC
VCC+0.1
V
VCC/2
VCC/2 + 0.1
See Note
ADC0817
See Note
VREF(+)
Input Resistance
From Ref(+)to Ref(−)
Analog Input Voltage Range
V(+) or V(−)
Voltage, Top of Ladder
Measured at Ref(+)
1.0
(2)
GND − 0.1
VCC/2 − 0.1
Voltage, Center of Ladder
VREF(−)
(1)
(2)
(3)
4
Voltage, Bottom of Ladder
Measured at Ref(−)
Comparator Input Current
fc = 640 kHz,
4.5
(3)
−0.1
0
−2
±0.5
kΩ
V
V
2
µA
Total unadjusted error includes offset, full-scale, and linearity errors. See Figure 3. None of these A/Ds requires a zero or full-scale
adjust. However, if an all zero code is desired for an analog input other than 0.0V,or if a narrow full-scale span exists (for example: 0.5V
to 4.5V full-scale)the reference voltages can be adjusted to achieve this. See Figure 13.
Two on-chip diodes are tied to each analog input which will forward conduct for analog input voltages one diode drop below ground or
one diode drop greater than the VCCsupply. The spec allows 100 mV forward bias of either diode. This means that as long as the analog
VIN does not exceed the supply voltage by more than 100 mV, the output code will be correct. To achieve an absolute0 VDC to 5 VDC
input voltage range will therefore require a minimum supply voltage of 4.900 VDC over temperature variations, initial tolerance and
loading.
Comparator input current is a bias current into or out of the chopper stabilized comparator. The bias current varies directly with clock
frequency and has little temperature dependence (Figure 6).
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Electrical Characteristics
Digital Levels and DC Specifications: ADC0816CCN, ADC0817CCN—4.75V ≤ VCC ≤ 5.25V, −40°C ≤ TA ≤ +85°C unless
otherwise noted.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
1.5
ANALOG MULTIPLEXER
(Any Selected Channel)
RON
ΔRON
Analog Multiplexer ON Resistance
ΔON Resistance Between Any 2
Channels
TA = 25°C, RL= 10k
3
kΩ
TA = 85°C
6
kΩ
TA = 125°C
9
kΩ
(Any Selected Channel)
RL=10k
Ω
75
VCC= 5V, VIN= 5V,
IOFF+
OFF Channel Leakage Current
TA = 25°C
10
TMIN to TMAX
200
nA
1.0
μA
VCC = 5V, VIN = 0,
IOFF(−)
OFF Channel Leakage Current
TA = 25°C
−200
nA
TMIN to TMax
−1.0
μA
VCC − 1.5
V
CONTROL INPUTS
VIN(1)
Logical “1”Input Voltage
VIN(0)
Logical “0”Input Voltage
IIN(1)
Logical “1”Input Current
(The Control Inputs)
VIN = 15V
IIN(0)
Logical “0”Input Current
(The Control Inputs)
VIN = 0
ICC
Supply Current
fCLK = 640 kHz
1.5
V
1.0
μA
−1.0
μA
0.3
3.0
mA
DATA OUTPUTS AND EOC (INTERRUPT)
VOUT(1)
Logical “1”Output Voltage
IO = −360 μA, TA = 85°C
IO = −300 μA, TA = 125°C
VOUT(0)
Logical “0”Output Voltage
IO = 1.6 mA
0.45
VOUT(0)
Logical “0”Output Voltage EOC
IO = 1.2 mA
0.45
V
VO = VCC
3.0
μA
IOUT
TRI-STATE Output Current
VCC − 0.4
VO = 0
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−3.0
V
V
μA
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Electrical Characteristics
Timing Specifications:VCC = VREF(+) = 5V, VREF(−) = GND, tr = tf = 20 ns and TA = 25°C unless otherwise noted.
Symbol
Parameter
Conditions
Min
(1)
Typ
Max
Units
tWS
Minimum Start Pulse Width
(Figure 5)
100
200
ns
tWALE
Minimum ALE Pulse Width
(Figure 5)
100
200
ns
ts
Minimum Address Set-Up Time
(Figure 5)
25
50
ns
TH
Minimum Address Hold Time
(Figure 5)
25
50
ns
tD
Analog MUX Delay Time
from ALE
RS= OΩ (Figure 5)
1
2.5
μs
tH1, tH0
OE Control to Q Logic State
CL= 50 pF, RL= 10k (Figure 8)
125
250
ns
t1H, t0H
OE Control to Hi-Z
CL= 10 pF, RL= 10k (Figure 8)
tC
Conversion Time
fc=640 kHz, (Figure 5)
fc
Clock Frequency
tEOC
EOC Delay Time
(Figure 5)
CIN
Input Capacitance
At Control Inputs
COUT
TRI-STATE Output
Capacitance
At TRI-STATE Outputs
(1)
(2)
(2)
125
250
ns
90
100
116
μs
10
640
1280
kHz
8 + 2μs
Clock
Periods
10
15
pF
10
15
pF
0
(2)
If start pulse is asynchronous with converter clock or if fc > 640 kHz, the minimum start pulse width is 8clock periods plus 2 μs. For
synchronous operation at fc ≤640 kHz take start high within 100 ns of clock going low.
The outputs of the data register are updated one clock cycle before the rising edge of EOC.
Functional Description
Multiplexer: The device contains a 16-channel single-ended analog signal multiplexer. A particular input channel
is selected by using the address decoder. Table 1 shows the input states for the address line and the expansion
control line to select any channel. The address is latched into the decoder on the low-to-high transition of the
address latch enable signal.
Table 1. Inputs States for the Address line
Address Line (1)
Selected
AnalogChannel
(1)
6
Expansion
D
C
B
A
Control
IN0
L
L
L
L
H
IN1
L
L
L
H
H
IN2
L
L
H
L
H
IN3
L
L
H
H
H
IN4
L
H
L
L
H
IN5
L
H
L
H
H
IN6
L
H
H
L
H
IN7
L
H
H
H
H
IN8
H
L
L
L
H
IN9
H
L
L
H
H
IN10
H
L
H
L
H
IN11
H
L
H
H
H
IN12
H
H
L
L
H
IN13
H
H
L
H
H
IN14
H
H
H
L
H
IN15
H
H
H
H
H
All Channels OFF
X
X
X
X
L
X = don't care
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Additional single-ended analog signals can be multiplexed to the A/D converter by disabling all the multiplexer
inputs using the expansion control. The additional external signals are connected to the comparator input and the
device ground. Additional signal conditioning (i.e., prescaling, sample and hold, instrumentation amplification,
etc.) may also be added between the analog input signal and the comparator input.
CONVERTER CHARACTERISTICS
The Converter
The heart of this single chip data acquisition system is its8-bit analog-to-digital converter. The converter is
designed to give fast, accurate, and repeatable conversions over a wide range of temperatures. The converter is
partitioned into 3 major sections: the 256R ladder network, the successive approximation register, and the
comparator. The converter's digital outputs are positive true.
The 256R ladder network approach Figure 1 was chosen over the conventional R/2R ladder because of its
inherent monotonicity, which specifies no missing digital codes. Monotonicity is particularly important in closed
loop feedback control systems. A non-monotonic relationship can cause oscillations that will be catastrophic for
the system. Additionally, the 256R network does not cause load variations on the reference voltage.
The bottom resistor and the top resistor of the ladder networking Figure 1 are not the same value as the
remainder of the network. The difference in these resistors causes the output characteristic to be symmetrical
with the zero and full-scale points of the transfer curve. The first output transition occurs when the analog signal
has reached + ½ LSB and succeeding output transitions occur every 1 LSB later up to full-scale.
Figure 1. Resistor Ladder and Switch Tree
Figure 2. 3-Bit A/D Transfer Curve
Figure 3. 3-Bit A/D Absolute Accuracy Curve
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Figure 4. Typical Error Curve
Timing Diagram
Figure 5.
The successive approximation register (SAR) performs 8 iterations to approximate the input voltage. For any
SAR type converter, n-iterations are required for an n-bit converter. Figure 2 shows a typical example of a 3-bit
converter. In the ADC0816,ADC0817, the approximation technique is extended to 8 bits using the 256Rnetwork.
The A/D converter's successive approximation register (SAR)is reset on the positive edge of the start conversion
(SC) pulse. The conversion is begun on the falling edge of the start conversion pulse. A conversion in process
will be interrupted by receipt of a new start conversion pulse. Continuous conversion may be accomplished by
tying the end-of-conversion(EOC) output to the SC input. If used in this mode, an external start conversion pulse
should be applied after power up. End-of-conversion will go low between 0 and 8 clock pulses after the rising
edge of start conversion.
The most important section of the A/D converter is the comparator. It is this section which is responsible for the
ultimate accuracy of the entire converter. It is also the comparator drift which has the greatest influence on the
repeatability of the device. A chopper-stabilized comparator provides the most effective method of satisfying all
the converter requirements.
The chopper-stabilized comparator converts the DC input signal into an AC signal. This signal is then fed through
a high gain AC amplifier and has the DC level restored. This technique limits the drift component of the amplifier
since the drift is a DC component which is not passed by the AC amplifier. This makes the entire A/D converter
extremely insensitive to temperature, long term drift and input offset errors.
Figure 4 shows a typical error curve for the ADC0816 as measured using the procedures outlined in AN-179.
8
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Typical Performance Characteristics
Figure 6. Comparator IIN vs. VIN
(VCC = VREF = 5V)
Figure 7. Multiplexer RON vs. VIN
(VCC = VREF = 5V)
spacer
TRI-STATE Test Circuits and Timing Diagrams
Figure 8.
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APPLICATION INFORMATION
OPERATION
Ratiometric Conversion
The ADC0816, ADC0817 is designed as a complete Data Acquisition System (DAS) for ratiometric conversion
systems. In ratiometric systems, the physical variable being measured is expressed as a percentage of full-scale
which is not necessarily related to an absolute standard. The voltage input to the ADC0816 is expressed by the
equation
(1)
Where:
VIN = Input voltage into the ADC0816
Vfs = Full-scale voltage
VZ = Zero voltage
DX = Data point being measured
DMAX = Maximum data limit
DMIN = Minimum data limit
A good example of a ratiometric transducer is a potentiometer used as a position sensor. The position of the
wiper is directly proportional to the output voltage which is a ratio of the full-scale voltage across it. Since the
data is represented as a proportion of full-scale, reference requirements are greatly reduced, eliminating a large
source of error and cost for many applications. A major advantage of the ADC0816, ADC0817 is that the input
voltage range is equal to the supply range so the transducers can be connected directly across the supply and
their outputs connected directly into the multiplexer inputs, (Figure 9).
Ratiometric transducers such as potentiometers, strain gauges, thermistor bridges, pressure transducers, etc.,
are suitable for measuring proportional relationships; however, many types of measurements must be referred to
an absolute standard such as voltage or current. This means a system reference must be used which relates the
full-scale voltage to the standard volt. For example, if VCC = VREF = 5.12V, then the full-scale range is divided into
256 standard steps. The smallest standard step is 1 LSB which is then 20 mV.
Resistor Ladder Limitations
The voltages from the resistor ladder are compared to the selected input 8 times in a conversion. These voltages
are coupled to the comparator via an analog switch tree which is referenced to the supply. The voltages at the
top, center and bottom of the ladder must be controlled to maintain proper operation.
The top of the ladder, Ref(+), should not be more positive than the supply, and the bottom of the ladder, Ref(−),
should not be more negative than ground. The center of the ladder voltage must also be near the center of the
supply because the analog switch tree changes from N-channel switches to P-channel switches. These
limitations are automatically satisfied in ratiometric systems and can be easily met in ground referenced systems.
Figure 10 shows a ground referenced system with a separate supply and reference. In this system, the supply
must be trimmed to match the reference voltage. For instance, if a5.12V reference is used, the supply should be
adjusted to the same voltage within 0.1V.
10
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Figure 9. Ratiometric Conversion System
The ADC0816 needs less than a milliamp of supply current so developing the supply from the reference is
readily accomplished. In Figure 11 a ground references system is shown which generates the supply from the
reference. The buffer shown can be an op amp of sufficient drive to supply the milliamp of supply current and the
desired bus drive, or if a capacitive bus is driven by the outputs a large capacitor will supply the transient supply
current as seen in Figure 12. The LM301 is overcompensated to insure stability when loaded by the 10 μF output
capacitor.
The top and bottom ladder voltages cannot exceed VCCand ground, respectively, but they can be symmetrically
less than VCC and greater than ground. The center of the ladder voltage should always be near the center of the
supply. The sensitivity of the converter can be increased, (i.e., size of the LSB steps decreased) by using a
symmetrical reference system. In Figure 13, a2.5V reference is symmetrically centered about VCC/2 since the
same current flows in identical resistors. This system with a 2.5V reference allows the LSB to be half the size of
the LSB in a 5V reference system.
Figure 10. Ground Referenced Conversion System Using Trimmed Supply
Figure 11. Ground Referenced Conversion System with Reference Generating VCC Supply
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Figure 12. Typical Reference and Supply Circuit
Figure 13. Symmetrically Centered Reference
Converter Equations
The transition between adjacent codes N and N + 1 is given by:
(2)
The center of an output code N is given by:
(3)
The output code N for an arbitrary input are the integers within the range:
(4)
where: VIN = Voltage at comparator input
VREF = Voltage at Ref(+)
VREF = Voltage at Ref(−)
VTUE = Total unadjusted error voltage(typically
VREF(+) ÷512)
12
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Analog Comparator Inputs
The dynamic comparator input current is caused by the periodic switching of on-chip stray capacitances These
are connected alternately to the output of the resistor ladder/switch tree network and to the comparator input as
part of the operation of the chopper stabilized comparator.
The average value of the comparator input current varies directly with clock frequency and with VIN as shown in
Figure 6.
If no filter capacitors are used at the analog or comparator inputs and the signal source impedances are low, the
comparator input current should not introduce converter errors, as the transient created by the capacitance
discharge will die out before the comparator output is strobed.
If input filter capacitors are desired for noise reduction and signal conditioning they will tend to average out the
dynamic comparator input current. It will then take on the characteristics of a DC bias current whose effect can
be predicted conventionally. See AN-258 for further discussion.
Typical Application
*Address latches needed for 8085 and SC/MP interfacing theADC0816, 17 to a microprocessor
Microprocessor Interface Table
PROCESSOR
READ
WRITE
INTERRUPT(COMMENT)
8080
MEMR
MEMW
INTR (Thru RST Circuit)
8085
RD
WR
INTR (Thru RST Circuit)
Z-80
RD
WR
INT (Thru RST Circuit, Mode 0)
SC/MP
NRDS
NWDS
SA (Thru Sense A)
6800
VMA•φ2•R/W
VMA•Q2•R/W
IRQA or IRQB (Thru PIA)
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REVISION HISTORY
Changes from Revision B (March 2013) to Revision C
•
14
Page
Changed layout of National Data Sheet to TI format .......................................................................................................... 13
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PACKAGE OPTION ADDENDUM
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1-Nov-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
ADC0816CCN
NRND
PDIP
NFJ
40
9
TBD
Call TI
Call TI
-40 to 85
ADC0816CCN
ADC0816CCN/NOPB
ACTIVE
PDIP
NFJ
40
9
Green (RoHS
& no Sb/Br)
SN
Level-1-NA-UNLIM
-40 to 85
ADC0816CCN
ADC0817CCN
NRND
PDIP
NFJ
40
9
TBD
Call TI
Call TI
-40 to 85
ADC0817CCN
ADC0817CCN/NOPB
ACTIVE
PDIP
NFJ
40
9
Green (RoHS
& no Sb/Br)
SN
Level-1-NA-UNLIM
-40 to 85
ADC0817CCN
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
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