ON MC10E167 5v ecl 6â bit 2:1 muxâ registe Datasheet

MC10E167
5 V ECL 6‐Bit 2:1
MUX‐Register
Description
The MC10E167 contains six 2:1 multiplexers followed by D
flip-flops with single-ended outputs. Input data are selected by the
Select control, SEL. The selected data are transferred to the flip-flop
outputs by a positive edge on CLK1 or CLK2 (or both). A HIGH on
the Master Reset (MR) pin asynchronously forces all Q outputs LOW.
The 100 Series contains temperature compensation.
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Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
1000 MHz Min. Operating Frequency
800 ps Max. Clock to Output
Single-Ended Outputs
Asynchronous Master Resets
Dual Clocks
PECL Mode Operating Range: VCC = 4.2 V to 5.7 V
with VEE = 0 V
NECL Mode Operating Range: VCC = 0 V
with VEE = −4.2 V to −5.7 V
Internal Input 50 kW Pulldown Resistors
ESD Protection:
♦ > 2 kV Human Body Model
♦ > 200 V Machine Model
♦ > 2 kV Charged Device Model
Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
Moisture Sensitivity: Level 3 (Pb-Free)
(For Additional Information, see Application Note AND8003/D)
Flammability Rating: UL 94 V−0 @ 0.125 in,
Oxygen Index: 28 to 34
Transistor Count = 323 Devices
This Device is Pb-Free, Halogen Free and is RoHS Compliant
PLCC−28
FN SUFFIX
CASE 776
MARKING DIAGRAM*
1
MC10E167FNG
AWLYYWW
A
WL
YY
WW
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb-Free Package
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
Device
MC10E167FNR2G
© Semiconductor Components Industries, LLC, 2016
July, 2016 − Rev. 9
1
Package
Shipping
PLCC−8
(Pb-Free)
37 Units/Tube
Publication Order Number:
MC10E167/D
MC10E167
D5 a
25
D4 b D4 a
24
23
D3 b
D3 a
NC
VCCO
22
21
20
19
D0 a
MUX
D0 b
SEL
D5 b
26
18
Q5
D1 a
MUX
CLK1
27
17
Q4
D1 b
SEL
CLK2
28
16
VCC
D2 a
MUX
SEL
1
15
Q3
D2 b
VEE
D3 a
MUX
Pinout: 28-Lead PLCC
(Top View)
MR
2
14
Q2
D3 b
SEL
SEL
3
13
VCCO
D4 a
MUX
D0 a
4
12
Q1
D4 b
SEL
D5 a
5
D0 b
6
7
8
9
D1 a
D1 b
D2 a
10
11
D5 b
D2b VCCO Q0
SEL
Q
Q0
Q
Q1
Q
Q2
Q
Q3
Q
Q4
Q
Q5
R
D
R
D
R
D
R
D
R
D
R
SEL
* All VCC and VCCO pins are tied together on the die.
CLK1
CLK2
MR
Warning: All VCC, VCCO, and VEE pins must be externally
connected to Power Supply to guarantee proper operation.
Figure 2. Logic Diagram
Figure 1. 28-Lead Pinout Assignment
Table 1. PIN DESCRIPTION
PIN
D0 a − D5 a
D0 b − D5 b
SEL
CLK1, CLK2
MR
Q0 − Q5
VCC, VCCO
VEE
NC
MUX
D
FUNCTION
ECL Input Data a
ECL Input Data b
ECL Select Input
ECL Clock Inputs
ECL Master Reset
ECL Data Outputs
Positive Supply
Negative Supply
No Connect
Table 2. FUNCTION TABLE
SEL
Data
H
L
a
b
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2
MC10E167
Table 3. MAXIMUM RATINGS
Symbol
Rating
Unit
VCC
PECL Mode Power Supply
Parameter
VEE = 0 V
Condition 1
Condition 2
8
V
VEE
NECL Mode Power Supply
VCC = 0 V
−8
V
VI
PECL Mode Input Voltage
NECL Mode Input Voltage
VEE = 0 V
VCC = 0 V
6
−6
V
Iout
Output Current
Continuous
Surge
50
100
mA
TA
Operating Temperature Range
0 to +85
°C
Tstg
Storage Temperature Range
−65 to +150
°C
qJA
Thermal Resistance (Junction-to-Ambient)
0 lfpm
500 lfpm
PLCC−28
PLCC−28
63.5
43.5
°C/W
qJC
Thermal Resistance (Junction-to-Case)
Standard Board
PLCC−28
22 to 26
°C/W
VEE
PECL Operating Range
NECL Operating Range
4.2 to 5.7
−5.7 to −4.2
V
Tsol
Wave Solder (Pb-Free)
265
°C
VI ≤ VCC
VI ≥ VEE
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
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3
MC10E167
Table 4. 10E SERIES PECL DC CHARACTERISTICS (VCCx = 5.0 V, VEE = 0.0 V (Note 1))
0°C
Symbol
Min
Characteristic
25°C
Typ
Max
94
113
Min
85°C
Typ
Max
94
113
Min
Typ
Max
Unit
94
113
mA
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 2)
3980
4070
4160
4020
4105
4190
4090
4185
4280
mV
VOL
Output LOW Voltage (Note 2)
3050
3210
3370
3050
3210
3370
3050
3227
3405
mV
VIH
Input HIGH Voltage
3830
3995
4160
3870
4030
4190
3940
4110
4280
mV
VIL
Input LOW Voltage
3050
3285
3520
3050
3285
3520
3050
3302
3555
mV
IIH
Input HIGH Current
150
mA
IIL
Input LOW Current
0.5
0.3
0.5
0.25
0.3
0.2
150
150
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
1. Input and output parameters vary 1:1 with VCC. VEE can vary −0.46 V / +0.06 V.
2. Outputs are terminated through a 50 W resistor to VCC − 2.0 V.
Table 5. 10E SERIES NECL DC CHARACTERISTICS (VCCx = 0.0 V; VEE = −5.0 V (Note 1))
0°C
Symbol
Characteristic
Min
25°C
Typ
Max
94
113
Min
85°C
Typ
Max
94
113
Min
Typ
Max
Unit
94
113
mA
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 2)
−1020
−930
−840
−980
−895
−810
−910
−815
−720
mV
VOL
Output LOW Voltage (Note 2)
−1950
−1790
−1630
−1950
−1790
−1630
−1950
−1773
−1595
mV
VIH
Input HIGH Voltage
−1170
−1005
−840
−1130
−970
−810
−1060
−890
−720
mV
VIL
Input LOW Voltage
−1950
−1715
−1480
−1950
−1715
−1480
−1950
−1698
−1445
mV
IIH
Input HIGH Current
150
mA
IIL
Input LOW Current
0.5
0.3
0.5
0.065
0.3
0.2
150
150
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
1. Input and output parameters vary 1:1 with VCC. VEE can vary −0.46 V / +0.06 V.
2. Outputs are terminated through a 50 W resistor to VCC − 2.0 V.
Table 6. 100E SERIES PECL DC CHARACTERISTICS (VCCx = 5.0 V; VEE = 0.0 V (Note 1))
0°C
Typ
Max
94
113
3975
4050
4120
Output LOW Voltage (Note 2)
3190
3295
Input HIGH Voltage
3835
3975
VIL
Input LOW Voltage
3190
3355
IIH
Input HIGH Current
IIL
Input LOW Current
Symbol
Characteristic
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 2)
VOL
VIH
Min
25°C
Min
Typ
Max
94
113
3975
4050
4120
3380
3190
3255
4120
3835
3975
3525
3190
3355
150
0.5
85°C
0.3
Min
Typ
Max
Unit
108
130
mA
3975
4050
4120
mV
3380
3190
3260
3380
mV
4120
3835
3975
4120
mV
3525
3190
3355
3525
mV
150
mA
150
0.5
0.25
0.5
0.2
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
1. Input and output parameters vary 1:1 with VCC. VEE can vary −0.46 V / +0.8 V.
2. Outputs are terminated through a 50 W resistor to VCC − 2.0 V.
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MC10E167
Table 7. 100E SERIES NECL DC CHARACTERISTICS (VCCx = 0 V; VEE = −5.0 V (Note 1))
0°C
Characteristic
Symbol
Min
25°C
Typ
Max
94
113
Min
85°C
Typ
Max
94
113
Min
Typ
Max
Unit
108
130
mA
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 2)
−1025
−950
−880
−1025
−950
−880
−1025
−950
−880
mV
VOL
Output LOW Voltage (Note 2)
−1810
−1705
−1620
−1810
−1745
−1620
−1810
−1740
−1620
mV
VIH
Input HIGH Voltage
−1165
−1025
−880
−1165
−1025
−880
−1165
−1025
−880
mV
VIL
Input LOW Voltage
−1810
−1645
−1475
−1810
−1645
−1475
−1810
−1645
−1475
mV
IIH
Input HIGH Current
150
mA
IIL
Input LOW Current
0.5
0.3
0.5
0.25
0.5
0.2
150
150
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
1. Input and output parameters vary 1:1 with VCC. VEE can vary −0.46 V / +0.8 V.
2. Outputs are terminated through a 50 W resistor to VCC − 2.0 V.
Table 8. AC CHARACTERISTICS (VCCx = 5.0 V; VEE = 0.0 V or VCCx = 0.0 V; VEE = −5.0 V (Note 1))
0°C
Characteristic
Min
Typ
fMAX
Maximum Toggle Frequency
1000
1400
tPLH
tPHL
Propagation Delay to Output
Clk, MR
650
850
ts
Setup Time
D
SEL
100
275
th
Hold Time
D
SEL
tRR
tPW
25°C
Min
Typ
1000
1400
650
850
− 50
125
100
275
300
75
50
−125
Reset Recovery Time
750
550
Minimum Pulse Width
Clk, MR
400
Symbol
Max
1050
85°C
Max
Min
Typ
1000
1400
650
850
− 50
125
100
275
− 50
125
300
75
50
−125
300
75
50
−125
750
550
750
550
1050
400
Max
Unit
MHz
1050
ps
ps
ps
ps
ps
400
tSKEW
Within-Device Skew (Note 2)
75
75
75
ps
tJITTER
Random Clock Jitter (RMS)
<1
<1
<1
ps
tr
tf
Rise/Fall Times (20−80%)
300
450
800
300
450
800
300
450
800
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
1. 10 Series: VEE can vary −0.46 V / +0.06 V.
100 Series: VEE can vary −0.46 V / +0.8 V.
2. Within-device skew is defined as identical transitions on similar paths through a device.
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5
MC10E167
Q
Zo = 50 W
D
Receiver
Device
Driver
Device
Q
D
Zo = 50 W
50 W
50 W
VTT
VTT = VCC − 2.0 V
Figure 3. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D − Termination of ECL Logic Devices)
Resource Reference of Application Notes
AN1405/D
− ECL Clock Distribution Techniques
AN1406/D
− Designing with PECL (ECL at +5.0 V)
AN1503/D
− ECLinPSt I/O SPiCE Modeling Kit
AN1504/D
− Metastability and the ECLinPS Family
AN1568/D
− Interfacing Between LVDS and ECL
AN1672/D
− The ECL Translator Guide
AND8001/D
− Odd Number Counters Design
AND8002/D
− Marking and Date Codes
AND8020/D
− Termination of ECL Logic Devices
AND8066/D
− Interfacing with ECLinPS
AND8090/D
− AC Characteristics of ECL Devices
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6
MC10E167
PACKAGE DIMENSIONS
28 LEAD PLLC
FN SUFFIX
CASE 776−02
ISSUE F
B
Y BRK
−N−
0.007 (0.180)
U
M
T L-M
0.007 (0.180)
M
N
S
T L-M
S
S
N
S
D
Z
−M−
−L−
W
28
D
X
V
1
G1
0.010 (0.250)
T L-M
S
N
S
S
VIEW D−D
Z
A
0.007 (0.180)
R
0.007 (0.180)
M
M
T L-M
S
T L-M
S
N
N
H
S
0.007 (0.180)
M
T L-M
N
S
S
S
K1
C
E
0.004 (0.100)
G
J
S
K
SEATING
PLANE
F
VIEW S
G1
0.010 (0.250)
−T−
T L-M
S
N
VIEW S
S
NOTES:
1. DATUMS -L-, -M-, AND -N- DETERMINED
WHERE TOP OF LEAD SHOULDER EXITS
PLASTIC BODY AT MOLD PARTING LINE.
2. DIMENSION G1, TRUE POSITION TO BE
MEASURED AT DATUM -T-, SEATING PLANE.
3. DIMENSIONS R AND U DO NOT INCLUDE
MOLD FLASH. ALLOWABLE MOLD FLASH IS
0.010 (0.250) PER SIDE.
4. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
5. CONTROLLING DIMENSION: INCH.
6. THE PACKAGE TOP MAY BE SMALLER THAN
THE PACKAGE BOTTOM BY UP TO 0.012
(0.300). DIMENSIONS R AND U ARE
DETERMINED AT THE OUTERMOST
EXTREMES OF THE PLASTIC BODY
EXCLUSIVE OF MOLD FLASH, TIE BAR
BURRS, GATE BURRS AND INTERLEAD
FLASH, BUT INCLUDING ANY MISMATCH
BETWEEN THE TOP AND BOTTOM OF THE
PLASTIC BODY.
7. DIMENSION H DOES NOT INCLUDE DAMBAR
PROTRUSION OR INTRUSION. THE DAMBAR
PROTRUSION(S) SHALL NOT CAUSE THE H
DIMENSION TO BE GREATER THAN 0.037
(0.940). THE DAMBAR INTRUSION(S) SHALL
NOT CAUSE THE H DIMENSION TO BE
SMALLER THAN 0.025 (0.635).
DIM
A
B
C
E
F
G
H
J
K
R
U
V
W
X
Y
Z
G1
K1
INCHES
MIN
MAX
0.485
0.495
0.485
0.495
0.165
0.180
0.090
0.110
0.013
0.021
0.050 BSC
0.026
0.032
0.020
--0.025
--0.450
0.456
0.450
0.456
0.042
0.048
0.042
0.048
0.042
0.056
--0.020
2_
10_
0.410
0.430
0.040
---
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7
MILLIMETERS
MIN
MAX
12.32
12.57
12.32
12.57
4.20
4.57
2.29
2.79
0.33
0.53
1.27 BSC
0.66
0.81
0.51
--0.64
--11.43
11.58
11.43
11.58
1.07
1.21
1.07
1.21
1.07
1.42
--0.50
2_
10_
10.42
10.92
1.02
---
0.007 (0.180)
M
T L-M
S
N
S
MC10E167
ECLinPS is a trademark of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
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