TI LP2986AILDX-3.3 Micropower, 200 ma ultra low-dropout fixed or adjustable voltage regulator Datasheet

LP2986
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SNVS137H – MARCH 1999 – REVISED APRIL 2013
Micropower, 200 mA Ultra Low-Dropout Fixed or Adjustable Voltage Regulator
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FEATURES
DESCRIPTION
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The LP2986 is a 200 mA precision LDO voltage
regulator which offers the designer a higher
performance version of the industry standard LP2951.
1
23
Ultra Low Dropout Voltage
Ensured 200 mA Output Current
SOIC-8 and VSSOP-8 Surface Mount Packages
<1 μA Quiescent Current when Shutdown
Low Ground Pin Current at All Loads
0.5% Output Voltage Accuracy (“A” Grade)
High Peak Current Capability (400 mA Typical)
Wide Supply Voltage Range (16V Max)
Overtemperature/Overcurrent Protection
−40°C to +125°C Junction Temperature Range
APPLICATIONS
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Cellular Phone
Palmtop/Laptop Computer
Camcorder, Personal Stereo, Camera
Using an optimized VIP™ (Vertically Integrated PNP)
process, the LP2986 delivers superior performance:
Dropout Voltage: Typically 180 mV @ 200 mA load,
and 1 mV @ 1 mA load.
Ground Pin Current: Typically 1 mA @ 200 mA
load, and 200 μA @ 10 mA load.
Sleep Mode: The LP2986 draws less than 1 μA
quiescent current when shutdown pin is pulled low.
Error Flag: The built-in error flag goes low when the
output drops approximately 5% below nominal.
Precision Output: The standard product versions
available can be pin-strapped (using the internal
resistive divider) to provide output voltages of 5.0V,
3.3V, or 3.0V with ensured accuracy of 0.5% (“A”
grade) and 1% (standard grade) at room temperature.
Block Diagram
1
2
3
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
VIP is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1999–2013, Texas Instruments Incorporated
LP2986
SNVS137H – MARCH 1999 – REVISED APRIL 2013
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Connection Diagram
Top View
GROUND
1
8
SHUTDOWN
FEEDBACK
2
7
ERROR
TAP
3
6
SENSE
INPUT
4
5
OUTPUT
Figure 1. 8-Lead SOIC Package
See Package Number D0008A
Top View
GROUND
1
8
SHUTDOWN
FEEDBACK
2
7
ERROR
TAP
3
6
SENSE
INPUT
4
5
OUTPUT
Figure 2. 8-Lead VSSOP Package
See Package Number DGK0008A
Top View
1
8
SHUTDOWN
FEEDBACK
2
7
ERROR
TAP
3
6
SENSE
INPUT
4
5
OUTPUT
GROUND
Exposed Pad
on Bottom
(DAP)
Figure 3. 8-Lead WSON Package
See Package Number NGN0008A
See WSON MOUNTING section
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
2
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Absolute Maximum Ratings (1) (2)
Storage Temperature Range
−65°C to +150°C
Operating Junction Temperature Range
−40°C to +125°C
Lead Temperature (Soldering, 5 seconds)
260°C
ESD Rating (3)
Power Dissipation
2 kV
(4)
Internally Limited
−0.3V to +16V
Input Supply Voltage (Survival)
Input Supply Voltage (Operating)
2.1V to +16V
−0.3V to +16V
Shutdown Pin
−0.3V to +5V
Feedback Pin
Output Voltage (Survival) (5)
−0.3V to +16V
IOUT (Survival)
Short Circuit Protected
Input-Output Voltage (Survival) (6)
(1)
(2)
(3)
(4)
(5)
(6)
−0.3V to +16V
Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Electrical specifications do not apply
when operating the device outside of its rated operating conditions.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
The ESD rating of the Feedback pin is 500V. The ESD rating of the VIN pin is 1kV and the Tap pin is 1.5 kV.
The maximum allowable power dissipation is a function of the maximum junction temperature, TJ(MAX), the junction-to-ambient thermal
resistance, θJ−A, and the ambient temperature, TA. The maximum allowable power dissipation at any ambient temperature is calculated
using:
The value of θJ−A for the SOIC-8 package is 160°C/W, and the VSSOP-8 package is 200°C/W. The value
θJ−A for the WSON package is specifically dependent on PCB trace area, trace material, and the number of layers and thermal vias. For
improved thermal resistance and power dissipation for the WSON package, refer to Application Note AN-1187. Exceeding the maximum
allowable power dissipation will cause excessive die temperature, and the regulator will go into thermal shutdown.
If used in a dual-supply system where the regulator load is returned to a negative supply, the LM2986 output must be diode-clamped to
ground.
The output PNP structure contains a diode between the V IN and VOUT terminals that is normally reverse-biased. Forcing the output
above the input will turn on this diode and may induce a latch-up mode which can damage the part (see Application Hints).
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Electrical Characteristics
Limits in standard typeface are for T J = 25°C, and limits in boldface type apply over the full operating temperature range.
Unless otherwise specified: VIN = VO(NOM) + 1V, IL = 1 mA, COUT = 4.7 µF, CIN = 2.2 µF, VS/D = 2V.
Symbol
Parameter
Conditions
VO
Typical
5.0
Output Voltage
(5.0V Versions)
0.1 mA < IL < 200 mA
5.0
3.3
Output Voltage
(3.3V Versions)
0.1 mA < IL < 200 mA
3.3
3.0
Output Voltage
(3.0V Versions)
Output Voltage Line
Regulation
VIN–VO
0.1 mA < IL < 200 mA
VO(NOM) + 1V ≤ VIN ≤ 16V
IL = 100 µA
Dropout Voltage (2)
IGND
Ground Pin Current
3.0
LM2986AI-X.X (1)
Min
Max
Min
Max
4.975
5.025
4.950
5.050
4.960
5.040
4.920
5.080
4.910
5.090
4.860
5.140
3.283
3.317
3.267
3.333
3.274
3.326
3.247
3.353
3.241
3.359
3.208
3.392
2.985
3.015
2.970
3.030
2.976
3.024
2.952
3.048
2.946
3.054
2.916
3.084
0.007
1
IL = 75 mA
90
IL = 200 mA
180
IL = 100 µA
100
IL = 75 mA
500
IL = 200 mA
1
VS/D < 0.3V
0.05
LM2986I-X.X (1)
0.014
0.014
0.032
0.032
2.0
2.0
3.5
3.5
120
120
170
170
230
230
350
350
120
120
150
150
800
800
1400
1400
2.1
2.1
3.7
3.7
1.5
1.5
Units
V
%/V
mV
µA
mA
µA
IO(PK)
Peak Output Current
VOUT ≥ VO(NOM) − 5%
400
IO(MAX)
Short Circuit Current
RL = 0 (Steady State) (3)
400
en
Output Noise Voltage
(RMS)
BW = 300 Hz to 50 kHz,
COUT = 10 µF
160
µV(RMS)
Ripple Rejection
f = 1 kHz, COUT = 10 µF
65
dB
Output Voltage
Temperature Coefficient
See (4)
20
ppm/°C
(1)
(2)
(3)
(4)
4
250
250
mA
Limits are 100% production tested at 25°C. Limits over the operating temperature range are ensured through correlation using Statistical
Quality Control (SQC) methods. The limits are used to calculate Average Outgoing Quality Level (AOQL).
Dropout voltage is defined as the input to output differential at which the output voltage drops 100 mV below the value measured with a
1V differential.
See Typical Performance Characteristics curves.
Temperature coefficient is defined as the maximum (worst-case) change divided by the total temperature range.
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Electrical Characteristics (continued)
Limits in standard typeface are for T J = 25°C, and limits in boldface type apply over the full operating temperature range.
Unless otherwise specified: VIN = VO(NOM) + 1V, IL = 1 mA, COUT = 4.7 µF, CIN = 2.2 µF, VS/D = 2V.
Symbol
Parameter
Conditions
Typical
LM2986AI-X.X (1)
LM2986I-X.X (1)
Min
Max
Min
Max
1.21
1.25
1.20
1.26
1.20
1.26
1.19
1.27
1.19
1.28
1.18
1.29
Units
FEEDBACK PIN
VFB
1.23
Feedback Pin Voltage
FB Pin Voltage
Temperature Coefficient
IFB
See (5)
1.23
See (6)
20
Feedback Pin Bias Current IL = 200 mA
150
FB Pin Bias Current
Temperature Coefficient
0.1
See (6)
V
ppm/°C
330
330
760
760
nA
nA/°C
SHUTDOWN INPUT
VS/D
IS/D
VH = O/P ON
1.4
VL = O/P OFF
0.55
0.18
0.18
VS/D = 0
0
−1
−1
VS/D = 5V
5
15
15
Output “HIGH” Leakage
VOH = 16V
0.01
1
1
2
2
Output “LOW” Voltage
VIN = VO(NOM) − 0.5V,
IO(COMP) = 300 µA
150
220
220
350
350
S/D Input Voltage (7)
S/D Input Current
1.6
1.6
V
µA
ERROR COMPARATOR
IOH
VOL
VTHR
(MAX)
Upper Threshold Voltage
−4.6
VTHR
(MIN)
Lower Threshold Voltage
−6.6
HYST
Hysteresis
2.0
(5)
(6)
(7)
−5.5
−3.5
−5.5
−3.5
−7.7
−2.5
−7.7
−2.5
−8.9
−4.9
−8.9
−4.9
−13.0
−3.3
−13.0
−3.3
µA
mV
%VOUT
VFB ≤ VOUT ≤ (VIN − 1), 2.5V ≤ VIN ≤ 16V, 100 µA ≤ IL ≤ 200 mA, TJ ≤ 125°C.
Temperature coefficient is defined as the maximum (worst-case) change divided by the total temperature range.
To prevent mis-operation, the Shutdown input must be driven by a signal that swings above VH and below VL with a slew rate not less
than 40 mV/µs (see Application Hints).
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Typical Performance Characteristics
Unless otherwise specified: TA = 25°C, COUT = 4.7 µF, CIN = 2.2 µF, S/D is tied to VIN, VIN = VO(NOM) + 1V, IL = 1 mA.
6
VOUT vs Temperature
Dropout Voltage vs Temperature
Figure 4.
Figure 5.
Dropout Voltage vs Load Current
Dropout Characteristics
Figure 6.
Figure 7.
Ground Pin Current vs
Temperature and Load
Ground Pin Current
vs Load Current
Figure 8.
Figure 9.
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Typical Performance Characteristics (continued)
Unless otherwise specified: TA = 25°C, COUT = 4.7 µF, CIN = 2.2 µF, S/D is tied to VIN, VIN = VO(NOM) + 1V, IL = 1 mA.
Input Current vs VIN
Input Current vs VIN
Figure 10.
Figure 11.
Load Transient Response
Load Transient Response
Figure 12.
Figure 13.
Line Transient Response
Line Transient Response
Figure 14.
Figure 15.
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Typical Performance Characteristics (continued)
Unless otherwise specified: TA = 25°C, COUT = 4.7 µF, CIN = 2.2 µF, S/D is tied to VIN, VIN = VO(NOM) + 1V, IL = 1 mA.
8
Turn-On Waveform
Turn-Off Waveform
Figure 16.
Figure 17.
Short Circuit Current
Short Circuit Current
Figure 18.
Figure 19.
Short Circuit Current
vs Output Voltage
Instantaneous Short Circuit Current
vs Temperature
Figure 20.
Figure 21.
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Typical Performance Characteristics (continued)
Unless otherwise specified: TA = 25°C, COUT = 4.7 µF, CIN = 2.2 µF, S/D is tied to VIN, VIN = VO(NOM) + 1V, IL = 1 mA.
DC Load Regulation
Feedback Bias Current vs Load
Figure 22.
Figure 23.
Feedback Bias Current
vs Temperature
Shutdown Pin Current vs
Shutdown Pin Voltage
Figure 24.
Figure 25.
Shutdown Voltage vs
Temperature
Input to Output Leakage vs
Temperature
Figure 26.
Figure 27.
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Typical Performance Characteristics (continued)
Unless otherwise specified: TA = 25°C, COUT = 4.7 µF, CIN = 2.2 µF, S/D is tied to VIN, VIN = VO(NOM) + 1V, IL = 1 mA.
10
Output Noise Density
Output Impedance vs
Frequency
Figure 28.
Figure 29.
Output Impedance vs
Frequency
Ripple Rejection
Figure 30.
Figure 31.
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Basic Application Circuits
Figure 32. Application Using Internal Resistive Divider
Figure 33. Application Using External Divider
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APPLICATION HINTS
WSON PACKAGE DEVICES
The LP2986 is offered in the 8 lead WSON surface mount package to allow for increased power dissipation
compared to the SOIC-8 and VSSOP-8. For details on WSON thermal performance as well as mounting and
soldering specifications, refer to the WSON MOUNTING section.
EXTERNAL CAPACITORS
Like any low-dropout regulator, external capacitors are required to assure stability. These capacitors must be
correctly selected for proper performance.
INPUT CAPACITOR: An input capacitor (≥ 2.2 µF) is required between the LP2986 input and ground (amount of
capacitance may be increased without limit).
This capacitor must be located a distance of not more than 0.5” from the input pin and returned to a clean analog
ground. Any good quality ceramic or tantalum may be used for this capacitor.
OUTPUT CAPACITOR: The output capacitor must meet the requirement for minimum amount of capacitance
and also have an appropriate E.S.R. (equivalent series resistance) value.
Curves are provided which show the allowable ESR range as a function of load current for various output
voltages and capacitor values (see ESR curves below).
Figure 34. ESR Curves For 5V Output
Figure 35. ESR Curves For 2.5V Output
IMPORTANT: The output capacitor must maintain its ESR in the stable region over the full operating temperature
range of the application to assure stability.
The minimum required amount of output capacitance is 4.7 µF. Output capacitor size can be increased without
limit.
It is important to remember that capacitor tolerance and variation with temperature must be taken into
consideration when selecting an output capacitor so that the minimum required amount of output capacitance is
provided over the full operating temperature range. A good Tantalum capacitor will show very little variation with
temperature, but a ceramic may not be as good (see next section).
CAPACITOR CHARACTERISTICS
TANTALUM: The best choice for size, cost, and performance are solid tantalum capacitors. Available from many
sources, their typical ESR is very close to the ideal value required on the output of many LDO regulators.
Tantalums also have good temperature stability: a 4.7 µF was tested and showed only a 10% decline in
capacitance as the temperature was decreased from +125°C to −40°C. The ESR increased only about 2:1 over
the same range of temperature.
However, it should be noted that the increasing ESR at lower temperatures present in all tantalums can cause
oscillations when marginal quality capacitors are used (where the ESR of the capacitor is near the upper limit of
the stability range at room temperature).
CERAMIC: For a given amount of a capacitance, ceramics are usually larger and more costly than tantalums.
12
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Be warned that the ESR of a ceramic capacitor can be low enough to cause instability: a 2.2 µF ceramic was
measured and found to have an ESR of about 15 mΩ.
If a ceramic capacitor is to be used on the LP2986 output, a 1Ω resistor should be placed in series with the
capacitor to provide a minimum ESR for the regulator.
Another disadvantage of ceramic capacitors is that their capacitance varies a lot with temperature:
Large ceramic capacitors are typically manufactured with the Z5U temperature characteristic, which results in the
capacitance dropping by a 50% as the temperature goes from 25°C to 80°C.
This means you have to buy a capacitor with twice the minimum COUT to assure stable operation up to 80°C.
ALUMINUM: The large physical size of aluminum electrolytics makes them unattractive for use with the LP2986.
Their ESR characteristics are also not well suited to the requirements of LDO regulators.
The ESR of an aluminum electrolytic is higher than a tantalum, and it also varies greatly with temperature.
A typical aluminum electrolytic can exhibit an ESR increase of 50X when going from 20°C to −40°C. Also, some
aluminum electrolytics can not be used below −25°C because the electrolyte will freeze.
USING AN EXTERNAL RESISTIVE DIVIDER
The LP2986 output voltage can be programmed using an external resistive divider (see Basic Application
Circuits).
The resistor connected between the Feedback pin and ground should be 51.1k. The value for the other resistor
(R1) connected between the Feedback pin and the regulated output is found using the formula:
VOUT = VFB × (1 + ( R1 / 51.1k ))
(1)
It should be noted that the 25 µA of current flowing through the external divider is approximately equal to the
current saved by not connecting the internal divider, which means the quiescent current is not increased by using
external resistors.
A lead compensation capacitor (CF) must also be used to place a zero in the loop response at about 50 kHz. The
value for C F can be found using:
CF = 1/(2π × R1 × 50k)
(2)
A good quality capacitor must be used for CF to ensure that the value is accurate and does not change
significantly over temperature. Mica or ceramic capacitors can be used, assuming a tolerance of ±20% or better
is selected.
If a ceramic is used, select one with a temperature coefficient of NPO, COG, Y5P, or X7R. Capacitor types Z5U,
Y5V, and Z4V can not be used because their value varies more that 50% over the −25°C to +85°C temperature
range.
SHUTDOWN INPUT OPERATION
The LP2986 is shut off by driving the Shutdown input low, and turned on by pulling it high. If this feature is not to
be used, the Shutdown input should be tied to VIN to keep the regulator output on at all times.
To assure proper operation, the signal source used to drive the Shutdown input must be able to swing above and
below the specified turn-on/turn-off voltage thresholds listed as VH and VL, respectively (see Electrical
Characteristics).
Since the Shutdown input comparator does not have hysteresis, It is also important that the turn-on (and turn-off)
voltage signals applied to the Shutdown input have a slew rate which is not less than 40 mV/µs when moving
between the VH and VL thresholds.
CAUTION: The regulator output state (either On or Off) can not be specified if a slow-moving AC (or DC) signal
is applied that is in the range between VH and VL.
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WSON MOUNTING
The LDC08A (Pullback) 8-Lead WSON package requires specific mounting techniques which are detailed in
Application Note AN-1187. Referring to the section PCB Design Recommendations in AN-1187 (Page 5), it
should be noted that the pad style which should be used with this WSON package is the NSMD (non-solder
mask defined) type. Additionally, for optimal reliability, there is a recommended 1:1 ratio between the package
pad and the PCB pad for the Pullback WSON.
The thermal dissipation of the WSON package is directly related to the printed circuit board construction and the
amount of additional copper area connected to the DAP.
The DAP (exposed pad) on the bottom of the WSON package is connected to the die substrate with a conductive
die attach adhesive. The DAP has no direct electrical (wire) connection to any of the eight pins. There is a
parasitic PN junction between the die substrate and the device ground. As such, it is strongly recommend that
the DAP be connected directly to the ground at device lead 1 (i.e. GROUND). Alternately, but not recommended,
the DAP may be left floating (i.e. no electrical connection). The DAP must not be connected to any potential
other than ground.
For the LP2986 in the NGN0008A 8-Lead WSON package, the junction-to-case thermal rating (θJC) is 7.2°C/W,
where the 'case' is on the bottom of the package at the center of the DAP.
The junction-to-ambient thermal performance for the LP2986 in the NGN0008A 8-Lead WSON package, using
the JEDEC JESD51 standards is summarized in the following table:
Board Type
Thermal Vias
θJC
θJA
JEDEC 2-Layer
JESD 51-3
None
7.2°C/W
184°C/W
1
7.2°C/W
64°C/W
2
7.2°C/W
55°C/W
4
7.2°C/W
46°C/W
6
7.2°C/W
43°C/W
JEDEC 4-Layer
JESD 51-7
14
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REVERSE INPUT-OUTPUT VOLTAGE
The PNP power transistor used as the pass element in the LP2986 has an inherent diode connected between
the regulator output and input.
During normal operation (where the input voltage is higher than the output) this diode is reverse-biased.
However, if the output voltage is pulled above the input, or the input voltage is pulled below the output, this diode
will turn ON and current will flow into the regulator output pin.
LP2986
VIN
VOUT
PNP
GND
In such cases, a parasitic SCR can latch which will allow a high current to flow into VIN (and out the ground pin),
which can damage the part.
In any application where the output voltage may be higher than the input, an external Schottky diode must be
connected from VIN to VOUT (cathode on VIN, anode on VOUT), to limit the reverse voltage across the LP2986 to
0.3V (see the Absolute Maximum Ratings section.
SCHOTTKY DIODE
LP2986
VIN
VOUT
PNP
GND
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REVISION HISTORY
Changes from Revision G (April 2013) to Revision H
•
16
Page
Changed layout of National Data Sheet to TI format .......................................................................................................... 15
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PACKAGE OPTION ADDENDUM
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1-Nov-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
LP2986AILD-3.3
NRND
WSON
NGN
8
1000
TBD
Call TI
Call TI
-40 to 125
L005A
LP2986AILD-3.3/NOPB
ACTIVE
WSON
NGN
8
1000
Green (RoHS
& no Sb/Br)
SN
Level-3-260C-168 HR
-40 to 125
L005A
LP2986AILDX-3.3/NOPB
ACTIVE
WSON
NGN
8
4500
Green (RoHS
& no Sb/Br)
SN
Level-3-260C-168 HR
-40 to 125
L005A
LP2986AIM-3.0/NOPB
ACTIVE
SOIC
D
8
95
Green (RoHS
& no Sb/Br)
SN | CU SN
Level-1-260C-UNLIM
-40 to 125
2986A
IM3.0
LP2986AIM-3.3
NRND
SOIC
D
8
95
TBD
Call TI
Call TI
-40 to 125
2986A
IM3.3
LP2986AIM-3.3/NOPB
ACTIVE
SOIC
D
8
95
Green (RoHS
& no Sb/Br)
SN | CU SN
Level-1-260C-UNLIM
-40 to 125
2986A
IM3.3
LP2986AIM-5.0
NRND
SOIC
D
8
95
TBD
Call TI
Call TI
-40 to 125
2986A
IM5.0
LP2986AIM-5.0/NOPB
ACTIVE
SOIC
D
8
95
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
2986A
IM5.0
LP2986AIMM-3.0/NOPB
ACTIVE
VSSOP
DGK
8
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
L39A
LP2986AIMM-3.3/NOPB
ACTIVE
VSSOP
DGK
8
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
L40A
LP2986AIMM-5.0/NOPB
ACTIVE
VSSOP
DGK
8
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
L41A
LP2986AIMMX-3.0/NOPB
ACTIVE
VSSOP
DGK
8
3500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
L39A
LP2986AIMMX-3.3/NOPB
ACTIVE
VSSOP
DGK
8
3500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
L40A
LP2986AIMMX-5.0/NOPB
ACTIVE
VSSOP
DGK
8
3500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
L41A
LP2986AIMX-3.0/NOPB
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
2986A
IM3.0
LP2986AIMX-3.3/NOPB
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
SN | CU SN
Level-1-260C-UNLIM
-40 to 125
2986A
IM3.3
LP2986AIMX-5.0
NRND
SOIC
D
8
2500
TBD
Call TI
Call TI
-40 to 125
2986A
IM5.0
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
1-Nov-2013
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
LP2986AIMX-5.0/NOPB
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
2986A
IM5.0
LP2986ILD-3.3/NOPB
ACTIVE
WSON
NGN
8
1000
Green (RoHS
& no Sb/Br)
SN
Level-3-260C-168 HR
-40 to 125
L005A
B
LP2986ILDX-3.3/NOPB
ACTIVE
WSON
NGN
8
4500
Green (RoHS
& no Sb/Br)
SN
Level-3-260C-168 HR
-40 to 125
L005A
B
LP2986IM-3.0
NRND
SOIC
D
8
95
TBD
Call TI
Call TI
-40 to 125
2986I
M3.0
LP2986IM-3.0/NOPB
ACTIVE
SOIC
D
8
95
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
2986I
M3.0
LP2986IM-3.3
NRND
SOIC
D
8
95
TBD
Call TI
Call TI
-40 to 125
2986I
M3.3
LP2986IM-3.3/NOPB
ACTIVE
SOIC
D
8
95
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
2986I
M3.3
LP2986IM-5.0
NRND
SOIC
D
8
95
TBD
Call TI
Call TI
-40 to 125
2986I
M5.0
LP2986IM-5.0/NOPB
ACTIVE
SOIC
D
8
95
Green (RoHS
& no Sb/Br)
SN | CU SN
Level-1-260C-UNLIM
-40 to 125
2986I
M5.0
LP2986IMM-3.0/NOPB
ACTIVE
VSSOP
DGK
8
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
L39B
LP2986IMM-3.3
NRND
VSSOP
DGK
8
1000
TBD
Call TI
Call TI
-40 to 125
L40B
LP2986IMM-3.3/NOPB
ACTIVE
VSSOP
DGK
8
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
L40B
LP2986IMM-5.0/NOPB
ACTIVE
VSSOP
DGK
8
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
L41B
LP2986IMMX-3.0/NOPB
ACTIVE
VSSOP
DGK
8
3500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
L39B
LP2986IMMX-3.3/NOPB
ACTIVE
VSSOP
DGK
8
3500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
L40B
LP2986IMMX-5.0/NOPB
ACTIVE
VSSOP
DGK
8
3500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
L41B
LP2986IMX-3.0/NOPB
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
2986I
M3.0
LP2986IMX-3.3/NOPB
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
2986I
M3.3
LP2986IMX-5.0
NRND
SOIC
D
8
2500
TBD
Call TI
Call TI
-40 to 125
2986I
Addendum-Page 2
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
1-Nov-2013
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
Op Temp (°C)
Device Marking
(4/5)
M5.0
LP2986IMX-5.0/NOPB
ACTIVE
SOIC
D
8
2500
-40 to 125
2986I
M5.0
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 3
Samples
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Sep-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
LP2986AILD-3.3
WSON
NGN
8
1000
178.0
12.4
4.3
4.3
1.3
8.0
12.0
Q1
LP2986AILD-3.3/NOPB
WSON
NGN
8
1000
178.0
12.4
4.3
4.3
1.3
8.0
12.0
Q1
LP2986AILDX-3.3/NOPB
WSON
NGN
8
4500
330.0
12.4
4.3
4.3
1.3
8.0
12.0
Q1
LP2986AIMM-3.0/NOPB
VSSOP
DGK
8
1000
178.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
LP2986AIMM-3.3/NOPB
VSSOP
DGK
8
1000
178.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
LP2986AIMM-5.0/NOPB
VSSOP
DGK
8
1000
178.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
LP2986AIMMX-3.0/NOPB VSSOP
DGK
8
3500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
LP2986AIMMX-3.3/NOPB VSSOP
DGK
8
3500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
LP2986AIMMX-5.0/NOPB VSSOP
DGK
8
3500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
LP2986AIMX-3.0/NOPB
SOIC
D
8
2500
330.0
12.4
6.5
5.4
2.0
8.0
12.0
Q1
LP2986AIMX-3.3/NOPB
SOIC
D
8
2500
330.0
12.4
6.5
5.4
2.0
8.0
12.0
Q1
LP2986AIMX-5.0
SOIC
D
8
2500
330.0
12.4
6.5
5.4
2.0
8.0
12.0
Q1
LP2986AIMX-5.0/NOPB
SOIC
D
8
2500
330.0
12.4
6.5
5.4
2.0
8.0
12.0
Q1
LP2986ILD-3.3/NOPB
WSON
NGN
8
1000
178.0
12.4
4.3
4.3
1.3
8.0
12.0
Q1
LP2986ILDX-3.3/NOPB
WSON
NGN
8
4500
330.0
12.4
4.3
4.3
1.3
8.0
12.0
Q1
LP2986IMM-3.0/NOPB
VSSOP
DGK
8
1000
178.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
LP2986IMM-3.3
VSSOP
DGK
8
1000
178.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
LP2986IMM-3.3/NOPB
VSSOP
DGK
8
1000
178.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Sep-2013
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
LP2986IMM-5.0/NOPB
VSSOP
DGK
8
1000
178.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
LP2986IMMX-3.0/NOPB
VSSOP
DGK
8
3500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
LP2986IMMX-3.3/NOPB
VSSOP
DGK
8
3500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
LP2986IMMX-5.0/NOPB
VSSOP
DGK
8
3500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
LP2986IMX-3.0/NOPB
SOIC
D
8
2500
330.0
12.4
6.5
5.4
2.0
8.0
12.0
Q1
LP2986IMX-3.3/NOPB
SOIC
D
8
2500
330.0
12.4
6.5
5.4
2.0
8.0
12.0
Q1
LP2986IMX-5.0
SOIC
D
8
2500
330.0
12.4
6.5
5.4
2.0
8.0
12.0
Q1
LP2986IMX-5.0/NOPB
SOIC
D
8
2500
330.0
12.4
6.5
5.4
2.0
8.0
12.0
Q1
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LP2986AILD-3.3
WSON
NGN
8
1000
210.0
185.0
35.0
LP2986AILD-3.3/NOPB
WSON
NGN
8
1000
213.0
191.0
55.0
LP2986AILDX-3.3/NOPB
WSON
NGN
8
4500
367.0
367.0
35.0
LP2986AIMM-3.0/NOPB
VSSOP
DGK
8
1000
210.0
185.0
35.0
LP2986AIMM-3.3/NOPB
VSSOP
DGK
8
1000
210.0
185.0
35.0
LP2986AIMM-5.0/NOPB
VSSOP
DGK
8
1000
210.0
185.0
35.0
LP2986AIMMX-3.0/NOPB
VSSOP
DGK
8
3500
367.0
367.0
35.0
LP2986AIMMX-3.3/NOPB
VSSOP
DGK
8
3500
367.0
367.0
35.0
LP2986AIMMX-5.0/NOPB
VSSOP
DGK
8
3500
367.0
367.0
35.0
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Sep-2013
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LP2986AIMX-3.0/NOPB
SOIC
D
8
2500
367.0
367.0
35.0
LP2986AIMX-3.3/NOPB
SOIC
D
8
2500
367.0
367.0
35.0
LP2986AIMX-5.0
SOIC
D
8
2500
367.0
367.0
35.0
LP2986AIMX-5.0/NOPB
SOIC
D
8
2500
367.0
367.0
35.0
LP2986ILD-3.3/NOPB
WSON
NGN
8
1000
213.0
191.0
55.0
LP2986ILDX-3.3/NOPB
WSON
NGN
8
4500
367.0
367.0
35.0
LP2986IMM-3.0/NOPB
VSSOP
DGK
8
1000
210.0
185.0
35.0
LP2986IMM-3.3
VSSOP
DGK
8
1000
210.0
185.0
35.0
LP2986IMM-3.3/NOPB
VSSOP
DGK
8
1000
210.0
185.0
35.0
LP2986IMM-5.0/NOPB
VSSOP
DGK
8
1000
210.0
185.0
35.0
LP2986IMMX-3.0/NOPB
VSSOP
DGK
8
3500
367.0
367.0
35.0
LP2986IMMX-3.3/NOPB
VSSOP
DGK
8
3500
367.0
367.0
35.0
LP2986IMMX-5.0/NOPB
VSSOP
DGK
8
3500
367.0
367.0
35.0
LP2986IMX-3.0/NOPB
SOIC
D
8
2500
367.0
367.0
35.0
LP2986IMX-3.3/NOPB
SOIC
D
8
2500
367.0
367.0
35.0
LP2986IMX-5.0
SOIC
D
8
2500
367.0
367.0
35.0
LP2986IMX-5.0/NOPB
SOIC
D
8
2500
367.0
367.0
35.0
Pack Materials-Page 3
MECHANICAL DATA
NGN0008A
LDC08A (Rev B)
www.ti.com
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