CM1209 4,6 & 8 Channel ESD Protection Arrays with Zener Supply Clamp Features Product Description • The CM1209 family of diode arrays are designed to provide either 4, 6 or 8 channels of ESD protection for electronic components or sub-systems. Each channel consists of a pair of diodes which steer the ESD current pulse either to the positive (VP) or negative (VN) supply. In addition, there is an integral Zener diode between VP and VN to suppress any voltage disturbance due to these ESD current pulses. The CM1209 devices will protect against ESD pulses up to 15kV contact discharge per the International Standard IEC61000-4-2. • • • • • • Four, six or eight channels of ESD protection for high data rate signals Zener diode protects supply rail and eliminates the need for external by-pass capacitors +15 kV contact, +15 kV air ESD protection per channel (IEC 61000-4-2 standard) Low loading capacitance of 6pF typical Low supply current Available in miniature MSOP and SOIC packages Lead-free versions available Applications • • • • • • • These devices are particularly well-suited for portable electronics (e.g. cellular phones, PDAs, notebook computers) because of its small package footprint, high ESD protection level, and low loading capacitance. They are also suitable for protecting video output lines and I/O ports in computers, set top boxes, digital TVs and peripheral equipment. ESD protection for a variety of electronic equipment Set Top Boxes Digital TVs I/O & VGA Port protection Desktop and Notebook computers PDAs Cellular Phones The CM1209 family of devices is optionally available with lead-free finishing. Electrical Schematics 8 7 6 5 8 7 6 5 8 7 6 2 3 4 CM1209-08 8-Channel 5 10 9 VP VP VP VN VN VN 1 2 3 4 CM1209-04 4-Channel 1 2 3 4 CM1209-06 6-Channel 1 © 2004 California Micro Devices Corp. All rights reserved. 01/09/04 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 ▲ Tel: 408.263.3214 ▲ Fax: 408.263.7846 ▲ www.calmicro.com 1 CM1209 PACKAGE / PINOUT DIAGRAMS TOP VIEW TOP VIEW TOP VIEW CH 1 1 8 CH 4 CH 1 1 8 CH 6 CH 2 2 7 CH 3 CH 2 2 7 VP VN 3 6 VP VN 3 6 CH 5 VN 4 5 VN CH 3 4 5 CH 4 8-pin MSOP CM1209-04MS/MR CH 1 1 10 CH 8 CH 2 2 9 CH 7 CH 3 3 8 VP CH 4 4 7 CH 6 VN 5 6 CH 5 8-pin SOIC/MSOP CM1209-06SN/SM CM1209-06MS/MR 10-pin MSOP CM1209-08MS/MR Note: These drawings are not to scale. PIN DESCRIPTIONS CM1209-04 CM1209-06 CM1209-08 NAME PIN NO. PIN NO PIN NO TYPE DESCRIPTION CH 1 1 1 1 I/O ESD Channel 1 CH 2 2 2 2 I/O ESD Channel 2 CH 3 7 4 3 I/O ESD Channel 3 CH 4 8 5 4 I/O ESD Channel 4 CH 5 6 6 I/O ESD Channel 5 CH 6 8 7 I/O ESD Channel 6 9 I/O ESD Channel 7 ESD Channel 8 CH 7 10 I/O VN 3,4,5 3 5 GND VP 6 7 8 Supply CH 8 Negative voltage supply rail or ground reference rail. Positive voltage supply rail. © 2004 California Micro Devices Corp. All rights reserved. 2 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 ▲ Tel: 408.263.3214 ▲ Fax: 408.263.7846 ▲ www.calmicro.com 01/09/04 CM1209 Ordering Information PART NUMBERING INFORMATION Standard Finish Lead-free Finish Ordering Part Ordering Part # of Channels Pins Package Number1 Part Marking Number1 Part Marking 4 8 MSOP-8 CM1209-04MS 0904 CM1209-04MR 0914 6 8 SOIC-8 CM1209-06SN CM1209-06S CM1209-06SM CM1209-06SM 6 8 MSOP-8 CM1209-06MS 0906 CM1209-06MR 0916 8 10 MSOP-10 CM1209-08MS 0908 CM1209-08MR 0918 Note 1: Parts are shipped in Tape & Reel form unless otherwise specified. Specifications ABSOLUTE MAXIMUM RATINGS PARAMETER RATING UNITS Supply Voltage (VP - VN) 6.0 V Diode Forward DC Current (Note 1) 20 mA -40 to +85 °C Operating Temperature Range Storage Temperature Range DC Voltage at any channel input -65 to +150 °C (VN - 0.5) to (VP + 0.5) V 350 200 mW mW RATING UNITS -40 to +85 °C 0 to 5.5 V Package Power Rating SOIC Package MSOP Package Note 1: Only one diode conducting at a time. STANDARD OPERATING CONDITIONS PARAMETER Operating Temperature Range Operating Supply Voltage (VP - VN) © 2004 California Micro Devices Corp. All rights reserved. 01/09/04 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 ▲ Tel: 408.263.3214 ▲ Fax: 408.263.7846 ▲ www.calmicro.com 3 CM1209 Specifications (cont’d) ELECTRICAL OPERATING CHARACTERISTICS(SEE NOTE 1) SYMBOL PARAMETER CONDITIONS IP Supply Current (VP-VN)=5.5V; TA=25°C VF ESD Diode Forward Voltage IF = 20mA; TA=25°C VZBD Zener Clamp Reverse Breakdown Voltage At 1mA; TA=25°C ILEAK Channel Leakage Current TA=25°C Channel Input Capacitance At 1 MHz, VP=5V, via 10K; VN=0V, VIN=2.5V; Notes 2 and 6 CIN VESD VCL ESD Protection Peak Discharge Voltage at any channel input and VP rail Contact discharge per IEC 61000-4-2 standard Air discharge per IEC 61000-4-2 standard Channel Clamp Voltage MIN TYP 0.65 MAX UNITS 10 µA 0.95 V 7 V +0.1 +1.0 µA 6 8 pF Notes 2, 3, 5, and 6 +15 kV Notes 2, 3, 5, and 6 +15 kV At 8kV ESD HBM; TA=25°C; Notes 2, 4 and 6 Positive Transients Negative Transients +12.5 - 5.1 V V ZPOS Dynamic Resistance of Channel Input for Positive Transients I = 1A; TA=25°C; See Figure 2; Note 6 applies 0.70 Ω ZNEG Dynamic Resistance of Channel Input for Negative Transients I = 1A; TA=25°C; See Figure 2; Note 6 applies 0.45 Ω Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: All parameters specified at TA=-40 to +85°C unless otherwise noted. These parameters guaranteed by design and characterization. From I/O pins to VP or VN only. Human Body Model per MIL-STD-883, Method 3015, CDischarge = 100pF, RDischarge = 1.5KΩ, VP = 5.0V, VN grounded. Standard IEC 61000-4-2 with CDischarge = 150pF, RDischarge = 330Ω, VP = 5.0V, VN grounded. These measurements performed with no external capacitor on VP.. © 2004 California Micro Devices Corp. All rights reserved. 4 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 ▲ Tel: 408.263.3214 ▲ Fax: 408.263.7846 ▲ www.calmicro.com 01/09/04 CM1209 Performance Information 10 Slope = I/ZPOS Current [I] Cin (pF) 8 6 4 VZBD Slope = I/ZNEG 2 0 0 1 2 3 4 5 Voltage [V] Vin Figure 2. IV Curve for CM1209 Figure 1. Typical Variation of Channel Input Capacitance (CIN) vs. Channel Input Voltage (VIN) (VP = 5V via 10K resistor, VN = 0V) Application Information 3 CM1209-06 7 0.22µF* 1 24 5 6 8 Expansion Connector I/O Port Buffers Typical ESD Protection * Optional capacitor should be placed as close as possible to the VP pin on all CM1209 devices. Refer to ’Design Considerations’ text. Figure 3. Application Example Using the CM1209-06 for I/O Port Protection © 2004 California Micro Devices Corp. All rights reserved. 01/09/04 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 ▲ Tel: 408.263.3214 ▲ Fax: 408.263.7846 ▲ www.calmicro.com 5 CM1209 Application Information Design Considerations In order to realize the maximum protection against ESD pulses, care must be taken in the PCB layout to minimize parasitic series inductances on the Supply/ Ground rails as well as the signal trace segment between the signal input (typically a connector) and the ESD protection device. Refer to Figure 4, which illustrates an example of a positive ESD pulse striking an input channel. The parasitic series inductance back to the power supply is represented by L 1 and L2. The voltage VCL on the line being protected is: The CM1209 has an integrated Zener diode between VP and VN. This greatly reduces the effect of supply rail inductance L2 on VCL by clamping VP at the breakdown voltage of the Zener diode. However, for the lowest possible VCL, especially when VP is biased at a voltage significantly below the Zener breakdown voltage, it is recommended that a 0.22µF ceramic chip capacitor be connected between VP and the ground plane. As a general rule, the ESD Protection Array should be located as close as possible to the point of entry of expected electrostatic discharges. The power supply bypass capacitor mentioned above should be as close to the VP pin of the Protection Array as possible, with minimum PCB trace lengths to the power supply, ground planes and between the signal input and the ESD device to minimize stray series inductance. VCL = Fwd voltage drop of D1 + VSUPPLY + L1 x d(IESD ) / dt + L2 x d(IESD ) / dt where IESD is the ESD current pulse, and VSUPPLY is the positive supply voltage. An ESD current pulse can rise from zero to its peak value in a very short time. As an example, a level 4 contact discharge per the IEC61000-4-2 standard results in a current pulse that rises from zero to 30 Amps in 1ns. Here d(IESD)/dt can be approximated by Additional Information See California Micro Devices Application Note AP209, “Design Considerations for ESD Protection", under Applications at www.calmicro.com. ∆IESD/∆t, or 30/(1x10-9). So just 10nH of series inductance (L1 and L2 combined) will lead to a 300V increment in VCL! Similarly for negative ESD pulses, parasitic series inductance from the VN pin to the ground rail will lead to drastically increased negative voltage on the line being protected. L2 VP POSITIVE SUPPLY RAIL PATH OF ESD CURRENT PULSE IESD 0.22µF D1 ONE CHANNEL D2 OF CM1209 L1 LINE BEING PROTECTED SYSTEM OR CIRCUITRY BEING PROTECTED CHANNEL INPUT 20A VCL 0A VN GROUND RAIL CHASSIS GROUND Figure 4. Application of Positive ESD Pulse between Input Channel and Ground © 2004 California Micro Devices Corp. All rights reserved. 6 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 ▲ Tel: 408.263.3214 ▲ Fax: 408.263.7846 ▲ www.calmicro.com 01/09/04 CM1209 Mechanical Details CM1209 devices are packaged in 8-pin and 10-pin MSOP and 8-pin SOIC packages. Dimensions for these packages are presented on the following pages. For complete information on the MSOP-8/-10 or SOIC- 8 packages, see the specific California Micro Devices Package Information document. MSOP-8 Mechanical Specifications Mechanical Package Diagrams PACKAGE DIMENSIONS Package MSOP Pins 8 Dimensions TOP VIEW D Millimeters Min Inches Max Min A 0.87 1.17 0.034 0.046 0.05 0.25 0.002 0.010 0.30 (typ) C 0.012 (typ) 0.18 2.90 3.10 0.114 0.122 E 2.90 3.10 0.114 0.122 0.025 BSC H 4.78 4.98 0.188 0.196 L 0.52 0.54 0.017 0.025 # per tube 80 pieces* # per tape and reel 4000 pieces 5 E H 0.007 0.65 BSC 6 Pin 1 Marking D e 7 Max A1 B 8 1 2 3 4 SIDE VIEW A SEATING PLANE Controlling dimension: inches A1 B e * This is an approximate number which may vary. END VIEW C L Package Dimensions for MSOP-8 © 2004 California Micro Devices Corp. All rights reserved. 01/09/04 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 ▲ Tel: 408.263.3214 ▲ Fax: 408.263.7846 ▲ www.calmicro.com 7 CM1209 Mechanical Details (cont’d) MSOP-10 Mechanical Specifications Mechanical Package Diagrams PACKAGE DIMENSIONS Package MSOP Pins 10 Dimensions TOP VIEW D Millimeters Inches Min Max Min Max A 0.75 0.95 0.028 0.038 A1 0.05 0.15 0.002 0.006 B 0.18 0.40 0.006 C 0.18 0.016 9 2.90 3.10 0.114 0.122 E 2.90 3.10 0.114 0.122 0.50 BSC 4.76 5.00 0.187 0.197 L 0.40 0.70 0.0137 0.029 # per tube 80 pieces* # per tape and reel 4000 Controlling dimension: inches 6 7 E Pin 1 Marking 0.0196 BSC H 8 H 0.007 D e 10 1 2 3 5 4 SIDE VIEW A SEATING PLANE A1 B e * This is an approximate number which may vary. END VIEW C L Package Dimensions for MSOP-10 © 2004 California Micro Devices Corp. All rights reserved. 8 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 ▲ Tel: 408.263.3214 ▲ Fax: 408.263.7846 ▲ www.calmicro.com 01/09/04 CM1209 Mechanical Details (cont’d) SOIC-8 Mechanical Specifications Mechanical Package Diagrams PACKAGE DIMENSIONS Package SOIC Pins 8 Dimensions TOP VIEW Millimeters Min Max Min Max A 1.35 1.75 0.053 0.069 A1 0.10 0.25 0.004 0.010 B 0.33 0.51 0.013 0.020 C 0.19 0.25 0.007 0.010 D 4.80 5.00 0.189 0.197 E 3.80 4.19 0.150 0.165 e D Inches 1.27 BSC 8 5.80 6.20 0.228 0.244 L 0.40 1.27 0.016 0.050 # per tube 100 pcs* # per tape and reel 2500 pcs 6 5 E H Pin 1 Marking 0.050 BSC H 7 1 2 3 4 SIDE VIEW A SEATING PLANE Controlling dimension: inches A1 B e * This is an approximate number which may vary. END VIEW C L Package Dimensions for SOIC-8 © 2004 California Micro Devices Corp. All rights reserved. 01/09/04 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 ▲ Tel: 408.263.3214 ▲ Fax: 408.263.7846 ▲ www.calmicro.com 9