MC10EL34, MC100EL34 5VECL ÷2, ÷4, ÷8 Clock Generation Chip The MC10/100EL34 is a low skew ÷2, ÷4, ÷8 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 F capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open. The common enable (EN) is synchronous so that the internal dividers will only be enabled/disabled when the internal clock is already in the LOW state. This avoids any chance of generating a runt clock pulse on the internal clock when the device is enabled/disabled as can happen with an asynchronous control. An internal runt pulse could lead to losing synchronization between the internal divider stages. The internal enable flip-flop is clocked on the falling edge of the input clock, therefore, all associated specification limits are referenced to the negative edge of the clock input. Upon startup, the internal flip-flops will attain a random state; the master reset (MR) input allows for the synchronization of the internal dividers, as well as multiple EL34s in a system. The 100 Series contains temperature compensation. • • • • • • 50 ps Output-to-Output Skew Synchronous Enable/Disable Master Reset for Synchronization ESD Protection: > 1 KV HBM, > 100 V MM http://onsemi.com MARKING DIAGRAMS 16 SO–16 D SUFFIX CASE 751B 16 1 A WL YY WW 10EL34 AWLYWW 1 = Assembly Location = Wafer Lot = Year = Work Week 16 100EL34 AWLYWW 1 ORDERING INFORMATION Device Package Shipping MC10EL34D SO–16 48 Units / Rail MC10EL34DR2 SO–16 2500 Units / Reel MC100EL34D SO–16 48 Units / Rail MC100EL34DR2 SO–16 2500 Units / Reel PECL Mode Operating Range: VCC= 4.2 V to 5.7 V with VEE= 0 V NECL Mode Operating Range: VCC= 0 V with VEE= –4.2 V to –5.7 V Internal Input Pulldown Resistors on CLK(s), EN, and MR Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test • • • Moisture Sensitivity Level 1 For Additional Information, see Application Note AND8003/D • Flammability Rating: UL–94 code V–0 @ 1/8”, Oxygen Index 28 to 34 • Transistor Count = 191 devices Semiconductor Components Industries, LLC, 2000 October, 2000 – Rev. 3 1 Publication Order Number: MC10EL34/D MC10EL34, MC100EL34 LOGIC DIAGRAM AND PINOUT ASSIGNMENT VCC EN NC CLK 16 15 14 CLK VBB 13 12 11 MR VEE 10 9 FUNCTION TABLE D Q R ÷2 Q R ÷4 Q R Q ÷8 CLK* EN* MR* FUNCTION Z ZZ X L H X L L H Divide Hold Q0–3 Reset Q0–3 R 1 2 3 4 5 6 7 8 Q0 Q0 VCC Q1 Q1 VCC Q2 Q2 Z = Low-to-High Transition ZZ = High-to-Low Transition * Pins will default low when left open. * All VCC pins are tied together on the die. Warning: All VCC and VEE pins must be externally connected to Power Supply to guarantee proper operation. PIN DESCRIPTION PIN FUNCTION CLK, CLK EN MR Q0, Q0 Q1, Q1 Q2, Q2 VBB VCC VEE NC ECL Diff Clock Inputs ECL Sync Enable ECL Master Reset ECL Diff ÷2 Outputs ECL Diff ÷4 Outputs ECL Diff ÷8 Outputs Reference Voltage Output Positive Supply Negative Supply No Connect MAXIMUM RATINGS (Note 1.) Symbol Parameter Condition 1 Condition 2 Rating Units 8 V VCC PECL Mode Power Supply VEE = 0 V VEE NECL Mode Power Supply VCC = 0 V –8 V VI PECL C Mode ode Input u Voltage o age VEE = 0 V VI VCC 6 V NECL Mode Input Voltage VCC = 0 V VI VEE –6 V Iout Output Current Continuous Surge 50 100 mA mA IBB VBB Sink/Source ± 0.5 mA TA Operating Temperature Range –40 to +85 °C Tstg Storage Temperature Range –65 to +150 °C θJA Thermal Resistance (Junction to Ambient) 0 LFPM 500 LFPM 16 SOIC 16 SOIC 130 75 °C/W °C/W θJC Thermal Resistance (Junction to Case) std bd 16 SOIC 33 to 36 °C/W Tsol Wave Solder <2 to 3 sec @ 248°C 265 °C 1. Maximum Ratings are those values beyond which device damage may occur. http://onsemi.com 2 MC10EL34, MC100EL34 10EL SERIES PECL DC CHARACTERISTICS VCC= 5.0 V; VEE= 0.0 V (Note 1.) –40°C Symbol Characteristic Min Typ 25°C Max Min Typ 39 85°C Max Min Typ 39 Max Unit 39 mA IEE Power Supply Current VOH Output HIGH Voltage (Note 2.) 3920 4010 4110 4020 4105 4190 4090 4185 4280 mV VOL Output LOW Voltage (Note 2.) 3050 3200 3350 3050 3210 3370 3050 3227 3405 mV VIH Input HIGH Voltage (Single Ended) 3770 4110 3870 4190 3940 4280 mV VIL Input LOW Voltage (Single Ended) 3050 3500 3050 3520 3050 3555 mV VBB Output Voltage Reference 3.57 3.7 3.65 3.75 3.69 3.81 V VIHCMR Input HIGH Voltage Common Mode Range (Differential) (Note 3.) 3.0 4.6 3.0 4.6 3.0 4.6 V IIH Input HIGH Current 150 µA IIL Input LOW Current 150 0.5 150 0.5 µA 0.3 NOTE: Devices are designed to meet the DC specifications shown in the above table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained. 1. Input and output parameters vary 1:1 with VCC. VEE can vary +0.06 V / –0.5 V. 2. Outputs are terminated through a 50 ohm resistor to VCC–2 volts. 3. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between VPPmin and 1V. 10EL SERIES NECL DC CHARACTERISTICS VCC= 0.0 V; VEE= –5.0 V (Note 1.) –40°C Symbol Characteristic 25°C Min Typ Max 85°C Min Typ Max 39 Min Typ Max Unit IEE Power Supply Current 39 mA VOH Output HIGH Voltage (Note 2.) –1080 –990 –890 –980 –895 –810 39 –910 –815 –720 mV VOL Output LOW Voltage (Note 2.) –1950 –1800 –1650 –1950 –1790 –1630 –1950 –1773 –1595 mV VIH Input HIGH Voltage (Single Ended) –1230 –890 –1130 –810 –1060 –720 mV VIL Input LOW Voltage (Single Ended) –1950 –1500 –1950 –1480 –1950 –1445 mV VBB Output Voltage Reference –1.43 –1.30 –1.35 –1.25 –1.31 –1.19 V VIHCMR Input HIGH Voltage Common Mode Range (Differential) (Note 3.) –2.0 –0.4 –2.0 –0.4 –2.0 –0.4 V IIH Input HIGH Current 150 µA IIL Input LOW Current 150 0.5 150 0.5 0.3 µA NOTE: Devices are designed to meet the DC specifications shown in the above table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained. 1. Input and output parameters vary 1:1 with VCC. VEE can vary +0.06 V / –0.5 V. 2. Outputs are terminated through a 50 ohm resistor to VCC–2 volts. 3. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between VPPmin and 1V. http://onsemi.com 3 MC10EL34, MC100EL34 100EL SERIES PECL DC CHARACTERISTICS VCC= 5.0 V; VEE= 0.0 V (Note 1.) –40°C Symbol Characteristic Min Typ 25°C Max Min Typ 39 85°C Max Min Typ 39 Max Unit 42 mA IEE Power Supply Current VOH Output HIGH Voltage (Note 2.) 3915 3995 4120 3975 4045 4120 3975 4050 4120 mV VOL Output LOW Voltage (Note 2.) 3170 3305 3445 3190 3295 3380 3190 3295 3380 mV VIH Input HIGH Voltage (Single Ended) 3835 4120 3835 4120 3835 4120 mV VIL Input LOW Voltage (Single Ended) 3190 3525 3190 3525 3190 3525 mV VBB Output Voltage Reference 3.62 3.74 3.62 3.74 3.62 3.74 V VIHCMR Input HIGH Voltage Common Mode Range (Differential) (Note 3.) 2.2 4.6 2.2 4.6 2.2 4.6 V IIH Input HIGH Current 150 µA IIL Input LOW Current 150 0.5 150 0.5 µA 0.5 NOTE: Devices are designed to meet the DC specifications shown in the above table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained. 1. Input and output parameters vary 1:1 with VCC. VEE can vary +0.8 V / –0.5 V. 2. Outputs are terminated through a 50 ohm resistor to VCC–2 volts. 3. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between VPPmin and 1V. 100EL SERIES NECL DC CHARACTERISTICS VCC= 0.0 V; VEE= –5.0 V (Note 1.) –40°C Symbol Characteristic 25°C Min Typ Max 85°C Min Typ Max 39 Min Typ Max Unit IEE Power Supply Current 42 mA VOH Output HIGH Voltage (Note 2.) –1085 –1005 –880 –1025 –955 –880 39 –1025 –955 –880 mV VOL Output LOW Voltage (Note 2.) –1830 –1695 –1555 –1810 –1705 –1620 –1810 –1705 –1620 mV VIH Input HIGH Voltage (Single Ended) –1165 –880 –1165 –880 –1165 –880 mV VIL Input LOW Voltage (Single Ended) –1810 –1475 –1810 –1475 –1810 –1475 mV VBB Output Voltage Reference –1.38 –1.26 –1.38 –1.26 –1.38 –1.26 V VIHCMR Input HIGH Voltage Common Mode Range (Differential) (Note 3.) –2.8 –0.4 –2.8 –0.4 –2.8 –0.4 V IIH Input HIGH Current 150 µA IIL Input LOW Current 150 0.5 150 0.5 0.5 µA NOTE: Devices are designed to meet the DC specifications shown in the above table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained. 1. Input and output parameters vary 1:1 with VCC. VEE can vary +0.8 V / –0.5 V. 2. Outputs are terminated through a 50 ohm resistor to VCC–2 volts. 3. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between VPPmin and 1V. http://onsemi.com 4 MC10EL34, MC100EL34 AC CHARACTERISTICS VCC= 5.0 V; VEE= 0.0 V or VCC= 0.0 V; VEE= –5.0 V (Note 1.) –40°C Symbol Characteristic Min Typ 25°C Max Min Typ Max Min Max tPLH tPHL Propagation Delay to Output tSKEW Within-Device Skew (Note 2.) 100 100 100 ps tJITTER Cycle–to–Cycle Jitter TBD TBD TBD ps tS Setup Time EN 400 400 400 ps tH Hold Time EN 250 250 250 ps tRR Set/Reset Recovery 400 VPP Input Swing (Note 3.) 150 1000 150 1000 150 1000 mV tr tf Output Rise/Fall Times Q (20% – 80%) 275 525 275 525 275 525 ps 1200 1140 1060 200 960 900 750 400 TBD Unit Maximum Toggle Frequency 960 900 750 TBD Typ fmax CLK to Q0 CLK to Q1,2 MR to Q TBD 85°C 1200 1140 1060 200 970 910 790 400 GHz 1210 1150 1090 200 ps 1. 10 Series: VEE can vary +0.06 V / –0.5 V. 100 Series: VEE can vary +0.8 V / –0.5 V. 2. Within-device skew is defined as identical transitions on similar paths through a device. 3. VPP(min) is minimum input swing for which AC parameters guaranteed. The device has a DC gain of ≈40. tRR Internal Clock Disabled Internal Clock Enabled RESET CLK Q0 Q1 Q2 EN The EN signal will freeze the internal clocks to the flip–flops on the first falling edge of CLK after its assertion. The internal dividers will maintain their state during the internal clock freeze and will return to clocking once the internal clocks are unfrozen. The outputs will transition to their next states in the same manner, time and relationship as they would have had the EN signal not been asserted. Figure 1. Timing Diagram http://onsemi.com 5 ps MC10EL34, MC100EL34 Q D Receiver Device Driver Device Qb Db 50 50 V TT V TT = V CC – 2.0 V Figure 2. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020 – Termination of ECL Logic Devices.) Resource Reference of Application Notes AN1404 – ECLinPS Circuit Performance at Non–Standard VIH Levels AN1405 – ECL Clock Distribution Techniques AN1406 – Designing with PECL (ECL at +5.0 V) AN1503 – ECLinPS I/O SPICE Modeling Kit AN1504 – Metastability and the ECLinPS Family AN1560 – Low Voltage ECLinPS SPICE Modeling Kit AN1568 – Interfacing Between LVDS and ECL AN1596 – ECLinPS Lite Translator ELT Family SPICE I/O Model Kit AN1650 – Using Wire–OR Ties in ECLinPS Designs AN1672 – The ECL Translator Guide AND8001 – Odd Number Counters Design AND8002 – Marking and Date Codes AND8020 – Termination of ECL Logic Devices http://onsemi.com 6 MC10EL34, MC100EL34 PACKAGE DIMENSIONS SO–16 D SUFFIX CASE 751B–05 ISSUE J –A – 16 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 9 –B – 1 P 8 PL 0.25 (0.010) 8 M B M G K F R X 45° C –T SEATING – PLANE D16PL 0.25 (0.010) J M M T B S A S http://onsemi.com 7 DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0° 7° 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 7° 0° 0.229 0.244 0.010 0.019 MC10EL34, MC100EL34 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. 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