AIC AIC1574 5-bit dac, synchronous pwm power regulator with triple linear controller Datasheet

AIC1574
5-bit DAC, Synchronous PWM Power Regulator
with Triple Linear Controllers
n FEATURES
n DESCRIPTION
The AIC1574 combines a synchronous voltage mode
l
Compatible with HIP6021.
l
Provides 4 Regulated Voltages for Microprocessor
Core, AGP Bus, Memory and GTL Bus Power.
l
l
l
l
l
controller with three linear controller as well as the
monitoring and protection functions in this chip. The
PWM controller regulates the microprocessor core
TTL Compatible 5-bit Digital-to-Analog Core Output
voltage with a synchronous rectified buck converter.
Voltage Selection. Range from 1.3V to 3.5V.
The three linear controllers regulate power for the
0.1V Steps from 2.1V to 3.5V.
1.5V or 3.3V AGP bus power, the 1.5V GTL bus and
0.05V Steps from 1.3V to 2.05V.
the 1.8V power for the chip set core voltage and/or
±1.0% Output Voltage for VCORE, ±3.0% Accu-
cache memory circuits.
racy for Linear Controller Outputs.
An integrated 5 bit D/A converter that adjusts the
Simple Voltage-Mode PWM Control and Built in
core PWM output voltage from 2.1V to 3.5V in 0.1V
Internal Compensation Networks.
increments and from 1.3V to 2.05V in 0.05V incre-
N-Channel MOSFET Driver for PWM Buck Con-
ments. The linear controller for AGP bus power is
verter.
selectable by TTL-compatible SELECT pin status for
Linear Controller Drives Compatible with both N–
1.5V or 3.3V with ±3% accuracy. The other two
Chanel MOSFET and NPN Bipolar Series Pass
linear controller provide 1.5V±3% and 1.8V±3% or
Transistor.
adjustable output voltage by means of external divided resistor based on FIX pin status.
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Operates from +3.3V, +5V and +12V Inputs.
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Fast Transient Response.
This chip monitors all the output voltages. Power
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Full 0% to 100% Duty Ratios.
Good signal is issued when the core voltage is
l
Adjustable Current Limit without External Sense
Resistor.
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within ±10% of the DAC setting and the other levels
are above their under-voltage levels. Over-voltage
protection for the core output uses the lower N-
Microprocessor Core Voltage Protection against
Upper MOSFET shorted to +5V.
channel MOSFET to prevent output voltage above
116% of the DAC setting.
l
Power Good Output Voltage Monitor.
l
Over-Voltage and Over-Current Fault Monitors.
l
200KHz Free-Running Oscillator Programmable up
to 700KHz.
The PWM over-current function monitors the output
current by using the voltage drop across the upper
MOSFET’s RDS(ON), eliminating the need for a current sensing resistor.
n APPLICATIONS
l
Full Motherboard Power Regulation for Computers.
Analog Integrations Corporation 4F, 9, Industry E. 9th Rd, Science Based Industrial Park, Hsinchu Taiwan, ROC
DS-1574-00 May 22, 01
TEL: 886-3-5772500
FAX: 886-3-5772510
www.analog.com.tw
1
AIC1574
n TYPICAL APPLICATION
+12VIN
10
2.2 µF
VCC
28
L1
+3.3VIN
VAUX
16
OCSET1
27
DRIVE2
Q3
VOUT2
1
3.3V or 1.5V
+5VIN
23
26
VSEN2
1 µH
+
GND
UGATE1
Q1
PHASE1
VOUT1
10
+
25
L1
LGATE1
Q2
COUT2
24
SELECT
DRIVE3
COUT1
D5820
PGND
11
22
Q4
+
18
VSEN1
FB
21
VOUT3
1.5V
VSEN3
19
+
COUT3
SD
9
20
Q5
VOUT4
DRIVE4
VESN4
7
15
6
5
14
4
1.8V
+
3
COUT4
FIX
8
2
13
NC
VID0
VID1
VID2
VID3
VID4
PGOOD
FAULT/RT
SS
17
GND
12
Css
2
AIC1574
n ORDERING INFORMATION
AIC1574-CX
PACKAGING TYPE
S: SMALL OUTLINE
ORDER NUMBER
AIC157 4CS
(SO2 8)
PIN CONFIGURATION
DRIVE2
1
28 VCC
FIX
2
27 UGATE1
VID 4 3
26 PHASE1
VID 3 4
25 LGATE1
VID 2 5
24 PGND
VID 1 6
23 OCSET
VID0 7
PGOOD 8
SD 9
22 VSEN1
21 FB
20 NC
VSEN2 10
19 VSEN3
SELECT 11
18 DRIVE3
S S 12
FAULT/RT 13
VSEN4 14
17 GND
16 VAUX
15 DRIVE4
n ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC ...............… … … … … .....… … … … ...… … ...… ..… … ..................... +15V
PGOOD, FAULT and GATE Voltage ...… … … … .....… … … ..… .... GND -0.3V to VCC +0.3V
Input, Output , or I/O Voltage
......… ...… … … … … … … … ..… … ............ GND -0.3V to 7V
Recommended Operating Conditions
Supply Voltage; VCC… … ...............… … … … ..................... +12V±10%
Ambient temperature Range … … ..… … … … … … ................. 0°C~70°C
Junction Temperature Range … … ......… ..… … .................. 0°C~125°C
Thermal Information
Thermal Resistance, θJA
SOIC package … … … … … … … … … … … ..… … ..… … .............. 70°C/W
SOIC package (with 3in2 of copper) … ...… … … .........… ......... 50°C/W
Maximum Junction Temperature (Plastic Package)
Maximum Storage Temperature Range
… … … … … … … ..… … ...... 150°C
… … … … … … … … … … … .... -65°C ~ 150°C
Maximum Lead Temperature (Soldering 10 sec)
… … … … … … … … … … ..… ... 300°C
n TEST CIRCUIT
Refer to APPLICATION CIRCUIT.
3
AIC1574
n ELECTRICAL CHARACTERISTICS
PARAMETER
(Vcc=12V, TJ=25°C, Unless otherwise specified)
TEST CONDITIONS
SYMBOL
MIN.
TYP.
MAX.
UNIT
VCC SUPPLY CURRENT
Supply Current
UGATE, LGATE, GATE3 and
VOUT2 open
ICC
3
mA
POWER ON RESET
Rising VCC Threshold
VOCSET=4.5V
Falling VCC Threshold
VOCSET=4.5V
VCCTHR
VCCTHF
10.4
8.2
V
V
Rising VAUX Threshold
VAUXTHR
2.5
V
VAUX Threshold Hysteresis
VAUXHYS
500
mV
Rising VOCSET1 Threshold
VOCSETH
1.26
V
OSCILLATOR
Free Running Frequency
RT=Open
Total Variation
6kΩ<RT to GND<200kΩ
Ramp. Amplitude
RT=open
F
170
200
-15
∆VOSC
230
KHz
+15
%
1.5
VP-P
REFERENCE AND DAC
DAC (VID0~VID4) Input Low
VIDL
Voltage
DAC (VID0~VID4) Input High
VIDH
Voltage
DACOUT Voltage Accuracy
VDAC=1.8V~3.5V
Bandgap Reference Voltage
0.8
2.0
V
-1.0
VREF
Bandgap Reference Toler-
+1.0
1.265
-2.5
ance
V
%
V
+2.5
%
LINEAR REGULATOR (OUT2, OUT3, OUT4)
Regulation
3
%
VSEN2 Regulation Voltage
Select<0.8V
VREG2
1.5
V
VSEN2 Regulation Voltage
Select>2.0V
VREG2
3.3
V
VSEN3 Regulation Voltage
VREG3
1.5
V
VSEN3 Regulation Voltage
VREG4
1.8
V
VSENUV
75
%
5
%
30
mA
Under-Voltage Level
( VSEN/VREG)
Under-Voltage Hysteresis
(V SEN/VREG)
Output Drive Current (All
Linears )
VSEN Rising
VSEN Falling
VAUX -V DRIVE > 0.6V
20
4
AIC1574
n ELECTRICAL CHARACTERISTICS
PARAMETER
TEST CONDITIONS
(Continued)
SYMBOL
MIN.
TYP.
MAX.
UNIT
SYNCHRONOUS PWM CONTROLLER AMPLIFIER
DC Gain
(G.B.D.)
Gain-Bandwidth Product
(G.B.D.)
Slew Rate
(G.B.D.) note 1.
80
dB
GBWP
13
MHz
SR
6
V/µs
A
PWM CONTROLLER GATE DRIVER
Upper Drive Source
VCC=12V, VUGATE = 6V
IUGH
0.9
Upper Drive Sink
VUGATE=1V
RUGL
2.8
Lower Drive Source
VCC=12V, VLGATE =6V
ILGH
1
Lower Drive Sink
VLGATE=1V
RLGL
2.2
3.0
Ω
VSEN1 Rising
OVP
116
120
%
FAULT Sourcing Current
VCC-VFAULT/RT =2.0V
IOVP
20
OCSET Current Source
VOCSET =4.5VDC
3.5
Ω
A
PROTECTION
VSEN1 Over-Voltage
( VSEN1 /DACOUT )
Soft-Start Current
IOCSET
170
ISS
200
mA
230
µA
µA
25
POWER GOOD
VSEN1 Upper Threshold
( VSEN1 /DA COUT )
VSEN1 Under-Voltage
( VSEN1/DACOUT )
VSEN1 Hysteresis
(VSEN1/DACOUT)
PGOOD Voltage Low
VSEN1 Rising
108
111
%
VSEN Falling
92
95
%
Upper and Lower Threshold
IPGOOD=-4mA
2
VPGOOD
0.4
%
0.8
V
Note 1. Without internal compensation network, the gain bandwidth product is 13MHz. Being associated with internal compensation networks, the Bode Plot is shown in Fig. 3, “Internal Compensation Gain of PWM Error Amplifier”.
5
AIC1574
n TYPICAL PERFORMANCE CHARACTERISTICS
PGOOD
SS
SS
VDAC=3.5V
VOUT3
VOUT4
VDAC=2V
VDAC=1.3V
VOUT2
VOUT1
Fig. 1 Soft Start Interval with 4 Outputs and P GOOD
Fig. 2
Soft Start Initiates PWM Output
R T Resistance vs. Frequency
Internal Compensation Gain of PWM Error Amplifier
10M
30
90 °C
25
RT Pull Up to 12V
Gain (dB)
20
Resistance (Ω)
1M
-40 °C
22°C
15
RT Pull Down to GND
100k
10
5
10k
0
1k
10k
-5
1k
10k
Fig. 3
100k
1M
100k
Fig. 4
Frequency (Hz)
1M
Switching Frequency (Hz)
Over Current ON Inductor
Supply Current vs. Frequency
120
Over Load
VCC=12V
100
C=4.7nF
CUG1=C LG1=C
Inductor
Applied
Current 5A/div
ICC (mA)
80
C=3.3nF
60
C=1.5nF
SS
40
C=680pF
20
Fault
0
200k
C=0
300k
Fig. 5
400k
500k
600k
700k
800k
Switching Frequency (Hz)
900k
1M
Fig. 6
6
AIC1574
n TYPICAL PERFORMANCE CHARACTERISTICS (Continued)
Temperature vs. Switching Frequency Drift
4
FSW =200KHz
3
2
Switching Frequency Drift (%)
0.1A to 3A
Load Step
V OUT
1
0
-1
-2
-3
-4
-5
-6
-7
-8
-40
Fig. 7 Load Transient of Linear Controller
-20
Temperature vs. OCSET Current Drift
40
60
80
100
120
100
120
Temperature Drift of 9 Different Parts
0.4
OCSET Current = 200 µA
5
0.3
4
VSEN2 Voltage Drift (%)
OCSET Current Drift (%)
20
Temperature (°C)
Fig. 8
6
3
2
1
0.2
0.1
0.0
-0.1
0
-0.2
-1
-0.3
-2
-3
-0.4
-4
-0.5
-5
-0.6
-6
VREG2=3.3V
-0.7
-7
-8
-40
-20
0
20
40
60
80
100
120
-0.8
-40
Temperature (°C)
Fig. 9
-20
0
20
40
60
80
Temperature (° C)
Fig. 10
Temperature Drift of 13 Different Parts
Temperature Drift of 9 Different Parts
0.4
0.4
0.3
0.3
0. 2
0.2
VSEN4 Voltage Drift (%)
PWM Output Voltage Drift (%)
0
0.1
0.0
-0. 1
0.1
0.0
-0.1
-0.2
-0.2
-0.3
-0.3
-0.4
-0.4
DACOUT=1.6V
-0.5
-0.5
-0.6
VREG4=1.8V
-0.6
-0.7
-40
-20
Fig. 11
0
20
40
60
Temperature (° C)
80
100
120
-0.7
-40
-20
Fig. 12
0
20
40
60
80
100
120
Temperature (°C)
7
AIC1574
n TYPICAL PERFORMANCE CHARACTERISTICS (Continued)
0 to 20A Load Step
V OUT1
0 to 20A Load Step
Fig. 13
VOUT1
Load Transient of PWM Output
Fig. 14
Stringent Load Transient of PWM Output
Bandgap Voltage Accuracy
FB Voltage Accuracy
70
60
Mean= -0.03%
FIX=0V
60
Ta = 25 °C
Ta = 25° C
3 std.= 0.8%
3 std.= 0.56%
Number of Parts
Number of Parts
50
Mean=1.266V
DACOUT=1.6V
40
30
20
50
40
30
20
10
10
0
0
-0.6
Fig. 15
-0.4
-0.2
0.0
0.2
Accuracy (%)
0.4
0.6
1.255
Fig. 16
1.260
1.265
1.270
1.275
Bandgap Voltage (V)
8
SS
INHB
VSEN2
POR
FIX
x 75%
SELECT
1.5V or 3.3V
1.26V
X 75%
0.2V
SS
4V
PHASE1
200uA
LUV
UGATE1
UP
PGND
DRV-L
VCC
R
SS
DRV-H
VCC
RESET
COUNTER
(3)
R
LGATE1
OC1
OVER
LATCH
FAULT
LOGIC
SOFT START
POR
R
LATCH
CURRENT
CONTROL
GATE
VSEN1
DRIVE2
VAUX
RESET
ON
POWER
VAUX
INHB
VCC
OCSET1
SD
VAUX
INHB
VSEN4
DRIVE4
DRIVE3
VAUX
VSEN3
COMP1
INHB
OV
NC
RAMP1
x 116%
x 110%
X 90%
RAMP1
Comp.
3 P, 2Z
OFF
ERROR
AMP1
DACOUT
VSEN1
FB
4.5V
25uA
VCC
CONVERTER
TTL D/A
OSCILLATOR
VCC
PGOOD
GND
SS
VID4
VID3
VID2
VID1
VID0
RT
FAULT /
AIC1574
n BLOCK DIAGRAM
9
AIC1574
n PIN DESCRIPTION
the other outputs are below their
Pin 1: DRIVE2: Connect this pin to the Gate of
under-voltage
the external N-MOS to supply
thresholds.
The
PGOOD output is open for VID
AGP power.
codes that inhibit operation. See
Pin 2 :
FIX:
Left this pin open, its
Table 1.
voltage is pulled high, enabling
fixed output voltage operation for
1.5V and 1.8V linear regulators. If
connect this pin to Ground, the
new output voltage set by external
resistors
RGND (Connected be-
tween VSEN and GND) and ROUT
(Connected between VSEN and
SD:
A
TTL-compatibe
logic level high signal applied
this pin immediately discharges
the soft-start capacitors, disabling all the outputs. Dedicated
internal circuitry insures the core
output voltage does not go nective during this process. When
VOUT) .
VOUT
Pin 9 :
1.265V × (R GND + ROUT )
=
RGND
re-enabled, this IC undergoes a
new soft-start cycle. Left open,
this pin is pulled low by an inter-
Pin 7: VID4:
nal pull-down resistor, enabling
Pin 6: VID3:
operation.
Pin 5: VID2:
Pin 10:VSEN2: Connect this pin to the output of
Pin 4: VID1:
Pin 3: VID0:
5bit DAC voltage select pin. TTLcompatible inputs used to set the
internal voltage reference VDAC.
When left open, these pins are internally pulled up to 5V and
provide logic ones. The level of
VDAC sets the converter output
voltage as well as the PGOOD
Table 1 specifies the VDAC voltage for the 32 combinations of
DAC inputs.
good
voltage at this pin is regulated to
the 1.5V/3.3V predetermined by
the logic Low/High level ststus of
the SELECT pin. This pin is also
monitored
for
under-voltage
events.
Pin 11:SELECT: This pin determines the output
voltage of the AGP bus linear
and OVP thresholds.
Pin 8: PGOOD: Power
the AGP linear regulator. The
regulator. A low TTL input sets
the output voltage to 1.5V, while
a high input sets the output voltage to 3.3V.
indicator
pin.
PGOOD is an open drain output.
This pin is pulled low when the
converter output is ±10% out of
the VDAC reference voltage and
10
AIC1574
Pin 12:SS:
Soft-start pin. Connect a ca-
Pin 17: GND:
Signal GND for IC. All voltage lev-
pacitor from this pin to ground.
els are measured with respect to
This capacitor, along with an
this pin.
internal 25µA (typically) cur-
Pin 18: DRIVE3: Connect this pin to the Gate of
rent source, sets the soft-start
the external N-MOS for providing
interval of the converter. Pulling
1.5V power to GTL bus.
this pin low will shut down the
Pin 19: VSEN3:
IC.
Connect this pin to
the 1.5V linear regulator’s output.
Pin 13: FAULT/RT: Frequency adjustment pin.
Connecting
a
resistor
This pin is monitored for under-
(RT)
voltage events.
from this pin to GND, increasing the frequency. Connecting
Pin 20: NC:
Not Connected.
a resistor (RT) from this pin to
Pin 21: FB:
The error amplifier inverting input
VCC, decreasing the frequency by the following figure (Fig.
4).
pin.
Pin 22: VSEN1: Converter output voltage sense
pin. Connect this pin to the con-
This pin is 1.26V during normal
verter output. The PGOOD and
operation, but it is pulled to
OVP comparator circuits use
VCC in the event of an over-
this signal to report output volt-
voltage or over-current condition.
age status and for over-voltage

25 .2K 
 , RT pulled to
f = f0 1 +
RT 

GND
protection function.
 VCC − 1.26V
f = f0 1 −
5 × RT

pulled to VCC,

,


Pin 23: OCSET:Current limit sense pin. Connect
a resistor ROCSET from this pin
to the drain of the external high-
RT
side N-MOSFET. ROCSET , an in-
where f0 is free run frequency.
ternal 200µA
current
(IOCSET ),
the
and
source
upper
N-
MOSFET on-resistance (RDS(ON))
Pin14:
VSEN4:
Connect this pin to
set the over-current trip point
the 1.8V linear regulator’s output.
according to the following equa-
This pin is monitored for under-
tion:
voltage events.
Pin15:
DRIVE4:
IPEAK =
Connect this pin to
IOCSET × R OCSET
R DS(ON)
the Gate of the external N-MOS to
drive for the 1~8V power.
Pin 24:PGND:
Driver power GND pin. PGND
should be connected to a low
Pin 16: VAUX:
This pin provides boost current for
impedance
ground
the linear regulator’s output. The
close
lower
voltage at this pin is also moni-
source.
to
plane
in
N-MOSFET
tored for power-on-reset purpose.
11
AIC1574
Pin 25: LGATE: Lower N-MOSFET gate drive pin.
Pin 26: PHASE: Over-current detection pin. Con-
ternal upper N-MOSFET gate.
Pin 28: VCC:
The chip power supply pin. It also
nect the PHASE pin to source of
provides the gate bias charge for
the external upper N-MOSFET.
all the MOSFETs controlled by
This pin detects the voltage drop
the IC. Recommended supply
across the upper N-MOSFET
voltage is 12V. The voltage at this
RDS(ON) for over-current protection.
pin is monitored for Power-OnReset purpose.
Pin 27: UGATE: Connect UGATE to pin of the ex-
n APPLICATION INFORMATIONS
The AIC1574 is designed for microprocessor computer
applications with 3.3V and 5V power, and 12V bias input. This IC has one synchronous PWM controller and
three linear controllers. The PWM controller is designed to regulate the microprocessor core voltage
(V OUT1 ) by driving 2 MOSFETs (Q1 and Q2) in a synchronous rectified buck converter configuration. The
core voltage is regulated to a level programmed by the
5-bit D/A converter. One of the linear controllers is
designed to regulate the advanced graphic port (AGP)
bus voltage (V OUT2) to a digitally programmable level
1.5V or 3.3V. Selection of either output voltage is
PWM error amplifier reference input (Non-inverting terminal) and output is clamped to a level proportional to
the SS pin voltage. As the SS pin voltage slew from 1V
to 4V, the output clamp generates PHASE pulses of
increasing width that charge the output capacitors. After the the output voltage increases to approximately
70% of the set value, the reference input clamp slows
the output voltage rate-to rise and provides a smooth
transition to the final set voltage. Additionally, all linear
regulator’s reference inputs are clamped to a voltage
proportional to the SS pin voltage. This method
provides a rapid and controlled output voltage rise.
achieved by applying the proper logic level at the SE-
Fig. 1 and Fig. 2 show the soft-start sequence for the
LECT pin. The remaining two linear controllers supply
typical application. The internal oscillator’s triangular
the 1.5V GTL bus power (V OUT3) and 1.8V memory
waveform is compared to the clamped error amplifier
power (V OUT4). All linear controllers are designed to
output voltage. As the SS pin voltage increases, the
employ an external pass transistor.
pulse width on PHASE pin increases. The interval of
The Power-On Reset (POR) function continually monitors the input supply voltage +12V at VCC pin, the 5V
input voltage at OCSET pin, and the 3.3V input at
increasing pulse width continues until output reaches
sufficient voltage to transfer control to the input reference clamp.
VAUX pin. The POR function initiates soft-start opera-
Each linear output initially follows a ramp. When each
tion after all three input supply voltage exceed their
output reaches sufficient voltage the input reference
POR thresholds.
clamp slows the rate of output voltage rise. The
Soft-Start
PGOOD signal toggles ‘high’ when all output voltage
levels have exceeded their under-voltage levels.
The POR function initiates the soft-start sequence. An
internal 25µA current source charges an external capacitor (CSS) on the SS pin from 0V to 4.5V. The
Fault Protection
All four outputs are monitored and protected against
12
AIC1574
extreme overload. A sustained overload on any output
and
drive
the
FAULT/RT
pin
to
VCC.
or over-voltage on PWM output disable all converters
OVER CURRENT
LATCH
LUV
S
OC1
R
0.15V
INHIBIT
Q
S
COUNTER
R
+
FAULT LATCH
VCC
S
SS
POR
+
R
Q
FAULT
4.0V
OV
Fig. 17 Simplified Schematic of Fault Logic
A simplified schematic is shown in figure 17. An
A separate over-voltage circuit provides protection
over-voltage detected on VSEN1 immediately sets
during the initial application of power. For voltage on
the fault latch. A sequence of three over-current
VCC pin below the power-on reset (and above ~4V),
fault signals also sets the fault latch. An under-
should VSEN1 exceed 1.0V, the lower MOSFET
voltage event on either linear output (VSEN2,
(Q2) is driven on as needed to regulate VOUT1 to
VSEN3, VSEN4) is ignored until the soft-start inter-
1.0V.
val. Cycling the bias input voltage (+12V off then on)
resets the counter and the fault latch.
Over-Current Protection
Gate Drive Overlap Protection
All outputs are protected against excessive overcurrent.
The
PWM
controller
uses
upper
The Overlap Protection circuit ensures that the Bot-
MOSFET’s on-resistance, RDS(ON) to monitor the
tom MOSFET does not turn on until the Upper
current for protection against shorted outputs. All
MOSFET source has reached a voltage low enough
linear controllers monitor VSEN for under-voltage
to ensure that shoot-through will not occur.
events to protect against excessive current.
Over-Voltage Protection
When the voltage across Q1 (ID•RDS(ON)) exceeds
During operation, a short on the upper PWM
MOSFET (Q1) causes VOUT1 to increase. When
the output exceed the over-voltage threshold of
116% of DACOUT, the FAULT pin is set to fault
latch and turns Q2 on as required in order to regulate VOUT1 to 115% of DACOUT. The fault latch
raises the FAULT/RT pin close to VCC potential.
the level (200µA • ROCSET ), this signal inhibit all
outputs. Discharge soft-start capacitor (Css) with
25µA current sink, and increments the counter.
Css recharges and initiates a soft-start cycle again
until the counter increments to 3. This sets the fault
latch to disable all outputs. Fig. 6 illustrates the
over-current protection until an over load on OUT1.
Should excessive current cause VSEN to fall below
13
AIC1574
the linear under-voltage threshold, the LUV signal
The status of the SELECT pin can not be changed
sets the over-current latch if CSS is fully charged.
during operation of the IC without immediatelly
Cycling the bias input power (off then on ) reset the
causing a fault condition.
counter and the fault latch.
The over-current function for PWM controller will trip
OUT3 and OUT4 Voltage Program
at a peak inductor current (IPEAK) determined by:
IPEAK =
IOCSET × R OCSET
R DS(ON)
The GTL bus voltage (1.5V, OUT3) and the chip set
and/or cache memorey voltage (1.8V,OUT4) are internally set for simpe, low cost implementation ba-
The OC trip point varies with MOSFET’s tempera-
se on the FIX pin left open. Grounding FIX pin al-
ture. To avoid over-current tripping in the normal op-
lows both output voltages to be set by means of ex-
erating load range, determine the ROCSET resistor
ternal resistor dividers.
from the equation above with:
3.3V
1. The maximum RDS(ON) at the temperature.
2. The minimum IOCSET from the specification table.
3. Determine P
I EAK > IOUT(MAX) + (inductor ripple
DRV
VOUT
+
ROUT
VSEN
current) /2.
AIC1574
FIX
RGND
PWM OUT1 Voltage Program
The output voltage of the PWM converter is programmed to discrete levels between 1.3V to 3.5V.
The VID pins program an internal voltage reference

R
VOUT = 1 .265V ×  1 + OUT
R GND





Adjusting the Output Voltage of OUTPUT 3 and 4
(DACOUT) through a TTL compatible 5 bit digital to
analog converter. The VID pins can be left open for
a logic 1 input, because they are internally pulled
up to 5V by a 70KΩ resistor. Changing the VID inputs during operation is not recommended. All VID
pin combinations resulting in an INHIBIT disable the
IC and the open collector at the PGOOD pin.
Shutdown
The AIC1574 features a dedicated shetdown pin
(SD). A TTL-compatible logic high signal applied to
this pin shuts down all four outputs and discharge
the soft-start capacitor.
The VID codes resulting in an INHIBIT as shown in
Table 1 also shut down the IC.
OUT2 Voltage Program
The AGP regulator output voltage is internally set to
one of two discrete levels based on the SELECT
pin status. Left SELECT pin open, internal pulled
high, the output voltage is 3.3V. Grounding SE-
n APPLICATION GUIDE LINES
Layout Considerations
LECT pin to GROUND will get the 1.5V output volt-
Any inductance in the switched current path gener-
age.
ates a large voltage spike during the switching interval. The voltage spikes can degrade efficiency,
14
AIC1574
radiate noise into the circuit, and lead to device
The AIC1574 is best placed over a quiet ground
over-voltage stress. Careful component selection
plane area. The GND pin should be connected to
and tight layout of critical components, and short,
the groundside of the output capacitors. Under no
wide metal trace minimize the voltage spike.
circumstances should GND be returned to a ground
A ground plane should be used. Locate the input
capacitors (CIN) close to the power switches.
Minimize the loop formed by CIN, the upper
MOSFET (Q1) and the lower MOSFET (Q2) as
possible. Connections should be as wide as short
as possible to minimize loop inductance.
The connection between Q1, Q2 and output inductor should be as wide as short as practical. Since
inside the CIN, Q1, Q2 loop. The GND and PGND
pins should be shorted right at the IC. This help to
minimize internal ground disturbances in the IC and
prevents differences in ground potential from disrupting internal circuit operation.
The wiring traces from the control IC to the MOSFET gate and source should be sized to carry peak
current.
this connection has fast voltage transitions will ea-
The Vcc pin should be decoupled directly to GND
sily induce EMI.
by a 2.2µF ceramic capacitor, trace lengths should
The output capacitor (COUT ) should be located as
be as short as possible.
close the load as possible. Because minimize the
transient load magnitude for high slew rate requires
low inductance and resistance in circuit board
15
AIC1574
Table 1 VOUT1 Voltage Program (0=connected to GND, 1=open or connected to 5V)
For all package versions
PIN NAME
PIN NAME
DACOUT
DACOUT
VID4
VID3
VID2
VID1
VID0
VOLTAGE
VID4
VID3
VID2
VID1
VID0
VOLTAGE
0
1
1
1
1
1.30V
1
1
1
1
1
INHIBIT
0
1
1
1
0
1.35V
1
1
1
1
0
2.1 V
0
1
1
0
1
1.40V
1
1
1
0
1
2.2 V
0
1
1
0
0
1.45V
1
1
1
0
0
2.3 V
0
1
0
1
1
1.50V
1
1
0
1
1
2.4 V
0
1
0
1
0
1.55V
1
1
0
1
0
2.5 V
0
1
0
0
1
1.60V
1
1
0
0
1
2.6 V
0
1
0
0
0
1.65V
1
1
0
0
0
2.7 V
0
0
1
1
1
1.70V
1
0
1
1
1
2.8 V
0
0
1
1
0
1.75V
1
0
1
1
0
2.9 V
0
0
1
0
1
1.80 V
1
0
1
0
1
3.0 V
0
0
1
0
0
1.85 V
1
0
1
0
0
3.1 V
0
0
0
1
1
1.90 V
1
0
0
1
1
3.2 V
0
0
0
1
0
1.95 V
1
0
0
1
0
3.3 V
0
0
0
0
1
2.00 V
1
0
0
0
1
3.4 V
0
0
0
0
0
2.05 V
1
0
0
0
0
3.5 V
A multi-layer-printed circuit board is recom-
tude, the output voltage transient change due to
mended. Figure 11 shows the connections of
the output capacitor can be note by the follow-
the critical components in the converter. The CIN
ing equation:
and COUT could each represent numerous
physical capacitors. Dedicate one solid layer for
a ground plane and make all critical component
∆VOUT = ESR × ∆IOUT + ESL ×
∆IOUT
∆T ,
∆IOUT is transient load current step.
where
ground connections with vias to this layer.
After the initial transient, the ESL dependent
PWM Output Capacitors
term drops off. Because the strong relationship
The load transient for the microprocessor core
between output capacitor ESR and output load
requires high quality capacitors to supply the
transient, the output capacitor is usually chosen
high slew rate (di/dt) current demand.
for ESR, not for capacitance value. A capacitor
The ESR (equivalent series resistance) and ESL
(equivalent series inductance) parameters rather
than actual capacitance determine the buck capacitor values. For a given transient load magni-
with suitable ESR will usually have a larger capacitance value than is needed for energy storage.
A common way to lower ESR and raise ripple
16
AIC1574
current capability is to parallel several capaci-
current without saturation, and the copper resis-
tors. In most case, multiple electrolytic capaci-
tance in the winding should be kept as low as
tors of small case size are better than a single
possible to minimize resistive power loss
large case capacitor.
Input Capacitor Selection
Output Inductor Selection
Most of the input supply current is supplied by
Inductor value and type should be chosen based
the input bypass capacitor, the resulting RMS
on output slew rate requirement, output ripple
current flow in the input capacitor will heat it up.
requirement and expected peak current. Induc-
Use a mix of input bulk capacitors to control the
tor value is primarily controlled by the required
voltage overshoot across the upper MOSFET.
current response time. The AIC1570 will provide
The ceramic capacitance for the high frequency
either 0% or 100% duty cycle in response to a
decoupling should be placed very close to the
load transient. The response time to a transient
upper MOSFET to suppress the voltage induced
is different for the application of load and remove
in the parasitic circuit impedance. The buck ca-
of load.
pacitors to supply the RMS current is approxi-
tRISE =
L × ∆IOUT
L × ∆IOUT
tFALL =
VIN − VOUT ,
VOUT .
Where ∆IOUT is transient load current step.
mate equal to:
IRMS = (1− D) × D × I2 OUT +
D=
In a typical 5V input, 2V output application, a
, where
1  VIN × D
×

12  f × L 
2
VOUT
VIN
3µH inductor has a 1A/µS rise time, resulting in
The capacitor voltage rating should be at least
a 5µS delay in responding to a 5A load current
1.25 times greater than the maximum input volt-
step. To optimize performance, different combi-
age.
nations of input and output voltage and expected
loads may require different inductor value. A
smaller value of inductor will improve the tran-
PWM MOSFET Selection
sient response at the expense of increase out-
In high current PWM application, the MOSFET
put ripple voltage and inductor core saturation
power dissipation, package type and heatsink
rating.
are the dominant design factors. The conduction
Peak current in the inductor will be equal to the
maximum output load current plus half of inductor ripple current. The ripple current is approximately equal to:
(V IN − VOUT) × VOUT
I RIPPLE =
f × L × VIN
;
f = AIC1574 oscillator frequency.
loss is the only component of power dissipation
for the lower MOSFET, since it turns on into
near zero voltage. The upper MOSFET has conduction loss and switching loss. The gate charge losses are proportional to the switching frequency and are dissipated by the AIC1574.
However, the gate charge increases the switching interval, tSW, which increase the upper MOSFET switching losses. Ensure that both MOS-
The inductor must be able to withstand peak
FETs are within their maximum junction tem-
17
AIC1574
perature at high ambient temperature by calcu-
breakdown voltage must be greater than twice
lating the temperature rise according to package
the maximum input voltage.
thermal resistance specifications.
PUPPER = IOUT 2 × RDS(ON) × D +
IOUT × VIN × tSW × f
2
PLOWER = IOUT 2 × RDS(ON) × (1 − D)
Linear Controller MOSFET Selection
The power dissipated in a linear regulator is :
The equations above do not model power loss
PLINEAR = IOUT2 × (VIN2 − VOUT2 )
due to the reverse recovery of the lower
Select a package and heatsink that maintains
MOSFET’s body diode.
junction temperature below the maximum rating
The RDS(ON) is different for the two previous
while operation at the highest expected ambient
equations even if the type devices is used for
temperature.
both. This is because the gate drive applied to
the upper MOSFET is different than the lower
MOSFET. Logic level MOSFETs should be se-
Linear Output Capacitor
lected based on on-resistance considerations,
The output capacitors for the linear regulator and
RDS(ON) should be chosen base on input and
linear controller provide dynamic load current.
output voltage, allowable power dissipation and
The linear controller uses dominant pole com-
maximum required output current. Power dissi-
pensation integrated in the error amplifier and is
pation should be calculated based primarily on
insensitive to output capacitor selection. COUT2,
required efficiency or allowable thermal dissipa-
COUT3 and COUT4 should be selected for tran-
tion.
sient load regulation.
Rectifier Schottky diode is a clamp that prevent
the loss parasitic MOSFET body diode from
conducting during the dead time between the
turn off of the lower MOSFET and the turn on of
PWM Feedback Analysis
the upper MOSFET. The diode’s rated reverse
VIN
∆V OSC
Q1
VDAC
VEA
Compensation
Networks
+
CO
PWM COMP.
ERROR AMP.
VOUT
LO
Q2
RESR
Modulation
Gain
18
AIC1574
The compensation network consists of the error
Gain are given by
amplifier and built in compensation networks.
FZ 1 = 2.6KHz ;
The goal of the compensation network is to
provide for fast response and adequate phase
FZ 2 = 24 KHz ;
margin. Phase Margin is the difference between
FP1 = 30 KHz ;
the closed loop phase at 0dB and 180 degree.
Closed Loop Gain(dB) = Modulation Gain(dB) +
FP 2 = 400 KHz
60
FZ1
Compensation Gain (dB)
F Z2
FP1
40
 VIN
≈ 20 log
 ∆VOSC
 

F
 + 10 log1 + 

  F

  ESR


 F
− 10 log 1 − 
   FLC

where
1
FLC =
2π LO CO
FESR =
1
=
Q
2
2



F
  +

 
 F ×Q 
 
 LC




2 



× R ESR +
20
F P2
FOdB
20log(VIN/δVOSC)
0
Modulation
Gain
FLC
F
-20
100
1k
Closed Loop
Gain
F ESR
10k
100k
1M
10M
Frequency (KHz)
Bode Plot of Converter Gain
Sampling theory shows that F0dB must be less
that half the switching frequency for the loop
2π × RESR × CO
LO
2
;
1
CO




Gain (dB)
Compensation Gain
Modulation Gain(dB)
stables. But it must be considerably less than
;
LO
CO
that, or there will be large amplitude switching
×
1
frequency ripple at the output. Thus, the usual
R LOAD
practices is to fix F0dB at 1/4 to 1/5 the switching
The break frequency of Internal Compensation
frequency.
19
AIC1574
PHYSICAL DIMENSIONS
l
28 LEAD PLASTIC SO (unit: mm)
D
SYMBOL
MIN
MAX
A
2.35
2.65
A1
0.10
0.30
B
0.33
0.51
C
0.23
0.32
D
17.70
18.10
E
7.40
7.60
E
H
e
B
e
A
A1
n
C
L
1.27 (TYP)
H
10.00
10.65
L
0.40
1.27
20
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