INNOVASIC N80C186EB13 8-bit/16-bit microcontroller Datasheet

IA186EB/IA188EB
8-Bit/16-Bit Microcontrollers
Data Sheet
July 10, 2011
IA186EB/IA188EB
8-Bit/16-Bit Microcontrollers
Data Sheet
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Copyright
Data Sheet
July 10, 2011
2011 by Innovasic Semiconductor, Inc.
Published by Innovasic Semiconductor, Inc.
3737 Princeton Drive NE, Suite 130, Albuquerque, NM 87107
MILES™ is a trademark Innovasic Semiconductor, Inc.
Intel is a registered trademark of Intel Corporation
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Data Sheet
July 10, 2011
TABLE OF CONTENTS
1.
2.
3.
4.
5.
6.
7.
8.
9.
Introduction.............................................................................................................................7
1.1 General Description.......................................................................................................7
1.2 Features .........................................................................................................................8
Packaging, Pin Descriptions, and Physical Dimensions .........................................................9
2.1 Packages and Pinouts ....................................................................................................9
2.1.1 IA186EB 84 PLCC Package ...........................................................................10
2.1.2 IA188EB 84 PLCC Package ...........................................................................12
2.1.3 PLCC Physical Dimensions ............................................................................14
2.1.4 IA186EB 80 PQFP Package ...........................................................................15
2.1.5 IA188EB 80 PQFP Package ...........................................................................17
2.1.6 PQFP Physical Dimensions ............................................................................19
2.1.7 IA186EB 80 LQFP Package ...........................................................................20
2.1.8 IA188EB 80 LQFP Package ...........................................................................22
2.1.9 LQFP Physical Dimensions ............................................................................24
2.2 IA186EB Pin/Signal Descriptions ...............................................................................25
2.3 IA188EB Pin/Signal Descriptions ...............................................................................34
Maximum Ratings, Thermal Characteristics, and DC Parameters .......................................42
Functional Description..........................................................................................................44
4.1 Device Architecture.....................................................................................................44
4.1.1 Bus Interface Unit ...........................................................................................44
4.1.2 Clock Generator ..............................................................................................46
4.1.3 Interrupt Control Unit .....................................................................................47
4.1.4 Timer/Counter Unit ........................................................................................47
4.1.5 Serial Communications Unit...........................................................................47
4.1.6 Chip-Select Unit .............................................................................................47
4.1.7 I/O Port Unit ...................................................................................................48
4.1.8 Refresh Control Unit.......................................................................................48
4.1.9 Power Management Unit ................................................................................48
4.2 Peripheral Architecture ...............................................................................................48
4.3 Reference Documents .................................................................................................51
AC Specifications .................................................................................................................51
5.1 AC Test Conditions .....................................................................................................55
5.2 Clock Input and Clock Output Timing Characteristics ...............................................56
5.3 Serial Port Mode 0 Timing Characteristics .................................................................58
Reset Operation ....................................................................................................................59
Bus Timing ...........................................................................................................................59
Instruction Execution Times .................................................................................................69
Errata.....................................................................................................................................77
9.1 Summary .....................................................................................................................77
9.2 Detail ...........................................................................................................................78
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10.
11.
Data Sheet
July 10, 2011
Revision History ...................................................................................................................83
For Additional Information...................................................................................................85
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July 10, 2011
LIST OF FIGURES
Figure 1. IA186EB 84-Pin PLCC Package Diagram ....................................................................10
Figure 2. IA188EB 84-Pin PLCC Package Diagram ....................................................................12
Figure 3. 84-Pin PLCC Physical Package Dimensions ................................................................14
Figure 4. IA186EB 80-Pin PQFP Package Diagram ....................................................................15
Figure 5. IA188EB 80-Pin PQFP Package Diagram ....................................................................17
Figure 6. 80-Pin PQFP Physical Package Dimensions .................................................................19
Figure 7. IA186EB 80-Pin LQFP Package Diagram ....................................................................20
Figure 8. IA188EB 80-Pin LQFP Package Diagram ....................................................................22
Figure 9. 80-Pin LQFP Physical Package Dimensions .................................................................24
Figure 10. IA186EB/IA188EB Functional Block Diagram ..........................................................45
Figure 11. Clock Circuit Connection Options ..............................................................................46
Figure 12. AC Input Characteristics .............................................................................................51
Figure 13. AC Output Characteristics ...........................................................................................52
Figure 14. Relative Timing Characteristics ..................................................................................54
Figure 15. AC Test Load ..............................................................................................................55
Figure 16. Clock Input and Clock Output Timing Characteristics ...............................................56
Figure 17. Serial Port Mode 0 Timing Characteristics .................................................................58
Figure 18. Cold Reset Timing.......................................................................................................60
Figure 19. Warm Reset Timing ....................................................................................................61
Figure 20. Read, Fetch, and Refresh Cycle Timing ......................................................................62
Figure 21. Write Cycle Timing .....................................................................................................63
Figure 22. Halt Cycle Timing .......................................................................................................64
Figure 23. Interrupt Acknowledge (inta1_n, inta0_n) Cycle Timing ...........................................65
Figure 24. hold/hlda Timing .........................................................................................................66
Figure 25. Refresh During Hold Acknowledge Timing ...............................................................67
Figure 26. Ready Timing ..............................................................................................................68
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LIST OF TABLES
Table 1. IA186EB 84-Pin PLCC Pin Listing ................................................................................11
Table 2. IA188EB 84-Pin PLCC Pin Listing ................................................................................13
Table 3. IA186EB 80-Pin PQFP Pin Listing ................................................................................16
Table 4. IA188EB 80-Pin PQFP Pin Listing ................................................................................18
Table 5. IA186EB 80-Pin LQFP Pin Listing ................................................................................21
Table 6. IA188EB 80-Pin LQFP Pin Listing ................................................................................23
Table 7. IA186EB Pin/Signal Descriptions ..................................................................................25
Table 8. IA188EB Pin/Signal Descriptions ..................................................................................34
Table 9. IA186EB and IA188EB Absolute Maximum Ratings ....................................................42
Table 10. IA186EB and IA188EB Thermal Characteristics .........................................................42
Table 11. IA186EB and IA188EB DC Parameters .......................................................................43
Table 12. Peripheral Control Block Registers ..............................................................................49
Table 13. AC Input Characteristics for 5.0-Volt Operation..........................................................52
Table 14. AC Input Characteristics for 3.3-Volt Operation..........................................................52
Table 15. AC Output Characteristics for 5.0-Volt Operation .......................................................53
Table 16. AC Output Characteristics for 3.3-Volt Operation .......................................................53
Table 17. Relative Timing Characteristics....................................................................................55
Table 18. Clock Input and Clock Output Timing Characteristics for 5.0-Volt Operation ...........56
Table 19. Clock Input and Output Characteristics for 3.3-Volt Operation ...................................57
Table 20. Serial Port Mode 0 Timing Characteristics...................................................................58
Table 21. Instruction Set Timing ..................................................................................................69
Table 22. Innovasic Part Number Cross-Reference for the PLCC ...............................................74
Table 23. Innovasic Part Number Cross-Reference for the PQFP................................................75
Table 24. Innovasic Part Number Cross-Reference for the LQFP ...............................................76
Table 25. Summary of Errata ........................................................................................................77
Table 26. Revision History ...........................................................................................................83
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IA186EB/IA188EB
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1.
Data Sheet
July 10, 2011
Introduction
The Innovasic Semiconductor IA186EB and IA188EB microcontrollers are form, fit, and
function replacements for the original Intel® 80C186EB, 80C188EB, 80L186EB, and 80L188EB
16-bit high-integration embedded processors.
These devices are produced using Innovasic’s Managed IC Lifetime Extension System
(MILES™). This cloning technology, which produces replacement ICs beyond simple
emulations, ensures complete compatibility with the original device, including any
―undocumented features.‖ Additionally, the MILES process captures the clone design in such a
way that production of the clone can continue even as silicon technology advances.
The IA186EB and IA188EB microcontrollers replace the obsolete Intel 80C186EB and
80C188EB devices, allowing users to retain existing board designs, software
compilers/assemblers, and emulation tools, thereby avoiding expensive redesign efforts.
1.1
General Description
The Innovasic Semiconductor IA186EB and IA188EB microcontrollers are an upgrade for the
80C186EB/80C188EB microcontroller designs with integrated peripherals to provide increased
functionality and reduce system costs. The IA186EB and IA188EB devices are designed to
satisfy requirements of embedded products designed for telecommunications, office automation
and storage, and industrial controls.
The IA186EB and IA188EB microcontrollers have a set of base peripherals beneficial to many
embedded applications and include a standard numeric interface, an interrupt control unit, a chipselect unit, a DRAM refresh control unit, a power management unit, and three 16-bit
timer/counters.
The IA186EB and IA188EB microcontrollers are capable of operating at 5.0 or 3.3 volts. This
datasheet discusses both modes of operation. Where applicable, characteristics specific to either
3.3 or 5.0 volt operation are identified separately throughout this datasheet.
Additionally, the IA186EB and IA188EB include two integrated serial ports that support both
synchronous and asynchronous communications, simplifying inter-processor and display
communications. The IA186EB and IA188EB also have an enhanced chip-select unit and two
multiplexed I/O ports. The enhanced chip-select unit offers 10 general chip selects, each with
the ability to address up to 1 Mbyte. This enhanced unit enables memory-bank switching to
expand the IA186EB/IA188EB 1 Mbyte address space. The I/O ports allow for basic functions
such as scanning keypads for input. The ports can also be used to control system power
consumption, disabling unneeded components.
The serial ports, I/O capabilities, and enhanced chip selects make the IA186EB/IA188EB an
excellent processor for portable data acquisition or communication applications.
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1.2
Data Sheet
July 10, 2011
Features
The primary features of the IA186EB and IA188EB microcontrollers are as follows:
Low-Power Operating Modes
– Idle (freezes CPU clocks; peripherals are kept active)
– Power-Down (freezes all internal clocks)
Low-Power CPU Core (static)
Direct Addressing Capability
– Memory: 1 Mbyte
– I/O: 64 Kbyte
I/O Ports
– 2 each, 8-Bit
– Multiplexed
Clock Generator
Chip Selects
– 10 each, Programmable
– Integral Wait-State Generator
Memory Refresh Control Unit
Interrupt Controller, Programmable
Counter/Timers
– 3 each, 16-Bit
– Programmable
Serial Channels
– 2 each, UARTs
– Integral Baud Rate Generator
Operating Frequency (system clock input)
– 50 MHz @ 5V
– 32 MHz @ 3.3V
Chapter 4, Functional Description, provides details of the IA186EB and IA188EB
microcontrollers, including the features listed above.
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2.
Data Sheet
July 10, 2011
Packaging, Pin Descriptions, and Physical Dimensions
Information on the packages and pin descriptions for the IA186EB and the IA188EB is provided
separately. Refer to sections, figures, and tables for information on the device of interest.
2.1
Packages and Pinouts
The Innovasic Semiconductor IA186EB and IA188EB microcontroller is available in the
following packages:
84-Pin Plastic Leaded Chip Carrier (PLCC), equivalent to original PLCC package
80-Pin Plastic Quad Flat Pack (PQFP), equivalent to original PQFP package
80-Pin Low-Profile Quad Flat Pack (LQFP), equivalent to original SQFP package
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2.1.1
Data Sheet
July 10, 2011
IA186EB 84 PLCC Package
The pinout for the IA186EB 84 PLCC Package is as shown in Figure 1. The corresponding
pinout is provided in Table 1.
Figure 1. IA186EB 84-Pin PLCC Package Diagram
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Table 1. IA186EB 84-Pin PLCC Pin Listing
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
Name
Vcc
Vss
error_n
rd_n
wr_n
ale
bhe_n
s2_n
s1_n
s0_n
den_n
hlda
hold
test_n/busy
lock_n
dt/r_n
nmi
ready
p1.7/gcs7_n
p1.6/gcs6_n
p1.5/gcs5_n
Pin
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
Name
Vss
Vcc
p1.4/gcs4_n
p1.3/gcs3_n
p1.2/gcs2_n
p1.1/gcs1_n
p1.0/gcs0_n
lcs_n
ucs_n
int0
int1
int2/inta0_n
int3/inta1_n
int4
pdtmr
resin_n
resout
pereq
oscout
clkin
Vcc
Pin
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
Name
Vss
clkout
t0out
t0in
t1out
t1in
p2.7
p2.6
cts0_n
txd0
rxd0
p2.5/bclk0
p2.3/sint1
p2.4/cts1_n
p2.0/rxd1
p2.1/txd1
p2.2/bclk1
ncs_n
ad0
ad8
Vss
Pin
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
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Name
Vcc
Vss
ad1
ad9
ad2
ad10
ad3
ad11
ad4
ad12
ad5
ad13
ad6
ad14
ad7
ad15
a16
a17
a18
a19/once_n
Vss
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2.1.2
Data Sheet
July 10, 2011
IA188EB 84 PLCC Package
The pinout for the IA188EB 84 PLCC Package is as shown in Figure 2. The corresponding
pinout is provided in Table 2.
Figure 2. IA188EB 84-Pin PLCC Package Diagram
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Table 2. IA188EB 84-Pin PLCC Pin Listing
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
Name
Vcc
Vss
Not Connected
rd_n
wr_n
ale
rfsh_n
s2_n
s1_n
s0_n
den_n
hlda
hold
test_n
lock_n
dt/r_n
nmi
ready
p1.7/gcs7_n
p1.6/gcs6_n
p1.5/gcs5_n
Pin
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
Name
Vss
Vcc
p1.4/gcs4_n
p1.3/gcs3_n
p1.2/gcs2_n
p1.1/gcs1_n
p1.0/gcs0_n
lcs_n
ucs_n
int0
int1
int2/inta0_n
int3/inta1_n
int4
pdtmr
resin_n
resout
Not Connected
oscout
clkin
Vcc
Pin
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
Name
Vss
clkout
t0out
t0in
t1out
t1in
p2.7
p2.6
cts0_n
txd0
rxd0
p2.5/bclk0
p2.3/sint1
p2.4/cts1_n
p2.0/rxd1
p2.1/txd1
p2.2/bclk1
Not Connected
ad0
a8
Vss
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Pin
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
Name
Vcc
Vss
ad1
a9
ad2
a10
ad3
a11
ad4
a12
ad5
a13
ad6
a14
ad7
a15
a16
a17
a18
a19/once_n
Vss
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2.1.3
Data Sheet
July 10, 2011
PLCC Physical Dimensions
The physical dimensions for the 84 PLCC are as shown in Figure 3.
Legend:
Symbol
A
A1
D
D1
E
E1
F
F1
Min
0.165˝
0.090˝
–
–
–
–
–
–
Nom
–
–
1.190˝
1.154˝
1.190˝
1.154˝
1.110˝
1.110˝
Max
0.180˝
0.120˝
–
–
–
–
–
–
Note: The bottom package is bigger
than the top package by 0.004
inches (0.002 inches per side).
Bottom package dimensions follow
those stated in this drawing.
Figure 3. 84-Pin PLCC Physical Package Dimensions
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2.1.4
Data Sheet
July 10, 2011
IA186EB 80 PQFP Package
The pinout for the IA186EB 80 PQFP Package is as shown in Figure 4. The corresponding
pinout is provided in Table 3.
Figure 4. IA186EB 80-Pin PQFP Package Diagram
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Table 3. IA186EB 80-Pin PQFP Pin Listing
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Name
cts0_n
txd0
rxd0
p2.5/bclk0
p2.3/sint1
p2.4/cts1_n
p2.0/rxd1
p2.1/txd1
p2.2/bclk1
ad0
ad8
Vss
Vcc
Vss
ad1
ad9
ad2
ad10
ad3
ad11
Pin
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
Name
ad4
ad12
ad5
ad13
ad6
ad14
ad7
ad15
a16
a17
a18
a19/once_n
Vss
Vcc
Vss
rd_n
wr_n
ale
bhe_n
s2_n
Pin
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
Name
s1_n
s0_n
den_n
hlda
hold
test_n
lock_n
nmi
ready
p1.7/gcs7_n
p1.6/gcs6_n
p1.5/gcs5_n
Vss
Vcc
p1.4/gcs4_n
p1.3/gcs3_n
p1.2/gcs2_n
p1.1/gcs1_n
p1.0/gcs0_n
lcs_n
Pin
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
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Name
ucs_n
int0
int1
int2/inta0_n
int3/inta1_n
int4
pdtmr
resin_n
resout
oscout
clkin
Vcc
Vss
clkout
t0out
t0in
t1out
t1in
p2.7
p2.6
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2.1.5
Data Sheet
July 10, 2011
IA188EB 80 PQFP Package
The pinout for the IA188EB 80 PQFP Package is as shown in Figure 5. The corresponding
pinout is provided in Table 4.
Figure 5. IA188EB 80-Pin PQFP Package Diagram
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Table 4. IA188EB 80-Pin PQFP Pin Listing
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Name
cts0_n
txd0
rxd0
p2.5/bclk0
p2.3/sint1
p2.4/cts1_n
p2.0/rxd1
p2.1/txd1
p2.2/bclk1
ad0
a8
Vss
Vcc
Vss
ad1
a9
ad2
a10
ad3
a11
Pin
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
Name
ad4
a12
ad5
a13
ad6
a14
ad7
a15
a16
a17
a18
a19/once_n
Vss
Vcc
Vss
rd_n
wr_n
ale
rfsh_n
s2_n
Pin
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
Name
s1_n
s0_n
den_n
hlda
hold
test_n
lock_n
nmi
ready
p1.7/gcs7_n
p1.6/gcs6_n
p1.5/gcs5_n
Vss
Vcc
p1.4/gcs4_n
p1.3/gcs3_n
p1.2/gcs2_n
p1.1/gcs1_n
p1.0/gcs0_n
lcs_n
Pin
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
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Name
ucs_n
int0
int1
int2/inta0_n
int3/inta1_n
int4
pdtmr
resin_n
resout
oscout
clkin
Vcc
Vss
clkout
t0out
t0in
t1out
t1in
p2.7
p2.6
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2.1.6
Data Sheet
July 10, 2011
PQFP Physical Dimensions
The physical dimensions for the 80 PQFP are as shown in Figure 6.
Legend:
Notes:
1. Dimension D1 and E1 do not include mold protrusion.
Allowable protrusion is 0.25mm per side. Dimension D1
and E1 do not include mold mismatch and are determined
a datum plane –H– .
2. Dimension b does not include dambar protrusion.
Allowable dambar protrusion will not cause the lead width
to exceed the maximum b dimension by more than
0.08mm. Dambar cannot be located on the lower radius of
the lead foot.
Millimeter
Inch
Symbol Min Nom Max Min Nom Max
A
–
– 3.40 –
– 0.134
A1
0.25 –
– 0.010 –
–
A2
2.55 2.72 3.05 0.100 0.107 0.120
D
23.90 Basic
0.941 Basic
D1
20.00 Basic
0.787 Basic
E
17.90 Basic
0.705 Basic
E1
14.00 Basic
0.551 Basic
R2 0.013 – 0.30 0.005 – 0.012
R1 0.013 –
– 0.005 –
–
θ
0° 3.5° 7° 0° 3.5° 7°
θ1
0°
–
–
0°
–
–
a
7°
REF
7°
REF
θ2, θ3
15° REF
15° REF
θ2, θ3b
c
0.11 0.15 0.23 0.004 0.006 0.009
L
0.73 0.88 1.03 0.029 0.035 0.041
L1
1.95 REF
0.077 REF
S
0.40 –
– 0.016 –
–
b
0.30 0.35 0.45 0.012 0.014 0.018
e
0.80 BSC
0.031 BSC
D2
18.40 REF
0.724
E2
12.00 REF
0.472
Tolerances of Form and Position
aaa
0.25
0.010
bbb
0.20
0.008
ccc
0.20
0.008
aAlloy 42 L/F.
bCopper L/F.
Figure 6. 80-Pin PQFP Physical Package Dimensions
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Data Sheet
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IA186EB 80 LQFP Package
The pinout for the IA186EB 80 LQFP Package is as shown in Figure 7. The corresponding
pinout is provided in Table 5.
Figure 7. IA186EB 80-Pin LQFP Package Diagram
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Table 5. IA186EB 80-Pin LQFP Pin Listing
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Name
hlda
hold
test_n
lock_n
nmi
ready
p1.7/gcs7_n
p1.6/gcs6_n
p1.5/gcs5_n
Vss
Vcc
p1.4/gcs4_n
p1.3/gcs3_n
p1.2/gcs2_n
p1.1/gcs1_n
p1.0/gcs0_n
lcs_n
ucs_n
int0
int1
Pin
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
Name
int2/inta0_n
int3/inta1_n
int4
pdtmr
resin_n
resout
oscout
clkin
Vcc
Vss
clkout
t0out
t0in
t1out
t1in
p2.7
p2.6
cts0_n
txd0
rxd0
Pin
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
Name
p2.5/bclk0
p2.3/sint1
p2.4/cts1_n
p2.0/rxd1
p2.1/txd1
p2.2/bclk1
ad0
ad8
Vss
Vcc
Vss
ad1
ad9
ad2
ad10
ad3
ad11
ad4
ad12
ad5
Pin
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
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Name
ad13
ad6
ad14
ad7
ad15
a16
a17
a18
a19/once_n
Vss
Vcc
Vss
rd_n
wr_n
ale
bhe_n
s2_n
s1_n
s0_n
den_n
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IA188EB 80 LQFP Package
The pinout for the IA188EB 80 LQFP Package is as shown in Figure 8. The corresponding
pinout is provided in Table 6.
Figure 8. IA188EB 80-Pin LQFP Package Diagram
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Table 6. IA188EB 80-Pin LQFP Pin Listing
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Name
hlda
hold
test_n
lock_n
nmi
ready
p1.7/gcs7_n
p1.6/gcs6_n
p1.5/gcs5_n
Vss
Vcc
p1.4/gcs4_n
p1.3/gcs3_n
p1.2/gcs2_n
p1.1/gcs1_n
p1.0/gcs0_n
lcs_n
ucs_n
int0
int1
Pin
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
Name
int2/inta0_n
int3/inta1_n
int4
pdtmr
resin_n
resout
oscout
clkin
Vcc
Vss
clkout
t0out
t0in
t1out
t1in
p2.7
p2.6
cts0_n
txd0
rxd0
Pin
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
Name
p2.5/bclk0
p2.3/sint1
p2.4/cts1_n
p2.0/rxd1
p2.1/txd1
p2.2/bclk1
ad0
a8
Vss
Vcc
Vss
ad1
a9
ad2
a10
ad3
a11
ad4
a12
ad5
Pin
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
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Name
a13
ad6
a14
ad7
a15
a16
a17
a18
a19/once_n
Vss
Vcc
Vss
rd_n
wr_n
ale
rfsh_n
s2_n
s1_n
s0_n
den_n
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LQFP Physical Dimensions
The physical dimensions for the 80 LQFP are as shown in Figure 9.
Legend:
Symbol
A
A1
A2
b
b1
c
c1
D
D1
E
E1
e
L
L1
R1
R2
S
θ
θ1
θ2
θ3
Dimension in mm
Min Nom Max
–
–
1.60
0.05
–
0.15
1.35 1.40 1.45
0.17 0.22 0.27
0.17 0.20 0.23
0.09
–
0.20
0.09
–
0.16
14.00 BSC
12.00 BSC
14.00 BSC
12.00 BSC
0.50 BSC
0.45 0.60 0.75
1.00 REF
0.08
–
–
0.08
–
0.20
0.20
–
–
0°
3.5°
7°
0°
–
–
11°
12°
13°
11°
12°
13°
Dimension in Inch
Min
Mom
Max
–
–
0.063
0.002
–
0.006
0.053 0.055 0.057
0.007 0.009 0.011
0.007 0.008 0.009
0.004
–
0.008
0.004
–
0.006
0.551 BSC
0.472 BSC
0.551 BSC
0.472 BSC
0.020 BSC
0.018 0.024 0.030
0.039 REF
0.003
–
–
0.003
–
0.008
0.008
–
–
0°
3.5°
7°
0°
–
–
11°
12°
13°
11°
12°
13°
1. To be determined at seating plane C.
2. Dimensions D1 and E1 do not include
mold protrusion. D1 and E1 are
maximum plastic body size
dimensions including mold mismatch.
3. Dimension b does not include dambar
protrusion. Dambar cannot be located
on the lower radius of the foot.
4. Exact shape of each corner is
optional.
5. These dimensions apply to the flat
section of the lead between 0.10 and
0.25mm from the lead tip.
6. A1 is defined as the distance from the
seating plane to the lowest point of the
package body.
Notes:
1. Exact shape of each corner is optional.
2. Controlling dimension: mm.
Figure 9. 80-Pin LQFP Physical Package Dimensions
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IA186EB Pin/Signal Descriptions
Descriptions of the pin and signal functions for the IA186EB microcontroller are provided in
Table 7.
Several of the IA186EB pins have different functions depending on the operating mode of the
device. Each of the different signals supported by a pin is listed and defined in Table 7—
indexed alphabetically in the first column of the table. Additionally, the name of the pin
associated with the signal as well as the pin numbers for the PLCC, LQFP, and PQFP packages
are provided in the ―Pin‖ column. Signals not used in a specific package type are designated
―NA.‖
Table 7. IA186EB Pin/Signal Descriptions
Signal
a16
(output
only)
Name
a16
Pin
PLCC
80
LQFP
66
PQFP
29
a17
(output
only)
a17
81
67
30
a18
(output
only)
a18
82
68
31
a19
a19/once_n
83
69
32
ad0
ad1
ad2
ad3
ad4
ad5
ad6
ad7
ad8
ad9
ad10
ad11
ad12
ad13
ad14
ad15
ad0
ad1
ad2
ad3
ad4
ad5
ad6
ad7
ad8
ad9
ad10
ad11
ad12
ad13
ad14
ad15
61
66
68
70
72
74
76
78
62
67
69
71
73
75
77
79
47
52
54
56
58
60
62
64
48
53
55
57
59
61
63
65
10
15
17
19
21
23
25
27
11
16
18
20
22
24
26
28
Description
address Bits [16–19]. Input/Output. These pins
provide the four most-significant bits of the
Address Bus. During the address portion of the
IA186EB bus cycle, Address Bits [16–19] are
presented on the bus and can be latched using
the ale signal (see table entry). During the data
portion of the IA186EB bus cycle, these lines
are driven to a logic 0.
address/data Bits [0–15]. Input/Output. These
pins provide the multiplexed Address Bus and
Data Bus. During the address portion of the
IA186EB bus cycle, Address Bits [0–15] are
presented on the bus and can be latched using
the ale signal (see next table entry). During the
data portion of the IA186EB bus cycle, 8- or
16-bit data are present on these lines.
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Table 7. IA186EB Pin/Signal Descriptions (Continued)
Signal
ale
Name
ale
Pin
PLCC
6
LQFP
75
PQFP
38
bclk0
p2.5/bclk0
54
41
4
bclk1
p2.2/bclk1
59
46
9
bhe_n
bhe_n
7
76
39
bhe_n is
multiplexed
with
refresh_n
bhe_n is
multiplexed with
refresh_n
busy
test_n/busy
Description
address latch enable. Output. Active High.
This signal is used to latch the address
information during the address portion of a bus
cycle.
baud clock, Serial Port 0. Input. The bclk0 pin
can be used to provide an alternate clock
source for Serial Port 0. The input clock rate
cannot be greater than one-half the operating
frequency of the IA186EB.
baud clock, Serial Port 1. Input. The bclk1 pin
can be used to provide an alternate clock
source for Serial Port 1. The input clock rate
cannot be greater than one-half the operating
frequency of the IA186EB.
byte high enable. Output. Active Low. When
bhe_n is asserted (low), it indicates that the
bus cycle in progress is transferring data over
the upper half of the data bus.
Additionally, bhe_n and ad0 encode the
following bus information:
14
NA
NA
ad0
bhe_n
0
0
1
1
0
1
0
1
Bus Status
Word Transfer
Even Byte Transfer
Odd Byte Transfer
Refresh Operation
Note: bhe_n is multiplexed with refresh_n.
busy. Input. Active High. When the busy
input is asserted, it causes the IA186EB to
suspend operation during the execution of the
Intel 80C187 Numerics Coprocessor
instructions. Operation resumes when the pin
is sampled low. This applies to the PLCC
package only.
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Table 7. IA186EB Pin/Signal Descriptions (Continued)
Signal
clkin
Name
clkin
Pin
PLCC
41
LQFP
28
PQFP
71
clkout
clkout
44
31
74
cts0_n
cts0_n
51
38
1
cts1_n
p2.4/cts1_n
56
43
6
den_n
den_n
11
80
43
dt/r_n
dt/r_n
16
NA
NA
error_n
error_n
3
NA
NA
Description
clock input. Input. The clkin pin is the input
connection for an external clock. An external
oscillator operating at two times the required
processor operating frequency can be
connected to this pin.
If a crystal is used to supply the clock, it is
connected between the clkin pin and the
oscout pin (see oscout table entry). When a
crystal is connected, it drives an internal Pierce
oscillator to the IA186EB.
clock output. Output. The clkout pin provides
a timing reference for inputs and outputs of the
IA186EB. This clock output is one-half the
input clock (clkin) frequency. The clkout
signal has a 50% duty cycle, transitioning every
falling edge of clkin.
clear to send, Serial Port 0. Input. Active Low.
When this input is high (i.e., not asserted), data
transmission from Serial Port 0 is inhibited.
When the signal is asserted (low), data
transmission is permitted.
clear to send, Serial Port 1. Input. Active Low.
When this input is high (i.e., not asserted), data
transmission from Serial Port 1 is inhibited.
When the signal is asserted (low), data
transmission is permitted.
data enable. Output. Active Low. This signal
is used to enable of bidirectional transceivers in
a buffered system. The den_n signal is
asserted (low) only when data is to be
transferred on the bus.
data transmit/receive. Output. This signal is
used to control the direction of data flow for
bidirectional buffers in a buffered system.
When dt/r_n is high, the direction indicated is
transmit; when dt/t_n is low, the direction
indicated is receive.
error. Input. Active Low. When this signal is
asserted (low), it indicates that the last
numerics coprocessor operation resulted in an
exception condition.
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Table 7. IA186EB Pin/Signal Descriptions (Continued)
Signal
gcs0_n
gcs1_n
gcs2_n
gcs3_n
gcs4_n
gcs5_n
gcs6_n
gcs7_n
hlda
Name
p1.0/gcs0_n
p1.1/gcs1_n
p1.2/gcs2_n
p1.3/gcs3_n
p1.4/gcs4_n
p1.5/gcs5_n
p1.6/gcs6_n
p1.7/gcs7_n
hlda
Pin
PLCC
28
27
26
25
24
21
20
19
12
LQFP
16
15
14
13
12
9
8
7
1
PQFP
59
58
57
56
55
52
51
50
44
hold
hold
13
2
45
int0
(input)
int1
(input)
int0
(input only)
int1
(input only)
31
19
62
32
20
63
int2
int2/inta0_n
33
21
64
int3
int3/inta1_n
34
22
65
int4
(input)
int4
(input only)
35
23
66
inta0_n
int2/inta0_n
33
21
64
Description
generic chip select n (n = 0–7). Output. Active
Low. When programmed and enabled, each of
these pins provide a chip select signal that will
be asserted (low) whenever the address of a
memory or I/O bus cycle is within the address
space programmed for that output.
hold acknowledge. Output. Active High.
When hlda is asserted (high), it indicates that
the IA186EB has relinquished control of the
local bus to another bus master in response to
a HOLD request (see next table entry).
When hlda is asserted, the IA186EB data bus
and control signals float, allowing another bus
master to drive the signals directly.
hold. Input. Active High. This signal is a
request indicating that an external bus master
wishes to gain control of the local bus. The
IA186EB will relinquish control of the local bus
between instruction boundaries not conditioned
by a LOCK prefix.
interrupt n (n = 0-4). Input/Output. Active
High. These maskable inputs interrupt program
flow and cause execution to continue at an
interrupt vector of a specific interrupt type as
follows:
int0:
int1:
int2:
int3:
int4:
Type 12
Type 13
Type 14
Type 15
Type 17
To allow interrupt expansion, int0 and int1 can
be used with the interrupt acknowledge signals
inta0_n and inta1_n (see next table entries) to
serve as external interrupt inputs or interrupt
acknowledge outputs.
interrupt acknowledge 0. Input/Output. Active
Low. This pin provides an interrupt
acknowledge handshake in response to an
interrupt request on the int0 pin (see previous
table entry).
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Table 7. IA186EB Pin/Signal Descriptions (Continued)
Signal
inta1_n
Name
int3/inta1_n
Pin
PLCC
34
LQFP
22
PQFP
65
lcs_n
lcs_n
29
17
60
lock_n
lock_n
15
4
47
ncs_n
ncs_n
60
NA
NA
nmi
nmi
17
5
48
once_n
a19/once_n
83
69
32
Description
interrupt acknowledge 1. Input/Output. Active
Low. This pin provides an interrupt
acknowledge handshake in response to an
interrupt request on the int1 pin (see previous
table entry).
lower chip select. Output. Active Low. This
pin provides a chip select signal that will be
asserted (low) whenever the address of a
memory bus cycle is within the address space
programmed for that output.
lock. Output. Active Low. When asserted
(low), this signal indicates that the bus cycle in
progress is cannot be interrupted. While
lock_n is active, the IA186EB will not service
bus requests such as HOLD.
numerics coprocessor select. Output. Active
Low. This signal is asserted (low) when the
IA186EB accesses an Intel 80C187 Numerics
Coprocessor.
non-maskable interrupt. Input. Active High.
When the nmi signal is asserted (high) it
causes a Type 2 interrupt to be serviced by the
IA186EB.
Note: The assertion of nmi is latched internally
by the IA186EB.
on-circuit emulation. Input. Active Low. Note:
ONCE Mode is used for device testing.
If the once_n pin is driven low during a reset
operation, all IA186EB output and input/output
pins are placed in a high-impedance state.
This pin is weakly held high while resin_n is
active.
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Table 7. IA186EB Pin/Signal Descriptions (Continued)
Signal
oscout
Name
oscout
Pin
PLCC
40
LQFP
27
PQFP
70
p1.0
p1.1
p1.2
p1.3
p1.4
p1.5
p1.6
p1.7
p2.0
p1.0/gcs0_n
p1.1/gcs1_n
p1.2/gcs2_n
p1.3/gcs3_n
p1.4/gcs4_n
p1.5/gcs5_n
p1.6/gcs6_n
p1.7/gcs7_n
p2.0/rxd1
28
27
26
25
24
21
20
19
57
16
15
14
13
12
9
8
7
44
59
58
57
56
55
52
51
50
7
p2.1
p2.1/txd1
58
45
8
p2.2
p2.2/bclk1
59
46
9
p2.3
p2.3/sint1
55
42
5
p2.4
p2.4/cts1_n
56
43
6
p2.5
p2.5/bclk0
54
41
4
p2.6
p2.6
50
37
80
p2.7
p2.7
49
36
79
Description
oscillator output. Output. The oscout pin is
the output connection for an external crystal
that drives the IA186EB internal Pierce
oscillator. (When an external crystal is used, it
is connected between this pin and the clkin pin.
See clkin table entry.)
Note: If an external oscillator or clock source is
used to drive the IA186EB instead of a crystal,
oscout must be left unconnected (i.e., must
float). When the IA186EB is operating in the
ONCE mode, oscout does not float.
port 1, Bit [N] (N = 0–7). Output. Each pin of
Port 1, p1.0–p1.7, can function individually as a
general-purpose output line.
port 2, Bit [0]. Input/Output. This pin functions
as a general-purpose I/O line.
port 2, Bit [1]. Output. This pin functions as a
general-purpose output line.
port 2, Bit [2]. Input. This pin functions as a
general-purpose input line.
port 2, Bit [3]. Output. This pin functions as a
general-purpose output line.
port 2, Bit [4]. Input. This pin functions as a
general-purpose input line.
port 2, Bit [5]. Input. This pin functions as a
general-purpose input line.
port 2, Bit [6]. Input/Output (open drain). This
pin functions as a general-purpose bidirectional
input/output line.
port 2, Bit [7]. Input/Output (open drain). This
pin functions as a general-purpose bidirectional
input/output line.
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Table 7. IA186EB Pin/Signal Descriptions (Continued)
Signal
pdtmr
Name
pdtmr
Pin
PLCC
36
LQFP
24
PQFP
67
Description
power-down timer. Input/Output (push-pull).
Note: The IA186EB enters Powerdown Mode
when the PWRDN bit in the Power Control
Register is set to 1 and a HALT instruction is
executed. Exit from the Powerdown Mode
occurs upon receipt of a non-maskable interrupt
(i.e., assertion of the nmi input) or a reset (i.e.,
assertion of the resin_n input).
The pdtmr pin, which is normally connected to
an external capacitor, determines the amount of
time that the IA186EB waits before resuming
normal operation after an exit from the
Powerdown when a non-maskable interrupt is
received—essentially a delay between the
assertion of the nmi input and the enabling of
the IA186EB internal clocks. The delay
required depends on the start-up characteristics
of the crystal oscillator.
pereq
pereq
39
NA
NA
rd_n
rd_n
4
73
36
ready
ready
18
6
49
resin_n
resin_n
37
25
68
The pdtmr pin does not apply when the
Powerdown Mode is exited by the receipt of a
reset (i.e., the assertion resin_n).
numerics coprocessor external request. Input.
Active High. When asserted (high), this signal
indicates that a data transfer between an Intel
80C187 Numerics Coprocessor.and memory is
pending. This applies to the PLCC only.
read. Output. Active Low. When asserted
(low), rd_n indicates that the accessed memory
or I/O device must drive data from the location
being accessed onto the data bus.
ready. Input. Active High. When asserted
(high) the ready line indicates a bus-cycle
completion. This signal must be active to
terminate any bus cycle unless the IA186EB
Chip-Select Unit is configured to ignore ready.
reset input. Input. Active Low. When resin_n
is asserted (low), the IA186EB immediately
terminates any bus cycle in progress and
assumes an initialized state. All pins are driven
to a known state, and resout (see next table
entry) is asserted.
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Table 7. IA186EB Pin/Signal Descriptions (Continued)
Signal
resout
Name
resout
Pin
PLCC
38
LQFP
26
PQFP
69
rxd0
rxd0
53
40
3
rxd1
p2.0/rxd1
57
44
7
s0_n
s0_n
10
79
42
s1_n
s1_n
9
78
41
s2_n
s2_n
8
77
40
sint1
p2.3/sint1
55
42
5
t0in
t0in
46
33
76
t0out
t0out
45
32
75
t1in
t1in
48
35
78
Description
reset output. Output. Active High. When
resout is asserted, it indicates that the
IA186EB is being reset. The resout signal will
remain active (high) as long as resin_n
remains active (low).
Receive (rx) data, Serial Port 0. Input/Output.
This pin is the serial data input for Serial Port 0.
During synchronous serial communications,
rxd0 is bidirectional and functions an output for
data transmission (txd0 becomes the clock).
Receive (rx) data, Serial Port 1. Input/Output.
This pin is the serial data input for Serial Port 1.
During synchronous serial communications,
rxd1 is bidirectional and functions an output for
data transmission (txd1 becomes the clock).
statusN (N = 0–2). Output. During a bus cycle
the status (i.e., type) of cycle is encoded on
these lines as follows:
s2_n s1_n s0_n Bus Cycle Status
0
0
0
Interrupt Acknowledge
0
0
1
Read I/O
0
1
0
Write I/O
0
1
1
Processor HALT
1
0
0
Queue Instruction Fetch
1
0
1
Read Memory
1
1
0
Write Memory
1
1
1
No Bus Activity
serial interrupt, Serial Port 1. Output. Active
High. When sint1 is asserted (high), it
indicates that Serial Port 1 requires service.
timer 0 input. Input. Depending on the Timer
Mode programmed for Timer 0, this input is
used either as clock input or a control signal.
timer 0 output. Output. Depending on the
Timer Mode programmed for Timer 0, this
output can provide a single clock or a
continuous waveform.
timer 1 input. Input. Depending on the Timer
Mode programmed for Timer 1, this input is
used either as clock input or a control signal.
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Table 7. IA186EB Pin/Signal Descriptions (Continued)
Signal
t1out
Name
t1out
Pin
PLCC
47
LQFP
34
PQFP
77
test_n
test_n/busy
14
3
46
txd0
txd0
52
39
2
txd1
p2.1/txd1
58
45
8
ucs_n
ucs_n
30
18
61
vcc
vcc
1, 23,
42, 64
11, 29,
50, 71
13, 34,
54, 72
vss
vss
wr_n
wr_n
2, 22,
43, 63,
65, 84
5
10, 30,
49, 51,
70, 72
74
12, 14,
33, 35,
53, 73
37
Description
timer 1 output. Output. Depending on the
Timer Mode programmed for Timer 1, this
output can provide a single clock or a
continuous waveform.
test. Input. Active Low. When the test_n
input is high (i.e., not asserted), it causes the
IA186EB to suspend operation during the
execution of the WAIT instruction. Operation
resumes when the pin is sampled low
(asserted).
Transmit (tx) data, Serial Port 0. Output. This
pin is the serial data output for Serial Port 0.
During synchronous serial communications,
txd0 becomes the transmit clock (rxd0
functions as an output for data transmission).
Transmit (tx) data, Serial Port 1. Output. This
pin is the serial data output for Serial Port 1.
During synchronous serial communications,
txd1 becomes the transmit clock (rxd1
functions as an output for data transmission).
upper chip select. Output. Active Low. This
pin provides a chip select signal that will be
asserted (low) whenever the address of a
memory bus cycle is within the address space
programmed for that output.
Power (vcc). This pin provides power for the
IA186EB device. It must be connected to a
+5V DC power source.
Ground (vss). This pin provides the digital
ground (0V) for the IA186EB. It must be
connected to a vss board plane.
write. Output. Active Low. When asserted
(low), wr_n indicates that data available on the
data bus are to be latched into the accessed
memory or I/O device.
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2.3
Data Sheet
July 10, 2011
IA188EB Pin/Signal Descriptions
Descriptions of the pin and signal functions for the IA188EB microcontroller are provided in
Table 8.
Several of the IA188EB pins have different functions depending on the operating mode of the
device. Each of the different signals supported by a pin is listed and defined in Table 8—
indexed alphabetically in the first column of the table. Additionally, the name of the pin
associated with the signal as well as the pin numbers for the PLCC, LQFP, and LQFP packages
are provided in the ―Pin‖ column.
Table 8. IA188EB Pin/Signal Descriptions
Signal
a8
a9
a10
a11
a12
a13
a14
a15
a16
a17
a18
a19
ad0
ad1
ad2
ad3
ad4
ad5
ad6
ad7
ale
Name
a8
a9
a10
a11
a12
a13
a14
a15
a16
a17
a18
a19/once_n
ad0
ad1
ad2
ad3
ad4
ad5
ad6
ad7
ale
Pin
PLCC
62
67
69
71
73
75
77
79
80
81
82
83
61
66
68
70
72
74
76
78
6
bclk0
p2.5/bclk0
54
LQFP
48
53
55
57
59
61
63
65
66
67
68
69
47
52
54
56
58
60
62
64
75
PQFP
11
16
18
20
22
24
26
28
29
30
31
32
10
15
17
19
21
23
25
27
38
41
4
Description
address Bits [8-19]. Output. These pins
provide the 12 most-significant bits of the
Address Bus. During the entire IA188EB bus
cycle, Address Bits [8–19] are presented on the
bus and can be latched using the ale signal
(see table entry).
address/data Bits [0–7]. Input/Output. These
pins provide a multiplexed Address Bus and
Data Bus. During the address portion of the
IA188EB bus cycle, Address Bits [0–7] are
presented on the bus and can be latched using
the ale signal (see next table entry). During the
data portion of the IA188EB bus cycle, 8-bit
data are present on these lines.
address latch enable. Output. Active High.
This signal is used to latch the address
information during the address portion of a bus
cycle.
baud clock, Serial Port 0. Input. The bclk0 pin
can be used to provide an alternate clock
source for Serial Port 0. The input clock rate
cannot be greater than one-half the operating
frequency of the IA188EB.
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Table 8. IA188EB Pin/Signal Descriptions (Continued)
Signal
bclk1
Name
p2.2/bclk1
Pin
PLCC
59
LQFP
46
PQFP
9
clkin
clkin
41
28
71
clkout
clkout
44
31
74
cts0_n
cts0_n
51
38
1
cts1_n
p2.4/cts1_n
56
43
6
den_n
den_n
11
80
43
dt/r_n
dt/r_n
16
NA
NA
Description
baud clock, Serial Port 1. Input. The bclk1 pin
can be used to provide an alternate clock
source for Serial Port 1. The input clock rate
cannot be greater than one-half the operating
frequency of the IA188EB.
clock input. Input. The clkin pin is the input
connection for an external clock. An external
oscillator, operating at two times the required
processor operating frequency, can be
connected to this pin.
If a crystal is used to supply the clock, it is
connected between the clkin pin and the
oscout pin (see oscout table entry). When a
crystal is connected, it drives an internal Pierce
oscillator to the IA188EB.
clock output. Output. The clkout pin provides
a timing reference for inputs and outputs of the
IA188EB. This clock output is one-half the input
clock (clkin) frequency. The clkout signal has
a 50% duty cycle, transitioning every falling
edge of clkin.
clear to send, Serial Port 0. Input. Active Low.
When this input is high (i.e., not asserted), data
transmission from Serial Port 0 is inhibited.
When the signal is asserted (low), data
transmission is permitted.
clear to send, Serial Port 1. Input. Active Low.
When this input is high (i.e., not asserted), data
transmission from Serial Port 1 is inhibited.
When the signal is asserted (low), data
transmission is permitted.
data enable. Output. Active Low. This signal
is used to enable of bidirectional transceivers in
a buffered system. The den_n signal is
asserted (low) only when data are to be
transferred on the bus.
data transmit/receive. Output. This signal is
used to control the direction of data flow for
bidirectional buffers in a buffered system.
When dt/r_n is high, the direction indicated is
transmit; when dt/t_n is low, the direction
indicated is receive.
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Table 8. IA188EB Pin/Signal Descriptions (Continued)
Signal
gcs0_n
gcs1_n
gcs2_n
gcs3_n
gcs4_n
gcs5_n
gcs6_n
gcs7_n
hlda
Name
p1.0/gcs0_n
p1.1/gcs1_n
p1.2/gcs2_n
p1.3/gcs3_n
p1.4/gcs4_n
p1.5/gcs5_n
p1.6/gcs6_n
p1.7/gcs7_n
hlda
Pin
PLCC
28
27
26
25
24
21
20
19
12
LQFP
16
15
14
13
12
9
8
7
1
PQFP
59
58
57
56
55
52
51
50
44
hold
(input)
hold
(input)
13
2
45
int0
(input)
int1
(input)
int0
(input only)
int1
(input only)
31
19
62
32
20
63
int2
int2/inta0_n
33
21
64
int3
int3/inta1_n
34
22
65
int4 (input)
int4
(input only)
35
23
66
int2/inta0_n
33
inta0_n
21
64
Description
generic chip select n (n = 0–7). Output. Active
Low. When programmed and enabled, each of
these pins provide a chip select signal that will
be asserted (low) whenever the address of a
memory or I/O bus cycle is within the address
space programmed for that output.
hold acknowledge. Output. Active High.
When hlda is asserted (high), it indicates that
the IA188EB has relinquished control of the
local bus to another bus master in response to
a HOLD request (see next table entry).
When hlda is asserted, the IA188EB data bus
and control signals are floated, allowing another
bus master to drive the signals directly.
hold. Input. Active High. This signal is a
request indicating that an external bus master
wishes to gain control of the local bus. The
IA188EB will relinquish control of the local bus
between instruction boundaries not conditioned
by a lock prefix.
interrupt N (N = 0–4). Input/Output. Active
High. These maskable inputs interrupt program
flow and cause execution to continue at an
interrupt vector of a specific interrupt type as
follows:
int0:
int1:
int2:
int3:
int4:
Type 12
Type 13
Type 14
Type 15
Type 17
To allow interrupt expansion, int0 and int1 can
be used with the interrupt acknowledge signals
inta0_n and inta1_n (see next table entries) to
serve as external interrupt inputs or interrupt
acknowledge outputs.
interrupt acknowledge 0. Output. Active Low.
This pin provides an interrupt acknowledge
handshake in response to an interrupt request
on the int0 pin (see previous table entry).
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Table 8. IA188EB Pin/Signal Descriptions (Continued)
Signal
inta1_n
Name
int3/inta1_n
Pin
PLCC
34
LQFP
22
PQFP
65
lcs_n
lcs_n
29
17
60
lock_n
lock_n
15
4
47
nmi
nmi
17
5
48
once_n
a19/once_n
83
69
32
Description
interrupt acknowledge 1. Input/Output. Active
Low. This pin provides an interrupt
acknowledge handshake in response to an
interrupt request on the int1 pin (see previous
table entry).
lower chip select. Input/Output. Active Low.
This pin provides a chip select signal that will be
asserted (low) whenever the address of a
memory bus cycle is within the address space
programmed for that output.
lock. Output. Active Low. When asserted
(low), this signal indicates that the bus cycle in
progress is cannot be interrupted. While
lock_n is active, the IA188EB will not service
bus requests such as HOLD.
non-maskable interrupt. Input. Active High.
When the nmi signal is asserted (high), it
causes a Type 2 interrupt to be serviced by the
IA188EB.
Note: The assertion of nmi is latched internally
by the IA188EB.
on-circuit emulation. Input. Active Low. Note:
ONCE Mode is used for device testing.
If the once_n pin is driven low during reset, all
IA188EB output and input/output pins are
placed in a high-impedance state.
oscout
oscout
40
27
70
This pin is weakly held high while resin_n is
active.
oscillator output. Output. The oscout pin is
the output connection for an external crystal
that drives the IA188EB internal Pierce
oscillator. (When an external crystal is used, it
is connected between this pin and the clkin
pin—see clkin table entry.)
Note: If an external oscillator or clock source is
used to drive the IA188EB instead of a crystal,
oscout must be left unconnected (i.e., must
float). When the IA188EB is operating in the
ONCE mode, oscout does not float.
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Table 8. IA188EB Pin/Signal Descriptions (Continued)
Signal
p1.0
p1.1
p1.2
p1.3
p1.4
p1.5
p1.6
p1.7
p2.0
Name
p1.0/gcs0_n
p1.1/gcs1_n
p1.2/gcs2_n
p1.3/gcs3_n
p1.4/gcs4_n
p1.5/gcs5_n
p1.6/gcs6_n
p1.7/gcs7_n
p2.0/rxd1
Pin
PLCC
28
27
26
25
24
21
20
19
57
LQFP
16
15
14
13
12
9
8
7
44
PQFP
59
58
57
56
55
52
51
50
7
p2.1
p2.1/txd1
58
45
8
p2.2
p2.2/bclk1
59
46
9
p2.3
p2.3/sint1
55
42
5
p2.4
p2.4/cts1_n
56
43
6
p2.5
p2.5/bclk0
54
41
4
p2.6
p2.6
50
37
80
p2.7
p2.7
49
36
79
Description
port 1, Bit [N] (N = 0–7). Output. Each pin of
Port 1, p1.0–p1.7, can function individually as a
general-purpose output line.
port 2, Bit [0]. Input/Output. This pin functions
as a general-purpose I/O line.
port 2, Bit [1]. Output. This pin functions as a
general-purpose output line.
port 2, Bit [2]. Input. This pin functions as a
general-purpose input line.
port 2, Bit [3]. Output. This pin functions as a
general-purpose output line.
port 2, Bit [4]. Input. This pin functions as a
general-purpose input line.
port 2, Bit [5]. Input. This pin functions as a
general-purpose input line.
port 2, Bit [6]. Input/Output (open drain). This
pin functions as a general-purpose bidirectional
input/output line.
port 2, Bit [7]. Input/Output (open drain). This
pin functions as a general-purpose bidirectional
input/output line.
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Table 8. IA188EB Pin/Signal Descriptions (Continued)
Signal
pdtmr
Name
pdtmr
Pin
PLCC
36
LQFP
24
PQFP
67
Description
Power-down timer. Input/Output (push-pull).
Note: The IA188EB enters Powerdown Mode
when the PWRDN bit in the Power Control
Register is set to 1 and a HALT instruction is
executed. Exit from the Powerdown Mode
occurs upon receipt of a non-maskable interrupt
(i.e., assertion of the nmi input) or a reset (i.e.,
assertion of the resin_n input).
The pdtmr pin, which is normally connected to
an external capacitor, determines the amount of
time that the IA188EB waits before resuming
normal operation after an exit from the
Powerdown when a non-maskable interrupt is
received—essentially a delay between the
assertion of the nmi input and the enabling of
the IA188EB internal clocks. The delay
required depends on the start-up characteristics
of the crystal oscillator.
rd_n
rd_n
4
73
36
ready
ready
18
6
49
resin_n
resin_n
37
25
68
resout
resout
38
26
69
rfsh_n
rfsh_n
7
76
39
The pdtmr pin does not apply when the
Powerdown Mode is exited by the receipt of a
reset (i.e., the assertion resin_n).
read. Output. Active Low. When asserted
(low), rd_n indicates that the accessed memory
or I/O device must drive data from the location
being accessed onto the data bus.
ready. Input. Active High. When asserted
(high) the ready line indicates the completion of
a bus cycle. This signal must be active to
terminate any bus cycle unless the IA188EB
Chip-Select Unit is configured to ignore ready.
reset input. Input. Active Low. When resin_n
is asserted (low), the IA188EB immediately
terminates any bus cycle in progress and
assumes an initialized state. All pins are driven
to a known state, and resout (see next table
entry) is asserted.
reset output. Output. Active High. When
resout is asserted, it indicates that the IA188EB
is being reset. The resout signal will remain
active (high) as long as resin_n remains active
(low).
refresh. Output. Active Low. When rfsh_n is
asserted (low), it indicates that a refresh cycle is
in progress.
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Table 8. IA188EB Pin/Signal Descriptions (Continued)
Signal
rxd0
Name
rxd0
Pin
PLCC
53
LQFP
40
PQFP
3
rxd1
p2.0/rxd1
57
44
7
s0_n
s0_n
10
79
42
s1_n
s1_n
9
78
41
s2_n
s2_n
8
77
40
sint1
p2.3/sint1
55
42
5
t0in
t0in
46
33
76
t0out
t0out
45
32
75
t1in
t1in
48
35
78
t1out
t1out
47
34
77
Description
Receive (rx) data, Serial Port 0. Input/Output.
This pin is the serial data input for Serial Port 0.
During synchronous serial communications,
rxd0 is bidirectional and functions an output for
data transmission (txd0 becomes the clock).
Receive (rx) data, Serial Port 1. Input/Output.
This pin is the serial data input for Serial Port 1.
During synchronous serial communications,
rxd1 is bidirectional and functions an output for
data transmission (txd1 becomes the clock).
statusN (N = 0–2). Output. During a bus cycle
the status (i.e., type) of cycle is encoded on
these lines as follows:
s2_n
s1_n
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
s0_n
0
1
0
1
0
1
0
1
Bus Cycle Status
Interrupt Acknowledge
Read I/O
Write I/O
Processor HALT
Queue Instruction Fetch
Read Memory
Write Memory
No Bus Activity
serial interrupt, Serial Port 1. Output. Active
High. When sint1 is asserted (high), it
indicates that Serial Port 1 requires service.
timer 0 input. Input. Depending on the Timer
Mode programmed for Timer 0, this input is
used either as clock input or a control signal.
timer 0 output. Output. Depending on the
Timer Mode programmed for Timer 0, this
output can provide a single clock or a
continuous waveform.
timer 1 input. Input. Depending on the Timer
Mode programmed for Timer 1, this input is
used either as clock input or a control signal.
timer 1 output. Output. Depending on the
Timer Mode programmed for Timer 1, this
output can provide a single clock or a
continuous waveform.
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Data Sheet
July 10, 2011
Table 8. IA188EB Pin/Signal Descriptions (Continued)
Signal
test_n
Name
test_n
Pin
PLCC
14
LQFP
3
PQFP
46
txd0
txd0
52
39
2
txd1
p2.1/txd1
58
45
8
ucs_n
ucs_n
30
18
61
vcc
vcc
1, 23,
42, 64
11, 29,
50, 71
13, 34,
54, 72
vss
vss
wr_n
wr_n
2, 22,
43, 63,
65, 84
5
10, 30,
49, 51,
70, 72
74
12, 14,
33, 35,
53, 73
37
Description
test. Input. Active Low. When the test_n input
is high (i.e., not asserted), it causes the
IA188EB to suspend operation during the
execution of the WAIT instruction. Operation
resumes when the pin is sampled low
(asserted).
Transmit (tx) data, Serial Port 0. Output. This
pin is the serial data output for Serial Port 0.
During synchronous serial communications,
txd0 becomes the transmit clock (rxd0
functions as an output for data transmission).
Transmit (tx) data, Serial Port 1. Output. This
pin is the serial data output for Serial Port 1.
During synchronous serial communications,
txd1 becomes the transmit clock (rxd1
functions as an output for data transmission).
upper chip select. Output. Active Low. This
pin provides a chip select signal that will be
asserted (low) whenever the address of a
memory bus cycle is within the address space
programmed for that output.
Power (vcc). This pin provides power for the
IA188EB device. It must be connected to a +5V
DC power source.
Ground (vss). This pin provides the digital
ground (0V) for the IA188EB. It must be
connected to a vss board plane.
write. Output. Active Low. When asserted
(low), wr_n indicates that data available on the
data bus are to be latched into the accessed
memory or I/O device.
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3.
Data Sheet
July 10, 2011
Maximum Ratings, Thermal Characteristics, and DC Parameters
For the Innovasic Semiconductor IA186EB and IA188EB microcontrollers, the absolute
maximum ratings, thermal characteristics, and DC parameters are provided in Tables 9
through 11, respectively.
Table 9. IA186EB and IA188EB Absolute Maximum Ratings
Parameter
Storage Temperature
Supply Voltage with Respect to vss
Voltage on Pins other than Supply with Respect to vss
Rating
−40°C to +125°C
−0.3V to +6.0V
−0.3V to +(Vcc + 0.3)V
Table 10. IA186EB and IA188EB Thermal Characteristics
Symbol
TA
PD
ΘJa
TJ
Characteristic
Ambient Temperature
Power Dissipation
84-Pin PLCC Package
80-Pin PQFP Package
80-Pin LQFP Package
Average Junction Temperature
Value
-40°C to 85°C
MHz ICC V/1000
30.7
46
52
TA + (PD ΘJa)
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W
°C/W
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Table 11. IA186EB and IA188EB DC Parameters
Symbol
5.0V
Operation
VCC
3.3V
Operation
VCC
VIL
VIH
VOL
VOH
ILEAK
ILO
IID
CIN
COUT
Supply Voltage
Parameter
Min
4.5
Max
5.5
Units
V
Notes
–
Supply Voltage
3.0
3.6
V
–
Input Low Voltage
−0.3
0.3
VCC
V
Input High Voltage
0.7
VCC
–
3.5/2.4
–
VCC +
0.3
0.4
–
±1
V
input
hysteresis on
resin_n =
0.50V
–
V
V
µA
IOL = 12mA
IOH = −12 mA
0V ≤ VIN ≤ VCC
+ .147
− .147
+.625
−.625
mA
mA
VIN = VCC
VIN =0V
+ .227
− .227
+.833
−.833
mA
mA
VIN = VCC
VIN =0V
–
± 10
µA
–
0
0
90
5
5
mA
pF
pF
0.45 ≤ VOUT ≤
VCC
–
TF = 1 MHz
TF = 1 MHz
Output Low Voltage Vcc = 5.5V or 3.6V
Output High Voltage Vcc = 4.5V/3.0V
Input Leakage Current for Pins: ad15–ad0,
ad7–ad0 (IA188EB), ready, hold, resin_n; clkin,
test_n, nmi, int4–int0, t0in, t1in, rdx0, bclk0_n,
cts0_n, rxd1, bclk1_n, cts1_n, p2.6, p2.7
Input Leakage Current for Pins (@3.3V): pereq
Input Leakage Current for Pins (@3.3V):
a19/once_n, a18–a16, lock_n, error_n
Input Leakage Current for Pins (@5V): pereq
Input Leakage Current for Pins (@5V):
a19/once_n, a18–a16, lock_n, error_n
Output Leakage Current
Supply Current (IDLE) - @ 50 MHz
Input Pin Capacitance
Output Pin Capacitance
Operating temperature is -40°C to +85°C.
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4.
Functional Description
4.1
Device Architecture
Architecturally, the IA186EB and IA188EB microcontrollers include the following functional
modules:
Bus Interface Unit
Clock Generator
Interrupt Control Unit
Timer/Counter Unit
Serial Communications Unit
Chip-Select Unit
I/O Port Unit
Refresh Control Unit
Power Management Unit
A functional block diagram of the IA186EB/IA188EB is shown in Figure 10. Descriptions of
the functional modules are provided in the following subsections.
4.1.1
Bus Interface Unit
The IA186EB/IA188EB bus controller that generates local bus control signals and uses a
hold/hlda protocol to share the local bus with other bus masters. The bus controller generates
20 address bits, read and write control signals, and bus-cycle status information. A ready input is
used to extend a bus cycle beyond the minimum four clock cycles.
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2
IA186EB/IA188EB
8-Bit/16-Bit Microcontrollers
Figure 10. IA186EB/IA188EB Functional Block Diagram
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4.1.2
Data Sheet
July 10, 2011
Clock Generator
The IA186EB/IA188EB uses an on-chip clock generator to supply internal and external clocks.
The clock generator makes use of a crystal oscillator and includes a divide-by-two counter.
Figure 11 shows the various operating modes of the clock circuit. The clock circuit can use
either a parallel resonant fundamental mode crystal network (A) or a third-overtone mode crystal
network (B), or it can be driven by an external clock source (C).
The following parameters are recommended when choosing a crystal:
Temperature Range
– Application Specific
– ESR (Equivalent Series Resistance): 40 max
– C0 (Shunt Capacitance of Crystal): 7.0 pF max
– CL (Load Capacitance): 20 pF ± 2 pF
– Drive Level: 1 mW max
Figure 11. Clock Circuit Connection Options
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4.1.3
Data Sheet
July 10, 2011
Interrupt Control Unit
The IA186EB/IA188EB can receive interrupts from a number of sources, both internal and
external. The interrupt control unit serves to merge these requests on a priority basis, for
individual service by the CPU. Each interrupt source can be independently masked by the
Interrupt Control Unit (ICU) or all interrupts can be globally masked by the CPU.
Internal interrupt sources include the Timers and Serial Channel 0. External interrupt sources
come from the five input pins int0–int4. The NMI interrupt pin is not controlled by the ICU and
is passed directly to the CPU. Although the Timer and Serial channel each have only one request
input to the ICU, separate vector types are generated to service individual interrupts within the
Timer and Serial channel units.
4.1.4
Timer/Counter Unit
The IA186EB/IA188EB Timer/Counter Unit (TCU) provides three 16-bit programmable timers.
Two of these are highly flexible and are connected to external pins for control or clocking. A
third timer is not connected to any external pins and can only be clocked internally. However, it
can be used to clock the other two timer channels. The TCU can be used to count external
events, time external events, generate non-repetitive waveforms, and generate timed interrupts,
etc.
4.1.5
Serial Communications Unit
The Serial Control Unit (SCU) of the IA186EB/IA188EB contains two independent channels.
Each channel is identical in operation except that only Channel 0 is supported by the integrated
interrupt controller (Channel 1 has an external interrupt pin). Each channel has its own baud rate
generator that is independent of the Timer/Counter Unit, and can be internally or externally
clocked at up to one half the IA186EB/IA188EB operating frequency.
Independent baud rate generators are provided for each of the serial channels. For the
asynchronous modes, the generator supplies an 8x baud clock to both the receive and transmit
register logic. A 1x baud clock is provided in the synchronous mode.
4.1.6
Chip-Select Unit
The IA186EB/IA188EB Chip-Select Unit (CSU) integrates logic that provides up to ten
programmable chip-selects to access both memories and peripherals. In addition, each chip
select can be programmed to automatically insert additional clocks (wait-states) into the current
bus cycle and automatically terminate a bus cycle independent of the condition of the ready input
pin.
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4.1.7
Data Sheet
July 10, 2011
I/O Port Unit
The I/O Port Unit (IPU) on the IA186EB/IA188EB supports two 8-bit channels of input, output,
or input/output operation. Port 1 is multiplexed with the chip select pins and is output only.
Most of Port 2 is multiplexed with the serial channel pins.
4.1.8
Refresh Control Unit
The Refresh Control Unit (RCU) automatically generates a periodic memory read bus cycle to
keep dynamic or pseudo-static memory refreshed. A 9-bit counter controls the number of clocks
between refresh requests.
A 12-bit address generator is maintained by the RCU and is presented on the a1–a12 address
lines during the refresh bus cycle. Address Bits [a13–a19] are programmable to allow the refresh
address block to be located on any 8-Kbyte boundary.
4.1.9
Power Management Unit
The IA186EB/IA188EB Power Management Unit (PMU) is provided to control the power
consumption of the device. The PMU provides three power modes: Active, Idle, and
Powerdown.
Active Mode indicates that all units on the IA186EB/IA188EB are functional and the device
consumes maximum power (depending on the level of peripheral operation). Idle Mode freezes
the clocks of the execution and bus units at a logic zero state (all peripherals continue to operate
normally).
The Powerdown mode freezes all internal clocks at a logic zero level and disables the crystal
oscillator. All internal registers hold their values provided VCC is maintained. Current
consumption is reduced to just transistor junction leakage.
4.2
Peripheral Architecture
The IA186EB/IA188EB has integrated several common system peripherals with a CPU core to
create a compact, yet powerful system. The integrated peripherals are designed to be flexible
and provide logical interconnections between supporting units (e.g., the interrupt control unit
supports interrupt requests from the timer/counters or serial channels). The list of integrated
peripherals includes:
7-Input Interrupt Control Unit
3-Channel Timer/Counter Unit
2-Channel Serial Communications Unit
10-Output Chip-Select Unit
I/O Port Unit
Refresh Control Unit
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Power Management Unit
The registers associated with each integrated peripheral are contained within a 128 16 register
file called the Peripheral Control Block (PCB). The PCB can be located in either memory or I/O
space on any 256-byte address boundary.
Table 12 provides a list of the registers associated with the PCB.
Table 12. Peripheral Control Block Registers
PCB
Offset
00H
02H
04H
06H
08H
0AH
0CH
0EH
10H
12H
14H
16H
18H
1AH
1CH
1EH
Function
Reserved
PCB
Offset
40H
PCB
Offset
80H
Function
GCS0 Start
PCB
Offset
C0H
Function
Reserved
82H
GCS0 Stop
C2H
Reserved
84H
86H
GCS1 Start
GCS1 Stop
C4H
C6H
Reserved
Reserved
88H
GCS2 Start
C8H
Reserved
End Of
Interrupt
Poll
Poll Status
42H
Interrupt
Mask
Priority
Mask
In-Service
Interrupt
Request
Interrupt
Status
Timer
Control
Serial
Control
INT4
Control
INT0
Control
INT1
Control
INT2
Control
INT3
Control
48H
Function
Timer2
Count
Timer2
Compare
Reserved
Timer2
Control
Reserved
4AH
Reserved
8AH
GCS2 Stop
CAH
Reserved
4CH
4EH
Reserved
Reserved
8CH
8EH
GCS3 Start
GCS3 Stop
CCH
CEH
Reserved
Reserved
50H
Port 1
Direction
Port 1 Pin
90H
GCS4 Start
D0H
Reserved
92H
GCS4 Stop
D2H
Reserved
Port 1
Control
Port 1 Latch
94H
GCS5 Start
D4H
Reserved
96H
GCS5 Stop
D6H
Reserved
Port 2
Direction
Port 2 Pin
98H
GCS6 Start
D8H
Reserved
9AH
GCS6 Stop
DAH
Reserved
9CH
GCS7 Start
DCH
Reserved
9EH
GCS7 Stop
DEH
Reserved
44H
46H
52H
54H
56H
58H
5AH
5CH
5EH
Port 2
Control
Port 2 Latch
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Table 12. Peripheral Control Block Registers (Continued)
PCB
Offset
20H
Function
Reserved
PCB
Offset
60H
22H
Reserved
62H
PCB
Offset
24H
Offset
Reserved
PCB
Offset
64H
26H
Reserved
66H
28H
Reserved
68H
2AH
Reserved
6AH
2CH
2EH
30H
Reserved
Reserved
Timer0
Count
Timer0
Compare A
Timer0
Compare B
Timer0
Control
Timer1
Count
Timer1
Compare A
Timer1
Compare B
Timer1
Control
6CH
6EH
70H
32H
34H
36H
38H
3AH
3CH
3EH
Function
Serial0
Baud
Serial0
Count
Function
7CH
Serial0
Control
Serial0
Status
Serial0
RBUF
Serial0
TBUF
Reserved
Reserved
Serial1
Baud
Serial1
Count
Serial1
Control
Serial1
Status
Serial1
RBUF
Serial1
TBUF
Reserved
7EH
Reserved
72H
74H
76H
78H
7AH
PCB
Offset
A0H
Function
LCS Start
PCB
Offset
E0H
Function
Reserved
A2H
LCS Stop
E2H
Reserved
PCB
Offset
A4H
Function
Function
UCS Start
PCB
Offset
E4H
Reserved
A6H
UCS Stop
E6H
Reserved
A8H
Relocation
E8H
Reserved
AAH
Reserved
EAH
Reserved
ACH
AEH
B0H
ECH
EEH
F0H
Reserved
Reserved
Reserved
F2H
Reserved
F4H
Reserved
F6H
Reserved
F8H
Reserved
BAH
Reserved
Reserved
Refresh
Base
Refresh
Time
Refresh
Control
Refresh
Address
Power
Control
Reserved
FAH
Reserved
BCH
Step ID
FCH
Reserved
BEH
Reserved
FEH
Reserved
B2H
B4H
B6H
B8H
1
Note:
1
The Step ID register (offset 0xBC) for Revision 2 of the Innovasic device is read-only, and is
uniquely identified in software by having a value of 0x0080. The original Intel device
established a value between 0x0000 and 0x0002, depending on the revision of the part.
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4.3
Data Sheet
July 10, 2011
Reference Documents
Additional information on the operation and programming of the 80C186EB/80C188EB can be
found in the following Intel publications:
80C186EB/80C188EB and 80L186EB/80L188EB 16-Bit High-Integration Embedded
Processors (272433-006)
80C186EB/80C188EB Microprocessor User’s Manual (270830-00n)
5.
AC Specifications
This chapter defines the AC specifications of the IA186EB/IA188EB. Input characteristics are
provided in Figure 12 and Tables 13 and 14. Output characteristics are provided in Figure 13
and Tables 15 and 16. Relative timing characteristics are provided in Figure 14 and Table 17.
Clock input and clock output timing characteristics are provided in Figure 18 and Tables 18
and 19. Additional timing information is provided in Chapter 7, Bus Timing, and Chapter 8,
Instruction Execution Times.
The following test conditions were used to derive the values in Tables 13 – 16: Rev. 0 was tested
at 100C and 4.75V; Rev. 2 was tested at 100C and 4.5V.
clkout
50%
tCHIH
tCHIS
Min
Min
Valid
tCLIH
tCLIS
Min
Min
Valid
Figure 12. AC Input Characteristics
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For specific 5.0- and 3.3-volt characteristics, refer to Tables 13 and 14, respectively.
Table 13. AC Input Characteristics for 5.0-Volt Operation
Symbol
tCHIS
tCHIH
tCLIS
tCLIS
tCLIH
tCLIH
Pins
test_n, nmi, int4–int0, bclk1–bclk0, t1in–t0in, ready, cts1_n–cts0_n, p2.6, p2.7
test_n, nmi, int4–int0, bclk1–bclk0, t1in–t0in, ready, cts1_n–cts0_n
ad15–ad0, ad7–ad0 (IA188EB), ready
hold, pereq, error_n
ad15–ad0, ad7–ad0 (IA188EB), ready
hold, pereq, error_n
Min Max Units
10
–
ns
3
–
ns
10
–
ns
10
–
ns
3
–
ns
3
–
ns
Table 14. AC Input Characteristics for 3.3-Volt Operation
Symbol
tCHIS
tCHIH
tCLIS
tCLIS
tCLIH
tCLIH
Pins
test_n, nmi, int4–int0, bclk1–bclk0, t1in–t0in, ready, cts1_n–cts0_n, p2.6, p2.7
test_n, nmi, int4–int0, bclk1–bclk0, t1in–t0in, ready, cts1_n–cts0_n
ad15–ad0, ad7–ad0 (IA188EB), ready
hold, pereq, error_n
ad15–ad0, ad7–ad0 (IA188EB), ready
hold, pereq, error_n
Min Max Units
10
–
ns
3
–
ns
10
–
ns
10
–
ns
3
–
ns
3
–
ns
Figure 13. AC Output Characteristics
For specific 5.0- and 3.3-volt characteristics, refer to Tables 15 and 16, respectively.
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Table 15. AC Output Characteristics for 5.0-Volt Operation
Symbol
tCHOV
tCLOV
tCHOF
tCLOF
Parameter
Min Max Units
ale, s2–s0_n, den_n, dt/r_n, bhe_n, rfsh_n (IA188EB), lock_n, a19–a16
3
17
ns
gcs0–gcs7_n, lcs_n, ucs_n, ncs_n, rd_n, wr_n
3
20
ns
bhe_n, rfsh_n (IA188EB), den_n, lock_n, resout, hlda, t0out, t1out, a19–a16 3
17
ns
rd_n , wr_n, gcs7–gcs0_n, lcs_n, ucs_n, ad15–ad0, ad7–ad0 (IA188EB),
3
20
ns
a15–a8 (IA188EB), ncs_n, inta1_n–inta0_n, s2_n–s0_n
re_n, wr_n, bhe_n, rfsh_n (IA188EB), dt/r_n, lock_n, s2_n–s0_n, a19–a16
0
20
ns
den_n, ad15–ad0, ad7–ad0 (IA188EB), a15–a8 (IA188EB)
0
20
ns
Table 16. AC Output Characteristics for 3.3-Volt Operation
Symbol
tCHOV
tCLOV
tCHOF
tCLOF
Parameter
Min Max Units
ale, s2–s0_n, den_n, dt/r_n, bhe_n, rfsh_n (IA188EB), lock_n, a19–a16
3
25
ns
gcs0–gcs7_n, lcs_n, ucs_n, ncs_n, rd_n, wr_n
3
30
ns
bhe_n, rfsh_n (IA188EB), den_n, lock_n, resout, hlda, t0out, t1out, a19–a16 3
25
ns
rd_n , wr_n, gcs7–gcs0_n, lcs_n, ucs_n, ad15–ad0, ad7–ad0 (IA188EB),
3
30
ns
a15–a8 (IA188EB), ncs_n, inta1_n–inta0_n, s2_n–s0_n
re_n, wr_n, bhe_n, rfsh_n (IA188EB), dt/r_n, lock_n, s2_n–s0_n, a19–a16
0
30
ns
den_n, ad15–ad0, ad7–ad0 (IA188EB), a15–a8 (IA188EB)
0
30
ns
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Figure 14. Relative Timing Characteristics
For specific relative timing characteristics, refer to Table 17.
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Table 17. Relative Timing Characteristics
Symbol
tLHLL
tAVLL
tPLLL
tLLAX
tLLWL
tLLRL
tWHLH
tAFRL
tRLRH
tWLWH
tRHAV
tWHDX
tWHPH
tRHPH
tPHPL
tOVRH
tRHOX
5.1
Parameter
ale Rising to ale Falling
Address Valid to ale Falling
Chip Selects Valid to ale Falling
Address Hold from ale Falling
ale Falling to wr_n Falling
ale Falling to rd_n Falling
wr_n Rising to ale Rising
Address Float to rd_n Falling
rd_n Falling to rd_n Rising
wr_n Falling to wr_n Rising
rd_n Rising to Address Active
Output Data Hold after wr_n Rising
wr_n Rising to Chip Select Rising
rd_n Rising to Chip Select Rising
cs_n inactive to cs_n active
once_n Active to resin_n Rising
once_n Hold to resin_n Rising
Min
t – 15
½t –10
½t –10
½t –10
½t –15
½t –15
½t –10
0
(2t) – 5
(2t) – 5
t – 15
t – 15
½t –10
½t –10
½t –10
t
t
Max
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Ns
AC Test Conditions
The AC specifications are tested with the 50-pF load shown in Figure 15. Specifications are
measured at the VCC/2 crossing point unless otherwise specified.
Figure 15. AC Test Load
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5.2
Data Sheet
July 10, 2011
Clock Input and Clock Output Timing Characteristics
For clock input and clock output timing characteristics for both 5.0- and 3.3-volt operation, see
Tables 18 and 19, respectively.
Figure 16. Clock Input and Clock Output Timing Characteristics
Table 18. Clock Input and Clock Output Timing Characteristics for 5.0-Volt Operation
Item
–
Symbol
XTF
Parameter
clkin
Frequency
clkin Period
Min
0
Max
50
Units
MHz
–
1
TCKIN
2
20
∞
ns
–
TCHCK
clkin High
Time
10
∞
ns
Measure for VIH for high time, NIL for
low time.
3
TCLCK
10
∞
ns
4
TCKLH
clkin Low
Time
clkin Rise
Time
1
5
ns
5
TCKHL
clkin Fall
Time
1
5
ns
6
TCICO
Measure for VIH for high time, NIL for
low time.
Only required to guarantee ICC.
Maximum limits are bounded for TC,
TCH, and TCL.
Only required to guarantee ICC.
Maximum limits are bounded for TC,
TCH, and TCL.
Specified for a 50-pF load.
7
8
TCLCL
TCHCL
9
TCCCH
10
TCH1CH2
11
TCL2CL1
clkin to clkout
0
11.5
Delay
clkout Period
–
2TCKIN
clkout High (TCLCL/2) (TCLCL/2)
Time
–5
+5
clkout Low (TCLCL/2) (TCLCL/2)
Time
–5
+5
clkout Rise
1
6
Time
clkout Fall
1
6
Time
ns
Notes
ns
–
Measure for VIH for high time, NIL for
low time.
Measure for VIH for high time, NIL for
low time.
Specified for a 50-pF load.
ns
Specified for a 50-pF load.
ns
ns
ns
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Table 19. Clock Input and Output Characteristics for 3.3-Volt Operation
Item
–
Symbol
XTF
1
2
TC
TCH
3
TCL
4
TCR
5
TCF
6
XTCD
7
8
T
TPH
9
TPL
10
TPR
11
TPF
Parameter
clkin
Frequency
clkin Period
clkin High
Time
clkin Low Time
Min
0
Max
32
Units
MHz
30
15
∞
∞
ns
ns
15
∞
ns
clkin Rise
Time
clkin Fall Time
1
5
ns
1
5
ns
clkin to clkout
Delay
clkout Period
clkout High
Time
clkout Low
Time
clkout Rise
Time
clkout Fall
Time
0
14.5
ns
–
(T/2)
–5
(T/2)
–5
1
2TC
(T/2)
+5
(T/2)
+5
6
ns
ns
ns
–
Measure for VIH for high time, NIL for low
time.
Measure for VIH for high time, NIL for low
time.
Specified for a 50-pF load.
1
6
ns
Specified for a 50-pF load.
ns
Notes
–
–
Measure for VIH for high time, NIL for low
time.
Measure for VIH for high time, NIL for low
time.
Only required to guarantee ICC. Maximum
limits are bounded for TC, TCH and TCL.
Only required to guarantee ICC. Maximum
limits are bounded for TC, TCH and TCL.
Specified for a 50-pF load.
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5.3
Data Sheet
July 10, 2011
Serial Port Mode 0 Timing Characteristics
Serial Port Mode 0 timing characteristics are illustrated in Figure 17 and collected in Table 20.
Figure 17. Serial Port Mode 0 Timing Characteristics
Table 20. Serial Port Mode 0 Timing Characteristics
Symbol
tXLXL
tXLXH
tXLXH
tXHXL
tXHXL
tQVXH
tQVXH
tXHQX
tXHQX
tXHQZ
tDVXH
tXHDX
Parameter
txd Clock Period
txd Clock Low to Clock High (n > 1)
txd Clock Low to Clock High (n = 1)
txd Clock High to Clock Low (n > 1)
txd Clock High to Clock Low (n = 1)
rxd Output Data Setup to txd Clock High (n > 1)
rxd Output Data Setup to txd Clock High (n = 1)
rxd Output Data Hold after txd Clock High (n > 1)
rxd Output Data Hold after txd Clock High (n = 1)
rxd Output Data Float after Last txd Clock High
rxd Input Data Setup to txd Clock High
rxd Input Data Hold after txd Clock High
Minimum
t (n +1)
2t – 35
t – 35
(n – 1) t – 35
t – 35
(n – 1) t – 35
t – 35
2t – 35
t – 35
–
t + 20
0
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Maximum
–
2t + 35
t + 35
(n – 1) t + 35
t + 35
–
–
–
–
t + 20
–
–
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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6.
Data Sheet
July 10, 2011
Reset Operation
The IA186EB/IA188EB will perform a reset operation any time the resin_n pin is active.
Figure 18 shows the reset sequence when power is applied to the IA186EB/IA188EB. An
external clock connected to clkin must not exceed the VCC threshold being applied to the
processor. This is normally not a problem if the clock driver is supplied with the same VCC that
supplies the processor. When attaching a crystal to the device, resin_n must remain active until
both VCC and clkout are stable (the length of time is application-specific and depends on the
startup characteristics of the crystal circuit). The resin_n pin is designed to operate correctly
using an RC reset circuit, but the designer must ensure that the ramp time for VCC is not so long
that resin_n is never really sampled at a logic low level when VCC reaches minimum operating
conditions.
Note: Failure to assert resin_n while the device is powering up will result in unpredictable
operation.
Figure 19, Warm Reset Timing, shows the timing sequence when resin_n is applied after Vcc is
stable and the device has been operating. Any bus operation that is in progress at the time
resin_n is asserted will terminate immediately.
While resin_n is active, bus signals lock_n, a19/once_n, and a18–a16 are configured as inputs
and weakly held high by internal pull-up transistors. Only a19/ once_n can be overdriven to a
low-to-enable ONCE Mode.
7.
Bus Timing
Figures 18 through 26 on the following pages present the various bus cycles that are generated
by the processor. The figures show the relationship of the various bus signals to clkout.
Together with the information present in AC Characteristics, the figures allow the user to
determine all the critical timing analysis needed for a given application.
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Figure 18. Cold Reset Timing
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Figure 19. Warm Reset Timing
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ad15-ad0 (IA186EB);
ad7-ad0 (IA188EB)
gcs7_n - gcs0_n,
lcs_n, ucs_n
Figure 20. Read, Fetch, and Refresh Cycle Timing
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gcs7_n - gcs0_n,
lcs_n, ucs_n
Figure 21. Write Cycle Timing
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Figure 22. Halt Cycle Timing
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Figure 23. Interrupt Acknowledge (inta1_n, inta0_n) Cycle Timing
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s2_n–s0_n
a19/once_n,
a18–a16
bhe_n (IA186EB),
rfsh_n (IA188EB)
ad15–ad0 (IA186EB);
a15–a8, ad7–ad0
(IA188EB)
gcs7_n–gcs0_n,
ucs_n, lcs_n
Figure 24. hold/hlda Timing
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s2_n–s0_n
s2_n–s0_n
a19/once_n,
a19/once_n,
a18–a16
a18–a16
bhe_n
(IA186EB),
wr_n, lock_n;
rfsh_n
bhe_n (IA188EB)
(IA186EB);
rfsh_n (IA188EB)
ad15–ad0 (IA186EB);
a15–a8, ad7–ad0
(IA188EB)
gcs7_n–gcs0_n,
ucs_n,
lcs_n
pcs6_n–pcs0_n,
mcs3_n–mcs0_n,
lcs_n, ucs_n
Figure 25. Refresh During Hold Acknowledge Timing
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Figure 26. Ready Timing
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8.
Data Sheet
July 10, 2011
Instruction Execution Times
Table 21 provides IA186EB and IA188EB execution times, mnemonic instruction, and
additional information on execution, if required. The execution times apply to all versions of the
parts.
Table 21. Instruction Set Timing
Instruction
AAA
AAD
AAM
AAS
ADC Immediate to accumulator
ADC Immediate to
register/memory
ADC Register/memory with
register to either
ADD Immediate to accumulator
ADD Immediate to
register/memory
ADD Register/memory with
register either
AND Immediate to accumulator
AND Immediate to
register/memory
AND Register/memory and
register to either
BOUND
CBW
CLC
CLD
CLI
CMC
CMPS
CS
CWD
DAA
DAS
DEC Register
DEC Register/memory
Clock Cycles
IA186EB
IA188EB
3
3
6
6
40
40
3
3
1
1
3
13
Comments
–
–
–
–
–
–
1/16
1/24
register/memory
1
1/19
1
1/32
register/memory
1/20
1/28
1
1/24
1
1/33
1/12
1/15
20/40
1
1
1
1
2
9
1
1
4
2
1
1/24
24/64
4
1
1
1
2
20
1
1
4
2
1
1/32
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–
–
register/memory
Interrupt not taken/Interrupt taken
–
–
–
–
–
–
–
–
–
–
–
register/memory
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Table 21. Instruction Set Timing (Continued)
Instruction
DIV Memory-Byte
DIV Memory-Word
DIV Register-Byte
DIV Register-Word
IDIV Memory-Byte
IDIV Memory-Word
IDIV Register-Byte
IDIV Register-Word
IMUL Immediate (signed)
IMUL Memory-Byte
IMUL Memory-Word
IMUL Register-Byte
IMUL Register-Word
INC Register
INS
INS (repeated n times)
INT Type specified
INT Type 3
INTO
IRET
JA
JAE
JB
JBE
JCXZ
JE
JG
JGE
JL
JLE
JMP Direct intersegment
JMP Direct within segment
JMP Short/long
JNA
JNAE
JNB
JNBE
JNE
JNG
JNGE
JNL
JNLE
JNO
JNP
Clock Cycles
IA186EB
IA188EB
46
46
49
51
39
39
39
39
46
46
49
51
39
39
39
39
5/24
5/33
4
20
13
28
5
5
5
5
1
1
8
16
8+8n
16+16n
33
41
33
41
33
48
30
30
3/5
3/5
3/5
3/5
3/5
3/5
3/5
3/5
3/4
3/4
3/5
3/5
3/5
3/5
3/5
3/5
3/5
3/5
3/5
3/5
3
3
3
3
4
4
3/5
3/5
3/5
3/5
3/5
3/5
3/5
3/5
3/5
3/5
3/5
3/5
3/5
3/5
3/5
3/5
3/5
3/5
3/5
3/5
3/5
3/5
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Comments
–
–
–
–
–
–
–
–
register/memory
–
–
–
–
–
–
–
–
–
–
–
Jump not taken/Jump taken
Jump not taken/Jump taken
Jump not taken/Jump taken
–
–
–
Jump not taken/Jump taken
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Table 21. Instruction Set Timing (Continued)
Instruction
JNS
JNZ
JO
JP
JPE
JPO
JS
JZ
LAHF
LDS
LEA
LEAVE
LES
LOCK
LODS
LODS (repeated n times)
LOOP
LOOPE
LOOPNE
LOOPNZ
LOOPZ
MOV Accumulator to memory
MOV Immediate to register
MOV Immediate to
register/memory
MOV Memory to accumulator
MOV Register to
Register/Memory
MOV Register/memory to
register
MOV Register/memory to
segment register
MOV Segment register to
register/memory
MOVS
MOVS (repeated n times)
MUL Memory-Byte
MUL Memory-Word
MUL Register-Byte
MUL Register-Word
NEG
NOP
NOT
OR Immediate to accumulator
Clock Cycles
IA186EB
IA188EB
3/5
3/5
3/5
3/5
3/5
3/5
3/5
3/5
3/5
3/5
3/5
3/5
3/5
3/5
3/5
3/5
2
2
1/24
1/33
3
3
12
12
12
32
1
1
8
12
8+8n
12+12n
3/4
3/4
3/4
3/4
3/4
3/4
3/4
3/4
3/4
3/4
5
8/12
1
1
1/5
1/12
5
2/5
8/12
2/20
2/5
2/20
2/5
2/20
2/5
2/20
24
24+24n
16
15
5
5
1/32
1
1/24
1
32
32+32n
20
25
5
5
1/15
1
1/24
1
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Comments
Jump not taken/Jump taken
–
register/memory
–
–
–
–
–
–
Loop not taken/Loop taken
Loop not taken/Loop taken
8-bit/16-bit
register/memory
8-bit/16-bit
register/memory
–
–
–
–
–
–
register/memory
–
register/memory
–
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Table 21. Instruction Set Timing (Continued)
Instruction
OR Immediate to
register/memory
OR Register/memory and
register to either
OUT Fixed port
OUT Variable port
OUTS
OUTS (repeated n times)
POP Memory
POP Register
POP Segment register
POPA
POPF
PUSH Immediate
PUSH Memory
PUSH Register
PUSH Segment register
PUSHA
PUSHF
RET Inter-segment
RET Inter-segment adding
immediate to SP
RET Within segment
RET Within segment adding
immediate to SP
ROL Register/Memory by 1
ROL Register/Memory by CL
ROL Register/Memory by
Count
ROR Register/Memory by 1
ROR Register/Memory by CL
ROR Register/Memory by
Count
SAHF
SBB Immediate from
accumulator
SBB Immediate from
register/memory
SBB Register/memory and
register to either
SCAS
SCAS (repeated n times)
SHL Register/Memory by 1
Clock Cycles
IA186EB
IA188EB
1/32
1/32
Comments
register/memory
1/32
1/24
5
5
8
8+8n
10
10
16
80
13
8
15
4
4
64
4
14
25
8/12
12
12/20
12/20+12/20n
20
12
12
93
13
12
28
12
12
72
16
21
21
8-bit/16-bit
–
8-bit/16-bit
8-bit/16-bit
–
–
–
–
–
–
–
–
–
–
–
–
–
14
16
13
13
–
–
1/8
1/8
1/8
1/16
1/16
1/24
register/memory
1/8
1/8
1/8
1/16
1/16
1/24
2
1
2
1
–
–
1/15
1/28
register/memory
1/11
1/40
register/memory
11
11+8n
5
8/12
8/12+8/12n
1/32
8-bit/16-bit
8-bit/16-bit
register/memory
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Table 21. Instruction Set Timing (Continued)
Instruction
SHL Register/Memory by CL
SHL Register/Memory by
Count
SHR Register/Memory by 1
SHR Register/Memory by CL
SHR Register/Memory by
Count
SS
STC
SUB Immediate from
accumulator
SUB Immediate from
register/memory
SUB Register/memory and
register to either
STD
STI
STOS
STOS (repeated n times)
TEST Immediate data and
accumulator
TEST Immediate data and
register/memory
TEST Register/memory and
register
WAIT
XCHG Register with
accumulator
XCHG Register/memory with
register
XLAT
XOR Immediate to accumulator
XOR Immediate to
register/memory
XOR Register/memory and
register to either
Clock Cycles
IA186EB
IA188EB
1/20
1/24
1/11
1/24
Comments
register/memory
1/5
1/20
1/11
1/24
1/28
1/24
1
1
1
1
1
1
–
–
-
1/11
1/28
register/memory
1/15
1/40
1
1
6
6+4n
1
1
1
8
8+8n
1
–
–
–
–
–
1/16
1/16
register/memory
1/12
1/20
register/memory
1
2
1
2
test_n = 0
–
3/16
3/20
register/memory
16
1
1/11
8
1
1/32
–
register/memory
1/16
1/32
register/memory
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Innovasic Part Number Cross-Reference
Tables 22 through 24 cross-reference the Innovasic part number with the corresponding Intel part
number.
Table 22. Innovasic Part Number Cross-Reference for the PLCC
Innovasic Part Number
IA186EBPLC84IR2
lead free (RoHS-compliant)
IA188EBPLC84IR2
lead free (RoHS-compliant)
Intel Part Number
EE80C186EB25
EE80C186EB20
EN80C186EB25
EN80C186EB20
EN80C186EB13
N80C186EB25
N80C186EB20
N80C186EB13
TN80C186EB25
TN80C186EB20
TN80C186EB13
N80L186EB16
N80L186EB13
TN80L186EB16
TN80L186EB13
EN80L186EB13
EE80C188EB25
EE80C188EB20
EE80C188EB13
EN80C188EB25
EN80C188EB20
EN80C188EB13
N80C188EB25
N80C188EB20
N80C188EB13
TN80C188EB25
TN80C188EB20
TN80C188EB13
EE80L188EB16
EN80L188EB13
N80L188EB16
N80L188EB13
TN80L188EB16
TN80L188EB13
Package Type
84-Pin PLCC
Temperature Grades
Commercial and
industrial
84-Pin PLCC
Commercial and
industrial
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Table 23. Innovasic Part Number Cross-Reference for the PQFP
Innovasic Part Number
IA186EBPQF80IR2
lead free (RoHS-compliant)
IA188EBPQF80IR2
lead free (RoHS-compliant)
Intel Part Number
EG80C186EB25
ES80C186EB20
ES80C186EB13
S80C186EB25
S80C186EB20
S80C186EB13
TS80C186EB25
TS80C186EB20
TS80C186EB13
EG80L186EB16
EG80L186EB13
S80L186EB16
S80L186EB13
TS80L186EB16
TS80L186EB13
EG80C188EB25
ES80C188EB20
S80C188EB25
S80C188EB20
S80C188EB13
TS80C188EB25
TS80C188EB20
TS80C188EB13
ES80L188EB13
TS80L188EB16
TS80L188EB13
Package Type
80-Pin PQFP
Temperature Grades
Commercial and
industrial
80-Pin PQFP
Commercial and
industrial
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Table 24. Innovasic Part Number Cross-Reference for the LQFP
Innovasic Part Number
IA186EBPLQ80IR2
lead free (RoHS-compliant)
IA188EBPLQ80IR2
lead free (RoHS-compliant)
Intel Part
Number
YW80C186EB25
YW80C186EB20
SB80C186EB25
SB80C186EB20
SB80C186EB13
YW80L186EB16
YW80L186EB13
SB80L186EB16
SB80L186EB13
YW80C188EB25
YW80C188EB20
SB80C188EB25
SB80C188EB20
SB80C188EB13
YW80L188EB16
YW80L188EB13
SB80L188EB16
SB80L188EB13
Package Type
Temperature Grades
80-Pin LQFP
Commercial and
industrial
80-Pin LQFP
Commercial and
industrial
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9.
Data Sheet
July 10, 2011
Errata
The following errata are associated with Version 0 of the IA186EB/IA188EB. A workaround to
the identified problem has been provided where possible.
9.1
Summary
Table 25 presents a summary of errata.
Table 25. Summary of Errata
Errata No.
Problem
Ver. 0
Ver. 2
Fixed
1
Alternate Mode (TxCON[1] == 1) for timer 0 and 1 has some functional
issues.
Exists
2
When the extension byte (mod field) is set to ―11,‖ some instructions will
cause the CPU to hang.
Exists
3
When the chip is put in SFNM mode for INT0 or INT1, the LVL bit is
automatically set for those interrupts.
Exists
4
Timer 2 will stop or not start counting.
Exists
Fixed
5
Write does not occur when counter is actively counting.
Exists
Fixed
6
Program Counter can become corrupted if an interrupt occurs.
Exists
Fixed
7
Bound instruction uses bad data when index addresses are on odd
boundary in memory.
Exists
Fixed
8
Pin LOCK_n does not have an internal pullup and will float during reset
and bus hold.
Exists
Exists
9
The Relocation Register (RELREG, PCB offset 0xA8) can only be modified
by an 8-bit write.
Exists
Exists
10
When the timer compare register for any of the timers is set to x0000, the
max count is xFFFF instead of x10000 as in the OEM part.
Exists
Exists
11
NMI cannot bring chip out of powerdown mode.
-
Exists
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Errata No.
Data Sheet
July 10, 2011
Problem
Ver. 0
Ver. 2
12
Illegal serial port modes do not match OEM part.
Exists
Exists
13
Non-maskable interrupt (NMI) can be pre-empted by maskable interrupt.
Exists
Exists
14
Ready signal may not be recognized in bus cycles with zero wait states.
Exists
Exists
9.2
Detail
Errata No. 1
Problem: Alternate Mode (TxCON[1] == 1) for timer 0 and 1 has some functional issues.
Description:
TxOUT will continuously toggle at 1/2 CLKOUT regardless of count register values.
The maxcount compare will not work. The live count will compare against TxCMPA and
TxCMPB in alternate cycles. This could cause a compare (and the associated interrupt,
or switch the intended compare, or stop counting altogether) to occur early or not at all.
The TxOUT pin may start in the wrong state if the user writes to TxCON register
Bit [12].
When in retrigger mode, Timer 1 will not function correctly. Input pulses on T0IN will
cause counter to begin counting.
Workaround: None.
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Errata No. 2
Problem: When the extension byte (mod field) is set to ―11,‖ some instructions will cause the
CPU to hang.
Description: Although there are faster versions of each instruction (these are not commonly
used by compilers), the following instructions will cause the CPU to hang when the extension
byte (mod field) is set to ―11‖:
8D (LEA)
8F (POP memory)
C6 (MOV immediate8 to memory/register)
C7 (MOV immediate16 to memory/register)
FE (PUSH memory)
FF (PUSH memory)
Workaround: Substitute instructions in the following table.
Instruction
8D (LEA)
8F (POP memory)
C6 (MOV immediate8 to memory/register)
C7 (MOV immediate16 to memory/register)
FE (PUSH memory)
FF (PUSH memory)
Workaround
Use MOV register (89 or 8B)
Use POP register (0101_0xxx)
Use MOV immediate8 to register (1011_0xxx)
Use MOV immediate16 to register (1011_1xxx)
Use PUSH register (0101_0xxx)
Use PUSH register (0101_0xxx)
Errata No. 3
Problem: When the chip is put in SFNM mode for INT0 or INT1, the LVL bit is automatically
set for those interrupts.
Workaround: None.
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Errata No. 4
Problem: Timer 2 will stop or not start counting.
Description: Writing a logic ―1‖ to unused bits in the timer control register can cause the timer
to stop counting or to never start counting.
Workaround: Do not write a logic ―1‖ to any unused or reserved bits in the timer control
register.
Errata No. 5
Problem: Write does not occur when counter is actively counting.
Description: If a timer incremented its count register to the currently active compare register
during a write to that count register, the write would not occur.
Workaround: Do not write count register while that counter is actively counting.
Errata No. 6
Problem: Program Counter can become corrupted if an interrupt occurs.
Description: If an interrupt occurs during the decode stage of a TEST instruction using an
opcode of the form 1111_0111_1100_0xxx, the Program Counter could become corrupted upon
returning from the interrupt handler.
Workaround: None.
Errata No. 7
Problem: Bound instruction uses bad data when index addresses are on odd boundary in
memory.
Description: BOUND instruction will use bad data if index address LSB is a ―1‖ in memory.
Workaround: None.
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Errata No. 8
Problem: Pin LOCK_n does not have an internal pullup.
Description: Because Pin LOCK_n does not have an internal pullup, it will float during reset
and bus hold.
Workaround: An external pullup may be necessary if there is high external load on the signal.
Errata No. 9
Problem:
The Relocation Register (RELREG, PCB offset 0xA8) can only be modified by an 8-bit write.
Description: The Relocation Register (RELREG, PCB offset 0xA8) can only be modified by an
8-bit write. A 16-bit write will have no effect. The 186 EB is unaffected.
Workaround: Use an 8-bit access to affect the RELREG register.
Errata No. 10
Problem:
When the timer compare register for any of the timers is set to x0000, the max count is xFFFF
instead of x10000 as in the OEM part.
Description: The timer output will change one count earlier than it should when the max count
is set to x0000.
Workaround: The workaround is application dependent. Please contact Innovasic Technical
Support if this erratum is an issue.
Errata No. 11
Problem:
NMI cannot bring chip out of powerdown mode.
Description: Only a reset brings the part out of powerdown after a HLT instruction is executed
with the PWRDN bit set in the PWRCON register.
Workaround: Use IDLE instead of PWRDN.
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Errata No. 12
Problem:
Illegal serial port modes do not match OEM part.
Description: If the mode bits of the serial control register (S1CON, S0CON) are set to an
illegal encoding (0x5, 0x6, or 0x7), the Innovasic part acts as though it were in mode 4. The
OEM part acts as if it were in mode 1.
Workaround: Use a valid encoding for serial mode.
Errata No. 13
Problem:
Non-maskable interrupt (NMI) can be pre-empted by maskable interrupt.
Description: When instruction execution unit is in Decode state for 2 or more consecutive
cycles and an NMI is recognized, it could be pre-empted by a maskable interrupt.
Workaround: None.
Errata No. 14
Problem:
Ready signal may not be recognized in bus cycles with zero wait states.
Description: When a chip select is set to use the ready signal to extend a bus cycle that
normally has no wait states (Start register bits 3-0 == 0000), the ready signal may not be
recognized in time to extend the bus cycle.
Workaround: Set wait states to 1 or more if using ready to extend bus cycles.
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Revision History
Table 26 presents the sequence of revisions to document IA211080314.
Table 26. Revision History
Date
July 30, 2008
Revision
Description
Page(s)
00
First edition released.
NA
October 13, 2008
01
Pin number range ―ad15–a8‖ corrected to ―a15–
a8‖ in Figures 26 and 27. Errata No. 4 added.
[Also cover page, header, footer, and errata
chapter reformatted to meet publication
standards.]
66, 67, 78, 79, 80, 81
January 14, 2009
02
Updated errata table for Version 00 – added 3
errata (#5 – 7).
81, 83
03
Updated instruction set timing for 186EB;
Changed 188EB column to TBD pending
completion of new tests; Updated Table 9 ratings;
Updated Table 11 parameters and ratings;
Removed Figures 16 and 17, and reordered
subsequent figures; Updates Table 18 ratings and
notes; Updated Table 19 parameters, ratings and
notes.
42, 43, 55, 56, 68-72
04
Added availability of a non-RoHS compliant
version of the 188EB in the 80-pin LQFP package.
Added two errata for Version 2 of the device.
Noted that all other errata have been fixed in
Version 2.
75, 76, 79
05
Noted the test conditions used to derive the
values in Tables 13 -16; Noted that the Instruction
Set Timing in Table 21 applies to all versions of
the parts.
51, 68
May 18, 2009
06
Updated Figures 4, 5 and 10. Updated Tables 3,
4, 6, 7, 8, 12. Updated Table 21 to provide revised
instruction set timing for the 186EB and to add
instruction set timing for the 188EB, based on the
most recent test results.
15-18, 23, 25-41, 45,
48, 50, 68-72
June 4, 2009
07
Updated VOH parameter on Table 11; corrected
labels on Figures 20-21; Added Errata 10.
43, 61, 62, 80
March 29, 2009
April 24, 2009
May 5, 2009
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Date
Revision
Description
September 4, 2009
08
Added a note to Table 12 regarding the Step ID
register.
50
February 25, 2011
09
Elimination of pages with SnPb lead plating
options
74-76
March 23, 2011
10
Updated Instruction Set Timing Table to
incorporate DIV and IDIV values.
70
June 12, 2011
11
Added Errata 11 and 12.
77, 78, 81
July 5, 2011
12
Added Errata 13.
78, 82
July 10, 2011
13
Added Errata 14.
78, 82
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10.
Data Sheet
July 10, 2011
For Additional Information
The Innovasic Semiconductor IA186EB and IA188EB microcontrollers are form, fit, and
function replacements for the original Intel® 80C186EB, 80C188EB, 80L186EB, and 80L188EB
16-bit high-integration embedded processors.
The Innovasic Support Team wants our information to be complete, accurate, useful, and easy to
understand. Please feel free to contact our experts at Innovasic at any time with suggestions,
comments, or questions.
Innovasic Support Team
3737 Princeton NE
Suite 130
Albuquerque, NM 87107
(505) 883-5263
Fax: (505) 883-5477
Toll Free: (888) 824-4184
E-mail: [email protected]
Website: http://www.Innovasic.com
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