AD AD8022AR Dual high-speed low-noise op amp Datasheet

a
Dual High-Speed
Low-Noise Op Amps
AD8022
FEATURES
Low-Noise Amplifiers Provide Low Noise and Low
Distortion, Ideal for xDSL Modem Receiver
+5 V to ⴞ12 V Voltage Supply
Low-Power Consumption
4.0 mA/Amp (Typ) Supply Current
Voltage Feedback Amplifiers
Low Noise and Distortion
2.5 nV/√Hz Voltage Noise @ 100 kHz
SFDR –95 dBc @ 1 MHz
MTPR < –66 dBc
High Speed
120 MHz Bandwidth (–3 dB), G = 1
50 V/␮s Slew Rate
Low-Offset Voltage, 1.5 mV Typical
FUNCTIONAL BLOCK DIAGRAM
OUT1 1
–IN1 2
+IN1 3
–VS 4
AD8022
–
+
–
+
8
+VS
7
OUT2
6
–IN2
5
+IN2
APPLICATIONS
ADSL, VDSL, HDSL, and Proprietary xDSL Systems
Low-Noise Instrumentation Front End
Ultrasound Preamp
3.0
PRODUCT DESCRIPTION
Low-noise receive amplifiers in the AD8022 are independent
voltage feedback amplifiers and can be configured as the differential receiver from the line transformer or as independent active
filters in an xDSL line interface circuit.
VOLTAGE NOISE, nV
2.5
pA AND nV/ Hz
The AD8022 consists of two low-noise, high-speed, voltage feedback amplifiers. Both inputs add only 2.5 nV/√Hz of voltage
noise. These dual amplifiers provide wideband, low-distortion
performance, with high-output current optimized for stability
when driving capacitive loads. Operating from +5 V to ± 12 V
supplies, the AD8022 typically consumes only 4.0 mA/Amp
quiescent current. The AD8022 is available in both an 8-lead
microSOIC and an 8-lead SOIC package. Fast overvoltage
recovery and wide bandwidth make the AD8022 ideal as the
receive channel front end to an ADSL, VDSL or proprietary
xDSL transceiver design.
2.0
1.5
CURRENT NOISE, pA
1.0
0.5
0
10k
100k
FREQUENCY – Hz
1M
Figure 1. Current and Voltage Noise vs. Frequency
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1999
(@ 25ⴗC, VS = ⴞ12 V, RL = 500 ⍀, G = 1, T MIN = –40ⴗC, TMAX = +85ⴗC, unless
AD8022–SPECIFICATIONS otherwise noted)
Parameter
DYNAMIC PERFORMANCE
–3 dB Small Signal Bandwidth
Bandwidth for 0.1 dB Flatness
Large Signal Bandwidth
Slew Rate
Rise and Fall Time
Settling Time 0.1%
Overdrive Recovery Time
NOISE/DISTORTION PERFORMANCE
Distortion
Second Harmonic
Third Harmonic
Multitone Input Power Ratio1
Voltage Noise (RTI)
Input Current Noise
Conditions
Min
VOUT = 0.2 V p-p
VOUT = 0.2 V p-p
VOUT = 4 V p-p
VOUT = 2 V p-p, G = 2
VOUT = 2 V p-p, G = 2
VOUT = 2 V p-p
VOUT = 150% of Max Output
Voltage, G = 2
VOUT = 2 V p-p
fC = 1 MHz
fC = 1 MHz
G = 7 Differential
26 kHz to 132 kHz
144 kHz to 1.1 MHz
f = 100 kHz
f = 100 kHz
INPUT CHARACTERISTICS
RTI Offset Voltage
–6
–7.25
–5
–7.5
TMIN to TMAX
Input Bias Current
TMIN to TMAX
Input Resistance (Differential)
Input Capacitance
Input Common-Mode Voltage Range
OUTPUT CHARACTERISTICS
Output Voltage Swing
Short Circuit Output Current
Capacitive Load Drive
Max
Single-Ended
MHz
MHz
MHz
V/µs
ns
ns
200
ns
–95
–100
dBc
dBc
–67.2
–66
2.5
1.2
dBc
dBc
nV/√Hz
pA/√Hz
–1.5
+2.5
–10.1
+6
+7.25
+5
+7.5
mV
mV
µA
µA
kΩ
pF
V
+10.1
V
mA
pF
± 13.0
5.5
6.1
V
mA/Amp
mA
dB
+85
°C
100
75
RS = 0 Ω, <3 dB of Peaking
+4.5
4.0
TMIN to TMAX
VS = ± 5 V to ± 12 V
OPERATING TEMPERATURE RANGE
80
–40
Unit
120
25
15
50
30
62
20
0.7
–11.25 to +11.75
POWER SUPPLY
Operating Range
Quiescent Current
Power Supply Rejection Ratio
Typ
NOTES
1
Multitone testing performed with 800 mV rms across a 500 Ω load at Points A and B on Figure 17.
Specifications subject to change without notice.
–2–
REV. 0
(@ 25ⴗC, VS = ⴞ2.5 V, RL = 500 ⍀, G = 1, TMIN = –40ⴗC, TMAX = +85ⴗC, unless
SPECIFICATIONS otherwise noted)
Parameter
DYNAMIC PERFORMANCE
–3 dB Small Signal Bandwidth
Bandwidth for 0.1 dB Flatness
Large Signal Bandwidth
Slew Rate
Rise and Fall Time
Settling Time 0.1%
Overdrive Recovery Time
NOISE/DISTORTION PERFORMANCE
Distortion
Second Harmonic
Third Harmonic
Multitone Input Power Ratio1
Voltage Noise (RTI)
Input Current Noise
Conditions
Min
VOUT = 0.2 V p-p
VOUT = 0.2 V p-p
VOUT = 3 V p-p
VOUT = 2 V p-p, G = 2
VOUT = 2 V p-p, G = 2
VOUT = 2 V p-p
VOUT = 150% of Max Output
Voltage, G = 2
VOUT = 2 V p-p
fC = 1 MHz
fC = 1 MHz
G = 7 Differential, VS = ± 6 V
26 kHz to 132 kHz
144 kHz to 1.1 MHz
f = 100 kHz
f = 100 kHz
INPUT CHARACTERISTICS
RTI Offset Voltage
–5.0
–6.25
–5.0
TMIN to TMAX
Input Bias Current
Typ
OUTPUT CHARACTERISTICS
Output Voltage Swing
Short Circuit Output Current
Capacitive Load Drive
Single-Ended
225
ns
–77.5
–94
dBc
dBc
–69
–66.7
2.3
1
dBc
dBc
nV/√Hz
pA/√Hz
–0.8
+2.0
–1.38
+4.5
3.5
TMIN to TMAX
∆VS = ± 1 V
mV
mV
µA
µA
kΩ
pF
V
+1.48
V
mA
pF
± 13.0
4.25
4.4
V
mA/Amp
mA
dB
+85
°C
86
OPERATING TEMPERATURE RANGE
–40
NOTES
1Multitone testing performed with 800 mV rms across a 500 Ω load at Points A and B on Figure 17.
Specifications subject to change without notice.
REV. 0
+5.0
+6.25
+5.0
7.5
80
75
RS = 0 Ω, <3 dB of Peaking
–3–
Unit
MHz
MHz
MHz
V/µs
ns
ns
20
0.7
–1.83 to +2.5
POWER SUPPLY
Operating Range
Quiescent Current
Power Supply Rejection Ratio
Max
94
22
10
42
40
75
TMIN to TMAX
Input Resistance (Differential)
Input Capacitance
Input Common-Mode Voltage Range
AD8022
AD8022
ABSOLUTE MAXIMUM RATINGS 1
MAXIMUM POWER DISSIPATION
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 V
Internal Power Dissipation2
Small Outline Package (R) . . . . . . . . . . . . . . . . . . . . . 1.6 W
microSOIC Package (RM) . . . . . . . . . . . . . . . . . . . . . 1.2 W
Input Voltage (Common Mode) . . . . . . . . . . . . . . . . . . . . ± VS
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . ± 0.8 V
Output Short Circuit Duration
. . . . . . . . . . . . . . . . . . . . . . Observe Power Derating Curves
Storage Temperature Range RM, R . . . . . . –65°C to +125°C
Operating Temperature Range (A Grade) . . . –40°C to +85°C
Lead Temperature Range (Soldering 10 sec) . . . . . . . . . 300°C
The maximum power that can be safely dissipated by the AD8022
is limited by the associated rise in junction temperature. The
maximum safe junction temperature for plastic encapsulated
devices is determined by the glass transition temperature of the
plastic, approximately 150°C. Temporarily exceeding this limit
may cause a shift in parametric performance due to a change
in the stresses exerted on the die by the package. Exceeding a
junction temperature of 175°C for an extended period can result
in device failure.
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2
Specification is for the device in free air:
8-Lead SOIC Package: θJA = 160°C/W.
8-Lead microSOIC Package: θJA = 200°C/W.
While the AD8022 is internally short circuit protected, this may not
be sufficient to guarantee that the maximum junction temperature
(150°C) is not exceeded under all conditions. To ensure proper
operation, it is necessary to observe the maximum power derating curves.
ORDERING GUIDE
Model
AD8022AR
AD8022ARM
AD8022AR-EVAL
Temperature
Range
Package
Description
Package
Option
–40°C to +85°C
–40°C to +85°C
8-Lead Plastic SOIC
8-Lead microSOIC
Evaluation Board
SO-8
RM-8
SO-8
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD8022 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
2.0
MAXIMUM POWER DISSIPATION – Watts
TJ = 150 8C
1.5
8-LEAD SOIC PACKAGE
1.0
8-LEAD MICROSOIC
0.5
0
–50 –40 –30 –20 –10 0 10 20 30 40 50 60 70
AMBIENT TEMPERATURE – 8C
80 90
Figure 2. Plot of Maximum Power Dissipation vs.
Temperature
–4–
REV. 0
AD8022
5
5
402V
4
453V
3
VIN
2
VOUT
3
VIN = 0.05V p-p
+
56.2V
50V
50V VOUT
+
50V
50V
RF = 715V
1
dB
dB
VIN
2
VIN = 0.2V p-p
1
0
0
–1
VIN = 2V p-p
–1
RF = 402V
–2
–2
VIN = 0.8V p-p
–3
–3
–5
0.1
1
RF = 0V
–4
VIN = 0.4V p-p
–4
10
FREQUENCY – MHz
100
–5
0.1
500
1
10
FREQUENCY – MHz
100
500
Figure 6. Frequency Response vs. R F, G = 1, VS = ±12 V,
VIN = 22 dBm
Figure 3. Frequency Response vs. Signal Level,
VS = ± 12 V, G = 1
0.4
0.4
G=1
RL = 509V
0.3
0.3
0.2
0.2
0.1
0.1
0
0
dB
dB
RF
4
–0.1
–0.2
G=2
RL = 509V
–0.1
–0.2
–0.3
612V
–0.3
–0.4
65.0V
–0.4
–0.5
62.5V
–0.5
–0.6
100k
1M
10M
FREQUENCY – Hz
612V
65.0V
62.5V
–0.6
100k
100M
Figure 4. Fine-Scale Gain Flatness vs. Frequency, G = 1
1M
10M
FREQUENCY – Hz
100M
Figure 7. Fine-Scale Gain Flatness vs. Frequency, G = 2
70
140
G = +1, RF = 402V
120
60
100
50
SLEW RATE – V/ms
FREQUENCY – MHz
NEGATIVE EDGE
80
G = +2, RF = 715V
60
30
40
20
20
10
0
0
2
4
6
8
10
SUPPLY VOLTAGE – 6Volts
12
0
2.5
14
4.5
6.5
8.5
SUPPLY VOLTAGE – Volts
10.5
12.5
Figure 8. Slew Rate vs. Supply Voltage, VS = ±12 V, G = 2
Figure 5. Bandwidth vs. Supply, RL = 500 Ω, V IN = –10 dBm
REV. 0
POSITIVE EDGE
40
–5–
AD8022
100mV
100mV
100ns
100
INPUT
100
OUTPUT
0%
INPUT
90
90
10
10
0%
OUTPUT
100mV
100mV
Figure 12. Noninverting Small Signal Pulse Response,
RL = 500 Ω, V S = ± 2.5 V, G = 1, RF = 0
Figure 9. Noninverting Small Signal Pulse Response,
RL = 500 Ω, V S = ±12 V, G = 1, R F = 0
2.00V
1.00V
100ns
100
INPUT
100
OUTPUT
0%
INPUT
10
10
0%
OUTPUT
1.00V
2.00V
Figure 13. Noninverting Large Signal Pulse Response,
RL = 500 Ω, V S = ± 2.5 V, G = 1, RF = 0
0.4
0.4
0.3
0.3
0.2
0.2
SETTLING TIME – %
SETTLING TIME – %
Figure 10. Noninverting Large Signal Pulse Response,
RL = 500 Ω, V S = ±12 V, G = 1, R F = 0
+0.1%
0.1
0
–0.1%
–0.1
0
–0.3
–0.3
–0.4
40
60
TIME – ns
80
100
120
–0.1%
–0.1
–0.2
20
+0.1%
0.1
–0.2
0
100ns
90
90
–0.4
100ns
0
20
40
60
TIME – ns
80
100
120
Figure 14. Settling Time to 0.1%, VS = ± 2.5 V,
Step Size = 2 V p-p, G = 2, RL = 500 Ω
Figure 11. Settling Time to 0.1%, V S = ± 12 V,
Step Size = 2 V p-p, G = 2, RL = 500 Ω
–6–
REV. 0
AD8022
–20
0
–20
HARMONIC DISTORTION – dBc
HARMONIC DISTORTION – dBc
–30
–40
–50
–60
3RD
–70
2ND
–80
–90
–40
–60
2ND
–80
3RD
–100
–100
–120
5
10
15
OUTPUT VOLTAGE – Volts p-p
0
–120
20
–50
–50
–60
–60
–70
3RD
–80
–90
–100
2ND
–110
1.0
1.5
2.0
OUTPUT VOLTAGE – Volts p-p
2.5
3.0
Figure 18. Distortion vs. Output Voltage, VS = ± 2.5 V,
G = 2, f = 1 MHz, RL = 500 Ω, R F = 715 Ω
HARMONIC DISTORTION – dB
HARMONIC DISTORTION – dB
Figure 15. Distortion vs. Output Voltage, VS = ± 12 V,
G = 2, f = 1 MHz, RL = 500 Ω, RF = 715 Ω
0.5
0
–120
–70
2ND
–80
–90
3RD
–100
–110
–120
–130
–130
1k
10k
100k
FREQUENCY – Hz
1M
1k
Figure 16. Distortion vs. Frequency, VS = ± 12 V,
RL = 500 Ω, R F = 715 Ω, V OUT = 2 V p-p, Gain = 1
10k
100k
FREQUENCY – Hz
1M
Figure 19. Distortion vs. Frequency, VS = ± 2.5 V,
RL = 500 Ω, R F = 715 Ω, V OUT = 2 V p-p, Gain = 1
+V
4
1kV
1kV
3
VIN
AD8022
2
1/2
1kV
VS = 62.5V
VOS – mV
1
715V
250V
500V
VOUT
500V
1kV
0
–1
715V
-
–2
AD8022
VS = 612V
1/2
–3
–4
–12.5
–V
–5.0 –2.5
0
2.5
VCM – Volts
5.0
7.5
10.0
12.5
Figure 20. Input Common-Mode Voltage Range
Figure 17. Multitone Power Ratio Test Circuit
REV. 0
–10.0 –7.5
–7–
AD8022
10dB/DIV
10dB/DIV
–69.0dBc
–66.7dBc
549.3 550.3 551.3 552.3 553.3 554.3 555.3 556.3 557.3 558.3 559.3
FREQUENCY – kHz
102.4 103.4 104.4 105.4 106.4 107.4 108.4 109.4 110.4 111.4 112.4
FREQUENCY – kHz
Figure 21. Multitone Power Ratio: V S = ± 6 V, RL = 500 Ω,
Full Rate ADSL (DMT), Downstream
Figure 24. Multitone Power Ratio: VS = ± 6 V, RL = 500 Ω,
Full Rate ADSL (DMT), Upstream
10dB/DIV
10dB/DIV
–67.2dBc
–66.0dBc
549.3 550.3 551.3 552.3 553.3 554.3 555.3 556.3 557.3 558.3 559.3
FREQUENCY – kHz
102.4 103.4 104.4 105.4 106.4 107.4 108.4 109.4 110.4 111.4 112.4
FREQUENCY – kHz
Figure 22. Multitone Power Ratio: V S = ± 12 V, RL = 500 Ω,
Full Rate ADSL (DMT), Downstream
Figure 25. Multitone Power Ratio: VS = ± 12 V, RL = 500 Ω,
Full Rate ADSL (DMT), Upstream
8.5
4.0
8.0
SUPPLY CURRENT – Total mA
4.5
BIAS CURRENT – mA
3.5
VS = 612V
3.0
2.5
VS = 62.5V
2.0
1.5
1.0
VS = 612V
7.5
7.0
6.5
VS = 62.5V
6.0
5.5
0.5
0
–60
–40
–20
0
20
40
60
80
TEMPERATURE – 8C
100
120
5.0
–50
140
0
50
TEMPERATURE – 8C
100
150
Figure 26. Total Supply Current Over Temperature
Figure 23. Bias Current vs. Temperature
–8–
REV. 0
AD8022
5
100
4
FREQUENCY RESPONSE – dB
OUTPUT IMPEDANCE – V
31.6
10
3.16
1
0.316
0.1
0.0316
3
2
VIN
RS
+
50V
CL
453V
VOUT
56.2V
715V
715V
50pF
1
0
–1
30pF
–2
0pF
–3
–4
30k
100k
1M
10M
FREQUENCY – Hz
100M
–5
0.1
500M
Figure 27. Output Impedance vs. Frequency, VS = ± 12 V
0
–10
–10
–20
–20
CROSSTALK – dB
CROSSTALK – dB
10
FREQUENCY – kHz
100
500
Figure 30. Frequency Response vs. Capacitive Load,
CL = 0 pF, 30 pF and 50 pF, RS = 0 Ω
0
–30
1
SIDE A OUT
–40
–50
–60
SIDE B OUT
–30
SIDE A OUT
–40
–50
–60
SIDE B OUT
–70
–70
–80
–80
–90
–90
–100
100k
1M
10M
FREQUENCY – Hz
–100
100k
100M
Figure 28. Output-to-Output Crosstalk vs. Frequency,
VS = ± 12 V
1M
10M
FREQUENCY – Hz
100M
Figure 31. Output -to-Output Crosstalk vs. Frequency,
VS = ± 2.5 V
–10
0
604V
604V
SIDE A
50V
–30
–0.5
CMRR – dB
56.7V
VOLTAGE OFFSET – mV
154V
154V
–50
–70
–90
–110
1k
SIDE A
–1.0
VS = 62.5V
SIDE B
–1.5
VS = +12V
–2.0
10k
100k
FREQUENCY – Hz
–2.5
–60
1M
Figure 29. CMRR vs. Frequency
REV. 0
SIDE B
–40
–20
0
20
40
60
80
TEMPERATURE – Degrees
100
120
140
Figure 32. Voltage Offset vs. Temperature
–9–
0
0
–10
–10
POWER SUPPLY REJECTION – dB
POWER SUPPLY REJECTION – dB
AD8022
–20
–30
–PSRR
–40
–50
+PSRR
–60
–70
–80
–PSRR
–30
–40
+PSRR
–50
–60
–70
–80
–90
–90
–100
10k
–20
100k
1M
FREQUENCY – Hz
10M
–100
10k
100M
100k
1M
FREQUENCY – Hz
10M
100M
Figure 34. Power Supply Rejection vs. Frequency,
VS = ± 2.5 V
Figure 33. Power Supply Rejection vs. Frequency,
VS = ± 12 V
THEORY OF OPERATION
APPLICATIONS
The AD8022 is a voltage-feedback op amp designed especially
for ADSL or other applications requiring very low voltage and
current noise along with low-supply current, low distortion, and
ease of use.
The low-noise AD8022 dual xDSL receiver amplifier is specifically designed for the dual differential receiver amplifier function
within xDSL transceiver hybrids as well as other low-noise
amplifier applications. The AD8022 may be used in receiving
modulated signals including Discrete Multitone (DMT) on either
end of the subscriber loop. Communication systems designers
can be challenged when designing an xDSL modem transceiver
hybrid capable of receiving the smallest signals embedded in noise
that inherently exists on twisted pair phone lines. Noise sources
include Near End Cross Talk (NEXT), Far End Cross Talk
(FEXT), background and impulse noise, all of which are fed, to
some degree, into the receiver front end. Based on a Bellcore
noise survey, the background noise level for typical twisted pair
telephone loop is said to be –140 dBm/√Hz or 31 nV/√Hz. It
is therefore important to minimize the noise added by the receiver
amplifiers in order to preserve as much Signal-to-Noise Ratio
(SNR) as is possible. With careful transceiver hybrid design
using the AD8022 dual low-noise receiver amplifier, maintaining
power density levels lower than –140 dBm/Hz in ADSL modems is
easily achieved.
The AD8022 is fabricated on Analog Devices’ proprietary eXtraFast Complementary Bipolar (XFCB) process, which enables
the construction of PNP and NPN transistors with similar fTs in
the 4 GHz region. The process is dielectrically isolated to eliminate
the parasitic and latch-up problems caused by junction isolation.
These features enable the construction of high-frequency, lowdistortion amplifiers with low-supply currents.
+VS
15V
+IN
OUTPUT
15V
DMT Modulation and Multitone Power Ratio (MTPR)
7.5pF
–IN
600mA
–VS
OFFSET NULL
Figure 35. Simplified Schematic
As shown in Figure 35, the AD8022 input stage consists of an
NPN differential pair in which each transistor operates a 300 µA
collector current. This gives the input devices a high transconductance and hence gives the AD8022 low-input noise of 2.5 nV/√Hz
@ 100 kHz. The input stage drives a folded cascode that consists
of a pair of PNP transistors. These PNP’s then drive a current
mirror that provides a differential-input to single-ended-output conversion. The output stage provides a high-current gain
of 10,000, so that the AD8022 can maintain a high-dc openloop gain, even into low-load impedances.
ADSL systems rely on Discrete Multitone (or DMT) modulation
to carry digital data over phone lines. DMT modulation appears
in the frequency domain as power contained in several individual
frequency subbands, sometimes referred to as tones or bins,
each of which is uniformly separated in frequency. (See Figures
21, 22, 24, and 25 for MTPR results while the AD8022 receives
DMT driving 800 mV rms across 500 Ω differential load). A
uniquely encoded, Quadrature Amplitude Modulation (QAM)
signal occurs at the center frequency of each subband or tone.
Difficulties will exist when decoding these subbands if a QAM
signal from one subband is corrupted by the QAM signal(s) from
other subbands, regardless of whether the corruption comes from
an adjacent subband or harmonics of other subbands. Conventional methods of expressing the output signal integrity of line
receivers such as spurious free dynamic range (SFDR), single
tone harmonic distortion or THD, two-tone Intermodulation
Distortion (IMD) and third-order intercept (IP3) become
significantly less meaningful when amplifiers are required to
–10–
REV. 0
AD8022
process DMT and other heavily modulated waveforms. A typical
xDSL downstream DMT signal may contain as many as 256
carriers (subbands or tones) of QAM signals. MTPR is the relative difference between the measured power in a typical subband
(at one tone or carrier) versus the power at another subband
specifically selected to contain no QAM data. In other words, a
selected subband (or tone) remains open or void of intentional
power (without a QAM signal) yielding an empty frequency
bin. MTPR, sometimes referred to as the “empty bin test,” is
typically expressed in dBc, similar to expressing the relative difference between single tone fundamentals and second or third
harmonic distortion components. Measurements of MTPR are
typically made at the output of the receiver directly across the
differential load. Other components aside, the receiver function
of an ADSL transceiver hybrid will be affected by the turns ratio
of the selected transformers within the hybrid design. Since a
transformer reflects the secondary voltage back to the primary
side by the inverse of the turns ratio 1/N, increasing the turns
ratio on the secondary side reduces the voltage across the primary side inputs of the differential receiver. Increasing the turns
ratio of the transformers may inadvertently cause a reduction
of the SNR by reducing the received signal strength.
Channel Capacity and SNR
The efficiency of an ADSL system in delivering the digital data
embedded in the DMT signals can be compromised when the
noise power of the transmission system increases. The graph
below shows the relationship between SNR and the relative maximum number of bits per tone or subband while maintaining a bit
error rate at 1E-7 errors per second.
60.00
50.00
SNR – dB
40.00
30.00
20.00
At this time, DMT modulated waveforms are not typically menu
selectable items contained within arbitrary waveform generators.
AWGs that are available today may not deliver DMT signals
sufficient in performance with regard to MTPR due to limitations in the D/A converters and output amplifiers used by AWG
manufacturers. Similar to evaluating single tone distortion performance of an amplifier, MTPR evaluation requires a DMT signal
generator capable of delivering MTPR performance better than
that of the driver under evaluation. Generating DMT signals can
be accomplished using a Tektronics AWG 2021 equipped with
Opt 4, (12-bit/24-bit, TTL Digital Data Out), digitally coupled
to Analog Devices’ AD9754, a 14-bit TxDAC, buffered by an
AD8002 amplifier configured as a differential driver. See Figure
37 for schematics of a circuit used to generate DMT signals
that can achieve down to –80 dBc of MTPR performance,
sufficient for use in evaluating xDSL receivers. WFM files are
needed to produce the necessary digital data required to drive
the TxDAC from the optional TTL Digital Data output of
the TEK AWG2021. Copies of .WFM files for upstream and
downstream DMT waveforms with a peak-to-average ratio (crest
factor) of ~5.3 can be obtained through the Analog Devices
web site. http://products.analog.com/products/info.asp?
product=AD8022
Upstream data is contained in the ...24.wfm files and downstream
data in the ...128.wfm files. These DMT modulated signals are
used to evaluate xDSL products for Multitone Power Ratio or
MTPR performance. The data files are used in pairs (adslu24.wfm
and adsll24.wfm go together, etc.) and are loaded into Tektronics
AWG2021 arbitrary waveform generator. The adslu24.wfm is
loaded via the TEK AWG2021 floppy drive into Channel 1
while the adsll24.wfm is simultaneously loaded into Channel
2. The number in the file name, prefixed with ‘u,’ goes into
CH1 or upper channel and the ‘l’ goes into CH2 or the lower
channel. Twelve bits from channel CH1 are combined with two
bits from CH2 to achieve 14-bit digital data at the digital outputs of the TEK 2021. The resulting waveforms produced at the
AD9754-EB outputs are then buffered and amplified by the
AD8002 differential driver to achieve 14-bit performance from
this DMT signal source.
Power Supply and Decoupling
10.00
0.00
0
5
10
BITS/TONE
Figure 36. ADSL DMT SNR vs. Bits/Tone
REV. 0
Generating DMT
15
The AD8022 should be powered with a good quality (i.e., low
noise) dual supply of ± 12 V for the best overall performance.
The AD8022 circuit will also function at voltages lower than
± 12 V. Careful attention must be paid to decoupling the power
supply pins. A pair of 10 µF capacitors located in near proximity
to the AD8022 is required to provide good decoupling for lower
frequency signals. In addition, 0.1 µF decoupling capacitors should
be located as close to each of the power supply pins as is physically possible.
–11–
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
1
–12–
A
J4
A
J3
OUT2
OUT1
R2
C13
22pF
C12
22pF
A
A
R5
C4
10mF
TP4
B3
1mF
R6
49.9V
1mF
A
A
10kV
10kV
226V
AVEE
16
15
14
13
12
11
10
9
AVEE
0.1mF
AD8002
750V
750V
AD8002
0.1mF
1
2
3
4
5
6
7
A
A
16
15
14
13
12
11
10
16 PINDIP
RES PK
1
2
3
4
5
6
7
8
16 PINDIP
RES PK
TP5
TP18
TP19
B4
AVCC
C30
C31
C32
C33
C34
C35
C36
C19
C1
C2
C25
C26
C27
C28
C29
A
AGND
DVDD
1
2 3 4 5 6 7 8 9 10
AVDD
10 9 8 7 6 5 4 3 2
1
49.9V
1
2 3 4 5 6 7 8 9 10
10 9 8 7 6 5 4 3 2
1
3
5
7
9
11
13
TO TEK
15
AWG
17
2021
19
21
23
25
27
29
31
33
35
37
39
P1
R1
DVDD
TP2
TP3
C3
10mF
B2
DGND
B1
DVDD
C6
10mF
TP7
B6
249V
249V
R4
A
A
R8
DVDD
1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
J1
2 3 4 5 6 7 8 9 10
EXTCLK
10 9 8 7 6 5 4 3 2
1
R7
DVDD
A
DIFFERENTIAL
DMT OUTPUTS
1
2 3 4 5 6 7 8 9 10
A
AVCC
10 9 8 7 6 5 4 3 2
1
R3
C5
10mF
TP6
B5
A
TP12
A
28
27
26
25
24
23
22
21
20
19
18
17
16
15
2
CLK
JP1
R17
49.9V
CLOCK
DVDD
DCOM
NC
AVDD
COMP2
IOUTA
IOUTB
ACOM
COMP1
FS ADJ
REFIO
REFLO
SLEEP
CT1
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
AD9754
U1
1
R15
49.9V
TP1
PDIN
J2
A
3
B
JP2
A
3
2
1
AVDD
TP11
AVDD
C7
1mF
A
A
JP4
TP14
R
20kV
R16
2kV
TP10
AVDD
C11
0.1mF
C8
0.1mF
TP9
OUT 2
TP8
OUT 1
C10
0.1mF
AVDD
A
C9
0.1mF
TP13
AD8022
Figure 37. DMT Signal Generator Schematic
REV. 0
AD8022
EVALUATION BOARDS
Layout Considerations
The evaluation board layout of Figures 40, 41, and 42 is our
standard dual SOIC noninverting evaluation circuit offering
the ability to evaluate the AD8022 in typical op amp circuits,
is available from Analog Devices Inc. In addition, the AD8022
receiver function may be added to on our ADSL EVAL boards.
The AD8016ARB-EVAL, the AD8016ARP-EVAL, the
AD8017AR-EVAL and AD8018ARU-EVAL boards are available through Analog Devices. These platforms provide the
capability to fully evaluate the Analog Devices ADSL transceiver hybrid. All of the ADSL evaluation boards mentioned
above can accommodate the evaluation of the AD8022 as a
receiver amplifier when installed in the U2 location. The receiver
circuit on these boards is typically unpopulated. Requesting
samples of the AD8022 along with the EVAL board of your
choice will provide the capability to evaluate the AD8022 along
with many other Analog Devices ADSL line driver products in a
typical transceiver circuit. The evaluation circuits have been
designed to replicate the CPE or CO side analog transceiver
hybrid circuits.
As is the case with all “hi speed” amplifiers, careful attention to
printed circuit board layout details will prevent associated board
parasitics from becoming problematic. Proper RF design technique
is mandatory. The PCB should have a ground plane covering all
unused portions of the component side of the board to provide a
low-impedance return path. Removing the ground plane from
the area near the input signal lines will reduce stray capacitance.
Chip capacitors should be used for the supply bypassing. One
end of the capacitor connected to the ground plane and the other
no more than 1/8 inch away from each supply pin. An additional
large (0.47 µF to 10 µF) tantalum capacitor should be connected
in parallel, although not necessarily as close, in order to supply
current for fast, large signal changes at the AD8022 output.
Signal lines connecting the feedback and gain resistors should
be as short as possible, minimizing the inductance and stray
capacitance associated with these traces. Locate termination
resistors and loads as close as possible to the input(s) and output respectively. Adhere to stripline design techniques for long
signal traces (greater than about 1 inch). Following these
generic guidelines will improve the performance of the AD8022
in all applications.
The ADSL EVAL circuits mentioned above are designed using a
two transformer transceiver topology, including a line receiver, line
driver, line matching network, an RJ11 jack for interfacing to
line simulators, and transformer-coupled inputs for single-todifferential input conversion.
7.5
2.5
–2.5
680pF
5% NPO
–7.5
–12.5
12V
2.43kV
1%
3
2
820pF
10%
8 AD8022
1
U27
–22.5
–32.5
1kV 1%
–37.5
1.69kV
1%
0.1mF
16V
10%
X7R
–42.5
0.1mF
50V
5%
NPO
820pF
10%
–47.5
10k
1kV 1%
7
4 AD8022
2.43kV
1%
100k
1M
FREQUENCY – Hz
10M
Figure 39. Frequency Response of Sallen-Key Filter
6
5 U27
680pF
5% NPO
Figure 38. Differential Input Sallen-Key Filter Using
AD8022 on Single Supply, 12 V
REV. 0
–17.5
–27.5
6V
1.91kV
1%
dB
1.91kV
1%
–13–
AD8022
Figure 40.
Figure 42.
Figure 41.
RF
715V
RF
715V
+VS
RO
0V
RO
0V
J4
J2
J1
RT
49.9V
G=2
RG
715V
G=2
RG
715V
AD8022
RC
0V
J3
499V
49.9V
AD8022
RC
0V
–VS
499V
AMP #2
AMP #1
BYPASSING
+VS
C3
0.01mF
C1
10mF
C4
0.01mF
C2
10mF
–VS
Figure 43. Evaluation Board Schematic
–14–
REV. 0
AD8022
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
8-Lead microSOIC
(RM-8)
8-Lead Plastic SOIC
(SO-8)
0.1574 (4.00)
0.1497 (3.80)
8
5
1
4
8
0.2440 (6.20)
0.2284 (5.80)
5
0.122 (3.10)
0.114 (2.90)
0.199 (5.05)
0.187 (4.75)
1
PIN 1
0.0196 (0.50)
3 458
0.0099 (0.25)
0.0500 (1.27)
BSC
0.0098 (0.25)
0.0040 (0.10)
SEATING
PLANE
4
PIN 1
0.0256 (0.65) BSC
0.0688 (1.75)
0.0532 (1.35)
0.0192 (0.49)
0.0138 (0.35)
C3714–8–10/99
0.122 (3.10)
0.114 (2.90)
0.1968 (5.00)
0.1890 (4.80)
0.120 (3.05)
0.112 (2.84)
88
0.0500 (1.27)
0.0098 (0.25) 08
0.0160 (0.41)
0.0075 (0.19)
0.006 (0.15)
0.002 (0.05)
0.011 (0.28)
0.003 (0.08)
338
278
0.028 (0.71)
0.016 (0.41)
PRINTED IN U.S.A.
0.018 (0.46)
SEATING 0.008 (0.20)
PLANE
0.120 (3.05)
0.112 (2.84)
0.043 (1.09)
0.037 (0.94)
REV. 0
–15–