Freescale MC33882PEP Six output low side switch with spi and parallel input control Datasheet

Freescale Semiconductor
Technical Data
Document Number: MC33882
Rev. 7.0, 3/2011
Six Output Low Side Switch with
SPI and Parallel Input Control
33882
The 33882 is a smart six output low side switch able to control
system loads up to 1.0 A. The six outputs can be controlled via both
serial peripheral interface (SPI) and parallel input control, making the
device attractive for fault-tolerant system applications. There are two
additional 30 mA low side switches with SPI diagnostic reporting (with
parallel input control only).
The 33882 is designed to interface directly with industry standard
microcontrollers via SPI to control both inductive and incandescent
loads. Outputs are configured as open-drain power MOSFETs
incorporating internal dynamic clamping and current limiting. The
device has multiple monitoring and protection features, including low
standby current, fault status reporting, internal 52 V clamp on each
output, output specific diagnostics, and protective shutdown. In
addition, it has a mode select pin affording a dual means of input
control.
SIX OUTPUT LOW SIDE SWITCH
VW SUFFIX
(PB-FREE)
98ASH70693A
30-PIN HSOP
EK SUFFIX
(PB-FREE)
98ARL10543D
32-PIN SOIC
ORDERING INFORMATION
Features
•
•
•
•
•
•
•
•
EP SUFFIX
(PB-FREE)
98ARH99032A
32-PIN QFN
Outputs clamped for switching inductive loads
Very low operational bias currents (< 2.0 mA)
CMOS input logic compatible with 5.0 V logic levels
Load dump robust (60 V transient at VPWR on OUT0 – OUT5)
Daisy chain operation of multiple devices possible
Switch outputs can be paralleled for higher currents
RDS(ON) of 0.4 Ω per output (25 °C) at 13 V VPWR
SPI operation guaranteed to 2.0 MHz
Device
Temperature
Range (TA)
MC33882PVW/R2
MC33882PEP/R2
30 HSOP
-40 to 125 °C
PC33882EK/R2
VDD
33882
MCU
Optional Parallel
Control of
Outputs 0 through 7
OUT0
OUT1
High Power
Outputs
OUT3
OUT4
OUT5
Low Power
LED
Outputs
OUT6
OUT7
IN0 & IN1
IN2 & IN3
IN4 & IN5
Optional Control
of Paired Outputs
MODE
GND
Figure 1. 33882 Simplified Application Diagram
Freescale Semiconductor, Inc. reserves the right to change the detail specifications,
as may be required, to permit improvements in the design of its products.
© Freescale Semiconductor, Inc., 2006 -2011. All rights reserved.
32 QFN
32 SOIC-EP
VPWR
VPWR
VDD
CS
SCLK
SI
SO
IN0
IN1
IN2
IN3
IN4
IN5
IN6
IN7
Package
INTERNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
16 (VDD)
1 (VPWR)
12 (SI)
V DD
DQ
C
DQ
C
DQ
C
DQ
C
DQ
C
DQ
C
DQ
C
DQ
C
Over-voltage
Shutdown
Under-voltage
Shutdown
On Open
3 (MODE)
Detect
Logic
OUT6
and OUT7
Unclamped
Low
Power
Gate 7
18 (IN7)
Gate 6
29 (IN6)
Internal
Bias
Gate 5
27 (IN5)
Gate 2
21 (IN3)
Gate 0
23 (OUT4)
OUT1
to OUT5
High
Power
Gate 3
28 (IN4 & IN5)
30 (OUT6)
26 (OUT5)
Gate 4
24 (IN4)
17 (OUT7)
20 (OUT3)
10 (OUT2)
7 (OUT1)
5 (OUT0)
9 (IN2)
52 V
19 (IN2 & IN3)
Gate 0
6 (IN1)
V REF
Output 0 Status
2 (IN0 & IN1)
13 (SCLK)
0
1
2
3
4
5
6
SO Fault Latch/Shift Register
7
Serial Out
V DD
Tri-state
GND (Heat Sink)
OFF/ON
Open
Load
Detect
-+
14 (CS)
I LIM
-+
Serial In
Output Status
1 through 7
+-
4 (IN0)
Shift
Enable
3.0 A
Load
Short
Detect
15 (SO)
V OF (th)
3.0 V
I O(OFF)
40 μA
Note Pin numbers shown in this figure are applicable only to the 30-lead HSOP package.
Figure 2. 33882 Simplified Internal Block Diagram
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Analog Integrated Circuit Device Data
Freescale Semiconductor
PIN CONNECTIONS
PIN CONNECTIONS
OUT5
IN4
OUT4
IN3
OUT3
IN2&IN3
IN7
30
29
28
27
26
25
OUT7
2
23
VDD
OUT6
3
22
GND
GND
4
21
GND
HEATSINK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
HEATSINK
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
IN0
GND
NC
SO
CS
SCLK
SI
OUT2
IN2
OUT1
IN1
OUT0
IN0
MODE
IN0&IN1
VPWR
GND
16
CS
SCLK
SO
17
SI
18
8
15
7
MODE
14
IN0&IN1
OUT2
GND
IN2
GND
19
13
20
6
12
5
OUT1
GND
VPWR
TRANSPARENT TOP VIEW
GND
NC
VDD
OUT7
IN7
IN2&IN3
OUT3
IN3
OUT4
IN4
OUT5
IN5
IN4&IN5
IN6
OUT6
GND
31
24
IN6
9
30 PIN HSOP
1
11
SO
HEATSINK
IN4&IN5
10
CS
GND
IN1
IN0
OUT0
IN1
OUT1
NC
IN2
OUT2
NC
SI
SCLK
OUT0
MODE
OUT6
IN6
IN4&IN5
IN5
OUT5
NC
IN4
OUT4
NC
IN3
OUT3
IN2&IN3
IN7
OUT7
VDD
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
IN5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
VPWR
IN0&IN1
32
TRANSPARENT TOP VIEW
TRANSPARENT TOP VIEW
32 PIN QFN
32 PIN SOIC
Figure 3. HSOP, QFN, and SOIC Pin Connections
Table 1. HSOP Pin Function Description
30 Pin
HSOP
32 Pin
QFN
32 Pin
SOIC
Pin Name
Formal Name
Definition
1
6
18
VPWR
Load Supply Voltage
This pin is connected to battery voltage. A decoupling cap is required from
VPWR to ground.
2
19
28
7
26
1
19
6
13
IN0 & IN1
IN2 & IN3
IN4 & IN5
Input 0 & Input 1
Input 2 & Input 3
Input 4 & Input 5
These input pins control two output channels each when the MODE pin is
pulled high. These pins may be connected to pulse width modulated (PWM)
outputs of the control IC while the MODE pin is high. The states of these pins
are ignored during normal operation (MODE pin low), and override the
normal inputs (serial or parallel) when the MODE pin is high. These pins
have internal active 25 μA pull-downs.
3
8
20
MODE
Mode Select
The MODE pin is connected to the MODE pin of the control IC. This pin has
an internal active 25 μA pull-up.
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Analog Integrated Circuit Device Data
Freescale Semiconductor
PIN CONNECTIONS
Table 1. HSOP Pin Function Description (continued)
30 Pin
HSOP
32 Pin
QFN
32 Pin
SOIC
Pin Name
Formal Name
Definition
4
6
9
18
21
24
27
29
9
11
13
25
28
30
32
2
21
23
25
5
8
10
12
14
IN0
IN1
IN2
IN7
IN3
IN4
IN5
IN6
Input 0 – Input7
These are parallel control input pins. These pins have internal 25 μA active
pull-downs.
5
7
10
17
20
23
26
30
10
12
14
24
27
29
31
3
22
24
26
4
7
9
11
15
OUT0
OUT1
OUT2
OUT7
OUT3
OUT4
OUT5
OUT6
Output 0 – Output7
2,31
NC
No Connect
Not connected.
8, 11, 22,
25
Each pin is one channel's drain, sinking current for the respective load.
12
15
27
SI
Serial Input
The Serial Input pin is connected to the SPI Serial Data Output pin of the
control IC from where it receives output command data. This input has an
internal active 25 μA pull-down and requires CMOS logic levels.
13
16
28
SCLK
Serial Clock
The SCLK pin of the control IC is a bit (shift) clock for the SPI port. It
transitions one time per bit transferred when in operation. It is idle between
command transfers. It is 50% duty cycle, and has CMOS levels.
14
17
29
CS
Chip Select
This pin is connected to a chip select output of the control IC. This input has
an internal active 25 μA pull-up and requires CMOS logic levels.
15
18
30
SO
Serial Output
This pin is connected to the SPI Serial Data Input pin of the control IC or to
the SI pin of the next device in a daisy chain. This output will remain tristated unless the device is selected by a low CS pin or the MODE pin goes
low. The output signal generated will have CMOS logic levels and the output
data will transition on the falling edges of SCLK. The serial output data
provides fault information for each output and is returned MSB first when the
device is addressed.
16
23
3
VDD
Logic Supply Voltage
This pin is connected to the 5.0 V power supply of the system. A decoupling
capacitor is required from VDD to ground.
GND
Ground
Ground continuity is required for the outputs to turn on. The heatsink must
be electrically connected to GND.
Heat
4,5,19- 1,16,17,
Sink
22
32
(exposed
pad)(1)
Notes
1. The exposed pad on this package provides the circuit ground connection for the IC.
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Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 2. Maximum Ratings
All voltages are with respect to ground unless otherwise noted.
Rating
Symbol
Value
Limit
VPWR(SS)
25
VPWR(T)
-1.5 to 60
VDD
-0.3 to 7.0
V
VIN
-0.3 to VDD + 0.3
V
ELECTRICAL RATINGS
Load Supply Voltage
V
Normal Operation (Steady-state)
Transient Survival (2)
Logic Supply Voltage (3)
Input Pin Voltage
(4)
Output Clamp Voltage (OUT0 to OUT5)
(5)
VO(OFF)
20 mA = IO = 0.2 A
V
48 to 64
Output Self-limit Current
IO(LIM)
OUT0 to OUT5
A
3.0 to 6.0
OUT6 and OUT7
0.05 to 0.15
ESD Voltage (HSOP, QFN, and SOIC)
V
Human Body Model (6)
VESD1
±2000
Machine Model (7)
VESD2
±200
Output Clamp Energy (8)
ECLAMP
mJ
OUT0 to OUT5: Single Pulse at 1.5 A, TJ = 150°C
100
OUT6 and OUT7: Single Pulse at 0.45 A, TJ = 150°C
50
Maximum Operating Frequency (SPI) SO (9)
fOF
3.2
MHz
TSTG
-55 to 150
°C
TJ
-40 to 150
°C
TPPRT
Note 11
°C
THERMAL RATINGS
Storage Temperature
Operating Junction Temperature
Peak Package Reflow Temperature During Reflow
Notes
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
(10), (11)
Transient capability with external 100 Ω resistor in series with the VPWR pin and supply.
Exceeding these voltages may cause a malfunction or permanent damage to the device.
Exceeding the limits on any parallel inputs or SPI pins may cause permanent damage to the device.
With output OFF.
ESD1 testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 Ω).
ESD2 testing is performed in accordance with the Machine Model (CZAP = 200 pF, RZAP = 0 Ω).
Maximum output clamp energy capability at indicated junction temperature using a single pulse method.
Serial Frequency Specifications assume the IC is driving 8 tri-stated devices (20 pF each).
Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may
cause malfunction or permanent damage to the device.
Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow
Temperature and Moisture Sensitivity Levels (MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes
and enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics.
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Analog Integrated Circuit Device Data
Freescale Semiconductor
5
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 2. Maximum Ratings (continued)
All voltages are with respect to ground unless otherwise noted.
Rating
THERMAL RESISTANCE
Symbol
Limit
,
Junction-to-Ambient, Natural Convection, Single-Layer Board (1s) (14)
RθJA
HSOP
QFN
SOIC
Junction-to-Ambient, Natural Convection, Four-Layer Board (2s2p) (15)
RθJMA
HSOP
QFN
SOIC(17)
Junction-to-Board (Bottom)
Junction-to-Case (Top) (16)
°C/W
41
85
72
°C/W
18
27
TBD
°C/W
RθJB
HSOP
QFN
SOIC(17)
HSOP
QFN
SOIC
Value
(12) (13)
3.0
10
TBD
°C/W
RθJC
0.2
1.2
1.0
Notes
12. Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient
temperature, air flow, power dissipation of other components on the board, and board thermal resistance.
13. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top
surface of the board near the package.
14. Per SEMI G38-87 and JEDEC JESD51-2 with the single-layer board horizontal.
15. Per JEDEC JESD51-6 with the board horizontal.
16. Indicates the average thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC
883, Method 1012.1) with the cold plate temperature used for the case temperature.
17. This value will be included when available.
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Analog Integrated Circuit Device Data
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics
Characteristics noted under conditions 4.75 V ≤ VDD ≤ 5.25 V, 9.0 V ≤ VPWR ≤ 17 V, -40 °C ≤ TA ≤ 125 °C, unless otherwise
noted.
Characteristic
Symbol
Min
Typ
Max
Unit
POWER INPUT
Supply Voltage Ranges
Functional Threshold
V
(18)
Full Operation
Logic Supply Voltage
VDD Supply Current (All Outputs ON) (19)
V PWR
4.5
5.5
V PWR
8.0
–
25
VDD
4.5
5.0
5.5
–
–
7.5
V PWR (OV)
30
–
40
V
I PWR (ON)
IO = 1.0 A Each
Over-voltage Shutdown (20)
Over-voltage Shutdown Hysteresis (21)
8.0
mA
V PWR (OV) HYS
0.4
–
1.5
V
Power-ON Reset Threshold, VDD (22)
V POR
2.5
–
3.5
V
Logic Supply Current (All Outputs ON)
I DD
VDD = 5.5 V
mA
–
–
5.0
–
0.6
0.8
–
0.4
0.6
3.0
–
6.0
2.5
–
3.5
POWER OUTPUT
Output Drain-to-Source ON Resistance
Output Drain-to-Source ON Resistance
I O (LIM)
VPWR = 13.0 V, VDD = 4.5 V, VIN = 5.0 V
Open Load OFF Detection (Outputs Programmed OFF)
Output OFF (Open Load Detect) Drain Current (Output Pins
Programmed OFF) (23)
Ω
RDS(ON)
OUT0 to OUT5: TJ = 25°C, VPWR = 13.0 V, IO = 1.0 A
Output Self-limiting Current
Ω
RDS(ON)
OUT0 to OUT5: TJ = 150°C, VPWR = 13.0 V, IO = 1.0 A
V OFF (TH)
A
μA
I O (OFF)
OUT0 to OUT5
20
–
120
OUT6 and OUT7
20
–
80
20
–
200
Output ON (Open Load Detect) Drain Current (Output Pins Programmed
ON) (24)
Output Clamp Voltage
OUT0 to OUT5: IO = 20 mA, tCLAMP = 100 μs
–
mA
V OK
V
48
52
64
–
1.0
10
ISD = 1.0 mA @ 25 °C
–
–
1.4
ISD = 1.0 mA @ 125 °C
–
–
0.9
Output Leakage Current
Drain-to-Source Diode Forward Voltage
μA
I OLK
VDD = VPWR = 0.5 V, VOUT = 24 V
V
V SD
V
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ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics (continued)
Characteristics noted under conditions 4.75 V ≤ VDD ≤ 5.25 V, 9.0 V ≤ VPWR ≤ 17 V, -40 °C ≤ TA ≤ 125 °C, unless otherwise
noted.
Characteristic
Symbol
Min
Typ
Max
Unit
SI Logic High
SIV IH
4.0
SI Logic Low
SIV IL
–
–
–
V
–
2.0
V
CS and SCLK Logic High
CSV IH
3.0
–
–
V
CS and SCLK Logic Low
CSV IL
–
–
3.0
V
V IH
3.15
–
–
V
V IL
–
–
1.35
V
5.0
–
25
DIGITAL INTERFACE
Input Logic High
Input Logic Low
Input Pull-down Current
(25)
Input Pull-up Current (26)
–
-5.0
3.5
–
–
0
–
0.4
V
V SOL
IOL = 1.0 mA
SO and Tri-state Leakage Current
-25
V SOH
IOH = -1.0 mA
SO and Low-state Output Voltage
μA
I IN (PU)
VIN = 3.5 V
SO and High-state Output Voltage
μA
I IN (PD)
VIN = 1.5 V
V
μA
I SOT
CS = 0.7 VDD, VSO = 0.3 VDD
-10
–
–
CS = 0.7 VDD, VSO = 0.7 VDD
–
–
10
–
–
12
–
–
20
Input Capacitance (27)
C IN
0 = VIN = 5.5 V
SO and Tri-state Capacitance (28)
0 = VIN = 5.5 V
pF
C SOT
pF
Notes
18. Outputs of device functionally turn-on (RDS(ON) = 0.95 Ω @125 °C). SPI / parallel inputs and power outputs are operational. Fault
detection and reporting may not be fully operational within this range.
19. Value reflects all outputs ON and equally conducting 1.0 A each. VPWR = 5.5 V, CS = 5.0 V.
20. An over-voltage condition will cause any enabled outputs to latch OFF (disabled).
21. This parameter is guaranteed by design; however, it is not production tested.
22. For VDD less than the Power-ON Reset voltage, all outputs are disabled and the serial fault register is reset to all 0s.
23. Drain current per output with VPWR = 24 V and VLOAD = 9.0 V.
24. Drain current per output with VPWR = 13 V, VLOAD = 9.0 V.
25. Inputs SI, IN0 & IN1, IN2 & IN3, IN4 & IN5, and IN0 to IN7 incorporate active internal pull-down current sinks for noise immunity
enhancement.
26. The MODE and CS inputs incorporate active internal pull-up current sources for noise immunity enhancement.
27. This parameter applies to inputs SI, CS, SCLK, MODE, IN0 & IN1, IN2 & IN3, IN4 & IN5, and IN0 to IN7. It is guaranteed by design;
however, it is not production tested.
28. This parameter applies to the OFF state (tri-stated) condition of SO and is guaranteed by design; however, it is not production tested.
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Analog Integrated Circuit Device Data
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics
Characteristics noted under conditions 4.75 V ≤ VDD ≤ 5.25 V, 9.0 V ≤ VPWR ≤ 17 V, -40 °C ≤ TA ≤ 125°C, unless otherwise
noted.
Characteristic
Symbol
Min
Typ
Max
Unit
Output Rise Time (29)
tR
1.0
–
10
μs
Output Fall Time (29)
POWER OUTPUT TIMING
tF
1.0
–
10
μs
Output Turn-ON Delay Time (30)
t DLY (ON)
1.0
–
10
μs
Output Turn-OFF Delay Time (31)
t DLY (OFF)
1.0
–
10
μs
25
–
100
Output Short Fault Sense Time (32)
μs
t SS
RLOAD = < 1.0 V
Output Short Fault Refresh Time (33)
t REF
RLOAD = < 1.0 V
ms
3.0
4.5
6.0
t OS(OFF)
25
60
100
μs
t OS(ON)
3.0
–
12
ms
SC DC
0.42
–
3.22
%
SCLK Clock High Time (SCLK = 3.2 MHz) (37)
t SCLKH
–
–
141
ns
(37)
t SCLKL
–
–
141
ns
Output OFF Open Load Sense Time
Output ON Open Load Sense Time
Output Short Fault ON Duty Cycle
(34)
(35)
(36)
DIGITAL INTERFACE TIMING
SCLK Clock Low Time (SCLK = 3.2 MHz)
Falling Edge (0.8 V) of CS to Rising Edge (2.0 V) of SCLK
Required Setup Time
Falling Edge (0.8 V) of SCLK to Rising Edge (2.0 V) of CS
Required Setup Time
t LEAD
(37)
–
–
140
–
–
50
t RSI
–
–
50
ns
t FSI
–
–
50
ns
t LAG
(37)
SI, CS, SCLK Incoming Signal Rise Time (37)
SI, CS, SCLK Incoming Signal Fall Time
(37)
ns
ns
Notes
29. Output Rise and Fall time measured at 10% to 90% and 90% to 10% voltage points respectively across 15 Ω resistive load to a VBAT
of 15 V, VPWR = 15 V.
30.
Output Turn-ON Delay Time measured from rising edge (3.0 V) VIN (CS for serial) to 90% VO using a 15 Ω load to a VBAT of 15 V,
VPWR = 15 V.
31.
Output Turn-OFF Delay Time measured from falling edge (1.0 V) VIN (3.0 V rising edge of CS for serial) to 10% VO using a 15 Ω load
to a VBAT of 15 V, VPWR = 15 V.
32.
The shorted output is turned ON during tSS to retry and check if the short has cleared. The shorted output is in current limit during tSS.
The tSS is measured from the start of current limit to the end of current limit.
33.
The Short Fault Refresh Time is the waiting period between tSS retry signals. The shorted output is disabled during this refresh time.
The tREF is measured from the end of current limit to the start of current limit.
34.
36.
The tOS(OFF) is measured from the time the faulted output is turned OFF until the fault bit is available to be loaded into the internal fault
register. To guarantee a fault is reported on SO, the falling edge of CS must occur at least 100 μs after the faulted output is off.
The tOS(ON) is measured from the time the faulted output is turned ON until the fault bit is available to be loaded into the internal fault
register. To guarantee a fault is reported on SO, the falling edge of CS must occur at least 12 ms after the faulted output is ON.
Percent Output Short Fault ON Duty Cycle is defined as (tSS) ÷ (tREF) x 100. This specification item is provided FYI and is not tested.
37.
Parameter is not tested and values suggested are for system design consideration only in preventing the occurrence of double pulsing.
35.
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ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics (continued)
Characteristics noted under conditions 4.75 V ≤ VDD ≤ 5.25 V, 9.0 V ≤ VPWR ≤ 17 V, -40 °C ≤ TA ≤ 125°C, unless otherwise
noted.
Characteristic
Symbol
SI Setup to Rising Edge (2.0 V) of SCLK (at 3.2 MHz)
Required Setup Time
Required Hold Time
Required Hold Time
–
45
ns
90
–
–
–
–
45
90
–
–
–
–
50
ns
ns
t RSO
CL = 200 pF
SO Fall Time
t FSO
ns
–
CL = 200 pF
Falling Edge of CS (0.8 V) to SO Low-impedance
(39)
t SOEN
Rising Edge of CS (2.0 V) to SO High-impedance
(40)
t SODIS
Falling Edge of SCLK (0.8 V) to SO Data Valid
CS Rising Edge to Next Falling Edge (38)
Notes
38.
39.
40.
41.
ns
–
50
–
–
110
ns
–
–
110
ns
–
65
80
–
–
1.0
t SOVALID
CL = 200 pF at 3.2 MHz (41)
Xfer DELAY
Unit
ns
t SOHOLD
(38)
SO Rise Time
–
t SIHOLD
(38)
SO Hold After SCLK Rising (2.0 V) / Falling (0.8 V) Edge
Max
t SOSU
(38)
SI Hold After Rising Edge (2.0 V) of SCLK (at 3.2 MHz)
Typ
t SISU
Required Setup Time (38)
SO Setup to SCLK Rising (2.0 V) / Falling (0.8 V) Edge
Min
ns
μs
Parameter is not tested and values suggested are for system design consideration only in preventing the occurrence of double pulsing.
Enable time required for SO. Pull-up resistor = 10 kΩ.
Disable time required for SO. Pull-up resistor = 10 kΩ.
Time required to obtain valid data out of SO following the falling edge of SCLK.
33882
10
Analog Integrated Circuit Device Data
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
TIMING DIAGRAMS
TIMING DIAGRAMS
NORMAL OPERATION
NPUT
InputXX
GateXX
GATE
IOUT
OUT
XX
5.0
5V V
0 0V
V
ON
ON
OFF
OFF
IO(LIM)
IDLIM
ILOAD
ILOAD
00AA
Normal
Operation
Fault BIT
Bit X X
FAULT
OFF
INPUT
X
Input X
5.0
5V V
00V
V
Gate XX
GATE
ON
ON
OFF
OFF
IOUT
OUT
XX
IO(LIM)
IDLIM
ILOAD
ILOAD
0A
0A
SHORT OCCURS W HILE ON, ENDS DURING REFRESH
SHORTED
LOAD
/ SHORT - TO - VBAT
Shorted
Load/Short-to-VPWR
tSSD
TSSD
TREF
tREF
Fault Bit X
FAULT BIT X
CSB
CB
TREF
tREF
FAULT
Fault
tSSA
TSSA
TREF
tREF
tSSD
TSSD
tREF
TREF
Shorted
Operation
FAULT
Fault
GATE X = COMMAND SIGNAL AT THE GATE OF DRIVER X
CommandFAULT
Signal at
the Gate of
X
FAULT Gate
BIT XX==INTERNAL
REGISTER
BITDriver
STATE
TREF x
Fault Bit X = Internal Fault Register Bit State
= FIRST
REFRESH
TIMTime
E M AY
BEbe
LESS
TREF
tREF
X = First
Refresh
may
lessTHAN
than tREF
ILOAD = 1.0 A
ILOAD = 1A
Figure 4. Short Occurring While On, Ending During Refresh (ILOAD = 1.0 A)
33882
Analog Integrated Circuit Device Data
Freescale Semiconductor
11
ELECTRICAL CHARACTERISTICS
TIMING DIAGRAMS
NORMAL OPERATION
INPUT
InputXX
GATE
GateXX
IOUT
XX
IOUT
5.0
5V V
0 0V
V
ON
ON
OFF
OFF
IDLIM
IO(LIM)
ILO
AD
ILOAD
0A
0A
Normal
Operation
Fault BIT
Bit X X
FAULT
SHORT OCCURS WHILE ON, ENDS DURING RETRY
SHORTED
/ SHORT - TO - VBAT
Shorted LOAD
Load/Short-to-VPWR
INPUT
X
Input X
Gate X
X
GATE
IOUT
IOUT
XX
5V V
5.0
0 0V
V
ON
ON
OFF
OFF
IO(LIM)
IDLIM
ILOAD
ILOAD
0A
0A
Fault Bit X
FAULT BIT X
CSB
CB
tSSA
tSSD
TSSD
TREF
tREF
tSSD
TSSA
TREF
tREF
TSSD
TREF
tREF
tREF
TREF
FAULT
Fault
Shorted
Operation
FAULT
Fault
GATE X = COM M AND SIGNAL AT THE GATE OF DRIVER X
Gate X = Command Signal at the Gate of Driver X
Fault
X INTERNAL
= Internal Fault
Register
Bit State
FAULT
BIT Bit
X =
FAULT
REGISTER
BIT STATE
tREF X = First Refresh Time may be less than tREF
TREF ILOAD
x = FIRST
TIME MAY BE LESS THAN TREF
= 1.0REFRESH
A
ILOAD = 1A
Figure 5. Short Occurring While On, Ending During Retry (ILOAD = 1.0 A)
NORMAL OPERATION
INPUT
InputXX
G ATE
GateXX
IO UT
XX
IOUT
5V V
5.0
0 0V
V
ON
ON
O FF
OFF
IO(LIM)
IDLIM
ILOAD
ILOAD
00AA
Normal
Operation
Fault BIT
Bit X X
FAULT
SHORT O CCURS WHILE ON, ENDS DURING REFRESH
SHORTED
Shorted
LOAD
Load/Short-to-VPWR
/ SHORT - TO - VBAT
INPUT
X
Input X
5.0
5V V
0 0V
V
Gate X
X
G ATE
ON
ON
OFF
OFF
IOUTX X
IOUT
IO(LIM)
IDLIM
ILOAD
ILO AD
0A
0A
tREF
TREF
Fault Bit X
FAULT BIT X
CSB
CB
tSSD
TSSD
TSSA
tSSA
tREF
TREF
FAULT
Fault
TR EF
tREF
TREF
tREF
Shorted
Operation
FAULT
Fault
GATE X = COM M AND SIGNAL AT THE G ATE OF DRIVER X
Gate X = Command Signal at the Gate of Driver X
FAULT Fault
BIT XBit
=X
INTERNAL
REGISTER
BIT STATE
= InternalFAULT
Fault Register
Bit State
TREF x
tREF
X = First Refresh Time may be less than tREF
= FIRST REFRESH TIM E MAY B E LESS THAN TREF
ILOAD = 20 mA
ILOAD = 20m A
Figure 6. Short Occurring While On, Ending During Refresh (ILOAD = 20 mA)
33882
12
Analog Integrated Circuit Device Data
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
TIMING DIAGRAMS
NORMAL OPERATION
INPUT
Input X
X
GATE
Gate X
IOUT
IOUTXX
5.05VV
0V
0V
ON
ON
OFF
OFF
IO(LIM)
IDLIM
ILOAD
ILOAD
0 0A
A
Normal
Operation
Fault Bit
X X
FAULT
BIT
SHORT OCCURS W HILE ON, ENDS DURING RETRY
SHORTED
/ SHORT - TO - VBAT
Shorted LOAD
Load/Short-to-VPWR
INPUT
Input XX
5.05VV
0V
0V
Gate XX
GATE
ON
ON
OFF
OFF
IO(LIM)
IDLIM
ILOAD
ILOAD
00AA
IOUTXX
IOUT
TSSA
tSSA
TREF
tREF
Fault Bit X
FAULT BIT X
CSB
CB
TSSD
tSSD
TREF
tREF
FAULT
Fault
tSSD
TSSD
TREF
tREF
TREF
tREF
Shorted
Operation
FAULT
Fault
GATE X = COMMAND SIGNAL AT THE GATE OF DRIVER X
Gate X = Command Signal at the Gate of Driver X
FAULTFault
BIT Bit
X =XINTERNAL
FAULT
REGISTER
BIT STATE
= Internal Fault
Register
Bit State
tREF X = First Refresh Time may be less than tREF
= FIRST REFRESH TIM E M AY BE LESS THAN TREF
ILOAD = 20 mA
TREF x
ILOAD = 20m A
Figure 7. Short Occurring While On, Ending During Retry (ILOAD = 20 mA)
33882
Analog Integrated Circuit Device Data
Freescale Semiconductor
13
ELECTRICAL CHARACTERISTICS
ELECTRICAL PERFORMANCE CURVES
ELECTRICAL PERFORMANCE CURVES
RDS(ON)
0.43
0.42
54.8
0.41
54.6
54.4
0.39
VOLTS
OHMS
0.4
0.38
0.37
54.2
54.0
53.8
0.36
0.35
VCLAMP
55.0
53.6
25
40
55
70
85
100
115
130
53.4
-50
AMBIENT TEMPERATURE (°C)
-25
0
25
50
75
100
125
AMBIENT TEMPERATURE (°C)
RDS(ON)
Figure 8. Output RDS(ON) Versus Temperature
Figure 9. Output Clamp Voltage Versus Temperature
Table 5. Logic Table
Mode of Operation
Normal Operation
Default Mode
Status
Status
Input Pins
Command
Transmitted Transmitted Mode Pin IN0&IN1 IN4&IN5
543210
Sent
SO
Next SO
Gates
543210
Outputs
543210
00111111
00000000
00111111
L
X
X
XXXXXX HHHHHH
001X1010
00000000
001Y1010
L
X
X
XHXLXL HHHLHL LLLHLH
LLLLLL
000101X1
00000000
000101Y1
L
X
X
LXLXHX LHLHHH HLHLLL
00XXX000
00000000
00YYY000
L
X
X
HHHLLL HHHLLL LLLHHH
00XXXXXX
11111111
11111111
H
H
H
XXHLXX HHHLHH LLLHLL
00XXXXXX
11111111
11111111
H
H
L
XXLHXX HHLHLL LLHLHH
00XXXXXX
11111111
11111111
H
L
H
XXHLXX LLHLHH HHLHLL
00XXXXXX
11111111
11111111
H
L
L
XXLHXX LLLHLL HHHLHH
Over-voltage Shutdown
00XXXXXX 00XXXXXX
00XXXXXX
X
X
X
XXXXXX L L L L L L H H H H H H
Short-to-Battery /
Short-circuit Output 0
00XXXXX0
00000000
00YYYYY0
L
X
X
XXXXXL YYYYYL YYYYYH
00XXXXX1
00000001
00YYYYY0
L
X
X
XXXXXX YY Y Y Y H Y Y YY Y H
Open Load /
00XXXXX0
Short-to-Ground Output 0 00XXXXX1
00000001
00YYYYY1
L
X
X
XXXXXL YYYYYL YYYYYL
00000000
00YYYYY1
L
X
X
XXXXXX YY Y Y Y H Y Y Y YY L
Legend
0011XXYY = Serial (SPI) commands and status bytes (8-bit operation mode) MSB to LSB.
0 = Off command, SO OK status.
1 = On command, SO FAULT status.
X = Don’t care.
Y = Defined by state of X.
H = High-voltage level: Active state for inputs / gates, inactive state for outputs.
L = Low-voltage level: Inactive state for inputs / gates, active state for outputs.
33882
14
Analog Integrated Circuit Device Data
Freescale Semiconductor
FUNCTIONAL DESCRIPTION
INTRODUCTION
FUNCTIONAL DESCRIPTION
INTRODUCTION
The 33882 incorporates six 1.0 A low side switches using
both Serial Peripheral Interface (SPI) I /O as well as optional
parallel input control to each output. There are also two lowpower (30 mA) low side switches with SPI diagnostic
feedback, but parallel-only input control. The 33882
incorporates SMARTMOS technology with CMOS logic,
bipolar / MOS analog circuitry, and DMOS power MOSFETs.
Designed to interface directly with a microcontroller, it
controls inductive or incandescent loads. Each output is
configured as an open drain transistor with dynamic
clamping.
FUNCTIONAL PIN DESCRIPTION
VPWR PIN
The VPWR pin is connected to battery voltage. This supply
is provided for over-voltage shutdown protection and for
added gate drive capabilities. A decoupling capacitor is
required from VPWR to ground.
corresponding SPI control bit to control each output channel.
These pins have internal 25 μA active pull-downs.
OUT0 TO OUT7 PINS
Each pin is one channel's low side switch output. OUT0 to
OUT5 are actively clamped to handle inductive loads.
IN0 & IN1, IN2 & IN3, AND IN4 & IN5 PINS
These input pins control two output channels each when
the MODE pin is pulled high: IN0 & IN1 controls OUT0 and
OUT1, IN2 & IN3 controls OUT2 and OUT3, while IN4 & IN5
controls OUT4 and OUT5. These pins may be connected to
PWM outputs of the control IC and pulled high or pulled low
to control output channel states while the MODE pin is high.
The states of these pins are ignored during normal operation
(MODE pin low) and override the normal inputs (serial or
parallel) when the MODE pin is high. These pins have internal
active 25 μA pull-downs.
MODE PIN
The MODE pin is connected to the MODE pin of the control
IC. This pin has an internal active 25 μA pull-up. When pulled
high, the MODE pin does the following:
• Disables all serial control of the outputs while still reading
any serial input commands.
• Disables parallel inputs IN0, IN1, IN2, IN3, IN4, and IN5
control of the outputs.
• Selects IN0 & IN1, IN2 & IN3, and IN4 & IN5 input pins for
control of OUT0 and OUT1, OUT2 and OUT3, OUT4 and
OUT5, respectively.
• Turns off OUT6 and OUT7.
• Tri-states the SO pin.
IN0 TO IN7 PINS
These are parallel input pins connected to output pins of
the control IC. Each parallel input is logic high with the
SI PIN
The Serial Input pin is connected to the SPI Serial Data
Output pin of the control IC from where it receives output
command data. This input has an internal active 25 μA pulldown and requires CMOS logic levels. The serial data
transmitted on this line is an 8- or 16-bit control command
sent MSB first, controlling the six output channels. Bits A5
through A0 control channels 5 through 0, respectively. Bits
A6 and A7 enable ON open load fault detection on channels
5 through 0. The control IC will ensure that data is available
on the rising edge of SCLK. Each channel has its serial
control bit high with its parallel input to determine its state.
SCLK PIN
The SCLK pin of the control IC is a bit (shift) clock for the
SPI port. It transitions one time per bit transferred when in
operation. It is idle between command transfers. It is 50%
duty cycle and has CMOS levels. This signal is used to shift
data to and from the device. For proper fault reporting
operation, the SCLK input must be low when CS transitions
from high to low.
CS PIN
The CS pin is connected to a chip select output of the
control IC. The control IC controls which device is addressed
by pulling the CS pin of the desired device low, enabling the
SPI communication with the device, while other devices on
the serial link keep their serial outputs tri-stated. This input
has an internal active 25 μA pull-up and requires CMOS logic
levels.
33882
Analog Integrated Circuit Device Data
Freescale Semiconductor
15
FUNCTIONAL DESCRIPTION
FUNCTIONAL PIN DESCRIPTION
SO PIN
The Serial Output pin is connected to the SPI Serial Data
Input pin of the control IC or to the SI pin of the next device in
a daisy chain. This output will remain tri-stated unless the
device is selected by a low CS pin or the MODE pin goes low.
The output signal generated will have CMOS logic levels and
the output data will transition on the falling edges of SCLK.
The serial output data provides fault information for each
output and is returned MSB first when the device is
addressed. Fault bit assignments for return data are as
follows: MSB-0 through MSB-7 are output fault bits for OUT7
to OUT0, respectively. In 8-bit SPI mode, under normal
conditions, the SO pin (not daisy chained) returns all 0s,
representing no faults. If a fault is present, a 1 is returned for
the appropriate bit. In 16-bit SPI mode, sending a double
command byte will provide a command verification byte
following the fault status byte returned from the SO pin (nondaisy chained). With the MODE pin high, the serial output pin
tri-states. If nothing is connected to the SO pin except an
external 10 kΩ pull-up resistor, data is read as all [1]s by the
control IC.
VDD PIN
This pin is connected to the 5.0 V power supply of the
system. A decoupling capacitor is required from VDD to
ground.
PERFORMANCE FEATURES
NORMAL OPERATION
SERIAL STATUS OUTPUT
OUT0 to OUT7 are independent during normal operation.
OUT0 to OUT5 may be driven serially or by their parallel input
pins. OUT6 and OUT7 can only be controlled by their parallel
input pins. Device operation is considered normal only if the
following conditions apply:
• VPWR of 5.5 V to 24 V, and VDD voltage of 4.75 V to 5.25 V.
• Junction temperatures less than 150 °C.
• For each output, drain voltage exceeds the Open Load
OFF Detection Voltage, specified in the specification table,
while the output is OFF. For open load detection, an open
condition existing for less than the Open Load Detection
time, specified in the specification table, is not considered
a fault nor is it reported to the fault status register.
• The MODE pin is held at the logic low level, keeping the
serial channel / parallel input pins in control of the eight
outputs.
Serial output information sent on the SPI port is a check on
the fault status of each output channel as well as a check for
MODE initiation. Serial command verification is also possible.
SERIAL / PARALLEL INPUT CONTROL
Input control is accomplished by the serial control byte
sent via the SPI port from the control IC or by the parallel
control pins for each channel. For channels 0 to 5 with serial
and parallel control the output state is determined by the OR
of the serial bit and the parallel input pin state. Serial
communication is initiated by a low state on the CS pin and
timed by the SCLK signal. After CS switches low, the IC
initiates eight or 16 clock pulses with the control bits being
available on the SI pin at the rising edge of SCLK.
The bits are transferred in descending bit-significant
order. Any fault or MODE indications on bits returned are logic
[1]s. The last six bits are the command signals to the six
outputs. Upon completion of the serial communication the CS
pin will switch high. This terminates the communication with
the slave device and loads the control bits just received to the
output channels. Upon device power-up, the serial register is
cleared.
In the application for non-daisy chain configurations, the
number of SPI devices available to be driven by the SO pin is
limited to eight devices.
SO PIN OPERATION
The SO pin provides SPI status, allowing daisy chaining.
The status bits returned to the IC are the fault register bits
with logic [1]s indicating a fault on the designated output or
MODE if all bits return logic [1] (with a 10 kΩ pull-up resistor
on the SO pin). A command verification is possible if the SPI
mode is switched to 16 bits. The first byte (8 bits) returned
would be the fault status, while the second byte returned
would be the first byte sent feeding through the 33882 IC.
The second command byte sent would be latched into the
33882 IC. The CS pin switching low indicates the device is
selected for serial communication with the IC. Once CS
switches low, the fault status register cannot receive new
fault information and serial communication begins. As the
control bits are clocked from the IC MSB first, they are
received on rising SCLK edges at the SI pin.
The fault status bits transition on the SO pin on falling
SCLK edges and are sampled on rising SCLK edges at the
input pin of the IC SPI device. When the command bit
transmissions for serial communication are complete, the CS
pin is switched high. This terminates communication with the
device. The SO pin tri-states, the fault status register is
opened to accept new fault information, and the transmitted
command data is loaded to the outputs. At the same time, the
IC can read the status byte it received.
DAISY CHAIN OPERATION (ONLY POSSIBLE WITH
SO PIN)
Daisy chain configurations can be used with the SO pin to
save CS outputs on the IC. Clocking and pin operations are
as defined in the SO Pin Operation paragraph. For daisy
chaining two 8-bit devices, a 16-bit SPI command is sent, the
first command byte for the second daisy chain device and the
second command byte for the first daisy chain device. A
command verification is possible if the SPI mode is switched
33882
16
Analog Integrated Circuit Device Data
Freescale Semiconductor
FUNCTIONAL DESCRIPTION
FUNCTIONAL PIN DESCRIPTION
to 32 bits. The first word sent is command verification data
fed through the two 33882 ICs. Data returned in the 32 bits is
the two fault status bytes, followed by the first word sent. Bits
sent out are sampled on rising SCLK edges at the input pin
of the next IC in the daisy chain.
Note Because SO pins of the 33882 ICs are tri-stated,
any device receiving its SPI data from a previous 33882 IC
SO pin in a daisy chain will not receive data if the MODE pin
is low. This prohibits setting SPI-controlled channels ON with
a SPI command while the MODE pin is low. Therefore, all
channels remain OFF when the MODE pin changes from low
to high at vehicle power-up.
MODE OPERATION
During normal operation output channels are controlled by
either the Serial Input control bits or the parallel input pins. If
the MODE pin is pulled high:
• Serial input control is disabled.
• Parallel input pins IN0 to IN5 are ignored.
• The SO pin is tri-stated.
OUT0 and OUT1, OUT2 and OUT3, and OUT4 and OUT5
are controlled by the IN0 & IN1, IN2 & IN3, and IN4 & IN5
pins, respectively. When a 10 kΩ pull-up resistor is used, a
logic high on the MODE pin or an open serial output pin is
flagged by the SPI when all bits are returned as logic [1]s.
Although a logic high on the MODE pin disables serial
control of outputs, data can still be clocked into the serial
input register. This allows programming of a desired state for
the outputs taking effect only when the MODE pin returns to a
logic low. For applications using the SO pin, daisy chaining is
permitted, but if the MODE pin is high, writing to other than the
first IC in a daisy chain is not possible because the serial
outputs are tri-stated.
OUTPUT DRIVERS
The high power OUT0 to OUT5 outputs are active
clamped, low side switches driving 1.0 A typical or less loads.
The low-power OUT6 and OUT7 outputs are unclamped lowside switches driving 30 mA typical or less loads. All outputs
are individually protected from short circuit or short-to-battery
conditions and transient voltages. The outputs are also
protected by short-circuit device shutdown. Each output
individually detects and reports open load /short-to-ground
and short-circuit /short-to-battery faults.
FAULT SENSE / PROTECTION CIRCUITRY
Each output channel individually detects shorted loads /
short-to-battery while the output is ON and open load /shortto-ground while the output is OFF. OUT0 to OUT5 may also
be programmed via SPI bits 6 and 7 to detect open loads and
shorts-to-ground while the output is ON. Whenever a short or
open fault condition is present on a particular output channel,
its fault bit in the internal fault register indicates the fault with
a logic [1].
When a fault ends, its fault bit remains set until the SPI
register is read, then it returns to a logic [0], indicating a
normal condition. When the CS pin is pulled low for serial
communication, the fault bits in the internal fault register
latch, preventing erroneous status transmissions and the
forthcoming communication reports this latched fault status.
The SO pin serial output data for 8-bit SPI mode are the fault
status register bits.
For 16-bit SPI mode and SO pin (non-daisy chained) use,
a transmitted double command provides the fault byte
followed by the first byte of the double command, becoming
a command verification. The status is sent back to the IC for
fault monitoring. Diagnostic interpretation of the following
fault types can be accomplished using the procedure
described in the paragraph entitled Extensive Fault
Diagnostics:
• Communication error
• Open load /short-to-ground
• Short-to-battery or short-circuit
When serial communication is ended, the CS pin returns
high, opening the fault status register to new fault information
and tri-stating the SO pin.
Two fault conditions initiate protective action by the device:
• A short-circuit or short-to-battery on a particular output will
cause that output to go into a low duty cycle operation until
the fault condition is removed or the input to that channel
turns OFF.
• A short-circuit condition causes all channels to shut down,
ignoring serial and parallel inputs to the device.
To be detected and reported as a fault, a fault condition
must last a specified time (fault sense time or fault mask
time). This prevents any normal switching transients from
causing inadvertent fault status indications.
Fault status information should be ignored for VBAT levels
outside the 9.0 V to 17 V range. The fault reporting may
appear to function properly but may not be 100 percent
reliable.
SHORT-CIRCUIT /SHORT-TO-BATTERY SENSING
AND PROTECTION
When an output is turned ON, if the drain current limit is
reached, the current remains at the limit until the short-circuit
sense time, tSS, has elapsed. At this time, the affected output
will shut down and its fault status bit switches to a logic [1].
The output goes into a low duty cycle operation as long as the
short-circuit condition exists and the input to that channel is
ON.
This duty cycle is defined by the sense and refresh times.
If a short occurs after the output is ON, the fault sense time
indicates the fault and enters the low duty cycle mode at
much less than t SS. The duty cycle is low enough to keep the
driver from exceeding its thermal capabilities. When the short
is removed, the driver resumes normal operation at the next
retry, but the fault status bit does not return to a normal
logic [0] state until it is read from the SPI. When the CS pin of
this device is pulled low, the fault status bits are latched, after
which any new fault information is not a part of this serial
communication event.
33882
Analog Integrated Circuit Device Data
Freescale Semiconductor
17
FUNCTIONAL DESCRIPTION
FUNCTIONAL PIN DESCRIPTION
The low duty cycle operation for a short-circuit condition is
required to protect the output. It is possible to override this
duty cycle if the input signal (parallel or SPI) turns the channel
ON and OFF faster than 10 kHz. For this reason control
signals should not exceed this frequency.
OPEN LOAD / SHORT-TO-GROUND WHILE OFF
SENSING
If the drain voltage falls below the Open Load OFF
Detection Voltage at turn OFF for a period of time exceeding
the Open Load Sense Time, the fault status bit for this output
switches to a logic [1].
If a drain voltage falls below the Open Load OFF Detection
Voltage threshold when the output has been OFF, a fault is
indicated with a delay much less than the Open Load Sense
Time. When the fault is removed, normal operation resumes
and the fault status bit will return to a normal logic [0] state.
When the CS pin of this device is pulled low, the fault status
bits are latched, after which any new fault information is not
part of this serial communication event.
OVER-VOLTAGE SENSING AND PROTECTION
When VPWR exceeds the Over-voltage Shutdown
Threshold, all channels are shut down. Serial input data and
parallel inputs are ignored. The device resumes normal
operation when the VPWR voltage drops below the Overvoltage Shutdown Hysteresis voltage. During over-voltage
shutdown, some faults may appear to report accurately;
however, fault sensing operation is only guaranteed for
battery voltage levels from 9.0 V to 17 V.
all logic [1]s are again returned, there is an open SO line, an
open MODE line, or the SPI is not functioning.
If the fault does not verify on the command resend, normal
operation is resumed. The error could be a communication
mistake, a momentary output fault, or a fault condition no
longer sensed due to switching the state of the output. For the
first two cases, normal operation is resumed and the software
continues its normal functions. However in the third case,
additional commands are required for extensive diagnosis of
the fault type, if this information is mandatory.
EXTENSIVE FAULT DIAGNOSTICS
More extensive diagnosis may be required under the
following conditions:
• When the fault type of a confirmed fault is desired, the
following scenarios are possible:
–
If MSB-2 to MSB-7 indicates a fault, it is an open
load / short-to-ground fault if the output is OFF when
the fault is reported because only open load / shortto-ground sensing remains operable while an output
is OFF.
–
If the output is ON when the fault is reported, the
fault is a short-circuit /short-to-battery if ON open
load detection is not enabled via SPI. If ON open
load detection is enabled, it must be disabled and
the fault status reread. If the fault remains, it is a
short-circuit / short-to-battery or it is an open load /
short-to-ground.
–
If MSB-0 to MSB-2 indicates a fault, it is an open
load / short-to-ground fault if the output is OFF when
the fault is reported because only open load /shortto-ground sensing remains operable while an output
is OFF.
FAULT STATUS MONITORING REQUIREMENTS
FOR SERIALLY CONTROLLED OUTPUTS, SO PIN
Fault monitoring over the serial channel by the IC requires
a minimal amount of overhead for normal operation. Each
status byte received consists of all logic [0]s when faults are
not present. If any logic [1]s are returned, a communication
error occurred, an output fault occurred, or the MODE pin has
been set low. Upon receiving any logic [1] bits, the IC must
resend the last command, verifying the returned logic [1]s, or
correct any communication error.
A 16-bit SPI transmission with a double command byte to
this 8-bit device allows verification of the command (second
byte returned) in addition to the fault byte (first byte returned).
The command (second) byte returned should mirror the bits
sent unless a communication error occurred, in which case
the command resent should accomplish the correction.
If the returned logic [1] validates, it may indicate a MODE
pin high or a confirmed output fault. If it was a confirmed
output fault, extensive diagnostics could be performed,
determining the fault type, especially if vehicle service is
being performed. If all bits return high and verify such, the IC
must verify sending a logic low to the MODE pin. It should
then resend the command, verifying the MODE pin is at a
logic low level, allowing resumption of a normal operation. If
–
If the output is ON when the fault is reported, the
fault is a short-circuit /short-to-battery.
• When a fault did not confirm on resend, the fault could
either be an short-circuit /short-to-battery fault, not sensed
when turned OFF; an open load /short-to-ground fault, not
sensed when turned ON; or a corrected communication
error.
To determine if it is an output fault condition, the faulted
output must be turned back to its previous state with a new
command. This command should be sent twice to read the
status after the output is latched in this state, thus
confirming the fault and reporting it again.
Parallel control of outputs is a mode of control, potentially
requiring extensive diagnostics if a fault is reported. This is
because parallel control signals are completely
asynchronous to the serial commands. Status reports for
parallel controlled outputs could require additional
information exchange in software to:
• Avoid status reads when outputs are transitioned, thereby
avoiding fault masking times.
• Obtain the state of a faulted output for determining fault
type (if required).
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FUNCTIONAL DESCRIPTION
FUNCTIONAL PIN DESCRIPTION
SYSTEM ACTUATOR ELECTRICAL
CHARACTERISTICS (AT ROOM TEMPERATURE)
All drains should have a 0.01 μF filter capacitor connected
to ground. Any unused output pin should not be energized. A
20 Ω resistor to the battery is required to prevent false open
load reporting. There must also be a maximum of 100 Ω of
resistance from VPWR to ground, keeping battery-powered
loads OFF when the IC is powered down. However, all loads
should be powered by VPWR to protect the device from full
transient voltages on the battery voltage.
POWER-UP
The device is insensitive to power sequencing for VPWR
and VDD, as well as intolerant to latch-up on all I /O pins.
Upon power-up, an internal power-ON reset clears the serial
registers, allowing all outputs to power up in the off-state
when parallel control pins are also low. Although the serial
register is cleared by this power-ON reset, software must still
initialize the outputs with an SPI command prior to changing
the MODE pin from a high to a low state. This assures known
output states when MODE is low.
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PACKAGING
PACKAGE DIMENSIONS
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For the most current package revision, visit www.freescale.com and perform a keyword search using the “98A” listed below.
VW SUFFIX
30-PIN HSOP
98ASH70693A
ISSUE A
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PACKAGING
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REVISION HISTORY
PACKAGE DIMENSIONS (CONTINUED)
REVISION HISTORY
REVISION
DATE
DESCRIPTION OF CHANGES
3.0
9/2005
• Implemented Revision History page
• Added Thermal Addendum
• Converted to Freescale format
4.0
5/2006
• Updated ordering information block on page 1
5.0
10/2006
• Updated data sheet format
• Removed Peak Package Reflow Temperature During Reflow (solder reflow) parameter
from Maximum Ratings on page 5. Added note with instructions to obtain this information
from www.freescale.com.
6.0
6/2009
• Changed Supply Voltage in Static Electrical Characteristics, Table 4, on page 9
7.0
x/2010
• New Fab transfer devices added. No electrical parameter changes.
• Removed Part Numbers MC33882FC/R2, MC33882EK/R2, MC33882VW, and
MC33882EP, and replaced with part numbers MC33882PVW, MC33882PEP.
• Added EK package to the ordering information and supporting data
• Removed all DH suffix information.
• Corrected HSOP 98A reference number and associated information
• Update the Packaging section 98A drawings
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MC33882
Rev. 7.0
3/2011