IDT IDT72403L10P Cmos parallel fifo 64 x 4 and 64 x 5 Datasheet

IDT72401
IDT72403
CMOS PARALLEL FIFO
64 x 4 and 64 x 5
FEATURES:
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has an Output Enable (OE) pin. The FlFOs accept 4-bit data at the data input
(D0-D3). The stored data stack up on a first-in/first-out basis.
A Shift Out (SO) signal causes the data at the next to last word to be shifted
to the output while all other data shifts down one location in the stack. The Input
Ready (IR) signal acts like a flag to indicate when the input is ready for new
data (IR = HIGH) or to signal when the FIFO is full (IR = LOW). The IR signal
can also be used to cascade multiple devices together. The Output Ready (OR)
signal is a flag to indicate that the output remains valid data (OR = HIGH) or
to indicate that the FIFO is empty (OR = LOW). The OR can also be used to
cascade multiple devices together.
Width expansion is accomplished by logically ANDing the IR and OR signals
to form composite signals.
Depth expansion is accomplished by tying the data inputs of one device to
the data outputs of the previous device. The IR pin of the receiving device is
connected to the SO pin of the sending device and the OR pin of the sending
device is connected to the Shift In (SI) pin of the receiving device.
Reading and writing operations are completely asynchronous allowing the
FIFO to be used as a buffer between two digital machines of widely varying
operating frequencies. The 45MHz speed makes these FlFOs ideal for highspeed communication and controller applications.
Military grade product is manufactured in compliance with the latest revision
of MIL-STD-883, Class B.
First-ln/First-Out Dual-Port memory
64 x 4 organization (IDT72401/72403)
RAM-based FIFO with low falI-through time
Low-power consumption
— Active: 175mW (typ.)
Maximum shift rate — 45MHz
High data output drive capability
Asynchronous and simultaneous read and write
Fully expandable by bit width
Fully expandable by word depth
IDT72403 have Output Enable pin to enable output data
High-speed data communications applications
High-performance CMOS technology
Available in CERDIP, plastic DIP and SOIC
Military product compliant to MlL-STD-883, Class B
Standard Military Drawing #5962-86846 and
5962-89523 is listed on this function.
Industrial temperature range (–40°°C to +85°°C) is available
(plastic packages only)
DESCRIPTION:
The IDT72401 and IDT72403 are asynchronous high-performance
First-ln/First-Out memories organized 64 words by 4 bits. The IDT72403 also
FUNCTIONAL BLOCK DIAGRAM
SI
IR
INPUT
CONTROL
LOGIC
D0-3
DATA IN
MR
MASTER
RESET
WRITE POINTER
WRITE MULTIPLEXER
OUTPUT
ENABLE
OE
(IDT72403 only)
MEMORY
ARRAY
DATA IN
Q0-3
READ MULTIPLEXER
READ POINTER
MASTER
RESET
SO
OR
2747 drw01
IDT and the IDT logo are trademarks of Integrated Device Technology, Inc.
FAST is a trademark of National Semiconductor, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
OCTOBER 2005
1
© 2005
Integrated Device Technology, Inc.
All rights reserved. Product specifications subject to change without notice.
DSC-2747/10
IDT72401/72403
CMOS PARALLEL FIFO 64 x 4, 64 x 5
MILITARY AND COMMERCIAL
TEMPERATURE RANGES
PIN CONFIGURATIONS
IDT72401/IDT72403
NC/OE(1)
IR
SI
D0
D1
D2
D3
GND
1
16
2
15
3
14
4
13
5
12
6
11
7
10
9
8
Vcc
SO
OR
Q0
Q1
Q2
Q3
MR
2747 drw 02
PLASTIC DIP (P16-1, ORDER CODE: P)
CERDIP (D16-1, ORDER CODE: D)
SOIC (SO16-1, ORDER CODE: SO)
TOP VIEW
NOTE:
1. Pin 1: NC - No Connection IDT72401, OE - IDT72403
RECOMMENDED OPERATING
CONDITIONS
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Parameter
Min.
Typ.
Max.
Unit
4.5
5.0
5.5
V
0
0
0
V
Input High Voltage
2.0
—
—
V
Input High Voltage
—
—
0.8
V
Operating Temperature Commercial
Operating Temperature Military
0
–55
—
—
70
125
°C
°C
Symbol
Rating
Commercial
Military
Unit
VCC
Supply Voltage Commercial/Military
VTERM
Terminal Voltage with
Respect to GND
–0.5 to +7.0
–0.5 to +7.0
V
GND
Supply Voltage
TSTG
IOUT
Storage Temp.
DC Output Current
–55 to +125
–50 to +50
–65 to +150
–50 to +50
°C
mA
VIH
VIL(1)
TA
TA
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
NOTE:
1. 1.5V undershoots are allowed for 10ns once per cycle.
DC ELECTRICAL CHARACTERISTICS
(Commercial: VCC = 5.0V ± 10%, TA = 0°C to +70°C; Military: VCC = 5.0V ± 10%, TA = –55°C to +125°C)
IDT72401
IDT72403
Commercial
fIN = 45, 35, 25, 15, 10 MHz
Symbol
IIL
IIH
VOL
VOH
IOS(1)
IHZ(2)
ILZ(2)
ICC(3,4)
Parameter
Low-Level Input Current
High-Level Input Current
Low-Level Output Voltage
High-Level Output Voltage
Output Short-Circuit Current
HIGH Impedance Output Current
LOW Impedance Output Current
Active Supply Current
Test Conditions
VCC = Max., GND ≤ VI ≤ VCC
VCC= Max., GND ≤ VI ≤ VCC
VCC= Min., IOL = 8mA
VCC= Min., IOH = –4mA
VCC= Max., VO = GND
VCC= Max., VO = 2.4V
VCC= Max., VO = 0.4V
VCC= Max., f = 10MHz
Min.
–10
—
—
2.4
–20
—
–20
—
Max.
—
10
0.4
—
–110
20
—
35
IDT72401
IDT72403(5)
Military
fIN = 35, 25, 15, 10 MHz
Min.
–10
—
—
2.4
–20
—
–20
—
NOTES:
1. Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second. Guaranteed but not tested.
2. IDT72403 only.
3. Tested with outputs open (IOUT = 0). OE is HIGH for IDT72403.
4. For frequencies greater than 10MHz, ICC = 35mA + (1.5mA x [f –10MHz]) commercial, and ICC = 45mA + (1.5mA x [f –10MHz]) military.
5. Military availability for IDT72403 is 10MHz, 35MHz. IDT72401 is available for all MHz.
2
Max.
—
10
0.4
—
–110
20
—
45
Unit
µA
µA
V
V
mA
µA
µA
mA
MILITARY AND COMMERCIAL
TEMPERATURE RANGES
IDT72401/72403
CMOS PARALLEL FIFO 64 x 4, 64 x 5
OPERATING CONDITIONS
(Commercial: VCC = 5.0V ± 10%, TA = 0°C to +70°C; Military: VCC = 5.0V ± 10%, TA = –55°C to +125°C)
Symbol
t SIH (1)
Parameter
Shift in HIGH Time
Figure
2
Commercial
IDT72401L45
IDT72403L45
Min.
Max.
9
—
IDT72401L35
IDT72403L35
Min.
Max.
9
—
Commercial and Military(5)
IDT72401L25
IDT72401L15
IDT72403L25
IDT72403L15
Min.
Max.
Min.
Max.
11
—
11
—
IDT72401L10
IDT72403L10
Min.
Max.
11
—
Unit
ns
tSIL
tIDS
Shift in LOW TIme
Input Data Set-up
2
2
11
0
—
—
17
0
—
—
24
0
—
—
25
0
—
—
30
0
—
—
ns
ns
tIDH
t SOH (1)
Input Data Hold Time
Shift Out HIGH Time
2
5
13
9
—
—
15
9
—
—
20
11
—
—
30
11
—
—
40
11
—
—
ns
ns
t SOL
tMRW
Shift Out LOW Time
Master Reset Pulse
5
8
11
20
—
—
17
25
—
—
24
25
—
—
25
25
—
—
25
30
—
—
ns
ns
tMRS
tSIR
Master Reset Pulse to SI
Data Set-up to IR
8
4
10
3
—
—
10
3
—
—
10
5
—
—
25
5
—
—
35
5
—
—
ns
ns
tHIR
t SOR (4)
Data Hold from IR
Data Set-up to OR HIGH
4
7
13
0
—
—
15
0
—
—
20
0
—
—
30
0
—
—
30
0
—
—
ns
ns
AC ELECTRICAL CHARACTERISTICS
(Commercial: VCC = 5.0V ± 10%, TA = 0°C to +70°C; Military: VCC = 5.0V ± 10%, TA = –55°C to +125°C)
Symbol
f IN
Parameter
Figure
Commercial
IDT72401L45
IDT72403L45
Min.
Max.
IDT72401L35
IDT72403L35
Min.
Max.
Commercial and Military(5)
IDT72401L25
IDT72401L15
IDT72403L25
IDT72403L15
Min.
Max.
Min.
Max.
IDT72401L10
IDT72403L10
Min.
Max.
Unit
Shift In Rate
2
—
45
—
35
—
25
—
15
—
10
MHz
(1)
Shift In to Input Ready LOW
2
—
18
—
18
—
21
—
35
—
40
ns
(1)
Shift In to Input Ready HIGH
2
—
18
—
20
—
28
—
40
—
45
ns
Shift Out Rate
5
—
45
—
35
—
25
—
15
—
10
MHz
Shift Out to Output Ready LOW
5
—
18
—
18
—
19
—
35
—
40
ns
Shift Out to Output Ready HIGH
5
—
19
—
20
—
34
—
40
—
55
ns
tODH
Output Data Hold (Previous Word)
5
5
—
5
—
5
—
5
—
5
—
ns
tODS
Output Data Shift (Next Word)
t PT
Data Throughput or "Fall-Through"
tMRORL
t IRL
t IRH
f OUT
t ORL (1)
(1)
t ORH
5
—
19
—
20
—
34
—
40
—
55
ns
4, 7
—
30
—
34
—
40
—
65
—
65
ns
Master Reset to OR LOW
8
—
25
—
28
—
35
—
35
—
40
ns
tMRIRH
Master Reset to IR HIGH
8
—
25
—
28
—
35
—
35
—
40
ns
tMRQ
Master Reset to Data Output LOW
8
—
20
—
20
—
25
—
35
—
40
ns
Output Valid from OE LOW
9
—
12
—
15
—
20
—
30
—
35
ns
Output High-Z from OE HIGH
9
—
12
—
12
—
15
—
25
—
30
ns
Input Ready Pulse HIGH
4
9
—
9
—
11
—
11
—
11
—
ns
Output Ready Pulse HIGH
7
9
—
9
—
11
—
11
—
11
—
ns
t OOE
(3)
t HZOE
t IPH
(3,4)
(2,4)
t OPH
(2,4)
NOTES:
1. Since the FIFO is a very high-speed device, care must be excercised in the design of the hardware and timing utilized within the design. Device grounding and decoupling
are crucial to correct operation as the FIFO will respond to very small glitches due to long reflective lines, high capacitances and/or poor supply decoupling and grounding.
A monolithic ceramic capacitor of 0.1µF directly between VCC and GND with very short lead length is recommended.
2. This parameter applies to FIFOs communicating with each other in a cascaded mode. IDT FIFOs are guaranteed to cascade with other IDT FIFOs of like speed grades.
3. IDT72403 only.
4. Guaranteed by design but not currently tested.
5. Military availability for IDT72403 is 10MHz, 35MHz. IDT72401 is available for all MHz.
3
IDT72401/72403
CMOS PARALLEL FIFO 64 x 4, 64 x 5
MILITARY AND COMMERCIAL
TEMPERATURE RANGES
ALL INPUT PULSES:
AC TEST CONDITIONS
Input Pulse Levels
GND to 3.0V
Input Rise/Fall Times
3.0V
3ns
Input Timing Reference Levels
1.5V
Output Reference Levels
90%
GND
1.5V
Output Load
90%
10%
10%
<3ns
<3ns
See Figure 1
2747 drw 04
5V
1.1KΩ
CAPACITANCE
OUTPUT
(TA = +25°C, f = 1.0MHz)
Symbol
Parameter
Conditions
Max.
Unit
CIN
Input Capacitance
VIN = 0V
5
pF
COUT
Output Capacitance
VOUT = 0V
7
pF
560Ω
30pF*
2747 drw 05
NOTE:
1. Characterized values, not currently tested.
or equivalent circuit
Figure 1. AC Test Load
*Including scope and jig
SIGNAL DESCRIPTIONS
INPUT READY (IR)
When Input Ready is HIGH, the FIFO is ready for new input data to be written
to it. When IR is LOW the FIFO is unavailable for new input data. IR is also used
to cascade many FlFOs together, as shown in Figures 10 and 11.
INPUTS:
DATA INPUT (D0-3)
Data input lines. The IDT72401 and IDT72403 have a 4-bit data input.
OUTPUT READY (OR)
When Output Ready is HIGH, the output (Q0-3) contains valid data. When
OR is LOW, the FIFO is unavailable for new output data. OR is also used to
cascade many FlFOs together, as shown in Figures 10 and 11.
CONTROLS:
SHIFT IN (SI)
Shift In controls the input of the data into the FIFO. When SI is HIGH, data
can be written to the FIFO via the D0-3 lines.
OUTPUT ENABLE (OE) (IDT72403 ONLY)
Output enable is used to read FIFO data onto a bus. OE is active LOW.
SHIFT OUT (SO)
Shift Out controls the output of data of the FIFO. When SO is HIGH, data can
be read from the FIFO via the Data Output (Q0-3) lines.
OUTPUTS:
DATA OUTPUT (Q0-3)
Data Output lines. The IDT72401 and IDT72403 have a 4-bit data output.
MASTER RESET (MR)
Master Reset clears the FIFO of any data stored within. Upon power up, the
FIFO should be cleared with a MR. MR is active LOW.
4
MILITARY AND COMMERCIAL
TEMPERATURE RANGES
IDT72401/72403
CMOS PARALLEL FIFO 64 x 4, 64 x 5
FUNCTIONAL DESCRIPTION
DATA OUTPUT
Data is shifted out on the HlGH-to-LOW transition of Shift Out (SO). This causes
the internal read pointer to be advanced to the next word location. If data is
present, valid data will appear on the outputs and Output Ready (OR) will go
HIGH. If data is not present, OR will stay LOW indicating the FIFO is empty. The
last valid word read from the FIFO will remain at the FlFOs output when it is empty.
When the FIFO is not empty, OR goes LOW on the LOW-to-HIGH transition of
SO. Previous data remains on the output until the HIGH-to-LOW transition of
SO).
FALL THROUGH MODE
The FIFO operates in a fall-through mode when data gets shifted into an empty
FIFO. After a fall-through delay the data propagates to the output. When the
data reaches the output, the Output Ready (OR) goes HIGH. Fall-through mode
also occurs when the FIFO is completely full. When data is shifted out of the full
FIFO, a location is available for new data. After a fall-through delay, the Input
Ready (IR) goes HIGH. If Shift In (SI) is HIGH, the new data can be written
to the FIFO.
Since these FlFOs are based on an internal dual-port RAM architecture with
separate read and write pointers, the fall-through time (tPT) is one cycle long.
A word may be written into the FIFO on a clock cycle and can be accessed on
the next clock cycle.
The 64 x 4 FIFO is designed using a dual port RAM architecture as opposed
to the traditional shift register approach. This FIFO architecture has a write
pointer, a read pointer and control logic, which allow simultaneous read and
write operations. The write pointer is incremented by the falling edge of the Shift
In (Sl) control; the read pointer is incremented by the falling edge of the Shift Out
(SO). The Input Ready (IR) signals when the FIFO has an available memory
location; Output Ready (OR) signals when there is valid data on the output.
Output Enable (OE) provides the capability of three-stating the FIFO outputs.
FIFO RESET
The FIFO must be reset upon power up using the Master Reset (MR) signal.
This causes the FlFO to enter an empty state, signified by Output Ready (OR)
being LOW and Input Ready (IR) being HIGH. In this state, the data outputs
(Q0-3) will be LOW.
DATA INPUT
Data is shifted in on the LOW-to-HlGH transition of Shift In (Sl). This loads
input data into the first word location of the FIFO and causes Input Ready (IR)
to go LOW. On the HlGH-to-LOW transition of SI, the write pointer is moved to
the next word position and IR goes HIGH, indicating the readiness to accept new
data. If the FIFO is full, IR will remain LOW until a word of data is shifted out.
1/fIN
tSIH
1/fIN
tSIL
SI
tIRH
IR
tIDS
tIRL
tIDH
INPUT DATA
2747 drw 06
Figure 2. Input Timing
SI
(7)
(2)
(4)
(1)
INPUT DATA
(5)
(3)
IR
(6)
STABLE DATA
2747 drw 07
NOTES:
1. IR HIGH indicates space is available and a SI pulse may be applied.
2. Input Data is loaded into the first word.
3. IR goes LOW indicating the first word is full.
4. The write pointer is incremented.
5. The FIFO is ready for the next word.
6. If the FIFO is full then the IR remains LOW.
7. SI pulses applied while IR is LOW will be ignored (see Figure 4).
Figure 3. The Mechanism of Shifting Data Into the FIFO
5
IDT72401/72403
CMOS PARALLEL FIFO 64 x 4, 64 x 5
MILITARY AND COMMERCIAL
TEMPERATURE RANGES
(2)
SO
(3)
SI
(5)
tIPH
tPT
(4)
IR
(1)
tSIR
tHIR
STABLE DATA
INPUT DATA
2747 drw 08
NOTES:
1. FIFO is initially full.
2. SO pulse is applied.
3. SI is held HIGH.
4. As soon as IR becomes HIGH the Input Data is loaded into the FIFO.
5. The write pointer is incremented. SI should not go LOW until (t PT + t IPH ).
Figure 4. Data is Shifted In Whenever Shift In and Input Ready are Both HIGH
1/fOUT
tSOH
1/fOUT
tSOL
SO
(2)
tORH
OR
(1)
tORL
tODS
tODH
A-DATA
OUTPUT DATA
B-DATA
C-DATA
2747 drw 09
NOTES:
1. This data is loaded consecutively A, B, C.
2. Data is shifted out when SO makes a HIGH to LOW transition.
Figure 5. Output TIming
(7)
(2)
SO
(4)
(1)
OR
(5)
(3)
(6)
A or B
OUTPUT DATA
A- DATA
B- DATA
2747 drw 10
NOTES:
1. OR HIGH indicates that data is available and a SO pulse may be applied.
2. SO goes HIGH causing the next step.
3. OR goes LOW.
4. The read pointer is incremented.
5. OR goes HIGH indicating that new data (B) is now available at the FIFO outputs.
6. If the FIFO has only one word loaded (A DATA) then OR stays LOW and the A DATA remains unchanged at the outputs.
7. SO pulses applied when OR is LOW will be ignored.
Figure 6. The Mechanism of Shifting Data Out of the FIFO
6
MILITARY AND COMMERCIAL
TEMPERATURE RANGES
IDT72401/72403
CMOS PARALLEL FIFO 64 x 4, 64 x 5
SI
SO
tOPH
tPT
OR
(1)
tSOR
DATA VALID
DATA OUTPUT
2747 drw 11
NOTE:
1. FIFO initially empty.
Figure 7. tPT and tOPH Specification
tMRW
MR
tMRIRH
IR
(1)
tMRORL
(1)
OR
tMRS
SI
tMRQ
DATA OUTPUT
2747 drw 12
NOTE:
1. Worst case, FIFO initially full.
Figure 8. Master Reset Timing
OE
tHZOE
tOOE
DATA OUT
2747 drw 13
NOTE:
1. High-Z transitions are referenced to the steady-state V OH –500mV and VOL +500mV levels on the output. tHZOE is tested with 5pF load capacitance instead of 30pF as
shown in Figure 1.
Figure 9. Output Enable Timing, IDT72403 Only
SHIFT IN
INPUT READY
DATA IN
SI
IR
D0
D1
D2
D3
MR
OR
SO
Q0
Q1
Q2
Q3
SI
IR
D0
D1
D2
D3
MR
OR
SO
Q0
Q1
Q2
Q3
OUTPUT READY
SHIFT OUT
DATA OUT
2747 drw 14
MR
NOTE:
1. FIFOs can be easily cascaded to any desired path. The handshaking and associated timing between the FIFOs are handled by the inherent timing of the devices.
Figure 10. 128 x 4 Depth Expansion
7
IDT72401/72403
CMOS PARALLEL FIFO 64 x 4, 64 x 5
IR
SI
D0
D1
D2
D3
COMPOSITE
INPUT
READY
SHIFT IN
IR
SI
D0
D1
D2
D3
IR
SI
D0
D1
D2
D3
MILITARY AND COMMERCIAL
TEMPERATURE RANGES
MR
MR
MR
SO
OR
Q0
Q1
Q2
Q3
IR
SI
D0
D1
D2
D3
SO
OR
Q0
Q1
Q2
Q3
IR
SI
D0
D1
D2
D3
SO
OR
Q0
Q1
Q2
Q3
IR
SI
D0
D1
D2
D3
MR
MR
MR
SO
OR
Q0
Q1
Q2
Q3
IR
SI
D0
D1
D2
D3
SO
OR
Q0
Q1
Q2
Q3
IR
SI
D0
D1
D2
D3
SO
OR
Q0
Q1
Q2
Q3
IR
SI
D0
D1
D2
D3
MR
MR
MR
SO
OR
Q0
Q1
Q2
Q3
SO
OR
Q0
Q1
Q2
Q3
SHIFT OUT
COMPOSITE
OUTPUT
READY
SO
OR
Q0
Q1
Q2
Q3
MR
2747 drw 15
NOTES:
1. When the memory is empty, the last word will remain on the outputs until the MR is strobed or a new data word falls through to the output. However, OR will remain LOW,
indicating data at the output is not valid.
2. When the output data changes as a result of a pulse on SO, the OR signal always goes LOW before there is any change in output data and stays LOW until the new data
has appeared on the outputs. Anytime OR is HIGH, there is valid stable data on the outputs.
3. If SO is held HIGH while the memory is empty and a word is written into the input, that word will appear at the output after a fall-through time. OR will go HIGH for one
internal cycle (at least tORL) and then go back LOW again. The stored word will remain on the outputs. If more words are written into the FIFO, they will line up behind the
first word and will not appear on the outputs until SO has been brought LOW.
4. When the MR is brought LOW, the outputs are cleared to LOW, IR goes HIGH and OR goes LOW. If SI is HIGH when the MR goes HIGH, the data on the inputs will be
written into the memory and IR will return to the LOW state until SI is brought LOW. If SI is LOW when the MR is ended, IR will go HIGH, but the data in the inputs will not
enter the memory until SI goes HIGH.
5. FIFOs are expandable on depth and width. However, in forming wider words, two external gates are required to generate composite Input and OR flags. This is due to the
variation of delays of the FIFOs.
Figure 11. 192 x 12 Depth and Width Expansion
8
ORDERING INFORMATION
IDT
XXXXX
X
X
X
X
Device Type
Power
Speed
Package
Process/
Temperature
Range
NOTE:
1. Industrial temperature range is available by special order.
Blank
B
Commercial (0°C to+70°C)
Military (-55°C to+125°C)
Compliant to MIL-STD-883, Class B
P
D
SO
Plastic DIP
300 mil, P16-1
CERDIP
300 mil, D16-1
Small Outline IC SOIC, SO16-1
45
35
25
15
10
Commercial Only
Commercial and Military
Commercial and Military>72401 only
Commercial and Military>72401 only
Commercial and Military
L
Low Power
72401
72403
64 x 4 FIFO
64 x 4 FIFO
Shift Frequency (fs)
Speed in MHz
2747 drw 16
DATASHEET DOCUMENT HISTORY
07/10/2003 pgs. 2, 3, and 9.
10/27/2005 pgs. 1- 9.
CORPORATE HEADQUARTERS
6024 Silver Creek Valley Road
San Jose, CA 95138
for SALES:
800-345-7015 or 408-284-8200
fax: 408-284-2775
www.idt.com
9
for Tech Support:
408-360-1753
email: [email protected]
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