Holtek HT66FB60 Enhanced a/d flash type 8-bit mcu Datasheet

HT66FB30/HT66FB40/HT66FB50/HT66FB60
Enhanced A/D Flash Type 8-Bit MCU
with EEPROM & USB Interface
Features
MCU Features
· Watchdog Timer function
· Operating voltage:
· Up to 39 bidirectional I/O lines
· Software controlled 4-SCOM lines LCD driver with
fSYS= 8MHz at 2.2V~5.5V
fSYS= 12MHz at 2.7V~5.5V
fSYS= 20MHz at 4.5V~5.5V
1/2 bias
· Multiple pin-shared external interrupts
· Up to 0.2ms instruction cycle with 20MHz system
· Multiple Timer Module for time measure, input
clock at VDD=5V
capture, compare match output, PWM output or
single pulse output functions
· Power down and wake-up functions to reduce
power consumption
2
· Serial Interface Module -- SIM for SPI or I C
· Five oscillators
- External High Speed Xtal
- External 32.768kHz Xtal
- External RC
- Internal High Speed -- no ext. components
- Internal 32kHz -- no ext. components
· Dual Comparator functions
· Multi-mode operation: NORMAL, SLOW, IDLE and
· Low voltage detect function
· Dual Time-Base functions for generation of fixed
time interrupt signal
· Multi-channel 12-bit resolution A/D converter
· Low voltage reset function
SLEEP
SPI to USB chip Features
· Fully integrated internal 4MHz, 8MHz and 12MHz
· Fully compliant with USB 2.0 Full-Speed
oscillator requires no external components
specification
· All instructions executed in one or two instruction
· 6 endpoints (including endpoint 0)
cycles
· FIFO: 8, 8, 8, 64, 8, 64 for endpoint 0 ~ endpoint 5
· Table read instructions
respectively
· 63 powerful instructions
· Suspend Mode and Remote Wake-up function
· Up to 8 subroutine nesting levels
· Bit manipulation instruction
· Multiple USB interrupt generation sources: endpoint
MCU Peripheral Features
· CMOS clock input with frequency of 6MHz/12MHz
access, suspend, resume and reset signals
for the USB PLL clock
· Flash Program Memory: 1K´14 ~ 12K´16
· RAM Data Memory: 64´8 ~ 576´8
· EEPROM Memory: 32´8 ~ 256´8
Rev. 1.30
1
December 12, 2012
HT66FB30/HT66FB40/HT66FB50/HT66FB60
General Description
A full choice of HXT, LXT, ERC, HIRC and LIRC oscillator functions are provided including a fully integrated
system oscillator which requires no external components for its implementation. The ability to operate and
switch dynamically between a range of operating modes
using different clock sources gives users the ability to
optimise microcontroller operation and minimize power
consumption.
The HT66FBx0 series of devices are Flash Memory A/D
type 8-bit high performance RISC architecture
microcontrollers with a USB interface. Offering users
the convenience of Flash Memory multi-programming
features, these devices also include a wide range of
functions and features. Other memory includes an area
of RAM Data Memory as well as an area of EEPROM
memory for storage of non-volatile data such as serial
numbers, calibration data etc.
The device contains a single USB Full-speed interface
to allow data communication with an external USB host
controller. It is particularly suitable for applications which
require data communication between PCs and peripheral USB hardware.
Analog features include a multi-channel 12-bit A/D converter and dual comparator functions. Multiple and extremely flexible Timer Modules provide timing, pulse
generation and PWM generation functions. Communication with the outside world is catered for by including
2
fully integrated SPI or I C interface functions, two popular interfaces which provide designers with a means of
easy communication with external peripheral hardware.
Protective features such as an internal Watchdog Timer,
Low Voltage Reset and Low Voltage Detector coupled
with excellent noise immunity and ESD protection ensure that reliable operation is maintained in hostile electrical environments.
An extensive choice of oscillator functions is provided
including a fully integrated system oscillator which requires no external components for its implementation.
The ability to operate and switch dynamically between a
range of operating modes using different clock sources
gives users the ability to optimise microcontroller operation and minimise power consumption. The devices also
include flexible I/O programming features, Time-Base
functions and a range of other features.
Selection Guide
Most features are common to all devices, the main feature distinguishing them are Memory capacity, A/D Converter,
Timer Module types and stack capacity. The following table summarises the main features of each device.
Part No.
VDD
Program
Memory
Data
Memory
Data
EEPROM
I/O
Ext.
Int.
Timer
Module
Interface
(SPI/I2C)
USB
Stack
Package
HT66FB30
2.2V~
5.5V
2K´14
96´8
64´8
16
2
10-bit CTM´1,
10-bit ETM´1
Ö
Ö
4
28SKDIP/SOP/SSOP
HT66FB40
2.2V~
5.5V
4K´15
192´8
128´8
33
2
10-bit CTM´1,
10-bit ETM´1,
10-bit STM´1
Ö
Ö
8
44LQFP, 48QFN
HT66FB50
2.2V~
5.5V
8K´16
384´8
256´8
34
2
10-bit CTM´2,
10-bit ETM´1,
10-bit STM´1
Ö
Ö
8
44LQFP, 48QFN
HT66FB60
2.2V~
5.5V
12K´16
576´8
256´8
39
4
10-bit CTM´2,
10-bit ETM´1,
10-bit STM´1
Ö
Ö
8
40/48QFN,
44/48LQFP, 52QFP
Note:
As devices exist in more than one package format, the table reflects the situation for the package with the most
pins.
Rev. 1.30
2
December 12, 2012
HT66FB30/HT66FB40/HT66FB50/HT66FB60
Block Diagram
The following block diagram illustrates the dual-chip structure of the devices, where an individual MCU and SPI to USB
chips are combined into a single package.
V D D
V D D
V D D
I/O
p o rts
S C K
S C K
T M
p in s
S D O
S D I
IN T p in s
A n a lo g in p u ts
S C O M
p in s
O S C
p in s
R E S
H T 6 6 F x 0
S C S
S C S
P IN T
IN T
P C K
C L K I
V S S
V S S U
V D D
V D D U
V D D
V D D
S C K
S C K
T M
p in s
S D O
S D I
IN T p in s
p in s
O S C
p in s
R E S
H T 6 6 F x 0
V 3 3 O
S D O
S D I
S C S
S C S
P IN T
IN T
P C K
C L K I
U D P
U D N
V S S
p o rts
S C O M
H T 4 5 B 0 K
V S S
I/O
A n a lo g in p u ts
V 3 3 O
S D O
S D I
H T 4 5 B 0 K
U D P
U D N
V S S
V S S
V S S
V S S U
Internal Chip Interconnection Diagram
Note:
The ground pins of the internal chips are NOT connected together. On some devices the positive power supply
pins are connected together and on some they remain independent.
Rev. 1.30
3
December 12, 2012
HT66FB30/HT66FB40/HT66FB50/HT66FB60
L o w
V o lta g e
D e te c t
W a tc h d o g
T im e r
R e s e t
C ir c u it
L o w
V o lta g e
R e s e t
F la s h /E E P R O M
P r o g r a m m in g
C ir c u itr y
In te rru p t
C o n tr o lle r
8 - b it
R IS C
M C U
C o re
E x te rn a l
R C /X ta l
O s c illa to r s
3 2 7 6 8 H z
O s c illa to r
S ta c k
In te rn a l R C
O s c illa to r s
F la s h
P ro g ra m
M e m o ry
E E P R O M
D a ta
M e m o ry
R A M
D a ta
M e m o ry
T im e B a s e
1 2 - B it A /D
C o n v e rte r
C o m p a ra to rs
T im e r
M o d u le s
U S B
M o d u le
I/O
Pin Assignment
P A 1 /T P 1 A /A N 1
1
2 8
P A 2 /T C K 0 /C 0 + /A N 2
P A 0 /C 0 X /T P 0 _ 0 /A N 0
2
2 7
P A 3 /IN T 0 /C 0 -/A N 3
V S S & A V S S
3
2 6
P A 4 /IN T 1 /T C K 1 /A N 4
P B 4 /X T 2
4
2 5
P A 5 /C 1 X /S D O /A N 5
P B 3 /X T 1
5
2 4
P A 6 /S D I/S D A /A N 6
P B 2 /O S C 2
6
2 3
P A 7 /S C K /S C L /A N 7
P B 1 /O S C 1
7
2 2
P B 5 /S C S /V R E F
V D D & A V D D & V D D U
8
2 1
P C 2 /P C K /C 1 +
P B 0 /R E S
9
2 0
P C 3 /P IN T /C 1 -
N C
1 0
1 9
V S S U
N C
1 1
1 8
U D N
N C
1 2
1 7
U D P
N C
1 3
1 6
V 3 3 O
N C
1 4
1 5
N C
N
R E
/A N
/A N
/A N
/A N
/A N
/A N
/A N
/A N
N
P F 1 /[C 1
P B 5 /S C S /V
P A 7 /S C K /S C L
P A 6 /S D I/S D A
P A 5 /C 1 X /S D O
P A 4 /IN T 1 /T C K 1
P A 3 /IN T 0 /C 0 P A 2 /T C K 0 /C 0 +
P A 1 /T P 1 A
P A 0 /C 0 X /T P 0 _ 0
C
4 8 4 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 3 9 3 8 3 7
1
F
2
3
3 4
4
3 3
5
4
3
1
3 5
7
6
0
2
C
X ]
3 6
5
3 2
6
3 1
H T 6 6 F B 4 0
4 8 Q F N -A
7
8
3 0
2 9
9
2 8
1 0
2 7
1 1
1 2
2 6
1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4
2 5
N C
P D
P D
P E
P E
P E
P E
P C
P C
P B 5 /S C S /V R
P A 7 /S C K /S C L /A
P A 6 /S D I/S D A /A
P A 5 /C 1 X /S D O /A
P A 4 /IN T 1 /T C K 1 /A
P A 3 /IN T 0 /C 0 -/A
P A 2 /T C K 0 /C 0 + /A
P A 1 /T P 1 A /A
P A 0 /C 0 X /T P 0 _ 0 /A
P F 1 /[C
P F 0 /[C
0
4 /[T P 2 _ 1 ]
5 /[T P 0 _ 1 ]
1
3
2
6 /[T P 0 _ 0 ]/S C O M 2
7 /[T P 1 A ]/S C O M 3
N C
P C 0 /T P 1 B _ 0 /S C O M 0
P C 1 /T P 1 B _ 1 /S C O M 1
4 4 4 3 4 2 4 1 4 0 3 9 3 8 3 7 3 6 3 5 3 4
E F
N 7
N 6
N 5
N 4
N 3
N 2
N 1
N 0
1 X ]
0 X ]
1
2
3 3
3 2
3
3 1
4
3 0
5
2 9
H T 6 6 F B 4 0
4 4 L Q F P -A
6
7
2 8
2 7
8
2 6
9
2 5
1 0
1 1
2 4
1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2
2 3
N C
P D
P D
P E
P E
P E
P E
P C
P C
P C
P C
4 /[T P 2 _ 1 ]
5 /[T P 0 _ 1 ]
0
1
3
2
6 /[T
7 /[T
0 /T
1 /T
P 0 _
P 1 A
P 1 B
P 1 B
0 ]/S
]/S C
_ 0 /S
_ 1 /S
C O
O M
C O
C O
M 2
3
M 0
M 1
P E 4
P E 5
P B 0
V D D
P B 1
P B 2
P B 3
P B 4
V S S
P E 6
P E 7
/[T P 1 B _ 2 ]
& V D D U
& V D D U
/[T P 1 B _ 2 ]
/R E S
& A V D D
/O S C 1
/O S C 2
/X T 1
/X T 2
& A V S S
/[IN T 0 ]
/[IN T 1 ]
/[C 0 X ]
/R E S
& A V D D
/O S C 1
/O S C 2
/X T 1
/X T 2
& A V S S
/[IN T 0 ]
/[IN T 1 ]
P E 4
P E 5
P B 0
V D D
P B 1
P B 2
P B 3
P B 4
V S S
P E 6
P E 7
P F 0
Rev. 1.30
N C
N C
N C
N C
N C
V 3 3 O
U D P
U D N
V S S U
P B 7 /[S D I/S D A ]
P B 6 /[S D O ]
N C
N C
N C
N C
N C
V 3 3 O
U D P
U D N
V S S U
P D 6 /[S C K /S C L ]
P B 7 /[S D I/S D A ]
P B 6 /[S D O ]
H T 6 6 F B 3 0
2 8 S K D IP -A /S O P -A /S S O P -A
4
December 12, 2012
HT66FB30/HT66FB40/HT66FB50/HT66FB60
N C
N C
N C
N C
N C
V 3 3 O
U D P
U D N
V S S U
P B 7 /[S D I/S D A ]
P B 6 /[S D O ]
N
N
N
N
N
V 3 3
U D
U D
V S S
P D 7 /[S C
P D 6 /[S C K /S C
P B 7 /[S D I/S D
C
C
C
C
C
O
P
N
U
S ]
L ]
A ]
P B 6 /[S D
P B 5 /S C S /V R
P A 7 /S C K /S C L /A
P A 6 /S D I/S D A /A
P A 5 /C 1 X /S D O /A
P A 4 /IN T 1 /T C K 1 /A
P A 3 /IN T 0 /C 0 -/A
P A 2 /T C K 0 /C 0 + /A
P A 1 /T P 1 A /A
P A 0 /C 0 X /T P 0 _ 0 /A
O ]
E F
N 7
N 6
N 5
N 4
N 3
N 2
N 1
N 0
N C
P F 1 /[C 1 X ]
4 8 4 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 3 9 3 8 3 7
1
2
N C
P D
P D
P E
P E
P E
P E
P C
P C
3 6
3 5
3
3 4
4
3 3
5
3 2
6
3 1
H T 6 6 F B 5 0
4 8 Q F N -A
7
8
3 0
2 9
9
1 0
2 8
1 2
2 6
2
3 /[T P 3 _ 1 ]
6 /[T P 0 _ 0 ]/S C O M 2
7 /[T P 1 A ]/S C O M 3
2 5
P B 5 /S C S /V R
P A 7 /S C K /S C L /A
P A 6 /S D I/S D A /A
P A 5 /C 1 X /S D O /A
P A 4 /IN T 1 /T C K 1 /A
P A 3 /IN T 0 /C 0 -/A
P A 2 /T C K 0 /C 0 + /A
P A 1 /T P 1 A /A
P A 0 /C 0 X /T P 0 _ 0 /A
P F 1 /[C
P F 0 /[C
E F
N 7
N 6
N 5
N 4
N 3
N 2
N 1
N 0
1 X ]
0 X ]
P B 5 /S C S /V R
P A 7 /S C K /S C L /A
P A 6 /S D I/S D A /A
P A 5 /C 1 X /S D O /A
P A 4 /IN T 1 /T C K 1 /A
P A 3 /IN T 0 /C 0 -/A
P A 2 /T C K 0 /C 0 + /A
P A 1 /T P 1 A /A
P A 0 /C 0 X /T P 0 _ 0 /A
P F 1 /[C 1 X ]/A N
P F 0 /[C 0 X ]/A N
E F
N 7
N 6
4 4 4 3 4 2 4 1 4 0 3 9 3 8 3 7 3 6 3 5 3 4
1
2
3 3
3 2
3
3 1
4
3 0
5
2 9
H T 6 6 F B 5 0
4 4 L Q F P -A
6
7
2 8
2 7
8
2 6
9
2 5
1 0
1 1
2 4
1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2
2 3
N C
P D
P D
P E
P E
P E
P E
P C
P C
P C
P C
4 /[T P
5 /[T P
0 /[IN
1 /[IN
2 /[IN
3 /[T P
6 /[T P
7 /[T P
0 /T P
1 /T P
2 _ 1 ]
0 _ 1 ]
T 0 ]
T 1 ]
T 2 ]
3 _ 1 ]
0 _ 0 ]/S
1 A ]/S C
1 B _ 0 /S
1 B _ 1 /S
C O
O M
C O
C O
M 2
3
M 0
M 1
N C
P D
P D
P E
P E
P E
P E
P C
P C
P C
P C
4 /[T P
5 /[T P
0 /[IN
1 /[IN
2 /[IN
3 /[T P
6 /[T P
7 /[T P
0 /T P
1 /T P
2 _ 1 ]
0 _ 1 ]
T 0 ]
T 1 ]
T 2 ]
3 _ 1 ]
0 _ 0 ]/S
1 A ]/S C
1 B _ 0 /S
1 B _ 1 /S
C O
O M
C O
C O
M 2
3
M 0
M 1
P E 4
P E 5
P B 0
V D D
P B 1
P B 2
P B 3
P B 4
V S S
P E 6
P E 7
1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4
1
N C
P C 0 /T P 1 B _ 0 /S C O M 0
P C 1 /T P 1 B _ 1 /S C O M 1
2 7
1 1
0
4 /[T P 2 _ 1 ]
5 /[T P 0 _ 1 ]
/[T P 1 B _ 2 ]
/[T P 3 _ 0 ]
/R E S
& A V D D & V D D U
/O S C 1
/O S C 2
/X T 1
/X T 2
& A V S S
/[IN T 0 ]
/[IN T 1 ]
/[C 0 X ]
/[T P 1 B _ 2 ]
/[T P 3 _ 0 ]
/R E S
& A V D D & V D D U
/O S C 1
/O S C 2
/X T 1
/X T 2
& A V S S
/[IN T 0 ]
/[IN T 1 ]
P E 4
P E 5
P B 0
V D D
P B 1
P B 2
P B 3
P B 4
V S S
P E 6
P E 7
P F 0
V 3
U
U
V D
V S
P B 6 /[S D
N C
N C
N C
N C
N C
3 O
D P
D N
D U
S U
O ]
N
N
N
N
N
V 3 3
U D
U D
N
V S S
O
U
C
C
C
C
C
N
C
P
V D
P A 7 /S C K /S C L /A
P A 6 /S D I/S D A /A
P A 5 /C 1 X /S D O /A
P A 4 /IN T 1 /T C K 1 /A
P A 3 /IN T 0 /C 0 -/A
P A 2 /T C K 0 /C 0 + /A
P A 1 /T P 1 A /A
P A 0 /C 0 X /T P 0 _ 0 /A
P F 1 /[C 1 X ]/A N
D U
N 7
N 6
N 5
N 4
N 3
N 2
N 1
N 0
1 1
4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 3 3 2 3 1
1
2
N C
P D
P D
P E
P G
P C
P C
P C
P C
P E
3 0
2 9
2 8
3
4
2 7
5
H T 6 6 F B 6 0
4 0 Q F N -A
6
7
2 6
2 5
2 4
8
2 3
2 2
9
1 0
1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0
2 1
4 /[T P 2 _ 1 ]
5 /[T P 0 _ 1 ]
0 /[IN T 0 ]
1 /[C 1 X ]
6 /[T P 0 _ 0 ]/S
7 /[T P 1 A ]/S C
0 /T P 1 B _ 0 /S
1 /T P 1 B _ 1 /S
4 /[T P 1 B _ 2 ]
C O
O M
C O
C O
M 2
3
M 0
M 1
2
N 5
N 4
N 3
N 2
N 1
N 0
1 1
1 0
5
7
5
3 2
6
3
H T 6 6 F B 6 0
4 8 L Q F P -A /Q F N -A
2
1
0
7
8
3 0
2 8
1 0
2 7
1 1
1 2
3 1
2 9
9
2 6
2 5
N C
P D
P D
P E
P E
P E
P E
P C
P C
4 /[T
5 /[T
0 /[IN
1 /[IN
2 /[IN
3 /[T
6 /[T
7 /[T
P F 3
P F 2
P B 5 /S C S /V R E F
P A 7 /S C K /S C L /A N 7
P A 6 /S D I/S D A /A N 6
P A 5 /C 1 X /S D O /A N 5
P A 4 /IN T 1 /T C K 1 /A N 4
P A 3 /IN T 0 /C 0 -/A N 3
P A 2 /T C K 0 /C 0 + /A N 2
P A 1 /T P 1 A /A N 1
P A 0 /C 0 X /T P 0 _ 0 /A N 0
P F 1 /[C 1 X ]/A N 1 1
P F 0 /[C 0 X ]/A N 1 0
P 2 _ 1 ]
P 0 _ 1 ]
T 0 ]
T 1 ]
T 2 ]
P 3 _ 1 ]
P 0 _ 0 ]/S C O M 2
P 1 A ]/S C O M 3
N C
P C 0 /T P 1 B _ 0 /S C O M 0
P C 1 /T P 1 B _ 1 /S C O M 1
1 1
2 4
1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2
2 3
5 2 5 1 5 0 4 9 4 8 4 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0
1
3 9
2
3 8
3
3 7
3 6
4
5
3 5
6
H T 6 6 F B 6 0
5 2 Q F P -A
7
8
9
1 0
1 1
1 2
1 3
1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6
3 4
3 3
3 2
3 1
3 0
2 9
2 8
2 7
N C
P D
P D
P E
P E
P E
P E
P F
P F
P G
P G
P C
P C
7
6
4 /[T
5 /[T
0 /[IN
1 /[IN
2 /[IN
3 /[T
P 2 _ 1 ]
P 0 _ 1 ]
T 0 ]
T 1 ]
T 2 ]
P 3 _ 1 ]
0 /[C
1 /[C
6 /[T
7 /[T
0 X
1 X
P 0
P 1
]
]
_ 0 ]/S C O M 2
A ]/S C O M 3
/S C O M 0
/S C O M 1
]
N 8
N 9
/[T P 1 B _ 2 ]
/[T P 3 _ 0 ]
/R E S
& A V D D
/O S C 1
/O S C 2
/X T 1
/X T 2
& A V S S
/[IN T 0 ]/A N 8
/[IN T 1 ]/A N 9
/[C 0 X ]/A N 1 0
/T P 1 B _ 0
/T P 1 B _ 1
/[T P 1 B _ 2
/[T P 3 _ 0 ]
/R E S
& A V D D
/O S C 1
/O S C 2
/X T 1
/X T 2
& A V S S
/[IN T 0 ]/A
/[IN T 1 ]/A
P E 4
P E 5
P B 0
V D D
P B 1
P B 2
P B 3
P B 4
V S S
P E 6
P E 7
P F 0
Note:
2 5
P C 0
P C 1
P E 4
P E 5
P B 0
V D D
P B 1
P B 2
P B 3
P B 4
V S S
P E 6
P E 7
1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4
2 6
1 0
N C
N C
N C
N C
N C
3 O
D P
D N
D U
S U
O ]
F 5
3 3
5
2 7
9
F 4
C
1
3 4
4
2 8
8
V 3
U
U
V D
V S
P B 6 /[S D
P
P
3
4
3 6
3 5
7
2 9
H T 6 6 F B 6 0
4 4 L Q F P -A
6
/[T P 1 B _ 2 ]
/[T P 3 _ 0 ]
/R E S
& A V D D
/O S C 1
/O S C 2
/X T 1
/X T 2
& A V S S
/[IN T 0 ]/A N 8
/[IN T 1 ]/A N 9
6
2
3 0
P E 4
P E 5
P B 0
V D D
P B 1
P B 2
P B 3
P B 4
V S S
P E 6
P E 7
N C
N C
N C
N C
N C
V 3 3 O
U D P
U D N
V D D U
V S S U
P B 7 /[S D I/S D A ]
P B 6 /[S D O ]
1
F
3 1
4
/R E S
& A V D D
/O S C 1
/O S C 2
/X T 1
/X T 2
& A V S S
/[IN T 0 ]/A N 8
/[IN T 1 ]/A N 9
/[C 0 X ]/A N 1 0
C
3 3
3 2
3
P B 0
V D D
P B 1
P B 2
P B 3
P B 4
V S S
P E 6
P E 7
P F 0
N
R E
/A N
/A N
/A N
/A N
/A N
/A N
/A N
/A N
N
P F 1 /[C 1 X ]/A N 1
P B 5 /S C S /V
P A 7 /S C K /S C L
P A 6 /S D I/S D A
P A 5 /C 1 X /S D O
P A 4 /IN T 1 /T C K 1
P A 3 /IN T 0 /C 0 P A 2 /T C K 0 /C 0 +
P A 1 /T P 1 A
P A 0 /C 0 X /T P 0 _ 0
4 8 4 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 3 9 3 8 3 7
4 4 4 3 4 2 4 1 4 0 3 9 3 8 3 7 3 6 3 5 3 4
1
1. Bracketed pin names indicate non-default pinout remapping locations.
2. For pin-shared pin functions, pin names to the right side of the ²/² sign have higher priority.
3. VDD & AVDD & VDDU means the VDD, AVDD and VDDU pins are bonded together.
Rev. 1.30
5
December 12, 2012
HT66FB30/HT66FB40/HT66FB50/HT66FB60
Pin Description
With the exception of the power pins, all pins on these devices can be referenced by their Port name, e.g. PA.0, PA.1
etc, which refer to the digital I/O function of the pins. However these Port pins are also shared with other function such
as the Analog to Digital Converter, Serial Port pins, etc. The function of each pin is listed in the following tables, however the details behind how each pin is configured is contained in individual MCU and SPI to USB chip datasheet. The
important point to note here is that some I/O lines are not bonded to the external pins. Users should take special care of
these I/O port lines. Refer to the Hardware Considerations section for more details.
HT66FB30
Pin Name
Function
OP
I/T
O/T
Pin-Shared Mapping
PA0~PA7
Port A
PAWU
PAPU
ST
CMOS
¾
PB0~PB5
Port B
PBPU
ST
CMOS
¾
PC2~PC3
Port C
PCPU
ST
CMOS
¾
AN0~AN7
A/D converter input
ACERL
AN
¾
PA0~PA7
VREF
A/D converter reference input
ADCR1
AN
¾
PB5
C0-, C1-
Comparator 0, 1 input
AN
¾
PA3, PC3
AN
¾
PA2, PC2
¾
CMOS
PA0, PA5
¾
ST
¾
PA2, PA4
C0+, C1+
Comparator 0, 1 input
C0X, C1X
Comparator 0, 1 output
CP0C
CP1C
TCK0, TCK1 TM0, TM1 input
TP0_0
TM0 I/O
TMPC0
ST
CMOS
PA0
TP1A
TM1 I/O
TMPC0
ST
CMOS
PA1
INT0, INT1
External interrupt 0, 1
¾
ST
¾
PA3, PA4
PINT
Peripheral Interrupt ***
PRM0
ST
¾
PC3 or PC4
PCK
Peripheral Clock Output ***
PRM0
¾
CMOS
PC2 or PC5
SDI
SPI data input ***
PRM0
ST
¾
PA6 or PC0
SDO
SPI data output ***
PRM0
¾
CMOS
PA5 or PC1
SCS
SPI slave select ***
PRM0
ST
CMOS
PB5 or PC6
SCK
SPI serial clock ***
PRM0
ST
CMOS
PA7 or PC7
PRM0
ST
NMOS
PA7
PRM0
ST
NMOS
PA6
SCL
2
I C clock
2
SDA
I C data
OSC1
HXT/ERC pin
CO
HXT
¾
PB1
OSC2
HXT pin
CO
¾
HXT
PB2
XT1
LXT pin
CO
LXT
¾
PB3
XT2
LXT pin
CO
¾
LXT
PB4
RES
Reset input
CO
ST
¾
PB0
VDD
MCU power supply *
¾
PWR
¾
¾
AVDD
A/D converter power supply *
¾
PWR
¾
¾
VSS
MCU ground **
¾
PWR
¾
¾
AVSS
A/D converter ground **
¾
PWR
¾
¾
UDP
USB D+ pin
¾
ST
CMOS
¾
UDN
USB D- pin
¾
ST
CMOS
¾
Rev. 1.30
6
December 12, 2012
HT66FB30/HT66FB40/HT66FB50/HT66FB60
Pin Name
Function
OP
I/T
O/T
V33O
3.3V regulator output pin
¾
¾
¾
¾
VDDU
USB power supply
¾
PWR
¾
¾
VSSU
USB ground
¾
PWR
¾
¾
NC
Not connected, can not be used
¾
¾
¾
¾
Note:
Pin-Shared Mapping
I/T: Input type; O/T: Output type
OP: Optional by configuration option (CO) or register option
PWR: Power; CO: Configuration option; ST: Schmitt Trigger input
CMOS: CMOS output; NMOS: NMOS output
AN: Analog input pin
HXT: High frequency crystal oscillator
LXT: Low frequency crystal oscillator
*: VDD is the device power supply while AVDD and VDDU are the ADC and USB power supply respectively.
The AVDD and VDDU pins are bonded together internally with VDD.
**: VSS is the device ground pin while AVSS is the ADC ground pin. The AVSS pin is bonded together internally
with VSS.
***: When the PINT, PCK and SPI functions are pin-shared remapping to PC4~PC5, PC0~PC1 and PC6~PC7
pins, the SPI pins are to be used as the master SPI signal to communicate with the slave SPI in HT45B0K
along with the PINT and PCK pins used as the interrupt input and clock output connected to the SPI to USB
chip to control the overall USB functions.
HT66FB40
Pin Name
Function
OP
I/T
O/T
Pin-Shared Mapping
PA0~PA7
Port A
PAWU
PAPU
ST
CMOS
¾
PB0~PB7
Port B
PBPU
ST
CMOS
¾
PC0~PC1,
PC6~PC7
Port C
PCPU
ST
CMOS
¾
PD4~PD6
Port D
PDPU
ST
CMOS
¾
PE0~PE7
Port E
PEPU
ST
CMOS
¾
PF0~PF1
Port F
PFPU
ST
CMOS
¾
AN0~AN7
A/D converter input
ACERL
AN
¾
PA0~PA7
VREF
A/D converter reference input
ADCR1
AN
¾
PB5
C0-
Comparator 0 input
AN
¾
PA3
AN
¾
PA2
CP0C
CP1C
PRM0
¾
CMOS
CP0C
C0+
Comparator 0 input
C0X, C1X
Comparator 0, 1 output
PA0, PA5 or PF0, ¾
PRM1
ST
¾
TM0 I/O
TMPC0
PRM2
ST
CMOS
PA0, ¾, or PC6, PD5
TP1A
TM1 I/O
TMPC0
PRM2
ST
CMOS
PA1 or PC7
TP1B_0~
TP1B_2
TM1 I/O
TMPC0
PRM2
ST
CMOS
TCK0, TCK1 TM0, TM1 input
TP0_0,
TP0_1
Rev. 1.30
7
PA2, PA4, ¾
PC0, PC1, ¾ or
¾, ¾, PE4
December 12, 2012
HT66FB30/HT66FB40/HT66FB50/HT66FB60
Pin Name
Function
OP
I/T
O/T
Pin-Shared Mapping
TMPC1
PRM2
ST
CMOS
¾
PA3, PA4 or PE6, PE7
¾ or PC4
¾ or PD4
TP2_1
TM2 I/O
INT0, INT1
External interrupt 0, 1
PRM1
ST
PINT
Peripheral Interrupt ***
PRM0
ST
¾
PCK
Peripheral Clock Output ***
PRM0
¾
CMOS
SDI
SPI data input ***
PRM0
ST
¾
PA6 or PD2 or PB7
SDO
SPI data output ***
PRM0
¾
CMOS
PA5 or PD3 or PB6
SCS
SPI slave select ***
PRM0
ST
CMOS
PB5 or PD0 or PD7
SCK
SPI serial clock ***
PRM0
ST
CMOS
PA7 or PD1 or PD6
PRM0
ST
NMOS
PA7 or PD1 or PD6
PRM0
ST
NMOS
PA6 or PD2 or PB7
SCOMC
¾
SCOM
PC0, PC1, PC6, PC7
2
SCL
I C clock
2
¾ or PC5
SDA
I C data
SCOM0~
SCOM3
SCOM0~SCOM3
OSC1
HXT/ERC pin
CO
HXT
¾
PB1
OSC2
HXT pin
CO
¾
HXT
PB2
XT1
LXT pin
CO
LXT
¾
PB3
XT2
LXT pin
CO
¾
LXT
PB4
RES
Reset input
CO
ST
¾
PB0
VDD
MCU power supply *
¾
PWR
¾
¾
AVDD
A/D converter power supply *
¾
PWR
¾
¾
VSS
MCU ground **
¾
PWR
¾
¾
AVSS
A/D converter ground **
¾
PWR
¾
¾
UDP
USB D+ pin
¾
ST
CMOS
¾
UDN
USB D- pin
¾
ST
CMOS
¾
V33O
3.3V regulator output pin
¾
¾
¾
¾
VDDU
USB power supply
¾
PWR
¾
¾
VSSU
USB ground
¾
PWR
¾
¾
NC
Not connected, can not be used
¾
¾
¾
¾
Note:
I/T: Input type; O/T: Output type
OP: Optional by configuration option (CO) or register option
PWR: Power; CO: Configuration option; ST: Schmitt Trigger input
CMOS: CMOS output; NMOS: NMOS output
SCOM: Software controlled LCD COM; AN: Analog input pin
HXT: High frequency crystal oscillator
LXT: Low frequency crystal oscillator
*: VDD is the device power supply while AVDD and VDDU are the ADC and USB power supply respectively.
The AVDD and VDDU pins are bonded together internally with VDD.
**: VSS is the device ground pin while AVSS is the ADC ground pin. The AVSS pin is bonded together internally
with VSS.
***: When the PINT, PCK and SPI functions are pin-shared remapping to PC4~PC5 and PD0~PD3 pins, the
SPI pins are to be used as the master SPI signal to communicate with the slave SPI in HT45B0K along with the
PINT and PCK pins used as the interrupt input and clock output connected to the SPI to USB chip to control the
overall USB functions.
Rev. 1.30
8
December 12, 2012
HT66FB30/HT66FB40/HT66FB50/HT66FB60
HT66FB50
Pin Name
Function
OP
I/T
O/T
Pin-Shared Mapping
PA0~PA7
Port A
PAWU
PAPU
ST
CMOS
¾
PB0~PB7
Port B
PBPU
ST
CMOS
¾
PC0~PC1,
PC6~PC7
Port C
PCPU
ST
CMOS
¾
PD4~PD7
Port D
PDPU
ST
CMOS
¾
PE0~PE7
Port E
PEPU
ST
CMOS
¾
PF0~PF1
Port F
PFPU
ST
CMOS
¾
AN0~AN7
A/D converter input
ACERL
AN
¾
PA0~PA7
VREF
A/D converter reference input
ADCR1
AN
¾
PB5
C0-
Comparator 0 input
AN
¾
PA3
AN
¾
PA2
CP0C
CP1C
PRM0
¾
CMOS
PRM1
ST
¾
CP0C
C0+
Comparator 0 input
C0X, C1X
Comparator 0, 1 output
TCK0, TCK1 TM0, TM1 input
PA0, PA5 or PF0, PF1
PA2, PA4, ¾, ¾
TP0_0,
TP0_1
TM0 I/O
TMPC0
PRM2
ST
CMOS
PA0, ¾, or PC6, PD5
TP1A
TM1 I/O
TMPC0
PRM2
ST
CMOS
PA1 or PC7
TP1B_0~
TP1B_2
TM1 I/O
TMPC0
PRM2
ST
CMOS
TP2_1
TM2 I/O
TMPC1
PRM2
ST
CMOS
¾ or PD4
TP3_0,
TP3_1
TM3 I/O
TMPC1
PRM2
ST
CMOS
¾, ¾, or PE5, PE3
INT0, INT1
External interrupt 0, 1
PRM1
ST
¾
PA3, PA4 or PE6, PE7
PINT
Peripheral Interrupt ***
PRM0
ST
¾
¾ or PC4
PCK
Peripheral Clock Output ***
PRM0
¾
CMOS
¾ or PC5
SDI
SPI data input ***
PRM0
ST
¾
PA6 or PD2 or PB7
SDO
SPI data output ***
PRM0
¾
CMOS
PA5 or PD3 or PB6
SCS
SPI slave select ***
PRM0
ST
CMOS
PB5 or PD0 or PD7
SCK
SPI serial clock ***
PRM0
ST
CMOS
PA7 or PD1 or PD6
PRM0
ST
NMOS
PA7 or PD1 or PD6
PRM0
ST
NMOS
PA6 or PD2 or PB7
SCOMC
¾
SCOM
PC0, PC1, PC6, PC7
2
PC0, PC1, ¾ or
¾, ¾, PE4
SCL
I C clock
SDA
I C data
SCOM0~
SCOM3
SCOM0~SCOM3
OSC1
HXT/ERC pin
CO
HXT
¾
PB1
OSC2
HXT pin
CO
¾
HXT
PB2
XT1
LXT pin
CO
LXT
¾
PB3
XT2
LXT pin
CO
¾
LXT
PB4
Rev. 1.30
2
9
December 12, 2012
HT66FB30/HT66FB40/HT66FB50/HT66FB60
Pin Name
Function
OP
I/T
O/T
Pin-Shared Mapping
RES
Reset input
CO
ST
¾
PB0
VDD
MCU power supply *
¾
PWR
¾
¾
AVDD
A/D converter power supply *
¾
PWR
¾
¾
VSS
MCU ground **
¾
PWR
¾
¾
AVSS
A/D converter ground **
¾
PWR
¾
¾
UDP
USB D+ pin
¾
ST
CMOS
¾
UDN
USB D- pin
¾
ST
CMOS
¾
V33O
3.3V regulator output pin
¾
¾
¾
¾
VDDU
USB power supply
¾
PWR
¾
¾
VSSU
USB ground
¾
PWR
¾
¾
NC
Not connected, can not be used
¾
¾
¾
¾
Note:
I/T: Input type; O/T: Output type
OP: Optional by configuration option (CO) or register option
PWR: Power; CO: Configuration option; ST: Schmitt Trigger input
CMOS: CMOS output; NMOS: NMOS output
SCOM: Software controlled LCD COM; AN: Analog input pin
HXT: High frequency crystal oscillator
LXT: Low frequency crystal oscillator
*: VDD is the device power supply while AVDD and VDDU are the ADC and USB power supply respectively.
The AVDD and VDDU pins are bonded together internally with VDD.
**: VSS is the device ground pin while AVSS is the ADC ground pin. The AVSS pin is bonded together internally
with VSS.
***: When the PINT, PCK and SPI functions are pin-shared remapping to PC4~PC5 and PD0~PD3 pins, the
SPI pins are to be used as the master SPI signal to communicate with the slave SPI in HT45B0K along with the
PINT and PCK pins used as the interrupt input and clock output connected to the SPI to USB chip to control the
overall USB functions.
HT66FB60
Pin Name
Function
OP
I/T
O/T
Pin-Shared Mapping
PA0~PA7
Port A
PAWU
PAPU
ST
CMOS
¾
PB0~PB6
Port B
PBPU
ST
CMOS
¾
PC0~PC1,
PC6~PC7
Port C
PCPU
ST
CMOS
¾
PD4~PD5
Port D
PDPU
ST
CMOS
¾
PE0~PE7
Port E
PEPU
ST
CMOS
¾
PF0~PF7
Port F
PFPU
ST
CMOS
¾
PG0~PG1
Port G
PFPU
ST
CMOS
¾
AN0~AN11
A/D converter input
ACERL
ACERH
AN
¾
PA0~PA7, PE6~PE7,
PF0~PF1
VREF
A/D converter reference input
ADCR1
AN
¾
PB5
C0-
Comparator 0 input
AN
¾
PA3
AN
¾
PA2
CP0C
C0+
Rev. 1.30
Comparator 0 input
10
December 12, 2012
HT66FB30/HT66FB40/HT66FB50/HT66FB60
Pin Name
C0X, C1X
Function
Comparator 0, 1 output
OP
I/T
O/T
Pin-Shared Mapping
CP0C
CP1C
PRM0
¾
CMOS
PA0, PA5 or PF0, PF1
or PG0, PG1
PRM1
ST
¾
TM0 I/O
TMPC0
PRM2
ST
CMOS
PA0, ¾, or PC6, PD5
TP1A
TM1 I/O
TMPC0
PRM2
ST
CMOS
PA1 or PC7
TP1B_0~
TP1B_2
TM1 I/O
TMPC0
PRM2
ST
CMOS
TP2_1
TM2 I/O
TMPC1
PRM2
ST
CMOS
¾ or PD4
TP3_0,
TP3_1
TM3 I/O
TMPC1
PRM2
ST
CMOS
¾, ¾, or PE5, PE3
TCK0, TCK1 TM0, TM1 input
TP0_0,
TP0_1
INT0~INT2
External interrupt 0~2
PRM1
ST
PA2, PA4, ¾, ¾
PC0, PC1, ¾ or
¾, ¾, PE4
¾
PA3, PA4, ¾ or
¾, ¾, PE2,
PE0, PE1, ¾, or
PE6, PE7, ¾
¾ or PC4
PINT
Peripheral Interrupt ***
PRM0
ST
¾
PCK
Peripheral Clock Output ***
PRM0
¾
CMOS
¾ or PC5
SDI
SPI data input ***
PRM0
ST
¾
PA6 or PD2
SDO
SPI data output ***
PRM0
¾
CMOS
PA5 or PB6 or PD1
SCS
SPI slave select ***
PRM0
ST
CMOS
PB5 or PD0
SCK
SPI serial clock ***
PRM0
ST
CMOS
PA7 or PD3
SCL
I C clock
PRM0
ST
NMOS
PA7
PRM0
ST
NMOS
PA6
SCOMC
¾
SCOM
PC0, PC1, PC6, PC7
2
2
SDA
I C data
SCOM0~
SCOM3
SCOM0~SCOM3
OSC1
HXT/ERC pin
CO
HXT
¾
PB1
OSC2
HXT pin
CO
¾
HXT
PB2
XT1
LXT pin
CO
LXT
¾
PB3
XT2
LXT pin
CO
¾
LXT
PB4
¾
PB0
RES
Reset input
CO
ST
VDD
MCU power supply *
¾
PWR
¾
¾
AVDD
A/D converter power supply *
¾
PWR
¾
¾
VSS
MCU ground **
¾
PWR
¾
¾
AVSS
A/D converter ground **
¾
PWR
¾
¾
UDP
USB D+ pin
¾
ST
CMOS
¾
UDN
USB D- pin
¾
ST
CMOS
¾
V33O
3.3V regulator output pin
¾
¾
¾
¾
VDDU
USB power supply
¾
PWR
¾
¾
VSSU
USB ground
¾
PWR
¾
¾
NC
Not connected, can not be used
¾
¾
¾
¾
Rev. 1.30
11
December 12, 2012
HT66FB30/HT66FB40/HT66FB50/HT66FB60
Note:
I/T: Input type; O/T: Output type
OP: Optional by configuration option (CO) or register option
PWR: Power; CO: Configuration option; ST: Schmitt Trigger input
CMOS: CMOS output; NMOS: NMOS output
SCOM: Software controlled LCD COM; AN: Analog input pin
HXT: High frequency crystal oscillator
LXT: Low frequency crystal oscillator
*: VDD is the device power supply while AVDD is the ADC power supply. The AVDD pin is bonded together internally with VDD.
**: VSS is the device ground pin while AVSS is the ADC ground pin. The AVSS pin is bonded together internally
with VSS.
***: When the PINT, PCK and SPI functions are pin-shared remapping to PC4~PC5 and PD0~PD3 pins, the
SPI pins are to be used as the master SPI signal to communicate with the slave SPI in HT45B0K along with the
PINT and PCK pins used as the interrupt input and clock output connected to the SPI to USB chip to control the
overall USB functions.
Internally Connected Pins
Among the pins mentioned in the tables above several pins are not connected to external package pins. These pins are
interconnection pins between the MCU and the SPI to USB chips and are listed in the following table. The description is
provided from the SPI to USB chip standpoint.
SPI to USB Chip
Pin Name
Type
SDI
I
Slave SPI Serial Data In Input Signal
Internally connected to the MCU Master SPI SDO output signal
SDO
O
Slave SPI Serial Data Out Output Signal
Internally connected to the MCU Master SPI SDI input signal
SCK
I
Slave SPI Serial Clock Input Signal
Internally connected to the MCU Master SPI SCK output signal
SCS
I
Slave SPI Device Select Input Signal
Internally connected to the MCU Master SPI SCS output signal - connected to pull high
resistor
CLKI
I
Clock Input Signal
Internally connected to the MCU Master PCK output signal
INT
O
USB Interrupt Output Signal
Internally connected to the MCU Master PINT input signal
A USB related interrupt will generate a low pulse signal on this line
Rev. 1.30
Description
12
December 12, 2012
HT66FB30/HT66FB40/HT66FB50/HT66FB60
Functional Description
· Power Down and Wake up
As these devices packages contain multiple internal
chips, for a detailed functional description, users must
refer to the relevant individual datasheets for both the
MCU and the SPI to USB chips. The following table
shows which individual devices are inside each package.
Device
MCU
SPI to USB Chip
HT66FB30
HT66F30
HT45B0K
HT66FB40
HT66F40
HT45B0K
HT66FB50
HT66F50
HT45B0K
HT66FB60
HT66F60
HT45B0K
The MCU and SPI to USB chip are powered down independently of each other. The method of powering
down the MCU is covered in the relevant MCU
datasheet. The SPI to USB chip must be powered
down before the MCU is powered down.
After the device is powered down, it could be also
woken up by the SPI to USB chip interrupt except by
wake-up sources mentioned in the MCU datasheet.
When a USB interrupt occurs on the INT line, it will
wake up the MCU if the MCU has entered a power
down mode. After the MCU is woken up, the application program must set the corresponding control bits
to make the device function normally.
· Interrupts
Multi-chip Internal Devices
When a USB interrupt occurs, a low pulse will be generated on the INT line and sent to the peripheral interrupt line PINT in the MCU to get the attention of the
microcontroller. When the USB interrupt caused by
one of the USB interrupt generation sources occurs, if
the corresponding interrupt control in the host MCU is
enabled and the stack is not full, the program will jump
to the corresponding interrupt vector where it can be
serviced before returning to the main program.
For a USB interrupt to be serviced, in addition to the
bits for the corresponding interrupt enable control in
the SPI to USB chip being set, the global interrupt enable control and the related interrupt enable control
bits in the host MCU must also be set. If these bits are
not set, then the interrupt signal will only be a wake-up
source and no interrupt will be serviced.
Although most of the functional description material will
be located in the individual datasheets, there are some
special considerations which need to be taken into account when using multi-chip devices. These points will
be mentioned in the hardware and software consideration sections
As the complexity of USB data protocol does not permit
comprehensive USB operation information to be provided in the related datasheets, the reader should therefore consult other external information for a detailed
USB understanding.
Multi-chip Hardware Considerations
As these single-package multi-chip devices are composed of an individual MCU and SPI to USB chip, using
them together requires the user to take care of some
special points.
· Unbonded MCU pins
Examination of the relevant MCU datasheet will reveal that not all of the MCU I/O port lines are bonded
out to external pins. As a result special attention regarding initialisation procedures should be paid to
these port lines. If the pins are pin-shared with the analog input pins, they will be setup as analog inputs and
the corresponding analog circuits will be disabled after a reset. When these pins are set as analog input
pins and the relevant analog circuits are disabled,
they will not consume any power even if the input pin
conditions are not kept as either high or low logic levels. However, if the pins are not pin-shared with analog input pins, they will be setup as input states
without pull high resistors after a reset. Users should
therefore ensure that these pins are setup in input
states with pull high resistors or in output states with
either a high or low levels to avoid additional power
consumption resulting from floating input pins.
· Absolute Maximum Ratings
The Absolute Maximum Ratings for the two individual
chips must be checked for discrepancies and the necessary care taken in device handling and usage.
· Power Supply
Examination of the block diagram will reveal that the
SPI to USB chip Ground pin, VSSU, has no internal
connection to the MCU Ground pin, VSS. For this reason these two pins must be connected externally. With
the exception of the HT66FB60 device, the SPI to
USB chip power supply pin, VDDU, is internally connected to the MCU power supply pin, VDD. For the
HT66FB60 device, the SPI to USB chip power supply
pin and the MCU power supply pin should be connected together externally.
To calculate the power consumption for the devices,
the total operating current is the sum of the operating
current for the MCU specified in the MCU datasheet
and the operating current for the SPI to USB chip
listed in its datasheet. Similarly, the standby current is
the sum of the two individual chip standby currents.
Rev. 1.30
13
December 12, 2012
HT66FB30/HT66FB40/HT66FB50/HT66FB60
· The PCK control bit is set to 1 to enable the PCK out-
Multi-chip Programming Considerations
put as the clock source for the USB external clock input with various PCK output frequencies determined
by the PCKP1 and PCKP0 bits in the SIMC0 Register.
To use the USB function, several important steps must
be implemented to ensure that the SPI to USB chip operates normally:
¨
· The SPI pin-remapping function must be properly
configured when the SPI functional pins of the
microcontroller are used to control the SPI to USB
chip and for transmission and reception.
To ensure proper setup between the MCU Master SPI
interface to the SPI to USB chip Slave SPI, the SIM
pin-remapping settings for PCK and PINT in the MCU
PRM0 register should be setup as shown in the following table.
¨
¨
¨
0
Name
SIMPS0
PCKPS
Setting Value
1
1
HT66FB40/HT66FB50 PRM0 Register PCK and PINT pin-remap setup
Bit
2
1
0
Name
SIMPS1
SIMPS0
PCKPS
Setting Value
0
1
1
2
1
0
Name
SIMPS1
SIMPS0
PCKPS
Setting Value
1
1
1
0
PCKP0
11, 10, 01 or 00
PCK output enable control bit PCKEN in the SIMC0
Register
Bit
4
Name
PCKEN
Setting Value
1
0: Disable PCK output
1: Enable PCK output
After the above setup conditions have been implemented, the MCU can enable the SIM interface by setting the SIMEN bit high. The MCU can then begin
communication with external USB connected appliances using its SPI interface. The detailed functional
descriptions of the MCU Master SPI are provided within
the Serial Interface Module section of the relevant MCU
datasheet.
HT66FB60 PRM0 Register PCK and PINT pin-remap setup
Bit
1
PCKP1
00: PCK output frequency is fSYS
01: PCK output frequency is fSYS/4
10: PCK output frequency is fSYS/8
11: PCK output frequency is TM0 CCRP match
frequency/2
¨
1
Bit
Name
Setting Value
HT66FB30 PRM0 Register PCK and PINT pin-remap setup
Bit
PCK output frequency selection bits PCKP1~
PCKP0 in the SIMC0 Register
· The SIM operating mode control bits SIM2~SIM0 in
the SIMC0 register have to be configured to enable
the SIM to operate in the SPI master mode with a different SPI clock frequency.
¨
SIM operating mode control bits SIM2~SIM0 in the
SIMC0 Register
Bit
2
1
0
Name
SIMPS1
SIMPS0
PCKPS
Setting Value
1
1
1
000: SPI master mode; SPI clock is fSYS/4
001: SPI master mode; SPI clock is fSYS/16
010: SPI master mode; SPI clock is fSYS/64
011: SPI master mode; SPI clock is fTBC
100: SPI master mode; SPI clock is TM0 CCRP
match frequency/2
101~111: must not be used
Rev. 1.30
14
December 12, 2012
HT66FB30/HT66FB40/HT66FB50/HT66FB60
Application Circuits
V
D D
0 .0 1 m F * *
0 .1 m F
V D D
R e s e t
C ir c u it
1 0 k W ~
1 0 0 k W
1 N 4 1 4 8 *
0 .1 ~ 1 m F
3 0 0 W *
R E S
I/O
T M
IN T
S C O M
A n a lo g
V S S
O S C
C ir c u it
O S C 2
X T 1
V D
V 3
U
U
V S
D U
3 O
D P
D N
S U
U S B
A p p lic a tio n
C ir c u it
S e e A p p lic a tio n C ir c u it in
U S B m o d u le d a ta s h e e t
X T 2
S e e O s c illa to r s e c tio n
in M C U d a ta s h e e t
Note:
rts
in s
in s
in s
in s
O S C 1
S e e O s c illa to r s e c tio n
in M C U d a ta s h e e t
O S C
C ir c u it
P o
P
P
P
P
²*² Recommended component for added ESD protection.
²**² Recommended component in environments where power line noise is significant.
Rev. 1.30
15
December 12, 2012
HT66FB30/HT66FB40/HT66FB50/HT66FB60
Package Information
Note that the package information provided here is for consultation purposes only. As this
information may be updated at regular intervals users are reminded to consult the Holtek website for
the latest version of the Package/Carton Information.
28-pin SKDIP (300mil) Outline Dimensions
B
2 8
1 5
1
1 4
H
C
D
F
Symbol
Dimensions in inch
Min.
Nom.
Max.
A
1.375
¾
1.395
B
0.278
¾
0.298
C
0.125
¾
0.135
D
0.125
¾
0.145
E
0.016
¾
0.020
F
0.050
¾
0.070
G
¾
0.100
¾
H
0.295
¾
0.315
I
¾
0.375
¾
Symbol
Rev. 1.30
I
G
Dimensions in mm
Min.
Nom.
Max.
A
34.93
¾
35.43
B
7.06
¾
7.57
C
3.18
¾
3.43
D
3.18
¾
3.68
E
0.41
¾
0.51
F
1.27
¾
1.78
G
¾
2.54
¾
H
7.49
¾
8.00
I
¾
9.53
¾
16
December 12, 2012
HT66FB30/HT66FB40/HT66FB50/HT66FB60
28-pin SOP (300mil) Outline Dimensions
2 8
1 5
A
B
1
1 4
C
C '
G
H
D
E
a
F
· MS-013
Symbol
Nom.
Max.
A
0.393
¾
0.419
B
0.256
¾
0.300
C
0.012
¾
0.020
C¢
0.697
¾
0.713
D
¾
¾
0.104
E
¾
0.050
¾
F
0.004
¾
0.012
G
0.016
¾
0.050
H
0.008
¾
0.013
a
0°
¾
8°
Symbol
Rev. 1.30
Dimensions in inch
Min.
Dimensions in mm
Min.
Nom.
Max.
A
9.98
¾
10.64
B
6.50
¾
7.62
C
0.30
¾
0.51
C¢
17.70
¾
18.11
D
¾
¾
2.64
E
¾
1.27
¾
F
0.10
¾
0.30
G
0.41
¾
1.27
H
0.20
¾
0.33
a
0°
¾
8°
17
December 12, 2012
HT66FB30/HT66FB40/HT66FB50/HT66FB60
28-pin SSOP (150mil) Outline Dimensions
1 5
2 8
A
B
1
1 4
C
C '
G
H
D
E
Symbol
Dimensions in inch
Min.
Nom.
Max.
A
0.228
¾
0.244
B
0.150
¾
0.157
C
0.008
¾
0.012
C¢
0.386
¾
0.394
D
0.054
¾
0.060
E
¾
0.025
¾
F
0.004
¾
0.010
G
0.022
¾
0.028
H
0.007
¾
0.010
a
0°
¾
8°
Symbol
A
Rev. 1.30
a
F
Dimensions in mm
Min.
Nom.
Max.
5.79
¾
6.20
B
3.81
¾
3.99
C
0.20
¾
0.30
C¢
9.80
¾
10.01
D
1.37
¾
1.52
E
¾
0.64
¾
F
0.10
¾
0.25
G
0.56
¾
0.71
H
0.18
¾
0.25
a
0°
¾
8°
18
December 12, 2012
HT66FB30/HT66FB40/HT66FB50/HT66FB60
SAW Type 40-pin (6mm´6mm for 0.75mm) QFN Outline Dimensions
D
D 2
3 1
4 0
3 0
b
1
E
E 2
e
2 1
A 1
A 3
1 0
2 0
L
1 1
K
A
· GTK
Symbol
Nom.
Max.
A
0.028
0.030
0.031
A1
0.000
0.001
0.002
A3
¾
0.008
¾
b
0.007
0.010
0.012
D
¾
0.236
¾
E
¾
0.236
¾
e
¾
0.020
¾
D2
0.173
0.177
0.179
E2
0.173
0.177
0.179
L
0.014
0.016
0.018
K
0.008
¾
¾
Symbol
Rev. 1.30
Dimensions in inch
Min.
Dimensions in mm
Min.
Nom.
Max.
A
0.70
0.75
0.80
A1
0.00
0.02
0.05
A3
¾
0.20
¾
b
0.18
0.25
0.30
D
¾
6.00
¾
E
¾
6.00
¾
e
¾
0.50
¾
D2
4.40
4.50
4.55
E2
4.40
4.50
4.55
L
0.35
0.40
0.45
K
0.20
¾
¾
19
December 12, 2012
HT66FB30/HT66FB40/HT66FB50/HT66FB60
SAW Type 48-pin (7mm´7mm) QFN Outline Dimensions
D
D 2
3 7
b
4 8
1
3 6
E
E 2
e
2 5
A 1
A 3
1 2
2 4
L
1 3
K
A
Symbol
Nom.
Max.
A
0.028
¾
0.031
A1
0.000
¾
0.002
A3
¾
0.008
¾
b
0.007
¾
0.012
D
¾
0.276
¾
E
¾
0.276
¾
e
¾
0.020
¾
D2
0.177
¾
0.227
E2
0.177
¾
0.227
L
0.012
¾
0.020
K
0.008
¾
¾
Symbol
Rev. 1.30
Dimensions in inch
Min.
Dimensions in mm
Min.
Nom.
Max.
A
0.70
¾
0.80
A1
0.00
¾
0.05
A3
¾
0.203
¾
b
0.18
¾
0.30
D
¾
7.00
¾
E
¾
7.00
¾
e
¾
0.50
¾
D2
4.50
¾
5.76
E2
4.50
¾
5.76
L
0.30
¾
0.50
K
0.20
¾
¾
20
December 12, 2012
HT66FB30/HT66FB40/HT66FB50/HT66FB60
44-pin LQFP (10mm´10mm) (FP2.0mm) Outline Dimensions
H
C
D
G
2 3
3 3
I
3 4
2 2
F
A
B
E
1 2
4 4
K
a
J
1
Symbol
Dimensions in inch
Min.
Nom.
Max.
A
0.469
¾
0.476
B
0.390
¾
0.398
C
0.469
¾
0.476
D
0.390
¾
0.398
E
¾
0.031
¾
F
¾
0.012
¾
G
0.053
¾
0.057
H
¾
¾
0.063
I
¾
0.004
¾
J
0.018
¾
0.030
K
0.004
¾
0.008
a
0°
¾
7°
Symbol
A
Rev. 1.30
1 1
Dimensions in mm
Min.
Nom.
Max.
11.90
¾
12.10
B
9.90
¾
10.10
C
11.90
¾
12.10
D
9.90
¾
10.10
E
¾
0.80
¾
F
¾
0.30
¾
G
1.35
¾
1.45
H
¾
¾
1.60
I
¾
0.10
¾
J
0.45
¾
0.75
K
0.10
¾
0.20
a
0°
¾
7°
21
December 12, 2012
HT66FB30/HT66FB40/HT66FB50/HT66FB60
48-pin LQFP (7mm´7mm) Outline Dimensions
C
H
D
3 6
G
2 5
I
3 7
2 4
F
A
B
E
4 8
1 3
K
a
J
1
Symbol
A
Dimensions in inch
Min.
Nom.
Max.
0.350
¾
0.358
B
0.272
¾
0.280
C
0.350
¾
0.358
D
0.272
¾
0.280
E
¾
0.020
¾
F
¾
0.008
¾
G
0.053
¾
0.057
H
¾
¾
0.063
I
¾
0.004
¾
J
0.018
¾
0.030
K
0.004
¾
0.008
a
0°
¾
7°
Symbol
Rev. 1.30
1 2
Dimensions in mm
Min.
Nom.
Max.
A
8.90
¾
9.10
B
6.90
¾
7.10
C
8.90
¾
9.10
D
6.90
¾
7.10
E
¾
0.50
¾
F
¾
0.20
¾
G
1.35
¾
1.45
H
¾
¾
1.60
I
¾
0.10
¾
J
0.45
¾
0.75
K
0.10
¾
0.20
a
0°
¾
7°
22
December 12, 2012
HT66FB30/HT66FB40/HT66FB50/HT66FB60
52-pin QFP (14mm´14mm) Outline Dimensions
C
H
D
3 9
G
2 7
I
2 6
4 0
F
A
B
E
1 4
5 2
K
J
1
Symbol
A
Dimensions in inch
Min.
Nom.
Max.
0.681
¾
0.689
B
0.547
¾
0.555
C
0.681
¾
0.689
D
0.547
¾
0.555
E
¾
0.039
¾
F
¾
0.016
¾
G
0.098
¾
0.122
H
¾
¾
0.134
I
¾
0.004
¾
J
0.029
¾
0.041
K
0.004
¾
0.008
L
¾
0.004
¾
a
0°
¾
7°
Symbol
A
Rev. 1.30
1 3
Dimensions in mm
Min.
Nom.
Max.
17.30
¾
17.50
B
13.90
¾
14.10
C
17.30
¾
17.50
D
13.90
¾
14.10
E
¾
1.00
¾
F
¾
0.40
¾
G
2.50
¾
3.10
H
¾
¾
3.40
I
¾
0.10
¾
J
0.73
¾
1.03
K
0.10
¾
0.20
a
0°
¾
7°
23
December 12, 2012
HT66FB30/HT66FB40/HT66FB50/HT66FB60
Product Tape and Reel Specifications
Reel Dimensions
D
T 2
A
C
B
T 1
SOP 28W (300mil)
Symbol
Description
Dimensions in mm
A
Reel Outer Diameter
330.0±1.0
B
Reel Inner Diameter
100.0±1.5
C
Spindle Hole Diameter
D
Key Slit Width
T1
Space Between Flange
T2
Reel Thickness
13.0
+0.5/-0.2
2.0±0.5
24.8
+0.3/-0.2
30.2±0.2
SSOP 28S (150mil)
Symbol
Description
A
Reel Outer Diameter
B
Reel Inner Diameter
C
330.0±1.0
100.0±1.5
13.0
Spindle Hole Diameter
D
Key Slit Width
T1
Space Between Flange
T2
Reel Thickness
Rev. 1.30
Dimensions in mm
+0.5/-0.2
2.0±0.5
16.8
+0.3/-0.2
22.2±0.2
24
December 12, 2012
HT66FB30/HT66FB40/HT66FB50/HT66FB60
Carrier Tape Dimensions
P 0
D
P 1
t
E
F
W
C
D 1
P
B 0
K 0
A 0
R e e l H o le
IC
p a c k a g e p in 1 a n d th e r e e l h o le s
a r e lo c a te d o n th e s a m e s id e .
SOP 28W (300mil)
Symbol
Description
Dimensions in mm
W
Carrier Tape Width
24.0±0.3
P
Cavity Pitch
12.0±0.1
E
Perforation Position
1.75±0.10
F
Cavity to Perforation (Width Direction)
11.5±0.1
D
Perforation Diameter
1.5
D1
Cavity Hole Diameter
1.50
P0
Perforation Pitch
P1
Cavity to Perforation (Length Direction)
A0
Cavity Length
10.85±0.10
B0
Cavity Width
18.34±0.10
K0
Cavity Depth
2.97±0.10
t
Carrier Tape Thickness
0.35±0.01
C
Cover Tape Width
21.3±0.1
+0.1/-0.0
+0.25/-0.00
4.0±0.1
2.0±0.1
SSOP 28S (150mil)
Symbol
Description
Dimensions in mm
W
Carrier Tape Width
16.0±0.3
P
Cavity Pitch
8.0±0.1
E
Perforation Position
1.75±0.1
F
Cavity to Perforation (Width Direction)
7.5±0.1
D
Perforation Diameter
1.55
D1
Cavity Hole Diameter
1.50
P0
Perforation Pitch
4.0±0.1
P1
Cavity to Perforation (Length Direction)
2.0±0.1
A0
Cavity Length
6.5±0.1
B0
Cavity Width
10.3±0.1
K0
Cavity Depth
2.1±0.1
+0.10/-0.00
+0.25/-0.00
t
Carrier Tape Thickness
0.30±0.05
C
Cover Tape Width
13.3±0.1
Rev. 1.30
25
December 12, 2012
HT66FB30/HT66FB40/HT66FB50/HT66FB60
Holtek Semiconductor Inc. (Headquarters)
No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan
Tel: 886-3-563-1999
Fax: 886-3-563-1189
http://www.holtek.com.tw
Holtek Semiconductor Inc. (Taipei Sales Office)
4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan
Tel: 886-2-2655-7070
Fax: 886-2-2655-7373
Fax: 886-2-2655-7383 (International sales hotline)
Holtek Semiconductor (China) Inc.
Building No. 10, Xinzhu Court, (No. 1 Headquarters), 4 Cuizhu Road, Songshan Lake, Dongguan, China 523808
Tel: 86-769-2626-1300
Fax: 86-769-2626-1311
Holtek Semiconductor (USA), Inc. (North America Sales Office)
46729 Fremont Blvd., Fremont, CA 94538, USA
Tel: 1-510-252-9880
Fax: 1-510-252-9885
http://www.holtek.com
Copyright Ó 2012 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used
solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable
without further modification, nor recommends the use of its products for application that may present a risk to human life
due to malfunction or otherwise. Holtek¢s products are not authorized for use as critical components in life support devices
or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information,
please visit our web site at http://www.holtek.com.tw.
Rev. 1.30
26
December 12, 2012