Product Folder Sample & Buy Support & Community Tools & Software Technical Documents Reference Design LP38513 SNVS361E – JULY 2007 – REVISED NOVEMBER 2015 LP38513 3-A Fast Response Ultra-Low Dropout Linear Regulator 1 Features 3 Description • • • • • The LP38513 fast-response ultra-low dropout linear regulator operates from a 2.25-V to 5.5-V input supply. This device responds very quickly to step changes in line or load conditions, making it suitable for low-voltage microprocessor applications. Developed on a CMOS process, with a PMOS pass transistor, the LP38513 has low quiescent-current operation independent of the output load current. • Ground Pin Current: Typically 12 mA at 3-A load current. • Disable Mode: Typically 60 µA quiescent current when the enable (EN) pin is pulled low. • ERROR Flag: The ERROR flag goes low if VOUT falls more than typically 15% below the nominal value. • Precision Output Voltage: A specified VOUT accuracy of ±2.6% with TJ from 0°C to 125°C. 1 • • • • • • Input Supply Voltage 2.25 V to 5.5 V Conversions from 2.5-V Rail to 1.8-V Rail Stable with Ceramic Capacitors Low Ground Pin Current Load Regulation of 0.1% for 10 mA to 3-A Load Current 60-μA Typical Quiescent Current in Shutdown Mode Specified Output Current of 3 A Specified VOUT Accuracy of ±2.6% With TJ from 0°C to +125°C ERROR Flag Indicates VOUT Status Overtemperature and Overcurrent Protection −40°C to +125°C Operating TJ Range 2 Applications • • • • • • • Device Information(1) PART NUMBER Microprocessor Power Supplies GTL, GTL+, BTL, and SSTL Bus Terminators Power Supplies for DSPs SCSI Terminator Post Regulators Battery Chargers Other Battery Powered Applications LP38513 PACKAGE TO-220 (5) BODY SIZE (NOM) 14.986 mm × 10.16 mm DDPAK/TO-263 (5) 10.16 mm × 8.42 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Typical Application IN VIN VEN ON OFF CIN 10 PF Ceramic OUT LP38513 EN ERROR COUT 10 PF Ceramic VOUT 10 k: GND GND GND VERROR 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. LP38513 SNVS361E – JULY 2007 – REVISED NOVEMBER 2015 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 4 6.1 6.2 6.3 6.4 6.5 6.6 4 4 4 4 5 7 Absolute Maximum Ratings ...................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Typical Characteristics .............................................. Detailed Description ............................................ 10 7.1 Overview ................................................................. 10 7.2 Functional Block Diagram ....................................... 10 7.3 Feature Description................................................. 10 7.4 Device Functional Modes........................................ 11 8 Application and Implementation ........................ 13 8.1 Application Information............................................ 13 8.2 Typical Application ................................................. 13 9 Power Supply Recommendations...................... 17 10 Layout................................................................... 17 10.1 Layout Guidelines ................................................. 17 10.2 Layout Example .................................................... 17 11 Device and Documentation Support ................. 18 11.1 11.2 11.3 11.4 11.5 Related Documentation ....................................... Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 18 18 18 18 18 12 Mechanical, Packaging, and Orderable Information ........................................................... 18 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision D (April 2013) to Revision E Page • Added Device Information and Pin Configuration and Functions sections, ESD Ratings table, Feature Description, Device Functional Modes, Application and Implementation, Power Supply Recommendations, Layout, Device and Documentation Support, and Mechanical, Packaging, and Orderable Information sections ................................................. 1 • Deleted lead temp from Abs Max - it is in POA ..................................................................................................................... 4 • Added updated thermal information ...................................................................................................................................... 4 • Deleted out-of-date heat sinking subsection ....................................................................................................................... 14 Changes from Revision C (April 2013) to Revision D • 2 Page Changed layout of National Data Sheet to TI format .......................................................................................................... 14 Submit Documentation Feedback Copyright © 2007–2015, Texas Instruments Incorporated Product Folder Links: LP38513 LP38513 www.ti.com SNVS361E – JULY 2007 – REVISED NOVEMBER 2015 5 Pin Configuration and Functions NDH Package 5-Pin TO-220 Top View KTT Package 5-Pin DDPAK/TO-263 Top View TAB IS GND EN 1 OUT 4 LP38513S-x.x LP38513T-x.x IN 2 GND 3 EN 1 IN 2 GND 3 OUT 4 ERROR 5 TAB IS GND ERROR 5 Pin Functions for TO-220 and DDPAK/TO-263 Packages PIN NUMBER 1 NAME EN TYPE DESCRIPTION I Enable. Pull high to enable the output, low to disable the output. This pin has no internal bias and must be tied to the input voltage, or actively driven. 2 IN I Input supply pin 3 GND G Ground 4 OUT O Regulated output voltage pin 5 ERROR O ERROR flag. A high level indicates that VOUT is within 15% of the nominal regulated voltage. TAB G The TO-220 and DDPAK/TO-263 TAB is used as a thermal connection to remove heat from the device to an external heat sink. The TAB is internally connected to device pin 3. TAB Submit Documentation Feedback Copyright © 2007–2015, Texas Instruments Incorporated Product Folder Links: LP38513 3 LP38513 SNVS361E – JULY 2007 – REVISED NOVEMBER 2015 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) (2) MIN MAX UNIT IN pin voltage (survival) −0.3 6 V EN pin voltage (survival) −0.3 6 V OUT pin Voltage (survival) −0.3 6 V ERROR pin voltage (survival) −0.3 6 V IOUT (Survival) Internally limited Power dissipation (3) Internally limited −65 Storage temperature, Tstg (1) (2) (3) 150 °C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. If Military/Aerospace specified devices are required, contact the TI Sales Office/ Distributors for availability and specifications. Device operation must be evaluated, and derated as needed, based on ambient temperature (TA), power dissipation (PD), maximum allowable operating junction temperature (TJ(MAX)), and package thermal resistance (RθJA). 6.2 ESD Ratings V(ESD) (1) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) VALUE UNIT ±2000 V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) (1) MIN Input supply voltage, VIN NOM MAX UNIT 2.25 5.5 V Enable input voltage, VEN 0 5.5 V ERROR pin voltage 0 VIN Output current (DC) 0 3 −40 125 Junction temperature (2) (1) (2) V mA/A °C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Device operation must be evaluated, and derated as needed, based on ambient temperature (TA), power dissipation (PD), maximum allowable operating junction temperature (TJ(MAX)), and package thermal resistance (RθJA). 6.4 Thermal Information LP38513 THERMAL METRIC (1) NDH (TO-220) KTT (DDPAK/TO-263) 5 PINS 5 PINS UNIT RθJA Junction-to-ambient thermal resistance 31.9 32.9 °C/W RθJC(top) Junction-to-case (top) thermal resistance 43.7 37.6 °C/W RθJB Junction-to-board thermal resistance 16.4 18.9 °C/W ψJT Junction-to-top characterization parameter 8.3 5.7 °C/W ψJB Junction-to-board characterization parameter 16.4 17.3 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 1.2 1.0 °C/W (1) 4 For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright © 2007–2015, Texas Instruments Incorporated Product Folder Links: LP38513 LP38513 www.ti.com SNVS361E – JULY 2007 – REVISED NOVEMBER 2015 6.5 Electrical Characteristics Unless otherwise specified: VIN = 2.5 V, IOUT = 10 mA, CIN = 10 µF, COUT = 10 µF, VEN = 2 V, and limits apply for TJ = 25°C. Minimum and Maximum limits are specified through test, design, or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. PARAMETER VOUT Output voltage tolerance (1) ΔVOUT/ΔVIN Output voltage line regulation (1) (2) ΔVOUT/ΔIOUT Output voltage load regulation (1) (3) VDO Dropout voltage (4) MIN TYP MAX 2.25 V ≤ VIN ≤ 5.5 V 10 mA ≤ IOUT ≤ 3 A TEST CONDITIONS –1.6% 0% 1.6% 2.25 V ≤ VIN ≤ 5.5 V 10 mA ≤ IOUT ≤ 3 A TJ = –40°C to +125°C –4.1% 2.25V ≤ VIN ≤ 5.5V 10 mA ≤ IOUT ≤ 3A 0°C ≤ TJ ≤ 125°C –2.6% Ground pin current, output enabled IGND 0% 0.03 2.25 V ≤ VIN ≤ 5.5 V TJ = –40°C to +125°C 0.06 10 mA ≤ IOUT ≤ 3 A 0.1 10 mA ≤ IOUT ≤ 3 A TJ = –40°C to +125°C 0.2 IOUT = 3 A, TJ = –40°C to +125°C Short-circuit current 2.6% %/V %/A 425 10 IOUT = 10 mA, ERROR pin = GND TJ = –40°C to +125°C mV 12 15 IOUT = 3 A, ERROR pin = GND 12 IOUT = 3 A, ERROR pin = GND TJ = –40°C to +125°C Ground pin current, output disabled ISC 2.6% 2.25 V ≤ VIN ≤ 5.5 V IOUT = 10 mA, ERROR pin = GND UNIT 15 mA 20 VEN = 0.5 V, ERROR pin = GND 60 VEN = 0.5 V, ERROR pin = GND TJ = –40°C to +125°C 100 110 VOUT = 0 V µA 5.6 A ENABLE INPUT VEN rising from 0 V until the output turns to an ON state, or VEN falling from ≥ 2 V until the output turns to an OFF state VEN(TH) Enable on/off threshold VEN rising from 0 V until the output turns to an ON state, or VEN falling from ≥ 2 V until the output turns to an OFF state TJ = –40°C to +125°C 0.74 0.85 V 0.56 1 td(OFF) Turnoff delay Time from VEN < VEN(TH) to VOUT = OFF, ILOAD = 3 A 5 td(ON) Turnon delay Time from VEN >VEN(TH) to VOUT = ON, ILOAD = 3 A 5 IEN EN pin current (1) (2) (3) (4) 0.92 µs VEN = VIN 1 VEN = 0 V –1 nA The line and load regulation specification contains only the typical number. However, the limits for line and load regulation are included in the output voltage tolerance specification. Output voltage line regulation is defined as the change in output voltage from the nominal value due to change in the voltage at the input. Output voltage load regulation is defined as the change in output voltage from the nominal value due to change in the load current at the output. Dropout voltage (VDO) is typically defined as the input to output voltage differential (VIN – VOUT) where the input voltage is low enough to cause the output voltage to drop 2% from the nominal value. For the LP38513, the minimum operating voltage of 2.25 V is the limiting factor, and the maximum dropout voltage is defined as: VDO(MAX) = VIN(MIN) – VOUT(MIN) = (2.25 V – (1.8 V × 95.9%) = 524 mV). Submit Documentation Feedback Copyright © 2007–2015, Texas Instruments Incorporated Product Folder Links: LP38513 5 LP38513 SNVS361E – JULY 2007 – REVISED NOVEMBER 2015 www.ti.com Electrical Characteristics (continued) Unless otherwise specified: VIN = 2.5 V, IOUT = 10 mA, CIN = 10 µF, COUT = 10 µF, VEN = 2 V, and limits apply for TJ = 25°C. Minimum and Maximum limits are specified through test, design, or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ERROR FLAG VOUT falling from VOUT(NOM) until ERROR flag goes low ERROR flag threshold (5) VTH ERROR flag threshold hysteresis (5) ΔVTH VERROR(SAT) ERROR flag saturation voltage Ilk ERROR flag pin leakage current td ERROR flag delay time VOUT falling from VOUT(NOM) until ERROR flag goes low TJ = –40°C to +125°C 85% 77% VOUT rising from VTH until ERROR flag goes high VOUT rising from VTH until ERROR flag goes high TJ = –40°C to +125°C ISINK = 1 mA 94% 4% 2.2% 5.8% 20 ISINK = 1 mA, TJ = –40°C to +125°C VERROR = 5.5 V 100 mV 100 nA 1 µs AC PARAMETERS VIN = 2.5 V, ƒ = 120 Hz 73 VIN = 2.5 V, ƒ = 1 kHz 70 Output noise density ƒ = 120 Hz 0.8 µV/√Hz Output noise voltage BW = 100 Hz – 100 kHz, VOUT = 1.8 V 45 µVRMS PSRR Ripple rejection ρn(l/f) en dB THERMAL CHARACTERISTICS TSD Thermal shutdown ΔTSD Thermal shutdown hysteresis TJ falling from TSD (5) 6 TJ rising 165 10 °C The ERROR flag thresholds are specified as percentage of the nominal regulated output voltage. See Application and Implementation section. Submit Documentation Feedback Copyright © 2007–2015, Texas Instruments Incorporated Product Folder Links: LP38513 LP38513 www.ti.com SNVS361E – JULY 2007 – REVISED NOVEMBER 2015 6.6 Typical Characteristics Unless otherwise specified: TJ = 25°C, VIN = 2.5V, VEN = 2 V, CIN = 10 µF, COUT = 10 µF, IOUT = 10 mA. Figure 1. VOUT vs Temperature Figure 2. VOUT vs VIN Figure 3. Ground Pin Current (IGND) vs VIN Figure 4. Ground Pin Current (IGND) vs Temperature Figure 5. Ground Pin Current (IGND) vs Temperature Figure 6. Enable Threshold vs Temperature Submit Documentation Feedback Copyright © 2007–2015, Texas Instruments Incorporated Product Folder Links: LP38513 7 LP38513 SNVS361E – JULY 2007 – REVISED NOVEMBER 2015 www.ti.com Typical Characteristics (continued) Unless otherwise specified: TJ = 25°C, VIN = 2.5V, VEN = 2 V, CIN = 10 µF, COUT = 10 µF, IOUT = 10 mA. 8 Figure 7. VOUT vs VEN Figure 8. VOUT ERROR Flag Threshold vs Temperature Figure 9. ERROR Flag Low vs Temperature Figure 10. ERROR Flag Leakage vs Temperature Figure 11. Load Regulation vs Temperature Figure 12. Line Regulation vs Temperature Submit Documentation Feedback Copyright © 2007–2015, Texas Instruments Incorporated Product Folder Links: LP38513 LP38513 www.ti.com SNVS361E – JULY 2007 – REVISED NOVEMBER 2015 Typical Characteristics (continued) Unless otherwise specified: TJ = 25°C, VIN = 2.5V, VEN = 2 V, CIN = 10 µF, COUT = 10 µF, IOUT = 10 mA. Figure 13. Current Limit vs Temperature Figure 14. PSRR Figure 15. Noise Submit Documentation Feedback Copyright © 2007–2015, Texas Instruments Incorporated Product Folder Links: LP38513 9 LP38513 SNVS361E – JULY 2007 – REVISED NOVEMBER 2015 www.ti.com 7 Detailed Description 7.1 Overview The LP38513 is a fast response, ultra-low-dropout linear regulator that operates from a 2.25-V to 5.5-V input supply. This linear regulator responds very quickly to step changes in line or load conditions, making it suitable for low-voltage microprocessor applications. The device has low quiescent current operation that is independent of the output load current, and it has an ERROR flag pin, which can indicate that VOUT is within 15% of the nominal regulated voltage. The LP38513 is designed to perform with a10-µF (minimum value) input capacitor and a 10-µF (minimum value) output capacitor. 7.2 Functional Block Diagram IN OUT Thermal Limit Current Limit EN VREF ERROR VREF GND LP38513 7.3 Feature Description 7.3.1 Short-Circuit Protection The LP38513 is short-circuit protected and, in the event of a peak overcurrent condition, the short-circuit control loop rapidly drives the output PMOS pass element off. Once the power pass element shuts down, the control loop rapidly cycles the output on and off until the average power dissipation causes the thermal shutdown circuit to respond to servo the on/off cycling to a lower frequency. Refer to the Power Dissipation section for power dissipation calculations. 7.3.2 Enable LP38513 has an EN pin to enable/disable the device. If the application does not require the enable function, the pin must be connected directly to the adjacent IN pin. The status of the EN pin also affects the behavior of the ERROR flag. While the EN pin is high the regulator control loop is active, and the ERROR flag reorts the status of the output voltage. When the EN pin is taken low the regulator control loop is shut down, the output is turned off, and the internal logic immediately forces the ERROR flag pin low. 7.3.3 ERROR Flag When the LP38513 EN pin is high, the ERROR flag pin produces a logic low signal when the output drops by more than 15% (VTH, typical) from the nominal output voltage. The drop in output voltage may be due to low input voltage, current limiting, or thermal limiting. This flag has a built-in hysteresis. The output voltage must to rise to greater than typically 89% of the nominal output voltage for the ERROR flag to return to a logic high state. Also, if the EN pin is pulled low, the ERROR flag pin is forced to low as well. 10 Submit Documentation Feedback Copyright © 2007–2015, Texas Instruments Incorporated Product Folder Links: LP38513 LP38513 www.ti.com SNVS361E – JULY 2007 – REVISED NOVEMBER 2015 7.4 Device Functional Modes 7.4.1 Enable Operation The Enable on/off threshold is typically 850 mV and has no hysteresis. The voltage signal must rise and fall cleanly, and promptly, through this threshold. The EN pin has no internal pullup or pulldown to establish a default condition and, as a result, this pin must be terminated either actively or passively. If the EN pin is driven from a single ended device (such as the collector of a discrete transistor) a pullup resistor to VIN, or a pulldown resistor to ground, is required for proper operation. A 1-kΩ to 100-kΩ resistor can be used as the pullup or pulldown resistor to establish default condition for the EN pin. The resistor value selected must be appropriate to swamp out any leakage in the external single-ended device, as well as any stray capacitance. If the EN pin is driven from a source that actively pulls high and low (such as a CMOS rail-to-rail comparator output), the pullup or pulldown resistor is not required. If the application does not require the enable function, the EN pin must be connected directly to the adjacent IN pin. 7.4.2 ERROR Flag Operation The internal ERROR flag comparator has an open-drain output stage. Hence, the ERROR pin requires an external pullup resistor. The value of the pullup resistor must be in the range of 2 kΩ to 20 kΩ and must be connected to the LP38513 OUT pin. The ERROR flag pin must not be pulled up to any voltage source higher than VIN as current flow through an internal parasitic diode may cause unexpected behavior. When the input voltage is less than typically 1.25 V the status of the ERROR flag output is not reliable. The ERROR flag pin must be connected to ground if this function is not used. The timing diagram in Figure 16 shows the relationship between the ERROR flag and the output voltage when a pullup resistor is connected to the output voltage pin. The timing diagram in Figure 17 shows the relationship between the ERROR flag and the output voltage when the pullup resistor is connected to the input voltage. ~2.50V ~2.25V VIN ~1.25V NOM ~89% ~85% PowerUp Load Transient Line Transient PowerDown VOUT VERROR Figure 16. ERROR Flag Operation (see Figure 18) Submit Documentation Feedback Copyright © 2007–2015, Texas Instruments Incorporated Product Folder Links: LP38513 11 LP38513 SNVS361E – JULY 2007 – REVISED NOVEMBER 2015 www.ti.com Device Functional Modes (continued) ~2.50V ~2.25V VIN ~1.25V Power -Up Load Transient Line Transient PowerDown NOM ~89% ~85% VOUT ~2.50V VERROR ~1.25V Figure 17. ERROR Flag Operation Biased from VIN 12 Submit Documentation Feedback Copyright © 2007–2015, Texas Instruments Incorporated Product Folder Links: LP38513 LP38513 www.ti.com SNVS361E – JULY 2007 – REVISED NOVEMBER 2015 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information The typical application of the LP38513 includes microprocessor supplies, bus terminators, post regulators, and battery-powered application. Figure 18 shows the typical application circuit for LP38513. The input and output capacitances may need to be increased above the 10-µF minimum for some applications. 8.2 Typical Application IN VIN VEN ON OFF CIN 10 PF Ceramic OUT LP38513 EN ERROR COUT 10 PF Ceramic VOUT 10 k: GND GND GND VERROR Figure 18. LP38513 Typical Application 8.2.1 Design Requirements For the typical LP38513 ultra-low-dropout linear regulator applications, use the parameters listed in Table 1. Table 1. Design Parameters DESIGN PARAMETER EXAMPLE VALUE Minimum input voltage 2.25 V Output voltage 1.8 V Output current 0 mA to 3 A 8.2.2 Detailed Design Procedure 8.2.2.1 External Capacitors Like any low-dropout regulator, external capacitors are required to assure stability. These capacitors must be correctly selected for proper performance. 8.2.2.1.1 Input Capacitor A ceramic input capacitor of at least 10 µF is required. For general usage across all load currents and operating conditions, a 10-µF ceramic input capacitor provides satisfactory performance. 8.2.2.1.2 Output Capacitor A ceramic capacitor with a minimum value of 10 µF is required at the output pin for loop stability. It must be located less than 1 cm from the device and connected directly to the OUT and GND pin using traces which have no other currents flowing through them. As long as the minimum of 10 µF ceramic is met, there is no limitation on any additional capacitance. Submit Documentation Feedback Copyright © 2007–2015, Texas Instruments Incorporated Product Folder Links: LP38513 13 LP38513 SNVS361E – JULY 2007 – REVISED NOVEMBER 2015 www.ti.com X7R and X5R dielectric ceramic capacitors are strongly recommended, as they typically maintain a capacitance range within ±20% of nominal over full operating ratings of temperature and voltage; they are typically larger and more costly than Z5U/Y5U types for a given voltage and capacitance. Z5U and Y5V dielectric ceramics are not recommended as the capacitance will drop severely with applied voltage. A typical Z5U or Y5V capacitor can lose 60% of its rated capacitance with half of the rated voltage applied to it. The Z5U and Y5V also exhibit a severe temperature effect, losing more than 50% of nominal capacitance at high and low limits of the temperature range. 8.2.2.2 Reverse Voltage A reverse voltage condition will exist when the voltage at the OUT pin is higher than the voltage at the IN pin. Typically this happens when VIN is abruptly taken low and COUT continues to hold a sufficient charge such that the input to output voltage becomes reversed. A less common condition is when an alternate voltage source is connected to the output. There are two possible paths for current to flow from the OUT pin back to the input during a reverse voltage condition. While VIN is high enough to keep the control circuity alive, and the EN pin is above the VEN(ON) threshold, the control circuitry attempts to regulate the output voltage. Because the input voltage is less than the output voltage the control circuit drives the gate of the pass element to the full ON condition when the output voltage begins to fall. In this condition, reverse current will flow from the OUT pin to the IN pin, limited only by the RDS(ON) of the pass element and the output-to-input voltage differential. Discharging an output capacitor up to 1000 µF in this manner does not damage the device as the current rapidly decays. However, continuous reverse current must be avoided. The internal PFET pass element in the LP38513 has an inherent parasitic diode. During normal operation, the input voltage is higher than the output voltage, and the parasitic diode is reverse biased. However, if the outputvoltage-to-input-voltage differential is more than 500 mV (typical), the parasitic diode becomes forward biased, and current flows from the OUT pin to the input through the diode. The current in the parasitic diode must be limited to less than 1-A continuous and 5-A peak. If used in a dual-supply system where the regulator output load is returned to a negative supply, the OUT pin must be diode clamped to ground. A Schottky diode is recommended for this protective clamp. 8.2.2.3 Power Dissipation A heat sink may be required depending on the maximum power dissipation (PD(MAX)), maximum ambient temperature (TA(MAX))of the application, and the thermal resistance (RθJA) of the package. Under all possible conditions, the junction temperature (TJ) must be within the range specified in the Recommended Operating Conditions. The total power dissipation of the device is given by: PD = ((VIN − VOUT) × IOUT) + ((VIN) × IGND) where • IGND is the operating ground current of the device (specified under Electrical Characteristics). (1) The maximum allowable junction temperature rise (ΔTJ) depends on the maximum expected ambient temperature (TA(MAX)) of the application, and the maximum allowable junction temperature (TJ(MAX)): ΔTJ = TJ(MAX)− TA(MAX) (2) The maximum allowable value for junction-to-ambient thermal resistance, RθJA, can be calculated using the formula: RθJA = ΔTJ / PD(MAX) (3) Knowing the device power dissipation and proper sizing of the thermal plane connected to the tab or pad is critical to ensuring reliable operation. Device power dissipation depends on input voltage, output voltage, and load conditions and can be calculated with Equation 4. PD(MAX) = (VIN(MAX) – VOUT) × IOUT(MAX) (4) Power dissipation can be minimized, and greater efficiency can be achieved, by using the lowest available voltage drop option that would still be greater than the dropout voltage (VDO). However, keep in mind that higher voltage drops result in better dynamic (that is, PSRR and transient) performance. 14 Submit Documentation Feedback Copyright © 2007–2015, Texas Instruments Incorporated Product Folder Links: LP38513 LP38513 www.ti.com SNVS361E – JULY 2007 – REVISED NOVEMBER 2015 The maximum allowable junction temperature (TJ(MAX)) determines maximum power dissipation allowed (PD(MAX)) for the device package. Power dissipation and junction temperature are most often related by the junction-to-ambient thermal resistance (RθJA) of the combined PCB and device package and the temperature of the ambient air (TA), according to Equation 5 or Equation 6: TJ(MAX) = TA(MAX) + (RθJA × PD(MAX)) PD(MAX) = (TJ(MAX) - TA(MAX)) / RθJA (5) (6) Unfortunately, this RθJA is highly dependent on the heat-spreading capability of the particular PCB design, and therefore varies according to the total copper area, copper weight, and location of the planes. The RθJA recorded in Thermal Information is determined by the specific EIA/JEDEC JESD51-7 standard for PCB and copperspreading area, and is to be used only as a relative measure of package thermal performance. For a welldesigned thermal layout, RθJA is actually the sum of the package junction-to-case (bottom) thermal resistance (RθJCbot) plus the thermal resistance contribution by the PCB copper area acting as a heat sink. 8.2.2.4 Estimating Junction Temperature The EIA/JEDEC standard recommends the use of psi (Ψ) thermal characteristics to estimate the junction temperatures of surface mount devices on a typical PCB board application. These characteristics are not true thermal resistance values, but rather package specific thermal characteristics that offer practical and relative means of estimating junction temperatures. These psi metrics are determined to be significantly independent of copper-spreading area. The key thermal characteristics (ΨJT and ΨJB) are given in Thermal Information and are used in accordance with Equation 7 or Equation 8. TJ(MAX) = TTOP + (ΨJT × PD(MAX)) where • • PD(MAX) is explained in Equation 4. TTOP is the temperature measured at the center-top of the device package. (7) TJ(MAX) = TBOARD + (ΨJB × PD(MAX)) where • • PD(MAX) is explained in Equation 4. TBOARD is the PCB surface temperature measured 1-mm from the device package and centered on the package edge. (8) For more information about the thermal characteristics ΨJT and ΨJB, see the TI Application Report: Semiconductor and IC Package Thermal Metrics (SPRA953), available for download at www.ti.com. For more information about measuring TTOP and TBOARD, see the TI Application Report: Using New Thermal Metrics (SBVA025), available for download at www.ti.com. For more information about the EIA/JEDEC JESD51 PCB used for validating RθJA, see the TI Application Report: Thermal Characteristics of Linear and Logic Packages Using JEDEC PCB Designs (SZZA017), available for download at www.ti.com. Submit Documentation Feedback Copyright © 2007–2015, Texas Instruments Incorporated Product Folder Links: LP38513 15 LP38513 SNVS361E – JULY 2007 – REVISED NOVEMBER 2015 www.ti.com 8.2.3 Application Curves 10 mA to 3 A COUT = 10 µF Ceramic 10 mA to 3 A Figure 19. Load Transient 10 mA to 3 A COUT = 10 µF ceramic + 100 µF aluminum Figure 20. Load Transient COUT = 10 µF Ceramic 10 mA to 3 A Figure 21. Load Transient COUT = 10 µF Ceramic + 100 µF Aluminum Figure 22. Load Transient Figure 23. Line Transient 16 Submit Documentation Feedback Copyright © 2007–2015, Texas Instruments Incorporated Product Folder Links: LP38513 LP38513 www.ti.com SNVS361E – JULY 2007 – REVISED NOVEMBER 2015 9 Power Supply Recommendations The LP38513 device is designed to operate from an input supply voltage range of 2.25 V to 5.5 V. The input supply should be well-regulated and free of spurious noise. A minimum capacitor value of 10 μF is required. 10 Layout 10.1 Layout Guidelines The dynamic performance of the LP38513 is dependent on the layout of the PCB. PCB layout practices that are adequate for typical LDOs may degrade the PSRR, noise, or transient performance of the device. Best performance is achieved by placing CIN and COUT on the same side of the PCB as the LP38513, and as close to the package as is practical. The ground connections for CIN and COUT must be back to the LP38513 GND pin using as wide and short of a copper trace as is practical. Good PC layout practices must be used or instability can be induced because of ground loops and voltage drops. The input and output capacitors must be directly connected to the IN, OUT, and GND pins of the LP38513 using traces which do not have other currents flowing in them (Kelvin connect). The best way to do this is to lay out CIN and COUT near the device with short traces to the IN, OUT, and GND pins. The regulator ground pin must be connected to the external circuit ground so that the regulator and its capacitors have a single-point ground. Stability problems have been seen in applications where vias to an internal ground plane were used at the ground points of the LP38513 device and the input and output capacitors. This was caused by varying ground potentials at these nodes resulting from current flowing through the ground plane. Using a single point ground technique for the regulator and its capacitors fixed the problem. Because high current flows through the traces going into the IN pin and coming from the OUT pin, Kelvin connect the capacitor leads to these pins so there is no voltage drop in series with the input and output capacitors. EN IN GND OUT ERROR 10.2 Layout Example 1 2 3 4 5 VIN VOUT CIN COUT Figure 24. LP38513 Layout Submit Documentation Feedback Copyright © 2007–2015, Texas Instruments Incorporated Product Folder Links: LP38513 17 LP38513 SNVS361E – JULY 2007 – REVISED NOVEMBER 2015 www.ti.com 11 Device and Documentation Support 11.1 Related Documentation For additional information, see the following: • TI Application Report Using New Thermal Metrics (SBVA025) • TI Application Report Thermal Characteristics of Linear and Logic Packages Using JEDEC PCB Designs (SZZA017) 11.2 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 11.3 Trademarks E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 11.4 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 11.5 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 18 Submit Documentation Feedback Copyright © 2007–2015, Texas Instruments Incorporated Product Folder Links: LP38513 PACKAGE OPTION ADDENDUM www.ti.com 15-Oct-2015 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) LP38513S-1.8/NOPB ACTIVE DDPAK/ TO-263 KTT 5 45 Pb-Free (RoHS Exempt) CU SN Level-3-245C-168 HR -40 to 125 LP38513S -1.8 LP38513SX-1.8/NOPB ACTIVE DDPAK/ TO-263 KTT 5 500 Pb-Free (RoHS Exempt) CU SN Level-3-245C-168 HR -40 to 125 LP38513S -1.8 LP38513T-1.8/NOPB ACTIVE TO-220 NDH 5 45 Green (RoHS & no Sb/Br) CU SN Level-1-NA-UNLIM -40 to 125 LP38513T -1.8 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 15-Oct-2015 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 15-Oct-2015 TAPE AND REEL INFORMATION *All dimensions are nominal Device LP38513SX-1.8/NOPB Package Package Pins Type Drawing SPQ DDPAK/ TO-263 500 KTT 5 Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 330.0 24.4 Pack Materials-Page 1 10.75 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 14.85 5.0 16.0 24.0 Q2 PACKAGE MATERIALS INFORMATION www.ti.com 15-Oct-2015 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LP38513SX-1.8/NOPB DDPAK/TO-263 KTT 5 500 367.0 367.0 45.0 Pack Materials-Page 2 MECHANICAL DATA NDH0005D www.ti.com MECHANICAL DATA KTT0005B TS5B (Rev D) BOTTOM SIDE OF PACKAGE www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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