Siemens C513A-HN 8-bit cmos microcontroller Datasheet

Microcomputer Components
8-Bit CMOS Microcontroller
C511/C511A
C513/C513A
C513A-H
Data Sheet 06.96
Data Sheet C511/C511A/C513/C513A/C513A-H
Revision History :
Current Version : 06.96
Previous Releases :
02.96, 05.95
Page
Subjects (changes since last revision)
Several
41
Corrections of text
Figure 22: external clock configuration corrected
C511
C511A
C513
C513A
C513A-H
8-Bit CMOS Microcontroller Family
Preliminary
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Fully software compatible to standard 8051/8052 microcontrollers
Up to 12 MHz operating frequency
Up to 12 K×8 ROM / EEPROM
Up to 256×8 RAM
Up to 256 x 8 XRAM
Four 8-bit ports
Up to three 16-bit Timers / Counters (Timer 2 with Up/Down and 16-bit Autoreload Feature)
Synchronous Serial Channel (SSC)
Optional USART
Up to seven interrupt sources, two priority levels
Power Saving Modes
P-LCC-44 package (C513A also in P-MQFP-44 package)
TA : 0 ˚C to 70 ˚C
Temperature Ranges : SAB-C511 / 511A / 513 / 513A / C513A-H
TA : -40 ˚C to 85 ˚C
SAF-C513A
Semiconductor Group
3
06.96
C511 / C513
The C511, C511A, C513, C513A, and C513A-H are members of a family of low cost microcontrollers, which are software compatible with the components of the SAB 8051, SAB 80C51 and
C500 families.
The first four versions contains a non-volatile read-only (ROM) program memory. The C513A-H is
a version with a 12 Kbyte EEPROM instead of ROM. This device can be used for prototype designs
which have a demand for reprogrammable on-chip code memory.
The members of the microcontroller family differ in functionality according table 1. They offer
different ROM sizes, different RAM/XRAM sizes and a different timer/USART configuration.
Common to all devices is an advanced SSC serial port, a second synchronous serial interface,
which is compatible to the SPI serial bus industry standard. The functionality of the C513A-H is a
superset of all ROM versions of the C511/C513 family.
Table 1
Functionality of the C511/C513 MCUs
Device
ROM Size
EEPROM
Size
RAM
Size
XRAM
Size
Timers 1)
USART
SSC
C511
2.5 KB
–
128 B
–
T0, T1
–
✓
C511A
4 KB
–
256 B
–
T0, T1
–
✓
C513
8 KB
–
256 B
–
T0, T1, T2
✓
✓
C513A
12, 16 KB
–
256 B
256 B
T0, T1, T2
✓
✓
C513A-H
–
12 KB
256 B
256 B
T0, T1, T2
✓
✓
1)
T0/T1 refers to the standard 8051 timer 0/1 units, T2 refers to the 8052 timer 2 unit.
Figure 1
C511/513 Logic Symbol
Semiconductor Group
4
C511 / C513
Table 2
Ordering Information
Type
Ordering
Code
C511-RN
Q67120-DXXXX P-LCC-44
with mask-programmable ROM (2.5K), 12 MHz
C511A-RN
Q67120-DXXXX P-LCC-44
with mask-programmable ROM (4K), 12 MHz
C513-1RN
Q67120-DXXXX P-LCC-44
with mask-programmable ROM (8K), 12 MHz
C513A-RN
Q67120-DXXXX P-LCC-44
with mask-programmable ROM (12K), 12 MHz
Q67120-DXXXX P-LCC-44
with mask-programmable ROM (12K), 12 MHz,
ext. temp. – 40 ˚C to 85 ˚C
Q67120-DXXXX P-LCC-44
with mask-programmable ROM (16K), 12 MHz
Q67120-DXXXX P-LCC-44
with mask-programmable ROM (16K), 12 MHz,
ext. temp. – 40 ˚C to 85 ˚C
C513A-2RN
C513A-2RM
Package
Description
(8-Bit CMOS microcontroller)
Q67120-DXXXX P-MQFP-44 with mask-programmable ROM (16K), 12 MHz
Q67120-DXXXX P-MQFP-44 with mask-programmable ROM (16K), 12 MHz,
ext. temp. – 40 ˚C to 85 ˚C
C513A-LN
C513A-LM
C513A-HN
Q67120-C1017
P-LCC-44
for external memory (12 MHz)
Q67120-C1035
P-LCC-44
for external memory (12 MHz),
ext. temp. – 40 ˚C to 85 ˚C
Q67120-C1026
P-MQFP-44 for external memory (12 MHz)
Q67120-C1036
P-MQFP-44 for external memory (12 MHz),
ext. temp. – 40 ˚C to 85 ˚C
Q67120-C0989
P-LCC-44
with reprogrammable EEPROM (12K), 12 MHz,
ext. temp. – 40 ˚C to 85 ˚C
Note : The ordering number of the ROM types (DXXXX extension) is defined after program release
(verification) of the customer.
Semiconductor Group
5
C511 / C513
Figure 2
P-LCC-44 Package Pin Configuration (Top View)
If the C513A-H is used in programming mode, the pin configuration is different to figure 2 and 3 (see
figure 5).
Semiconductor Group
6
C511 / C513
Figure 3
P-MQFP-44 Package Pin Configuration of the C513A (Top View)
Semiconductor Group
7
C511 / C513
Table 3
Pin Definitions and Functions
Symbol
Pin Number
I/O*) Function
P-LCC- P-MQFP44
44
P1.7-P1.0
9-2
3-1,
44-40
I/O
Port 1
is a bidirectional I/O port with internal pull-up resistors.
Port 1 pins that have 1s written to them are pulled high by
the internal pullup resistors, and in that state can be used
as inputs. As inputs, port 1 pins being externally pulled
low will source current (IIL, in the DC characteristics)
because of the internal pullup resistors. Port 1 also
contains the timer 2 and SSC pins as secondary function.
In general the output latch corresponding to a secondary
function must be programmed to a one (1) for that
function to operate.
For the outputs of the SSC (SCLK, STO) special circuitry
is implemented, providing true push-pull capability. The
STO output in addition will have true tristate capability.
When used for SSC inputs, the pull-up resistors will be
switched off and the inputs will float (high ohmic inputs).
The alternate functions are assigned to port 1, as follows:
2
3
40
41
P1.0
P1.1
T2
T2EX
4
42
P1.2
SCLK
5
6
7
43
44
1
P1.3
P1.4
P1.5
SRI
STO
SLS
Input to counter 2 1)
Capture -Reload trigger of timer 2
Up-Down count
SSC Master Clock Output
SSC Slave Clock Input
SSC Receive Input
SSC Transmit Output
Slave Select Input
1) not available in the C511/511A
*) I = Input
O = Output
Semiconductor Group
8
1)
C511 / C513
Table 3
Pin Definitions and Functions (cont’d)
Symbol
Pin Number
I/O*) Function
P-LCC- P-MQFP44
44
P3.0-P3.7
11,
13-19
5, 7-13
I/O
Port 3
is a bidirectional I/O port with internal pull-up resistors.
Port 3 pins that have 1s written to them are pulled high by
the internal pullup resistors, and in that state can be used
as inputs. As inputs, port 3 pins being externally pulled
low will source current (IIL, in the DC characteristics)
because of the internal pullup resistors. Port 3 also
contains the interrupt, timer, serial port and external
memory strobe pins that are used by various options. The
output latch corresponding to a secondary function must
be programmed to a one (1) for that function to operate.
The secondary functions are assigned to the pins of port
3 as follows:
11
5
P3.0
RXD
13
7
P3.1
TXD
14
15
16
17
18
8
9
10
11
12
P3.2
P3.3
P3.4
P3.5
P3.6
INT0
INT1
T0
T1
WR
19
13
P3.7
RD
1)
XTAL2
20
14
–
not available in the C511/511A
XTAL2
Output of the inverting oscillator amplifier.
*) I = Input
O = Output
Semiconductor Group
Receiver data input (asynchronous)
or data input/output (synchronous)
of serial interface (USART) 1)
Transmitter data output (USART) 1)
(asynchronous) or clock output
(synchronous) of serial interface
Interrupt 0 input / timer 0 gate control
Interrupt 1 input / timer 1 gate control
Counter 0 input
Counter 1 input
Write control signal : latches the data
byte from port 0 into the external
data memory
Read control signal : enables the
external data memory to port 0
9
C511 / C513
Table 3
Pin Definitions and Functions (cont’d)
Symbol
Pin Number
I/O*) Function
P-LCC- P-MQFP44
44
XTAL1
21
15
–
XTAL1
Input to the inverting oscillator amplifier and input to the
internal clock generator circuits.
To drive the device from an external clock source, XTAL1
should be driven, while XTAL2 is left unconnected. There
are no requirements on the duty cycle of the external
clock signal, since the input to the internal clocking
circuitry is divided down by a divide-by-two flip-flop.
Minimum and maximum high and low times as well as
rise/fall times specified in the AC characteristics must be
observed.
P2.0-P2.7
24-31
18-25
I/O
Port 2
is a bidirectional I/O port with internal pullup resistors.
Port 2 pins that have 1s written to them are pulled high by
the internal pullup resistors, and in that state can be used
as inputs. As inputs, port 2 pins being externally pulled
low will source current (IIL, in the DC characteristics)
because of the internal pullup resistors. Port 2 emits the
high-order address byte during fetches from external
program memory and during accesses to external data
memory that use 16-bit addresses (MOVX @DPTR). In
this application it uses strong internal pullup resistors
when issuing 1s. During accesses to external data
memory that use 8-bit addresses (MOVX @Ri), port 2
issues the contents of the P2 special function register.
PSEN
32
26
O
The Program Store Enable
output is a control signal that enables the external
program memory to the bus during external fetch
operations. It is activated every six oscillator periodes
except during external data memory accesses. Remains
high during internal program execution.
RESET
10
4
I
RESET
A high level on this pin for two machine cycles while the
oscillator is running resets the device. An internal resistor
to VSS permits power-on reset using only an external
capacitor to VCC.
*) I = Input
O = Output
Semiconductor Group
10
C511 / C513
Table 3
Pin Definitions and Functions (cont’d)
Symbol
Pin Number
I/O*) Function
P-LCC- P-MQFP44
44
ALE
33
27
O
The Address Latch Enable
output is used for latching the low-byte of the address into
external memory during normal operation. It is activated
every six oscillator periodes except during an external
data memory access.
If no external memory is used, the ALE signal generation
can be inhibited, reducing system RFI, by clearing
register bit EALE in the SYSCON register.
EA
35
29
I
External Access Enable
When held at high level, instructions are fetched from the
internal ROM when the PC is less than the size of the
internal ROM :
C511
0A00H
C511A
1000H
C513
2000H
C513A/A-H
3000H
C513A-2R
4000H
When held at low level, the microcontroller fetches all
instructions from external program memory.
P0.0-P0.7
43-36
37-30
I/O
Port 0
is an 8-bit open-drain bidirectional I/O port. Port 0 pins
that have 1s written to them float, and in that state can be
used as high-impendance inputs. Port 0 is also the
multiplexed low-order address and data bus during
accesses to external program or data memory. In this
application it uses strong internal pullup transistors when
issuing 1s. External pullup resistors are required during
program verification.
VSS
22
16
–
Circuit ground potential
VCC
44
38
–
Power Supply terminal for all operating modes
N.C.
1, 12,
23, 34
6, 17,
28, 39
–
No connection, do not connect externally
*) I = Input
O = Output
Semiconductor Group
11
C511 / C513
Figure 4
C513A-H Logic Symbol in Programming Mode
Figure 5
C513A-H Pin Configuration in Programming Mode (P-LCC-44)
Semiconductor Group
12
C511 / C513
Table 4
Pin Definitions and Functions in Programming Mode (C513A-H only)
Symbol
Pin Number
I/O*) Function
P-LCC-44
PRES
15
I
Programming Interface Reset
A high level on this input resets the programming interface and
its registers to their initial state.
AD0 - AD7 43 - 36
I/O
Bidirectional Address/Data Bus
AD0-7 is used to transfer data to and from the registers of the
programming interface and to read the data of the memory field
during EEPROM verification.
PALE
16
I
Programming Address Latch Enable
This input is used to latch address information at AD0-7. The
trailing edge of PALE is used to latch the register addresses.
Each read or write access in programming mode must be
initiated by a PALE high pulse.
PRD
18
I
Programming Read Control
A low level at this pin (and PCS=low) enables the AD0-7 buffers
for reading of the data or control registers of the programming
interface.
PWR
19
I
Programming Write Control
A low level at this pin (and PCS=low) causes the data at AD07 to be written into the data or control registers of the
programming interface.
PCS
17
I
Programming Chip Select
A low level at this pin enables the access to the registers of the
programming interface. If PCS is active, either PRD or PWR
control whether data is read or written into the registers.
PCS should be always deactivated between subsequent
accesses to the programming interface.
XTAL2
20
–
XTAL2
Output of the inverting oscillator amplifier.
XTAL1
21
–
XTAL1
Input to the inverting oscillator amplifier and input to the internal
clock generator circuits.
To drive the device from an external clock source, XTAL1
should be driven, while XTAL2 is left unconnected. During the
device programming a clock must be always supplied.
*) I = Input
O = Output
Semiconductor Group
13
C511 / C513
Table 4
Pin Definitions and Functions in Programming Mode (C513A-H only) (cont’d)
Symbol
Pin Number
I/O*) Function
P-LCC-44
PMS0
PMS1
PMS2
PMS3
35
33
32
10
I
Programming Mode Select
PMS0-3 are used to put the C513A-H into the program-ming
mode. In normal mode the programming mode select pins have
the meaning as shown in the table below. PMS0-3 must be set
to the logic level as described in the table below.
Normal Mode
Pin Names
Progr. Mode
Pin Names
Required
Logic Level
EA
PMS0
0
ALE
PMS1
1
PSEN
PMS2
0
RESET
PMS3
1
VSS
22
–
Circuit ground potential
VCC
44
–
Power supply terminal for all operating modes
N.C.
1-9, 11-14,
23-31, 34
–
No connection
These pins must not be connected.
*) I = Input
O = Output
Semiconductor Group
14
C511 / C513
Functional Description
The C511/C513 microcontrollers are fully compatible to the standard 8051/80C52 and C500
microcontroller family. While maintaining all architectural and operational characteristics of the
80C52/C500 the C511/C513 incorporates enhancements such as additional internal XRAM and a
second (synchronous) serial interface unit.
Figure 6 shows a block diagram of the C511/C513 microcontroller family.
Figure 6
Block Diagram of the C511/C513 Units
Semiconductor Group
15
C511 / C513
CPU
The C511/C513 are efficient both as a controller and as an arithmetic processor. It has extensive
facilities for binary and BCD arithmetic and for bit-handling capabilities. Efficient use of program
memory results from an instruction set consisting of 44 % one-byte, 41 % two-byte, and 15 % threebyte instructions. With a 12 MHz crystal, 58 % of the instructions execute in 1 µs.
Special Function Register PSW (Address D0H)
Bit No.
D0H
Reset Value : 00H
MSB
7
6
5
4
3
2
1
LSB
0
CY
AC
F0
RS1
RS0
OV
F1
P
PSW
Bit
Function
CY
Carry Flag
AC
Auxiliary Carry Flag (for BCD operations)
F0
General Purpose Flag
RS1 RS0
0
0
0
1
1
0
1
1
Register Bank select control bits
Bank 0 selected, data address 00H-07H
Bank 1 selected, data address 08H-0FH
Bank 2 selected, data address 10H-17H
Bank 3 selected, data address 18H-1FH
OV
Overflow Flag
F1
General Purpose Flag
P
Parity Flag
Set/cleared by hardware each instruction cycle to indicate an odd/even number of
"one" bits in the accumulator, i.e. even parity.
Semiconductor Group
16
C511 / C513
Special Function Registers
All registers except the program counter and the four general purpose register banks reside in the
special function register area.
The 34 special function registers (SFR) include pointers and registers that provide an interface
between the CPU and the other on-chip peripherals. There are also 128 directly addressable bits
within the SFR area.
All SFRs are listed in table 5 and table 6. In table 5 they are organized in groups which refer to the
functional blocks of the C511/C513. Table 6 illustrates the contents of the SFRs, e.g. the bits of the
SFRs, in numeric order of their addresses.
Semiconductor Group
17
C511 / C513
Table 5
SFRs - Functional Blocks
Block
Symbol
Name
Address
Contents after
Reset
CPU
ACC
B
DPH
DPL
PSW
SP
SYSCON
Accumulator
B-Register
Data Pointer, High Byte
Data Pointer, Low Byte
Program Status Word
Stack Pointer
System Control Reg. C511/C511A/C513
C513A/C513A-H
E0H 1)
F0H 1)
83H
82H
D0H 1)
81H
B1H
B1H
00H
00H
00H
00H
00H
07H
101X0XXXB 3)
101X0XX0B 3)
Interrupt
System
IE
IP
Interrupt Enable Register
Interrupt Priority Register
A8H1)
B8H 1)
00H
X0000000B 3)
Ports
P0
P1
P2
P3
Port 0
Port 1
Port 2
Port 3
80H 1)
90H 1)
A0H 1)
B0H 1)
FFH
FFH
FFH
FFH
SSC
SSCCON
STB
SRB
SCF
SCIEN
SSCMOD
SSC Control Register
SSC Transmit Buffer
SSC Receive Register
SSC Flag Register
SSC Interrupt Enable Register
SSC Mode Test Register
E8H 1)
E9H
EAH
F8H 1)
F9H
EBH
07H
XXH 3)
XXH 3)
XXXXXX00B 3)
XXXXXX00B 3)
00H
USART
PCON
SBUF
SCON
Power Control Register
Serial Channel Buffer Register
Serial Channel 1 Control Register
87H
99H
98H 1)
0XXX0000B 3)
XXH 3)
00H
Timer 0 /
Timer 1
TCON
TMOD
TL0
TL1
TH0
TH1
Timer Control Register
Timer Mode Register
Timer 0, Low Byte
Timer 1, Low Byte
Timer 0, High Byte
Timer 1, High Byte
88H 1)
89H
8AH
8BH
8CH
8DH
00H
00H
00H
00H
00H
00H
Timer 2
T2CON
T2MOD
RC2L
RC2H
TL2
TH2
Timer 2 Control Register
Timer 2 Mode Register
Timer 2 Reload/Capture Register, Low Byte
Timer 2 Reload/Capture Register, High Byte
Timer 2 Low Byte
Timer 2 High Byte
C8H 1)
C9H
CAH
CBH
CCH
CDH
00H
XXXXXXX0B 3)
00H
00H
00H
00H
Power Control Register
87H
0XXX0000B 3)
Power
PCON
Save Mode
1)
2)
3)
2)
2)
Bit-addressable special function registers
This special function register is listed repeatedly since some bits of it also belong to other functional blocks.
X means that the value is indeterminate and the location is reserved
Semiconductor Group
18
C511 / C513
Table 6
Contents of the SFRs, SFRs in Numeric Order of their Addresses
Addr Register
Content
after
Reset 1)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
80H
81H
P0
FFH
07H
.7
.6
.5
.4
.3
.2
.1
.0
.7
.6
.5
.4
.3
.2
.1
.0
82H
83H
DPL
00H
00H
.7
.6
.5
.4
.3
.2
.1
.0
.7
.6
.5
.4
.3
.2
.1
.0
87H
PCON
0XXX0000B
SMOD
–
–
–
GF1
GF0
PDE
IDLE
88H
89H
TCON
00H
00H
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
GATE
C/T
M1
M0
GATE
C/T
M1
M0
8AH
8BH
TL0
00H
00H
.7
.6
.5
.4
.3
.2
.1
.0
.7
.6
.5
.4
.3
.2
.1
.0
8CH
8DH
TH0
00H
00H
.7
.6
.5
.4
.3
.2
.1
.0
.7
.6
.5
.4
.3
.2
.1
.0
90H
98H
P1
FFH
00H
–
–
SLS
STO
SRI
SCLK
T2EX
T2
SM0
SM1
SM2
REN
TB8
RB8
TI
RI
99H
A0H
SBUF
XXH
FFH
.7
.6
.5
.4
.3
.2
.1
.0
.7
.6
.5
.4
.3
.2
.1
.0
EAL
ESSC
ET2
ES0
ET1
EX1
ET0
EX0
RD
WR
T1
T0
INT1
INT0
TxD0
RxD0
1
0
EALE
–
0
–
–
XMAP2)
A8H
B0H
SP
DPH
TMOD
TL1
TH1
SCON
P2
IE
P3
SYSCON
00H
FFH
2)
B1H
B8H
IP
X0000000B
–
PSSC
PT2
PS
PT1
PX1
PT0
PX0
C8H
T2CON
00H
TF2
EXF2
RCLK
TCLK
EXEN2
TR2
C/T2
CP/
RL2
C9H
T2MOD
–
–
–
–
–
–
–
DCEN
CAH
CBH
RC2L
XXXXXXX0B
00H
.7
.6
.5
.4
.3
.2
.1
.0
.7
.6
.5
.4
.3
.2
.1
.0
CCH
CDH
TL2
00H
00H
.7
.6
.5
.4
.3
.2
.1
.0
.7
.6
.5
.4
.3
.2
.1
.0
D0H
E0H
PSW
CY
AC
F0
RS1
RS0
OV
F1
P
.7
.6
.5
.4
.3
.2
.1
.0
E8H
E9H
SSCCON
00H
07H
SCEN
TEN
MSTR
CPOL
CPHA
BRS2
BRS1
BRS0
.7
.6
.5
.4
.3
.2
.1
.0
EAH
EBH
SRB
XXH
XXH
.7
.6
.5
.4
.3
.2
.1
.0
0
0
0
0
0
0
0
0
F0H
B
.7
.6
.5
.4
.3
.2
.1
.0
RC2H
TH2
ACC
STB
SSCMOD
00H
00H
00H
00H
Semiconductor Group
3)
19
C511 / C513
Table 6
Contents of the SFRs, SFRs in Numeric Order of their Addresses (cont’d)
Addr Register
Content
after
Reset 1)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
F8H
XXXXXX00B
–
–
–
–
–
–
WCOL
TC
XXXX–
–
–
–
–
–
WCEN TCEN
XX00B
X means that the value is indeterminate and the location is reserved.
The availability of the XMAP bit and the reset value of SYSCON depends on the specific microcontroller :
C511/C511A/C513 :
101X0XXXB - bit XMAP is not available
C513A/C513A-H :
101X0XX0B - bit XMAP is available
This register ist only used for test purposes and must not be written. Otherwise unpredictable results may
occur.
Shaded registers are bit-addressable special function registers.
F9H
1)
2)
3)
SCF
SCIEN
Semiconductor Group
20
C511 / C513
Timer/ Counter 0 and 1
Timer/Counter 0 and 1 can be used in four operating modes as listed in table 7:
Table 7
Timer/Counter 0 and 1 operating modes
Mode Description
TMOD
Input Clock
Gate
C/T
M1
M0
internal
external (max)
0
8-bit timer/counter with a
divide-by-32 prescaler
X
X
0
0
fOSC/12 × 32
fOSC/24 × 32
1
16-bit timer/counter
X
X
0
1
fOSC/12
fOSC/24
2
8-bit timer/counter with
8-bit auto-reload
X
X
1
0
fOSC/12
fOSC/24
3
Timer/counter 0 used as one
8-bit timer/counter and one
8-bit timer
Timer 1 stops
X
X
1
1
fOSC/12
fOSC/24
In “timer” function (C/T = ‘0’) the register is incremented every machine cycle. Therefore the count
rate is fOSC/12.
In “counter” function the register is incremented in response to a 1-to-0 transition at its
corresponding external input pin (P3.4/T0, P3.5/T1). Since it takes two machine cycles to detect a
falling edge the max. count rate is fOSC/24. External inputs INT0 and INT1 (P3.2, P3.3) can be
programmed to function as a gate to facilitate pulse width measurements. Figure 7 illustrates the
input clock logic.
Figure 7
Timer/Counter 0 and 1 Input Clock Logic
Semiconductor Group
21
C511 / C513
Timer / Counter 2 (not available in the C511/C511A)
Timer 2 is a 16-bit Timer/Counter with up/down count feature. It can operate either as timer or as an
event counter which is selected by bit C/T2 (T2CON.1). It has three operating modes as shown in
table 8.
Table 8
Timer/Counter 2 Operating Modes
T2CON
Mode
T2MOD T2CON
R×CLK
or
T×CLK
CP/
RL2
TR2
0
0
0
0
16-bit
Autoreload
Input Clock
P1.1/
Remarks
T2EX
DCEN
EXEN
1
0
0
X
1
0
1
↓
0
0
0
0
1
1
1
1
X
X
0
1
0
1
1
X
0
X
0
1
1
X
1
↓
Baud
Rate
Generator
1
X
1
X
0
X
1
X
1
X
1
↓
off
X
X
0
X
X
X
16-bit
Capture
Note: ↓ =
falling edge
Semiconductor Group
22
internal
external
(P1.0/T2)
reload upon
overflow
reload trigger
(falling edge)
Down counting
Up counting
fOSC/12
16-bit Timer/
Counter (only
up-counting)
capture TH2,
TL2 → RC2H,
RC2L
fOSC/12
no overflow
interrupt
request (TF2)
extra external
interrupt
(“Timer 2”)
fOSC/2
max
fOSC/24
Timer 2 stops
–
–
max
fOSC/24
max
fOSC/24
C511 / C513
Serial Interface (USART, not available in the C511/C511A)
The serial port is full duplex and can operate in four modes (one synchronous mode, three
asynchronous modes) as illustrated in table 9. Figure 8 illustrates the block diagram of Baudrate
generation for the serial interface.
Table 9
USART Operating Modes
Mode
SCON
Baudrate
Description
SM0
SM1
0
0
0
fOSC/12
1
0
1
Timer 1/2 overflow rate
2
1
0
fOSC/32 or fOSC/64
9-bit UART
11 bits are transmitted (T×D) or
received (R×D)
3
1
1
Timer 1/2 overflow rate
9-bit UART
Like mode 2 except the variable
baud rate
Serial data enters and exits through R×D.
T×D outputs the shift clock. 8-bit are
transmitted/received (LSB first)
8-bit UART
10 bits are transmitted (through T×D) or
received (R×D)
Figure 8
Block Diagram of Baud Rate Generation for the Serial Interface
Semiconductor Group
23
C511 / C513
The possible baudrates can be calculated using the formulas given in table 10.
Table 10
Baudrates Selection
Baud rate
derived from
Interface Mode
Baudrate
Oscillator
0
2
fOSC/12
(2SMOD × fOSC)/64
Timer 1 (16-bit timer)
(8-bit timer with
8-bit autoreload)
1,3
1,3
(2SMOD × timer 1 overflow rate)/32
(2SMOD × fOSC)/(32 × 12 × (256-TH1))
Timer 2
1,3
fOSC/(32 × (65536-(RC2H, RC2L))
Semiconductor Group
24
C511 / C513
Synchronous Serial Channel (SSC)
The C511/C513 microcontrollers provide a Synchronous Serial Channel unit, the SSC. This
interface is compatible to the popular SPI serial bus interface. It can be used for simple I/O
expansion via shift registers, for connection of a variety of peripheral components, such as A/D
converters, EEPROMs etc., or for allowing several microcontrollers to be interconnected in a
master/slave structure. It supports full-duplex or half-duplex operation and can run in a master or a
slave mode. Figure 9 shows the block diagram of the SSC.
Figure 9
SSC Blockdiagram
Semiconductor Group
25
C511 / C513
Additional On-Chip XRAM (not available in the C511/C511A/C513)
The C513A/C513A-H contain another 256 byte of on-chip RAM additional to the 256 byte internal
RAM. This RAM is called XRAM (‘eXtended RAM’).
The additional on-chip XRAM is logically located in the external data memory range from address
FF00H to FFFFH. The contents of the XRAM are not affected by a reset. After power up the content
is undefined, while it remains unchanged during and after reset as long as the power supply is not
turned off. The XRAM is controlled by SFR SYSCON as shown in table 11.
Table 11
Control of the XRAM
SFR SYSCON
Bit XMAP
Description
0
Reset value. Access to XRAM is disabled.
1
XRAM enabled. The signals RD and WR are not activated during MOVX
accesses in the XRAM address range.
The XRAM is accessed as external data memory. Therefore, MOVX instruction types must be used
for accessing the XRAM. A general overview gives table 12.
Table 12
Accessing the XRAM
Instruction
using
Instruction
DPTR
(16-bit addr.)
MOVX A @DPTR
MOVX @DPTR,A
R0/R1
(8-bit addr.)
MOVX A, @Ri
MOVX @Ri,A
Semiconductor Group
Remarks
Normally the use of these instructions would use a
physically external memory. However, in the C513A/
C513A-H the XRAM is accessed if it is enabled by bit
XMAP and the 16-bit address (DPTR) is within the
XRAM address range FF00H - FFFFH.
If XRAM is enabled in the C513A/C513A-H, MOVX
instructions using Ri will always access the internal
XRAM. External data memory cycles will not be
generated in this case. If the XRAM is disabled, MOVX
instructions using Ri will generate normal external data
memory cycles.
26
C511 / C513
Interrupt System
The C511/C513 provide 7 interrupt sources with two priority levels. Figure 10 gives a general
overview of the interrupt sources and illustrates the request and control flags.
Figure 10
Interrupt Request Sources
Semiconductor Group
27
C511 / C513
Table 13
Interrupt Sources and their Corresponding Interrupt Vectors
Source (Request Flags)
Vector
Vector Address
IE0
TF0
IE1
TF1
RI + TI
External interrupt 0
Timer 0 interrupt
External interrupt 1
Timer 1 interrupt
USART serial port interrupt,
(C513/C513A/C513A-H only)
Timer 2 interrupt
Synchronous serial channel
interrupt (SSC)
0003H
000BH
0013H
001BH
0023H
TF2 + EXF2
SSCI
002BH
0043H
A low-priority interrupt can itself be interrupted by a high-priority interrupt, but not by another lowpriority interrupt. A high-priority interrupt cannot be interrupted by any other interrupt source.
If two requests of different priority level are received simultaneously, the request of higher priority is
serviced. If requests of the same priority are received simultaneously, an internal polling sequence
determines which request is serviced. Thus within each priority level there is a second priority
structure determined by the polling sequence as shown in table 14.
Table 14
Priority-within-Level Structure
Interrupt Source
External Interrupt 0,
Synchronous Serial Channel
Timer 0 Interrupt,
External Interrupt 1,
Timer 1 Interrupt,
Universal Serial Channel,
Timer 2 Interrupt,
Semiconductor Group
Priority
IE0
SSC
TF0
IE1
TF1
RI or TI
TF2 or EXF2
High
↓
Low
28
C511 / C513
Power Saving Modes
Two power down modes are available, the idle mode and the power down mode. In the idle mode
only the CPU will be deactivated while in the power down mode the on-chip oscillator is stopped.
The bits PDE and IDLE select the power down mode or the idle mode, respectively. If the power
down mode and the idle mode are set at the same time, power down takes precedence. Table 15
gives a general overview of the power saving modes.
Table 15
Entering and leaving the power saving modes
Mode
Entering
Example
Leaving by
Remarks
Idle mode
ORL PCON, #01H
– enabled interrupt
– Hardware Reset
CPU is gated off
CPU status registers maintain
their data.
Peripherals are active
Power Down
Mode
ORL PCON, #02H
Hardware Reset
Oscillators are stopped. Contents
of on-chip RAM and SFR’s are
maintained
(leaving power down mode means
redefinition of SFR’s contents)
In the power down mode of operation, VCC can be reduced to minimize power consumption. It must
be ensured, however, that VCC is not reduced before the power down mode is invoked, and that VCC
is restored to its normal operating level, before the power down mode is terminated. The reset signal
that terminates the power down mode also restarts the oscillator. The reset should not be activated
before VCC is restored to its normal operating level and must be held active long enough to allow the
oscillator to restart and stabilize (similar to power-on reset).
Semiconductor Group
29
C511 / C513
Absolute Maximum Ratings
Ambient temperature under bias (TA) .............................................................. 0 ˚C to + 70 ˚C
Storage temperature (TST) ...............................................................................– 65 ˚C to + 150 ˚C
Voltage on VCC pins with respect to ground (VSS) ............................................– 0.5 V to 6.5 V
Voltage on any pin with respect to ground (VSS) ..............................................– 0.5 V to VCC + 0.5 V
Input current on any pin during overload condition..........................................– 10 mA to + 10 mA
Absolute sum of all input currents during overload condition ..........................| 100 mA |
Power dissipation.............................................................................................TBD
Note:
Stresses above those listed under “Absolute Maximum Ratings” may cause permanent
damage of the device. This is a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for longer
periods may affect device reliability. During overload conditions (VIN > VCC or VIN < VSS) the
Voltage on VCC pins with respect to ground (VSS) must not exceed the values defined by the
absolute maximum ratings.
Semiconductor Group
30
C511 / C513
DC Characteristics
VCC = 5 V + 10 %, – 15 %; VSS = 0 V;
Parameter
TA = 0 to + 70 ˚C
Symbol
Limit Values
min.
max.
Unit Test Condition
Input low voltage
(except EA, RESET)
VIL
– 0.5
0.2 VCC
– 0.1
V
–
Input low voltage (EA)
VIL1
– 0.5
0.2 VCC
– 0.3
V
–
Input low voltage (RESET)
VIL2
– 0.5
0.2 VCC
+ 0.1
V
–
Input high voltage
(except EA, RESET, XTAL1)
VIH
0.2 VCC
+ 0.9
VCC + 0.5
V
–
Input high voltage to XTAL1
VIH1
0.7 VCC
VCC + 0.5
V
–
Input high voltage to EA, RESET VIH2
0.6 VCC
VCC + 0.5
V
–
Output low voltage
Ports 1, 2, 3 (except P1.2, P1.4)
Port 0, ALE, PSEN
P1.2 / P1.4 pull-down transistor
resistance
VOL
VOL1
RDSon
–
–
–
0.45
0.45
120
V
Ω
IOL = 1.6 mA 1)
IOL = 3.2 mA 1)
VOL = 0.45 V
VOH
–
–
–
–
120
V
V
V
V
Ω
IOH = – 80 µA
IOH = – 10 µA
IOH = – 800 µA
IOH = – 80 µA
VOH = 0.9 VCC
Output high voltage
Ports 1, 2, 3
V
Port 0 in ext. bus mode, ALE,
PSEN
P1.2 / P1.4 pull-up transistor
resistance
VOH1
RDSon
2.4
0.9 VCC
2.4
0.9 VCC
–
Logic 0 input current
(Ports 1, 2, 3)
IIL
– 10
– 50
µA
VIN = 0.45 V
Logical 1-to-0 transition current
(Ports 1, 2, 3)
ITL
– 65
– 650
µA
VIN = 2 V
Maximum output low current per
pin (Ports 0, 1, 2, 3)
IOLM
–
5
mA
VOL ≤ 1 V
Maximum output low current per
port
IPL
–
30
mA
–
ILI
–
±1
µA
0.45 < VIN < VCC
CIO
–
10
pF
fC = 1 MHz,
TA = 25 ˚C
Input leakage current
Port 0 (if EA=0), EA,
P1.2, P1.3, P1.5 as SSC inputs
Pin capacitance
7)
Semiconductor Group
31
C511 / C513
DC Characteristics (cont’d)
VCC = 5 V + 10 %, – 15 %; VSS = 0 V;
Parameter
Power supply current:
C511/C511A/C513/C513A
Active mode, 12 MHz 6)
Idle mode, 12 MHz 6)
Power Down Mode
C513A-H
Active mode, 12 MHz 6)
Idle mode, 12 MHz 6)
Power Down Mode
Symbol
TA = 0 to + 70 ˚C
Limit Values
Unit Test Condition
typ. 8)
max.
ICC
ICC
IPD
7
3.5
TBD
9.5
4.5
50
mA
mA
µA
VCC = 5 V,4)
VCC = 5 V,5)
VCC = 2 … 5.5 V,3)
ICC
ICC
IPD
16
6
TBD
TBD
TBD
50
mA
mA
µA
VCC = 5 V,4)
VCC = 5 V,5)
VCC = 2 … 5.5 V3)
Notes:
1)
Capacitive loading on ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOL of ALE
and port 3. The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these
pins make 1-to-0 transitions during bus operation. In the worst case (capacitive loading > 100 pF), the noise
pulse on ALE line may exceed 0.8 V. In such cases it may be desirable to qualify ALE with a schmitt-trigger,
or use an address latch with a schmitt-trigger strobe input.
2)
Capacitive loading on ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall bellow the
0.9 VCC specification when the address lines are stabilizing.
3)
IPD (Power Down Mode) is measured under following conditions:
EA = Port0 = VCC; RESET = VSS; XTAL2 = N.C.; XTAL1 = VCC; all other pins are disconnected.
4)
ICC (active mode) is measured with:
XTAL1 driven with tCLCH, tCHCL = 5 ns, VIL = VSS + 0.5 V, VIH = VCC – 0.5 V; XTAL2 = N.C.;
EA = Port0 = RESET = VCC; all other pins are disconnected. ICC would be slightly higher if a crystal oscillator
is used (appr. 1 mA).
5)
ICC (Idle mode) is measured with all output pins disconnected and with all peripherals disabled;
XTAL1 driven with tCLCH, tCHCL = 5 ns, VIL = VSS + 0.5 V, VIH = VCC – 0.5 V; XTAL2 = N.C.;
RESET = EA = VSS; Port0 = VCC; all other pins are disconnected;
6)
ICC Max at other frequencies is given by:
C511/C511A/C513/C513A : Active mode: TBD
Idle mode:
TBD
C513A-H :
Active mode: TBD
Idle mode:
TBD
where fOSC is the oscillator frequency in MHz. ICC values are given in mA and measured at VCC = 5 V.
7)
This parameter is periodically sampled and not 100% tested.
8)
The typical ICC values are periodically measured at TA = +25 ˚C but not 100% tested.
Semiconductor Group
32
C511 / C513
AC Characteristics (applies to all C511/513 Family Microcontrollers)
VCC = 5 V + 10 %, – 15 %; VSS = 0 V
TA = 0 ˚C to + 70 ˚C
(CL for port 0, ALE and PSEN outputs = 100 pF; CL for all other outputs = 80 pF)
Program Memory Characteristics
Parameter
Symbol
Limit Values
12 MHz
Clock
Unit
Variable Clock
1/tCLCL = 3.5 MHz to 12 MHz
min.
max.
min.
max.
ALE pulse width
tLHLL
127
–
2tCLCL – 40
–
ns
Address setup to ALE
tAVLL
43
–
tCLCL – 40
–
ns
Address hold after ALE
tLLAX
60
–
tCLCL – 23
–
ns
ALE low to valid instr in
tLLIV
–
233
–
4tCLCL – 100
ns
ALE to PSEN
tLLPL
58
–
tCLCL – 25
–
ns
PSEN pulse width
tPLPH
215
–
3tCLCL – 35
–
ns
PSEN to valid instr in
tPLIV
–
150
–
3tCLCL – 100
ns
Input instruction hold after PSEN
tPXIX
0
–
0
–
ns
Input instruction float after PSEN
tPXIZ*)
–
63
–
tCLCL – 20
ns
Address valid after PSEN
tPXAV*)
75
–
tCLCL – 8
–
ns
Address to valid instr in
tAVIV
–
302
–
5tCLCL – 115
ns
Address float to PSEN
tAZPL
0
–
0
–
ns
*) Interfacing the C511/513 microcontrollers to devices with float times up to 75 ns is permissible. This limited
bus contention will not cause any damage to port 0 drivers.
Semiconductor Group
33
C511 / C513
External Data Memory Characteristics
Parameter
Symbol
Limit Values
12 MHz
Clock
Unit
Variable Clock
1/tCLCL = 3.5 MHz to 12 MHz
min.
max.
min.
max.
RD pulse width
tRLRH
400
–
6tCLCL – 100
–
ns
WR pulse width
tWLWH
400
–
6tCLCL – 100
–
ns
Address hold after ALE
tLLAX2
132
–
2tCLCL – 35
–
ns
RD to valid data in
tRLDV
–
252
–
5tCLCL – 165
ns
Data hold after RD
tRHDX
0
–
0
–
ns
Data float after RD
tRHDZ
–
97
–
2tCLCL – 70
ns
ALE to valid data in
tLLDV
–
517
–
8tCLCL – 150
ns
Address to valid data in
tAVDV
–
585
–
9tCLCL – 165
ns
ALE to WR or RD
tLLWL
200
300
3tCLCL – 50
3tCLCL + 50
ns
Address valid to WR or RD
tAVWL
203
–
4tCLCL – 130
–
ns
WR or RD high to ALE high
tWHLH
43
123
tCLCL – 40
tCLCL + 40
ns
Data valid to WR transition
tQVWX
33
–
tCLCL – 50
–
ns
Data setup before WR
tQVWH
433
–
7tCLCL – 150
–
ns
Data hold after WR
tWHQX
33
–
tCLCL – 50
–
ns
Address float after RD
tRLAZ
–
0
–
0
ns
Semiconductor Group
34
C511 / C513
SSC Interface Characteristics
Parameter
Symbol
Limit Values
Unit
12 MHz Clock
min.
max.
Clock Cycle Time : Master Mode
Slave Mode
tSCLK
tSCLK
666
600
–
–
ns
ns
Clock high time
tSCH
250
–
ns
Clock low time
tSCL
250
–
ns
Data output delay
tD
–
100
ns
Data output hold
tHO
0
–
ns
Data input setup
tS
100
–
ns
Data input hold
tHI
100
–
ns
TC bit set delay
tDTC
–
16 tCLCL
ns
External Clock Characteristics
Parameter
Symbol
Limit Values
Unit
Variable Clock
Freq. = 3.5 MHz to 12 MHz
min.
max.
Oscillator period
tCLCL
83.3
285
ns
High time
tCHCX
20
tCLCL – tCLCX
ns
Low time
tCLCX
20
tCLCL – tCHCX
ns
Rise time
tCLCH
–
20
ns
Fall time
tCHCL
–
20
ns
Semiconductor Group
35
C511 / C513
Figure 11
Program Memory Read Cycle
Figure 12
Data Memory Read Cycle
Semiconductor Group
36
C511 / C513
Figure 13
Data Memory Write Cycle
Semiconductor Group
37
C511 / C513
Notes: Shown is the data/clock relationship for CPOL = CPHA = 1. The timing diagram is
valid for the other cases accordingly.
In the case of slave mode and CPHA = 0, the output delay for the MSB applies to the
falling edge of SLS (if transmitter is enabled).
In the case of master mode and CPHA = 0, the MSB becomes valid after the data has
been written into the shift register, i.e. at least one half SCLK clock cycle before the
first clock transition.
Figure 14
SSC Timing
Figure 15
External Clock Drive at XTAL1
Semiconductor Group
38
C511 / C513
ROM Verification Characteristics (only ROM versions C511 / C511A / C513 / C513A)
Parameter
Symbol
Limit Values
min.
max.
Unit
Address to valid data
tAVQV
–
48tCLCL
ns
ENABLE to valid data
tELQV
–
48tCLCL
ns
Data float after ENABLE
tEHQZ
0
48tCLCL
ns
Oscillator frequency
1/tCLCL
4
6
MHz
Device Type ROM Size
Active Address
Lines at Port 2
Inactive Address
Lines at Port 2
C511
2.5 KB
P2.0 - P2.3 = A8 - A11
P2.4 - P2.6 = VSS
C511A
4 KB
P2.0 - P2.3 = A8 - A11
P2.4 - P2.6 = VSS
C513
8 KB
P2.0 - P2.4 = A8 - A12
P2.5 - P2.6 = VSS
C513A
12/16 KB
P2.0 - P2.5 = A8 - A13
P2.6 = VSS
Figure 16
ROM Verification Timing
Semiconductor Group
39
C511 / C513
AC Characteristics of C513A-H Programming Interface
VCC = 5 V ± 10 %, VSS = 0 V; TA = +25 ˚C ± 10 ˚C; 1/tCLCL = 8 MHz
Parameter
Symbol
Limit Values
min.
max.
Unit
ALE pulse width
tPLL
60
–
ns
Address setup to ALE
tPAL
20
–
ns
Address hold after ALE
tPLA
20
–
ns
Address to valid data out
tPAD
–
230
ns
PRD/PWR pulse width
tPCC
250
–
ns
PRD to valid data out
tPRDV
–
200
ns
Data hold after PWR
tPWDH
0
–
ns
Data float after PRD
tPDZ
–
40
ns
Chip select setup to ALE active
tPCS
0
–
ns
Chip select hold after PRD/PWR inactive
tPCH
0
–
ns
ALE to PWR or PRD
tPLC
90
–
ns
PWR or PRD high to ALE high
tPCL
20
–
ns
Data setup before PWR rising edge
tPWDS
50
–
ns
Data hold after PWR rising edge
tPWDH
0
–
ns
Data float after PCS
tPDF
–
40
ns
Semiconductor Group
40
C511 / C513
Figure 17
C513A-H Programming Interface Read Cycle
Figure 18
C513A-H Programming Interface Write Cycle
Semiconductor Group
41
C511 / C513
Reset Characteristics (C513A-H only)
Parameter
Symbol
Limit Values
12 MHz
Clock
RESET pulse width
tRLRH
Variable Clock
1/tCLCL = 3.5 MHz to 12 MHz
min.
max.
min.
max.
10
–
10
–
Figure 19
C513A-H Reset Pulse
Semiconductor Group
Unit
42
ms
C511 / C513
AC Inputs during testing are driven at VCC - 0.5 V for a logic ’1’ and 0.45 V for a logic ’0’.
Timing measurements are made at VIHmin for a logic ’1’ and VILmax for a logic ’0’.
Figure 20
AC Testing: Input, Output Waveforms
For timing purposes a port pin is no longer floating when a 100 mV change from load voltage
occurs and begins to float when a 100 mV change from the loaded VOH/VOL level occurs.
IOL/IOH ≥ ± 20 mA
Figure 21
AC Testing: Float Waveforms
Figure 22
Recommended Oscillator Circuits for Crystal Oscillator
Semiconductor Group
43