ON MC74LCX373MELG Low-voltage cmos octal transparent latch Datasheet

MC74LCX373
Low-Voltage CMOS
Octal Transparent Latch
With 5 V-Tolerant Inputs and Outputs
(3-State, Non-Inverting)
http://onsemi.com
The MC74LCX373 is a high performance, non-inverting octal
transparent latch operating from a 2.3 to 3.6 V supply. High
impedance TTL compatible inputs significantly reduce current
loading to input drivers while TTL compatible outputs offer improved
switching noise performance. A VI specification of 5.5 V allows
MC74LCX373 inputs to be safely driven from 5 V devices.
The MC74LCX373 contains 8 D-type latches with 3-state outputs.
When the Latch Enable (LE) input is HIGH, data on the Dn inputs
enters the latches. In this condition, the latches are transparent, i.e., a
latch output will change state each time its D input changes. When LE
is LOW, the latches store the information that was present on the D
inputs a setup time preceding the HIGH-to-LOW transition of LE.
The 3-state standard outputs are controlled by the Output Enable (OE)
input. When OE is LOW, the standard outputs are enabled. When OE
is HIGH, the standard outputs are in the high impedance state, but this
does not interfere with new data entering into the latches.
MARKING
DIAGRAMS
20
20
1
SOIC-20
DW SUFFIX
CASE 751D
LCX373
AWLYYWWG
1
20
20
1
LCX
373
ALYWG
G
TSSOP-20
DT SUFFIX
CASE 948E
1
Features
•Designed for 2.3 to 3.6 V VCC Operation
•5 V Tolerant - Interface Capability With 5 V TTL Logic
•Supports Live Insertion and Withdrawal
•IOFF Specification Guarantees High Impedance When VCC = 0 V
•LVTTL Compatible
•LVCMOS Compatible
•24 mA Balanced Output Sink and Source Capability
•Near Zero Static Supply Current in all Three Logic States (10 mA)
Substantially Reduces System Power Requirements
•Latchup Performance Exceeds 500 mA
20
20
1
SOEIAJ-20
M SUFFIX
CASE 967
1
A
L, WL
Y, YY
W, WW
G or G
74LCX373
AWLYWWG
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb-Free Package
(Note: Microdot may be in either location)
•ESD Performance:
Human Body Model >2000 V
Machine Model >200 V
•Pb-Free Packages are Available*
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
*For additional information on our Pb-Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2007
November, 2007 - Rev. 8
1
Publication Order Number:
MC74LCX373/D
MC74LCX373
OE
LE
VCC
O7
D7
D6
O6
O5
D5
D4
O4
LE
20
19
18
17
16
15
14
13
12
11
1
11
3
D0
D1
2
3
4
5
6
7
8
9
10
OE
O0
D0
D1
O1
O2
D2
D3
O3
GND
D2
8
D3
D4
OE
LE
D0-D7
O0-O7
Output Enable Input
Latch Enable Input
Data Inputs
3-State Latch Outputs
D5
9
nLE
D6
12
nLE
15
nLE
O5
Q
16
nLE
O6
Q
19
nLE
Q
D
Figure 2. Logic Diagram
TRUTH TABLE
OUTPUTS
OE
LE
Dn
On
OPERATING MODE
L
L
H
H
H
L
H
L
Transparent (Latch Disabled); Read Latch
L
L
L
L
h
l
H
L
Latched (Latch Enabled) Read Latch
L
L
X
NC
Hold; Read Latch
H
L
X
Z
Hold; Disabled Outputs
H
H
H
H
H
L
Z
Z
Transparent (Latch Disabled); Disabled Outputs
H
H
L
L
h
l
Z
Z
Latched (Latch Enabled); Disabled Outputs
H
= High Voltage Level
h
= High Voltage Level One Setup Time Prior to the Latch Enable High-to-Low Transition
L
= Low Voltage Level
l
= Low Voltage Level One Setup Time Prior to the Latch Enable High-to-Low Transition
NC = No Change, State Prior to the Latch Enable High-to-Low Transition
X
= High or Low Voltage Level or Transitions are Acceptable
Z
= High Impedance State
For ICC Reasons DO NOT FLOAT Inputs
2
O4
Q
D
18
http://onsemi.com
O3
Q
D
17
INPUTS
O2
Q
D
14
D7
6
nLE
D
13
FUNCTION
O1
Q
D
Figure 1. Pinout (Top View)
PINS
5
nLE
D
7
PIN NAMES
O0
Q
D
4
1
2
nLE
O7
MC74LCX373
MAXIMUM RATINGS
Symbol
Parameter
VCC
DC Supply Voltage
VI
DC Input Voltage
VO
DC Output Voltage
Value
Condition
Unit
-0.5 to +7.0
V
-0.5 ≤ VI ≤ +7.0
V
-0.5 ≤ VO ≤ +7.0
Output in 3-State
V
-0.5 ≤ VO ≤ VCC + 0.5
Output in HIGH or LOW State (Note 1)
V
IIK
DC Input Diode Current
-50
VI< GND
mA
IOK
DC Output Diode Current
-50
VO < GND
mA
+50
VO > VCC
mA
IO
DC Output Source/Sink Current
±50
mA
ICC
DC Supply Current Per Supply Pin
±100
mA
IGND
DC Ground Current Per Ground Pin
±100
mA
TSTG
Storage Temperature Range
-65 to +150
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. IO absolute maximum rating must be observed.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Operating
Data Retention Only
Min
Typ
Max
Unit
2.0
1.5
2.5, 3.3
2.5, 3.3
3.6
3.6
V
0
5.5
V
0
0
VCC
5.5
V
VCC
Supply Voltage
VI
Input Voltage
VO
Output Voltage
IOH
HIGH Level Output Current
VCC = 3.0 V - 3.6 V
VCC = 2.7 V - 3.0 V
VCC = 2.3 V - 2.7 V
- 24
- 12
-8
mA
IOL
LOW Level Output Current
VCC = 3.0 V - 3.6 V
VCC = 2.7 V - 3.0 V
VCC = 2.3 V - 2.7 V
+ 24
+ 12
+8
mA
TA
Operating Free-Air Temperature
-40
+85
°C
Dt/DV
Input Transition Rise or Fall Rate, VIN from 0.8 V to 2.0 V, VCC = 3.0 V
0
10
ns/V
(HIGH or LOW State)
(3-State)
http://onsemi.com
3
MC74LCX373
DC ELECTRICAL CHARACTERISTICS
TA = -40°C to +85°C
Symbol
VIH
Characteristic
HIGH Level Input Voltage (Note 2)
VIL
LOW Level Input Voltage (Note 2)
VOH
HIGH Level Output Voltage
Condition
Min
2.3 V ≤ VCC ≤ 2.7 V
1.7
2.7 V ≤ VCC ≤ 3.6 V
2.0
Max
V
2.3 V ≤ VCC ≤ 2.7 V
0.7
2.7 V ≤ VCC ≤ 3.6 V
VOL
LOW Level Output Voltage
Unit
V
0.8
2.3 V ≤ VCC ≤ 3.6 V; IOL = 100 mA
VCC-0.2
VCC = 2.3 V; IOH = -8 mA
1.8
VCC = 2.7 V; IOH = -12 mA
2.2
VCC = 3.0 V; IOH = -18 mA
2.4
VCC = 3.0 V; IOH = -24 mA
2.2
V
2.3 V ≤ VCC ≤ 3.6 V; IOL = 100 mA
0.2
VCC = 2.3 V; IOL= 8 mA
0.6
VCC = 2.7 V; IOL= 12 mA
0.4
VCC = 3.0 V; IOL = 16 mA
0.4
V
VCC = 3.0 V; IOL = 24 mA
0.55
II
Input Leakage Current
2.3 V ≤ VCC ≤ 3.6 V; 0 V ≤ VI ≤ 5.5 V
±5
mA
IOZ
3-State Output Current
2.3 ≤ VCC ≤ 3.6 V; 0V ≤ VO ≤ 5.5 V;
VI = VIH or V IL
±5
mA
IOFF
Power-Off Leakage Current
VCC = 0 V; VI or VO = 5.5 V
10
mA
ICC
Quiescent Supply Current
2.3 ≤ VCC ≤ 3.6 V; VI = GND or VCC
10
mA
2.3 ≤ VCC ≤ 3.6 V; 3.6 ≤ VI or VO ≤ 5.5 V
±10
2.3 ≤ VCC ≤ 3.6 V; VIH = VCC - 0.6 V
500
DICC
Increase in ICC per Input
mA
2. These values of VI are used to test DC electrical characteristics only.
AC CHARACTERISTICS tR = tF = 2.5 ns; RL = 500 W
Limits
TA = -40°C to +85°C
VCC = 3.3 V ± 0.3 V
VCC = 2.7 V
VCC = 2.5 V ± 0.2 V
CL = 50 pF
CL = 50 pF
CL = 30 pF
Waveform
Min
Max
Min
Max
Min
Max
Unit
tPLH
tPHL
Propagation Delay
Dn to On
1
1.5
1.5
8.0
8.0
1.5
1.5
9.0
9.0
1.5
1.5
9.6
9.6
ns
tPLH
tPHL
Propagation Delay
LE to On
3
1.5
1.5
8.5
8.5
1.5
1.5
9.5
9.5
1.5
1.5
10.5
10.5
ns
tPZH
tPZL
Output Enable Time to HIGH
and LOW Level
2
1.5
1.5
8.5
8.5
1.5
1.5
9.5
9.5
1.5
1.5
10.5
10.5
ns
tPHZ
tPLZ
Output Disable Time From
High and Low Level
2
1.5
1.5
7.5
7.5
1.5
1.5
8.5
8.5
1.5
1.5
9.0
9.0
ns
ts
Setup TIme, HIGH or LOW
Dn to LE
3
2.5
2.5
4.0
th
Hold TIme, HIGH or LOW
Dn to LE
3
1.5
1.5
2.0
tw
LE Pulse Width, HIGH
3
3.3
3.3
4.0
tOSHL
tOSLH
Output-to-Output Skew
(Note 3)
Symbol
Parameter
1.0
1.0
ns
3. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device.
The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH); parameter
guaranteed by design.
http://onsemi.com
4
MC74LCX373
DYNAMIC SWITCHING CHARACTERISTICS
TA = +25°C
Symbol
Characteristic
Condition
Min
Typ
Max
Unit
VOLP
Dynamic LOW Peak Voltage (Note 4)
VCC = 3.3 V, CL = 50 pF, VIH = 3.3 V, VIL = 0 V
VCC = 2.5 V, CL = 30 pF, VIH = 2.5 V, VIL = 0 V
0.8
0.6
V
V
VOLV
Dynamic LOW Valley Voltage (Note 4)
VCC = 3.3 V, CL = 50 pF, VIH = 3.3 V, VIL = 0 V
VCC = 2.5 V, CL = 30 pF, VIH = 2.5 V, VIL = 0 V
-0.8
-0.6
V
V
4. Number of outputs defined as “n”. Measured with “n-1” outputs switching from HIGH-to-LOW or LOW-to-HIGH. The remaining output is
measured in the LOW state.
CAPACITIVE CHARACTERISTICS
Symbol
Parameter
Condition
Typical
Unit
CIN
Input Capacitance
VCC = 3.3 V, VI = 0 V or VCC
7
pF
CI/O
Input/Output Capacitance
VCC = 3.3 V, VI = 0 V or VCC
8
pF
CPD
Power Dissipation Capacitance
10 MHz, VCC = 3.3 V, VI = 0 V or VCC
25
pF
VCC
OE
Vmi
Vmi
VCC
Dn
Vmi
0V
tPZH
Vmi
On
0V
tPLH
tPHZ
VOH
VHZ
Vmo
tPHL
VOH
On
Vmo
tPZL
Vmo
tPLZ
VOL
Vmo
On
VLZ
VOL
WAVEFORM 1 - PROPAGATION DELAYS
tR = tF = 2.5 ns, 10% to 90%; f = 1 MHz; tW = 500 ns
WAVEFORM 2 - OUTPUT ENABLE AND DISABLE TIMES
tR = tF = 2.5 ns, 10% to 90%; f = 1 MHz; tW = 500 ns
2.7 V
Dn
1.5 V
VCC
0V
ts
2.7 V
LE
1.5 V
tw
1.5 V
0V
tPLH, tPHL
VOH
On
3.3 V ± 0.3 V
2.7 V
Vmi
1.5 V
1.5 V
VCC/2
Vmo
1.5 V
1.5 V
VCC/2
VHZ
VOL + 0.3 V
VOL + 0.3 V
VOL + 0.15 V
VLZ
VOH - 0.3 V
VOH - 0.3 V
VOH - 015 V
Symbol
th
1.5 V
VOL
WAVEFORM 3 - LE to On PROPAGATION DELAYS, LE MINIMUM
PULSE WIDTH, Dn to LE SETUP AND HOLD TIMES
tR = tF = 2.5 ns, 10% to 90%; f = 1 MHz; tW = 500 ns except when noted
Figure 3. AC Waveforms
http://onsemi.com
5
2.5 V ± 0.2 V
MC74LCX373
VCC
PULSE
GENERATOR
DUT
RT
CL
TEST
RL
SWITCH
tPLH, tPHL
Open
tPZL, tPLZ
6 V at VCC = 3.3 0.3 V
6 V at VCC = 2.5 0.2 V
Open Collector/Drain tPLH and tPHL
6V
tPZH, tPHZ
CL =
CL =
RL =
RT =
6V
OPEN
GND
R1
GND
50 pF at VCC = 3.3 0.3 V or equivalent (includes jig and probe capacitance)
30 pF at VCC = 2.5 0.2 V or equivalent (includes jig and probe capacitance)
R1 = 500 W or equivalent
ZOUT of pulse generator (typically 50 W)
Figure 4. Test Circuit
ORDERING INFORMATION
Package
Shipping†
MC74LCX373DWR2
SOIC-20
1000 Tape & Reel
MC74LCX373DWR2G
SOIC-20
(Pb-Free)
1000 Tape & Reel
MC74LCX373DT
TSSOP-20*
75 Units / Rail
MC74LCX373DTG
TSSOP-20*
(Pb-Free)
75 Units / Rail
MC74LCX373DTR2
TSSOP-20*
2500 Tape & Reel
MC74LCX373DTR2G
TSSOP-20*
(Pb-Free)
2500 Tape & Reel
MC74LCX373MEL
SOEIAJ-20
2000 Tape & Reel
MC74LCX373MELG
SOEIAJ-20
(Pb-Free)
2000 Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb-Free.
http://onsemi.com
6
MC74LCX373
PACKAGE DIMENSIONS
SOIC-20
DW SUFFIX
CASE 751D-05
ISSUE G
20
11
X 45 _
h
1
10
20X
B
B
0.25
M
T A
S
B
S
A
L
H
M
E
0.25
10X
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF B
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
q
A
B
M
D
18X
e
A1
SEATING
PLANE
C
T
http://onsemi.com
7
DIM
A
A1
B
C
D
E
e
H
h
L
q
MILLIMETERS
MIN
MAX
2.35
2.65
0.10
0.25
0.35
0.49
0.23
0.32
12.65
12.95
7.40
7.60
1.27 BSC
10.05
10.55
0.25
0.75
0.50
0.90
0_
7_
MC74LCX373
PACKAGE DIMENSIONS
TSSOP-20
DT SUFFIX
CASE 948E-02
ISSUE C
20X
0.15 (0.006) T U
K REF
0.10 (0.004)
S
M
T U
V
S
S
ÍÍÍÍ
ÍÍÍÍ
ÍÍÍÍ
K
K1
2X
L/2
20
11
J J1
B
-U-
L
PIN 1
IDENT
SECTION N-N
1
10
0.25 (0.010)
N
0.15 (0.006) T U
S
M
A
-V-
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION:
MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE
MOLD FLASH, PROTRUSIONS OR GATE
BURRS. MOLD FLASH OR GATE BURRS
SHALL NOT EXCEED 0.15 (0.006) PER
SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION
SHALL NOT EXCEED 0.25 (0.010) PER
SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
6. TERMINAL NUMBERS ARE SHOWN
FOR REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE -W-.
N
F
DETAIL E
-W-
C
D
G
H
DETAIL E
0.100 (0.004)
-T- SEATING
PLANE
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
MILLIMETERS
MIN
MAX
6.40
6.60
4.30
4.50
--1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.27
0.37
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0_
8_
SOLDERING FOOTPRINT
7.06
1
0.65
PITCH
16X
0.36
16X
1.26
DIMENSIONS: MILLIMETERS
http://onsemi.com
8
INCHES
MIN
MAX
0.252
0.260
0.169
0.177
--0.047
0.002
0.006
0.020
0.030
0.026 BSC
0.011
0.015
0.004
0.008
0.004
0.006
0.007
0.012
0.007
0.010
0.252 BSC
0_
8_
MC74LCX373
PACKAGE DIMENSIONS
SOEIAJ-20
M SUFFIX
CASE 967-01
ISSUE A
20
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
LE
11
Q1
E HE
1
M_
L
10
DETAIL P
Z
D
VIEW P
e
A
c
A1
b
0.13 (0.005)
M
0.10 (0.004)
DIM
A
A1
b
c
D
E
e
HE
L
LE
M
Q1
Z
MILLIMETERS
MIN
MAX
--2.05
0.05
0.20
0.35
0.50
0.15
0.25
12.35
12.80
5.10
5.45
1.27 BSC
7.40
8.20
0.50
0.85
1.10
1.50
10 _
0_
0.70
0.90
--0.81
INCHES
MIN
MAX
--0.081
0.002
0.008
0.014
0.020
0.006
0.010
0.486
0.504
0.201
0.215
0.050 BSC
0.291
0.323
0.020
0.033
0.043
0.059
10 _
0_
0.028
0.035
--0.032
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada
Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada
Email: [email protected]
N. American Technical Support: 800-282-9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81-3-5773-3850
http://onsemi.com
9
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative
MC74LCX373/D