CY26049-36 FailSafe™ PacketClock™ Global Communications Clock Generator Features • Fully integrated phase-locked loop (PLL) • FailSafe output • PLL driven by a crystal oscillator that is phase aligned with external reference • Output frequencies selectable and/or programmed to standard communication frequencies • Low-jitter, high-accuracy outputs • Commercial and Industrial operation • 3.3V ± 5% operation • 16-lead TSSOP Benefits • Integrated high-performance PLL tailored for telecommunications frequency synthesis eliminates the need for external loop filter components • When reference is in range, SAFE pin is driven high. • When reference is off, DCXO maintains clock outputs. SAFE pin is low. • DCXO maintains continuous operation should the input reference clock fail • Glitch-free transition simplifies system design • Selectable output clock rates include T1/DS1, E1, T3/DS3, E3, and OC-3. • Works with commonly available, low-cost 18.432-MHz crystal • Zero-ppm error for all output frequencies • Performance guaranteed for applications that require an extended temperature range • Compatible across industry standard design platforms • Industry standard package with 6.4 x 5.0 mm2 footprint and a height profile of just 1.1 mm. Logic Block Diagram external pullable crystal (18.432 MHz) XIN XOUT Input reference (typical 8 kHz) ICLK FAILSAFETM CONTROL DIGITAL CONTROLLED CRYSTAL OSCILLATOR PHASE LOCKED LOOP CLK OUTPUT DIVIDERS FS[3:0] frequency select CLK/2 8K SAFE High=ICLK detected Pin Configuration CY26049-36 16-pin TSSOP Top View ICLK 1 15 CLK FS1 3 14 FS0 FS2 4 13 FS3 VDD 5 12 VDD VSS 6 Cypress Semiconductor Corporation Document #: 38-07415 Rev. *C • 16 NC 8K 2 11 VSS CLK/2 7 10 SAFE XIN 8 9 XOUT 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised July 16, 2004 CY26049-36 Pin Definitions Pin Name Pin Number Pin Description ICLK 1 Reference Input Clock; 8 kHz or 10 to 60 MHz. 8K 2 Clock Output; 8 kHz or high impedance in buffer mode. FS1 3 Frequency Select 1; Determines CLK outputs per Table 1. FS2 4 Frequency Select 2; Determines CLK outputs per Table 1. VDD 5 Voltage Supply; 3.3V. VSS 6 Ground CLK/2 7 Clock Output; Frequency per Table 1. XIN 8 Pullable Crystal Input; 18.432 MHz. XOUT 9 Pullable Crystal Output; 18.432 MHz. SAFE 10 High = reference ICLK within range, Low = reference ICLK out of range. VSS 11 Ground VDD 12 Voltage Supply; 3.3V. FS3 13 Frequency Select 3; Determines CLK outputs per Table 1. FS0 14 Frequency Select 0; Determines CLK outputs per Table 1. CLK 15 Clock Output; Frequency per Table 1. NC 16 No Connect Selector Guide Part Number CY26049-36 Input Frequency Range Outputs 8 kHz or 10 to 60 MHz Reference Input Crystal: 18.432-MHz pullable Crystal per Cypress Specification Functional Description CY26049 is a FailSafe frequency synthesizer with a reference clock input and three clock outputs. The device provides an optimum solution for applications where continuous operation is required in the event of a primary clock failure. The continuous, glitch-free operation is achieved by using a DCXO which serves as a primary clock source. The FailSafe control circuit synchronizes the DCXO with the reference as long as the reference is within the pull range of the crystal. 3 Output Frequencies 8 kHz to 155.52 MHz Selectable (see Table 1) is in fact the primary clocking source. When the reference clock is restored, the DCXO automatically re-synchronizes to the reference. The status of the reference clock input, as detected by the CY26049-36, is reported by the SAFE pin. In the buffer mode (FS3:FS0 = 1110 or 1111), the CY26049-36 can be used as a jitter attenuator. In this mode, extensive jitter on the input clock will be “filtered”, resulting in a low-jitter output clock. In the event of a reference clock failure the DCXO maintains the last frequency and phase information of the reference clock. The unique feature of the CY26049-36 is that the DCXO Document #: 38-07415 Rev. *C Page 2 of 7 CY26049-36 Frequency Select Tables Table 1. CY26049-36 Frequency Select–Output Decoding Table–External Mode (MHz except as noted) ICLK FS3 FS2 FS1 FS0 CLK/2 CLK 8K Crystal 8 kHz 0 0 0 0 1.544 3.088 8 kHz 18.432 8 kHz 0 0 0 1 2.048 4.096 8 kHz 18.432 8 kHz 0 0 1 0 22.368 44.736 8 kHz 18.432 8 kHz 0 0 1 1 17.184 34.368 8 kHz 18.432 8 kHz 0 1 0 0 77.76 155.52 8 kHz 18.432 8 kHz 0 1 0 1 16.384 32.768 8 kHz 18.432 8 kHz 0 1 1 0 14.352 28.704 8 kHz 18.432 8 kHz 0 1 1 1 High Z[1] High Z[1] High Z[1] 18.432 8 kHz 1 0 0 0 18.528 37.056 8 kHz 18.432 8 kHz 1 0 0 1 12.352 24.704 8 kHz 18.432 8 kHz 1 0 1 0 7.68 15.36 8 kHz 18.432 8 kHz 1 0 1 1 High Z[1] High Z[1] High Z[1] 18.432 8 kHz 1 1 0 0 12.288 24.576 8 kHz 18.432 8 kHz 1 1 0 1 16.384 32.768 8 kHz 18.432 CLK 8K Crystal Table 2. CY26049-36 Frequency Select–Output Decoding Table–Buffer Mode ICLK FS3 FS2 FS1 FS0 CLK/2 20 to 60 1 1 1 0 ICLK/2 ICLK 10 to 30 1 1 1 1 2*ICLK 4*ICLK High Z[1] High Z[1] ICLK/2 ICLK Note: 1. High Z = high impedance. Document #: 38-07415 Rev. *C Page 3 of 7 CY26049-36 Absolute Maximum Conditions Data Retention @ Tj=125°C...................................>10 years Supply Voltage (VDD) ........................................–0.5 to +7.0V DC Input Voltage........................................ –0.5V to VDD+0.5 Storage Temperature (Non-Condensing) .... –55°C to +125°C Junction Temperature ................................ –40°C to +125°C Package Power Dissipation...................................... 350 mW ESD (Human Body Model) MIL-STD-883.................... 2000V (Above which the useful life may be impaired. For user guidelines, not tested. Recommended Pullable Crystal Specifications[2] Parameter Description FNOM Nominal crystal frequency CLNOM Nominal load capacitance Comments Min. Typ. Max. Units Parallel resonance, fundamental mode, AT cut – 18.432 – MHz – 14 – pF Ω R1 Equivalent series resistance (ESR) Fundamental mode – – 25 R3/R1 Ratio of third overtone mode ESR to fundamental mode ESR Ratio used because typical R1 values are much less than the maximum spec 3 – – DL Crystal drive level No external series resistor assumed – 0.5 2 F3SEPHI Third overtone separation from 3*FNOM High side 400 – – ppm F3SEPLO Third overtone separation from 3*FNOM Low side – – –200 ppm C0 Crystal shunt capacitance – – 7 pF C0/C1 Ratio of shunt to motional capacitance 180 – 250 C1 Crystal motional capacitance 14.4 18 21.6 mW fF Recommended Operating Conditions Parameter Description Min. Typ. Max. Unit 3.15 3.3 3.45 V 0 – 70 °C –40 – 85 °C VDD Operating Voltage TAC Ambient Temperature (Commercial Temperature) TAI Ambient Temperature (Industrial Temperature) CLOAD Max Output Load Capacitance – – 15 pF tpu Power-up time for all VDDs to reach minimum specified voltage (power ramps must be monotonic) 0.05 – 500 ms tER(I) 8 kHz Input Edge Rate, 20% to 80% of VDD = 3.3V 0.07 – – V/ns Min. Typ. Max. Unit 12 24 – mA DC Electrical Specifications (Commercial Temp: 0° to 70°C) Parameter Description IOH Output High Current Test Conditions VOH = VDD – 0.5, VDD = 3.3V (source) IOL Output Low Current VOL = 0.5, VDD = 3.3V (sink) 12 24 – mA VIH Input High Voltage CMOS Levels 0.7 – – VDD VIL Input High Voltage CMOS Levels – – 0.3 VDD IIH Input High Current VIH=VDD – 5 10 µA IIL Input Low Current VIL=0V – 5 10 µA CIN Input Capacitance – – 7 pF Z[1] output IOZ Output Leakage Current High – ±5 – µA IDD Supply Current CLOAD = 15 pF, VDD = 3.45V, FS [3:0] = 0100 – – 45 mA CLOAD = 15 pF, VDD = 3.45V, FS [3:0] = 1101 Note: 2. Ecliptek ECX-5761-18.432 M and ECX-5762-18.432 M meets these specifications. – – 30 mA Document #: 38-07415 Rev. *C Page 4 of 7 CY26049-36 DC Electrical Specifications (Industrial Temp: –40° to 85°C) Parameter Description Test Conditions Min. Typ. Max. Unit IOH Output High Current VOH = VDD – 0.5, VDD = 3.3V (source) 10 20 – mA IOL Output Low Current VOL = 0.5, VDD = 3.3V (sink) 10 20 – mA VIH Input High Voltage CMOS Levels 0.7 – – VDD VIL Input High Voltage CMOS Levels – – 0.3 VDD IIH Input High Current VIH = VDD – 5 10 µA IIL Input Low Current VIL = 0V – 5 10 µA CIN Input Capacitance IOZ Output Leakage Current IDD Supply Current – – 7 pF High Z[1] output – ±5 – µA CLOAD = 15 pF, VDD = 3.45V, FS [3:0] = 0100 – – 50 mA CLOAD = 15 pF, VDD = 3.45V, FS [3:0] = 1101 – – 35 mA Min. Typ. Max. Unit – 8.00 AC Electrical Specifications (Commercial Temp: 0° to 70° C and Industrial Temp: –40° to 85°C) Parameter Description Test Conditions fICLK-E Frequency, Input Clock Input Clock Frequency, External Mode fICLK-B Frequency, Input Clock Input Clock Frequency, Buffer Mode LR FailSafe Lock Range[3] Range of reference ICLK for Safe = High Duty Cycle defined in Figure 1, measured at 50% of VDD – kHz 60 MHz 10 – –250 – 45 50 55 % – – 250 ps – – 50 ps – – 500 ps +250 ppm DC = t2/t1 Output Duty Cycle TPJIT1 Clock Jitter; output > 5 MHz Period Jitter, Peak to Peak, 10,000 periods TPJIT2 Clock Jitter; output <5 MHz Period Jitter, Peak to Peak, 10,000 periods RMS Period Jitter, RMS – – 100 ps t6 PLL Lock Time Time for PLL to lock within ± 150 ppm of target frequency – – 3 ms tfs_lock Failsafe Lock Time Time for PLL to lock to ICKL (outputs phase aligned with ICKL and Safe = High) – – 7 s ferror Frequency Synthesis Error Actual mean frequency error vs. target – 0 – ppm ER Rising Edge Rate Output Clock Edge Rate, Measured from 20% to 80% of VDD, CLOAD = 15 pF See Figure 2. 0.8 1.4 2 V/ns EF Falling Edge Rate Output Clock Edge Rate, Measured from 20% to 80% of VDD, CLOAD = 15 pF See Figure 2. 0.8 1.4 2 V/ns RMS Period Jitter, RMS Voltage and Timing Definitions t1 t2 CLK 50% 50% Figure 1. Duty Cycle Definition; DC = t2/t1 t4 t3 80% CLK 20% Figure 2. Rise and Fall Time Definitions: ER = 0.6 x VDD / t3, EF = 0.6 x VDD / t4 Note: 3. Dependent on crystals chosen and crystal specs. Document #: 38-07415 Rev. *C Page 5 of 7 CY26049-36 Test Circuit ICLK 8K 1 16 2 15 CLK CLOAD CLOAD VDD 3 14 4 13 5 12 VDD 0.1uF 0.1uF CLK/2 6 11 7 10 8 9 CLOAD 18.432 MHz Ordering Information Ordering Code CY26049ZC-36 CY26049ZC-36T CY26049ZI-36 CY26049ZI-36T Lead Free CY26049ZXC-36 CY26049ZXC-36T CY26049ZXI-36 CY26049ZXI-36T Package Type 16-lead TSSOP 16-lead TSSOP–Tape and Reel 16-lead TSSOP 16-lead TSSOP–Tape and Reel Operating Temperature Range Commercial 0 to 70°C Commercial 0 to 70°C Industrial –40 to 85°C Industrial –40 to 85°C 16-lead TSSOP 16-lead TSSOP–Tape and Reel 16-lead TSSOP 16-lead TSSOP–Tape and Reel Commercial 0 to 70°C Commercial 0 to 70°C Industrial –40 to 85°C Industrial –40 to 85°C Package Diagram 16-lead TSSOP 4.40 MM Body Z16.173 PIN 1 ID DIMENSIONS IN MM[INCHES] MIN. MAX. 1 REFERENCE JEDEC MO-153 6.25[0.246] 6.50[0.256] PACKAGE WEIGHT 0.05 gms PART # 4.30[0.169] 4.50[0.177] Z16.173 STANDARD PKG. ZZ16.173 LEAD FREE PKG. 16 0.65[0.025] BSC. 0.19[0.007] 0.30[0.012] 1.10[0.043] MAX. 0.25[0.010] BSC GAUGE PLANE 0°-8° 0.076[0.003] 0.85[0.033] 0.95[0.037] 4.90[0.193] 5.10[0.200] 0.05[0.002] 0.15[0.006] SEATING PLANE 0.50[0.020] 0.70[0.027] 0.09[[0.003] 0.20[0.008] 51-85091-*A FailSafe and PacketClock are trademarks of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-07415 Rev. *C Page 6 of 7 © Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. CY26049-36 Document History Page Document Title: CY26049-36 FailSafe™ PacketClock™ Global Communications Clock Generator Document Number: 38-07415 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 114749 08/08/02 CKN New Data Sheet *A 120067 01/06/03 CKN Changed “FailSafe is a trademark of Silicon Graphics, Inc.” to read “FailSafe is a trademark of Cypress Semiconductor” *B 128000 07/15/03 IJA Changed Benefits to read “When reference is in range, SAFE pin is driven high” Changed first sentence to “CY26049 is a FailSafe frequency synthesizer with a reference clock input and three clock outputs” Changed title from “Failsafe PacketClock Global Communications Clocks” to “FailSafe PacketClock Global Communications Clock Generator” Changed definitions in Pin Description Table Replaced format for Absolute Maximum Conditions Replaced Recommended Pullable Crystal Specifications table Added tpu to Recommended Operating Conditions Added IIH and IIL to DC Electrical Specifications Replaced AC Electrical Specifications from Cy26049-16 data sheet Changed Voltage and Timing Definitions to match CY2410 data sheet Moved Package Diagram to end of data sheet *C 244412 See ECN RGL Spec. (tER(I)) Input Edge Rate in the Recommended Operating Conditions Table Added Lead Free Devices Document #: 38-07415 Rev. *C Page 7 of 7