N-Channel PowerTrench® MOSFET
100V, 61A, 16mΩ
Features
Applications
• r DS(ON) = 14mΩ (Typ.), VGS = 10V, ID = 61A
• DC/DC Converters and Off-line UPS
• Qg(tot) = 41nC (Typ.), VGS = 10V
• Distributed Power Architectures and VRMs
• Low Miller Charge
• Primary Switch for 24V and 48V Systems
• Low QRR Body Diode
• High Voltage Synchronous Rectifier
• UIS Capability (Single Pulse and Repetitive Pulse)
• Direct Injection / Diesel Injection Systems
• Qualified to AEC Q101
• 42V Automotive Load Control
• RoHS Compliant
• Electronic Valve Train Systems
Formerly developmental type 82769
D
DRAIN
(FLANGE)
GATE
G
S
SOURCE
TO-263AB
FDB SERIES
MOSFET Maximum Ratings TC = 25°C unless otherwise noted
Symbol
VDSS
Drain to Source Voltage
Parameter
Ratings
100
Units
V
VGS
Gate to Source Voltage
±20
V
Continuous (TC = 25oC, VGS = 10V)
61
A
Continuous (TC = 100oC, VGS = 10V)
43
A
9
A
Drain Current
ID
Continuous (Tamb = 25oC, VGS = 10V) with RθJA = 43oC/W)
Pulsed
EAS
PD
TJ, TSTG
Figure 4
A
Single Pulse Avalanche Energy (Note 1)
182
mJ
Power dissipation
150
W
Derate above 25oC
1.0
W/oC
Operating and Storage Temperature
o
-55 to 175
C
Thermal Characteristics
RθJC
Thermal Resistance Junction to Case TO-263
RθJA
Thermal Resistance Junction to Ambient TO-263
RθJA
Thermal Resistance Junction to Ambient TO-263, 1in2 copper pad area
(Note 2)
1.0
o
C/W
62
o
C/W
43
o
C/W
This product has been designed to meet the extreme test conditions and environment demanded by the automotive industry. For a
copy of the requirements, see AEC Q101 at: http://www.aecouncil.com/
Reliability data can be found at: http://www.fairchildsemi.com/products/discrete/reliability/index.html.
All Fairchild Semiconductor products are manufactured, assembled and tested under ISO9000 and QS9000 quality systems
certification.
©2008 Fairchild Semiconductor Corporation
1
FDB3652_F085 Rev. A1
FDB3652_F085 N-Channel PowerTrench® MOSFET
October 2008
FDB3652_F085
Device Marking
FDB3652
Device
FDB3652_F085
Package
TO-263AB
Reel Size
330mm
Tape Width
24mm
Quantity
800 units
Electrical Characteristics TC = 25°C unless otherwise noted
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
100
-
-
-
V
-
1
-
-
250
µA
VGS = ±20V
-
-
±100
nA
V
Off Characteristics
BVDSS
Drain to Source Breakdown Voltage
IDSS
Zero Gate Voltage Drain Current
IGSS
Gate to Source Leakage Current
ID = 250µA, VGS = 0V
VDS = 80V
VGS = 0V
TC= 150oC
On Characteristics
VGS(TH)
rDS(ON)
Gate to Source Threshold Voltage
Drain to Source On Resistance
VGS = VDS, ID = 250µA
2
-
4
ID = 61A, VGS = 10V
-
0.014
0.016
ID = 30A, VGS = 6V
-
0.018
0.026
ID = 61A, VGS = 10V,
TJ = 175oC
-
0.035
0.043
-
2880
-
pF
-
390
-
pF
-
100
-
pF
41
53
nC
-
5
6.5
nC
-
15
-
nC
-
10
-
nC
-
10
-
nC
Ω
Dynamic Characteristics
CISS
Input Capacitance
COSS
Output Capacitance
CRSS
Reverse Transfer Capacitance
Qg(TOT)
Total Gate Charge at 10V
VGS = 0V to 10V
Qg(TH)
Threshold Gate Charge
VGS = 0V to 2V
Qgs
Gate to Source Gate Charge
Qgs2
Gate Charge Threshold to Plateau
Qgd
Gate to Drain “Miller” Charge
VDS = 25V, VGS = 0V,
f = 1MHz
VDD = 50V
ID = 61A
Ig = 1.0mA
FDB3652_F085 N-Channel PowerTrench® MOSFET
Package Marking and Ordering Information
Switching Characteristics (VGS = 10V)
tON
Turn-On Time
-
-
146
ns
td(ON)
Turn-On Delay Time
-
12
-
ns
tr
Rise Time
td(OFF)
Turn-Off Delay Time
tf
tOFF
-
85
-
ns
-
26
-
ns
Fall Time
-
45
-
ns
Turn-Off Time
-
-
107
ns
V
VDD = 50V, ID = 61A
VGS = 10V, RGS = 6.8Ω
Drain-Source Diode Characteristics
ISD = 61A
-
-
1.25
ISD = 30A
-
-
1.0
V
Reverse Recovery Time
ISD = 61A, dISD/dt = 100A/µs
-
-
62
ns
Reverse Recovered Charge
ISD = 61A, dISD/dt = 100A/µs
-
-
45
nC
VSD
Source to Drain Diode Voltage
trr
QRR
Notes:
1: Starting T J = 25°C, L = 0.228mH, IAS = 40A.
2: Pulse Width = 100s
©2008 Fairchild Semiconductor Corporation
2
FDB3652 _F085 Rev. A1
1.2
75
ID, DRAIN CURRENT (A)
POWER DISSIPATION MULTIPLIER
1.0
0.8
0.6
0.4
50
25
0.2
0
0
0
25
50
75
100
150
125
175
25
50
75
TC , CASE TEMPERATURE (o C)
100
125
150
175
TC, CASE TEMPERATURE (oC)
Figure 1. Normalized Power Dissipation vs
Ambient Temperature
Figure 2. Maximum Continuous Drain Current vs
Case Temperature
2
DUTY CYCLE - DESCENDING ORDER
0.5
0.2
0.1
0.05
0.02
0.01
ZθJC, NORMALIZED
THERMAL IMPEDANCE
1
PDM
FDB3652_F085 N-Channel PowerTrench® MOSFET
Typical Characteristics TC = 25°C unless otherwise noted
0.1
t1
t2
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJC x RθJC + TC
SINGLE PULSE
0.01
10-5
10-4
10-3
10-2
10-1
100
101
t , RECTANGULAR PULSE DURATION (s)
Figure 3. Normalized Maximum Transient Thermal Impedance
1000
TC = 25oC
IDM, PEAK CURRENT (A)
FOR TEMPERATURES
ABOVE 25oC DERATE PEAK
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
CURRENT AS FOLLOWS:
175 - TC
I = I25
150
VGS = 10V
100
50
10-5
10-4
10-3
10-2
10-1
100
101
t, PULSE WIDTH (s)
Figure 4. Peak Current Capability
©2008 Fairchild Semiconductor Corporation
3
FDB3652_F085 Rev. A1
1000
500
If R = 0
tAV = (L)(I AS)/(1.3*RATED BVDSS - VDD)
If R ¼ 0
tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1]
IAS, AVALANCHE CURRENT (A)
ID, DRAIN CURRENT (A)
10µs
100
100µs
10
OPERATION IN THIS
AREA MAY BE
LIMITED BY rDS(ON)
1ms
1
10ms
SINGLE PULSE
TJ = MAX RATED
TC = 25oC
100
STARTING TJ = 25oC
10
STARTING TJ = 150oC
DC
0.1
1
1
10
100
VDS, DRAIN TO SOURCE VOLTAGE (V)
200
10
NOTE: Refer to Fairchild Application Notes AN7514 and AN7515
Figure 5. Forward Bias Safe Operating Area
Figure 6. Unclamped Inductive Switching
Capability
125
125
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VDD = 15V
VGS = 10V
75
TJ = 175o C
50
o
o
TJ = 25 C
VGS = 7V
100
ID, DRAIN CURRENT (A)
100
ID , DRAIN CURRENT (A)
0.1
1
tAV, TIME IN AVALANCHE (ms)
0.01
TJ = -55 C
VGS = 6V
75
FDB3652_F085 N-Channel PowerTrench® MOSFET
Typical Characteristics TC = 25°C unless otherwise noted
TC = 25oC
50
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
25
25
VGS = 5V
0
0
3
4
5
6
VGS , GATE TO SOURCE VOLTAGE (V)
7
0
Figure 7. Transfer Characteristics
4
Figure 8. Saturation Characteristics
20
3.0
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
NORMALIZED DRAIN TO SOURCE
ON RESISTANCE
DRAIN TO SOURCE ON RESISTANCE(mΩ)
1
2
3
VDS , DRAIN TO SOURCE VOLTAGE (V)
18
VGS = 6V
16
14
VGS = 10V
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
2.5
2.0
1.5
1.0
0.5
VGS = 10V, I D = 61A
12
0
0
20
40
ID, DRAIN CURRENT (A)
60
-80
Figure 9. Drain to Source On Resistance vs Drain
Current
©2008 Fairchild Semiconductor Corporation
-40
0
40
80
120
160
TJ, JUNCTION TEMPERATURE (oC)
200
Figure 10. Normalized Drain to Source On
Resistance vs Junction Temperature
4
FDB3652_F085 Rev. A1
1.4
1.2
VGS = VDS, ID = 250µA
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE
ID = 250µA
NORMALIZED GATE
THRESHOLD VOLTAGE
1.2
1.0
0.8
0.6
0.4
-80
0
40
80
120
160
TJ, JUNCTION TEMPERATURE (oC)
200
-80
0
40
80
120
160
TJ , JUNCTION TEMPERATURE (oC)
200
10
VGS , GATE TO SOURCE VOLTAGE (V)
CISS = CGS + CGD
C, CAPACITANCE (pF)
-40
Figure 12. Normalized Drain to Source
Breakdown Voltage vs Junction Temperature
5000
COSS ≅ CDS + CGD
CRSS = CGD
100
VGS = 0V, f = 1MHz
1
10
VDS, DRAIN TO SOURCE VOLTAGE (V)
100
8
6
4
WAVEFORMS IN
DESCENDING ORDER:
ID = 61A
ID = 30A
2
0
Figure 13. Capacitance vs Drain to Source
Voltage
©2008 Fairchild Semiconductor Corporation
VDD = 50V
0
40
0.1
1.0
0.9
-40
Figure 11. Normalized Gate Threshold Voltage vs
Junction Temperature
1000
1.1
FDB3652_F085 N-Channel PowerTrench® MOSFET
Typical Characteristics TC = 25°C unless otherwise noted
10
20
30
Qg, GATE CHARGE (nC)
40
50
Figure 14. Gate Charge Waveforms for Constant
Gate Currents
5
FDB3652_F085 Rev. A1
VDS
BVDSS
tP
L
VDS
VARY tP TO OBTAIN
IAS
+
RG
REQUIRED PEAK IAS
VDD
VDD
-
VGS
DUT
tP
IAS
0V
0
0.01Ω
tAV
Figure 15. Unclamped Energy Test Circuit
Figure 16. Unclamped Energy Waveforms
VDS
VDD
Qg(TOT)
VDS
L
VGS
VGS
VGS = 10V
+
Qgs2
VDD
-
FDB3652_F085 N-Channel PowerTrench® MOSFET
Test Circuits and Waveforms
DUT
VGS = 2V
Ig(REF)
0
Qg(TH)
Qgs
Qgd
Ig(REF)
0
Figure 17. Gate Charge Test Circuit
Figure 18. Gate Charge Waveforms
VDS
tON
tOFF
td(ON)
td(OFF)
RL
tr
VDS
tf
90%
90%
+
VGS
VDD
-
10%
0
10%
DUT
90%
RGS
VGS
50%
50%
PULSE WIDTH
VGS
0
Figure 19. Switching Time Test Circuit
©2008 Fairchild Semiconductor Corporation
10%
Figure 20. Switching Time Waveforms
6
FDB3652_F085 Rev. A1
RθJA = 26.51+ 19.84/(0.262+Area) EQ.2
RθJA = 26.51+ 128/(1.69+Area) EQ.3
60
RθJA (o C/W)
(T
–T )
JM
A
P D M = ----------------------------R θ JA
80
40
(EQ. 1)
In using surface mount devices such as the TO-263
package, the environment in which it is applied will have a
significant influence on the part’s current and maximum
power dissipation ratings. Precise determination of PDM is
complex and influenced by many factors:
20
0.1
1
10
(0.645)
(6.45)
AREA, TOP COPPER AREA in2 (cm2 )
(64.5)
Figure 21. Thermal Resistance vs Mounting
Pad Area
1. Mounting pad area onto which the device is attached and
whether there is copper on one side or both sides of the
board.
2. The number of copper layers and the thickness of the
board.
3. The use of external heat sinks.
4. The use of thermal vias.
5. Air flow and board orientation.
6. For non steady state applications, the pulse width, the
duty cycle and the transient thermal response of the part,
the board and the environment they are in.
FDB3652_F085 N-Channel PowerTrench® MOSFET
Thermal Resistance vs. Mounting Pad Area
The maximum rated junction temperature, TJM , and the
thermal resistance of the heat dissipating path determines
the maximum allowable device power dissipation, PDM , in an
application.
Therefore the application’s ambient
temperature, TA (oC), and thermal resistance RθJA (oC/W)
must be reviewed to ensure that TJM is never exceeded.
Equation 1 mathematically represents the relationship and
serves as the basis for establishing the rating of the part.
Fairchild provides thermal information to assist the
designer’s preliminary application evaluation. Figure 21
defines the RθJA for the device as a function of the top
copper (component side) area. This is for a horizontally
positioned FR-4 board with 1oz copper after 1000 seconds
of steady state power with no air flow. This graph provides
the necessary information for calculation of the steady state
junction temperature or power dissipation. Pulse
applications can be evaluated using the Fairchild device
Spice thermal model or manually utilizing the normalized
maximum transient thermal impedance curve.
Thermal resistances corresponding to other copper areas
can be obtained from Figure 21 or by calculation using
Equation 2 or 3. Equation 2 is used for copper area defined
in inches square and equation 3 is for area in centimeter
square. The area, in square inches or square centimeters is
the top copper area including the gate and source pads.
R
θ JA
19.84
( 0.262 + Area )
= 26.51 + -------------------------------------
(EQ. 2)
Area in Iches Squared
R
θ JA
128
( 1.69 + Area )
= 26.51 + ----------------------------------
(EQ. 3)
Area in Centimeter Squared
©2008 Fairchild Semiconductor Corporation
7
FDB3652_F085 Rev. A1
LDRAIN
DPLCAP
10
Dbody 7 5 DbodyMOD
Dbreak 5 11 DbreakMOD
Dplcap 10 5 DplcapMOD
RLDRAIN
RSLC1
51
5
51
ESLC
EVTHRES
+ 19 8
+
LGATE
GATE
1
11
+
17
EBREAK 18
-
50
RDRAIN
6
8
ESG
DBREAK
+
RSLC2
Ebreak 11 7 17 18 108.2
Eds 14 8 5 8 1
Egs 13 8 6 8 1
Esg 6 10 6 8 1
Evthres 6 21 19 8 1
Evtemp 20 6 18 22 1
It 8 17 1
DRAIN
2
5
EVTEMP
RGATE + 18 22
9
20
21
16
DBODY
MWEAK
6
MMED
MSTRO
RLGATE
Lgate 1 9 7.16e-9
Ldrain 2 5 1.0e-9
Lsource 3 7 2.29e-9
LSOURCE
CIN
8
7
SOURCE
3
RSOURCE
RLSOURCE
RLgate 1 9 71.6
RLdrain 2 5 10
RLsource 3 7 22.9
Mmed 16 6 8 8 MmedMOD
Mstro 16 6 8 8 MstroMOD
Mweak 16 21 8 8 MweakMOD
S1A
12
S2A
13
8
15
14
13
S1B
RBREAK
17
18
RVTEMP
S2B
13
CA
CB
6
8
Rbreak 17 18 RbreakMOD 1
Rdrain 50 16 RdrainMOD 5.7e-3
Rgate 9 20 1.06
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
Rsource 8 7 RsourceMOD 6.5e-3
Rvthres 22 8 RvthresMOD 1
Rvtemp 18 19 RvtempMOD 1
S1a 6 12 13 8 S1AMOD
S1b 13 12 13 8 S1BMOD
S2a 6 15 14 13 S2AMOD
S2b 13 15 14 13 S2BMOD
5
8
EDS
-
IT
14
+
+
EGS
19
VBAT
+
-
8
22
RVTHRES
FDB3652_F085 N-Channel PowerTrench® MOSFET
PSPICE Electrical Model
.SUBCKT FDP3652 2 1 3 rev March 2002
Ca 12 8 1.1e-9
Cb 15 14 1.1e-9
Cin 6 8 2.8e-9
Vbat 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*150),7))}
.MODEL DbodyMOD D (IS=1.5E-11 N=1.06 RS=2.5e-3 TRS1=2.4e-3 TRS2=1.1e-6
+ CJO=1.9e-9 M=5.8e-1 TT=2.5e-8 XTI=3.9)
.MODEL DbreakMOD D (RS=2.7e-1 TRS1=1e-3 TRS2=-8.9e-6)
.MODEL DplcapMOD D (CJO=7e-10 IS=1e-30 N=10 M=0.58)
.MODEL MmedMOD NMOS (VTO=3.6 KP=5.5 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=1.06)
.MODEL MstroMOD NMOS (VTO=4.3 KP=110 IS=1e-30 N=10 TOX=1 L=1u W=1u)
.MODEL MweakMOD NMOS (VTO=3 KP=0.03 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=1.06e1 RS=.1)
.MODEL RbreakMOD RES (TC1=1.05e-3 TC2=1e-6)
.MODEL RdrainMOD RES (TC1=1.7e-2 TC2=3.2e-5)
.MODEL RSLCMOD RES (TC1=1e-3 TC2=1e-7)
.MODEL RsourceMOD RES (TC1=1e-3 TC2=1e-6)
.MODEL RvthresMOD RES (TC1=-5.3e-3 TC2=-1.2e-5)
.MODEL RvtempMOD RES (TC1=-3.3e-3 TC2=1.3e-6)
.MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-8 VOFF=-5)
.MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-5 VOFF=-8)
.MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-1 VOFF=0.5)
.MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=0.5 VOFF=-1)
.ENDS
Note: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank
Wheatley.
©2008 Fairchild Semiconductor Corporation
8
FDB3652_F085 Rev. A1
dp.dbody n7 n5 = model=dbodymod
dp.dbreak n5 n11 = model=dbreakmod
dp.dplcap n10 n5 = model=dplcapmod
RDRAIN
6
8
ESG
EVTHRES
+ 19 8
+
spe.ebreak n11 n7 n17 n18 = 108.2
spe.eds n14 n8 n5 n8 = 1
GATE
1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evthres n6 n21 n19 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
LGATE
EVTEMP
RGATE + 18 22
9
20
21
11
DBODY
16
MWEAK
6
EBREAK
+
17
18
-
MMED
MSTRO
RLGATE
CIN
8
LSOURCE
7
RSOURCE
i.it n8 n17 = 1
RLSOURCE
S1A
l.lgate n1 n9 = 7.16e-9
l.ldrain n2 n5 = 1.0e-9
l.lsource n3 n7 = 2.29e-9
res.rlgate n1 n9 = 71.6
res.rldrain n2 n5 = 10
res.rlsource n3 n7 = 22.9
DBREAK
50
-
12
S2A
13
8
CA
15
14
13
S1B
RBREAK
17
18
RVTEMP
S2B
13
CB
EGS
-
19
IT
14
+
+
6
8
SOURCE
3
FDB3652_F085 N-Channel PowerTrench® MOSFET
SABER Electrical Model
REV March 2002
template FDP3652 n2,n1,n3
electrical n2,n1,n3
{
var i iscl
dp..model dbodymod = (isl=1.5e-11,nl=1.06,rs=2.5e-3,trs1=2.4e-3,trs2=1.1e-6,cjo=1.9e-9,m=5.8e-1,tt=2.5e-8,xti=3.9)
dp..model dbreakmod = (rs=2.7e-1,trs1=1e-3,trs2=-8.9e-6)
dp..model dplcapmod = (cjo=7e-10,isl=10e-30,nl=10,m=0.58)
m..model mmedmod = (type=_n,vto=3.6,kp=5.5,is=1e-30, tox=1)
m..model mstrongmod = (type=_n,vto=4.3,kp=110,is=1e-30, tox=1)
m..model mweakmod = (type=_n,vto=3,kp=0.03,is=1e-30, tox=1,rs=.1)
sw_vcsp..model s1amod = (ron=1e-5,roff=0.1,von=-8,voff=-5)
LDRAIN
DPLCAP 5
sw_vcsp..model s1bmod = (ron=1e-5,roff=0.1,von=-5,voff=-8)
DRAIN
2
sw_vcsp..model s2amod = (ron=1e-5,roff=0.1,von=-1,voff=0.5)
10
sw_vcsp..model s2bmod = (ron=1e-5,roff=0.1,von=0.5,voff=-1)
RLDRAIN
RSLC1
c.ca n12 n8 = 1.1e-9
51
c.cb n15 n14 = 1.1e-9
RSLC2
c.cin n6 n8 = 2.8e-9
ISCL
VBAT
5
8
EDS
-
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u
+
8
22
RVTHRES
res.rbreak n17 n18 = 1, tc1=1.05e-3,tc2=1e-6
res.rdrain n50 n16 = 5.7e-3, tc1=1.7e-2,tc2=3.2e-5
res.rgate n9 n20 = 1.06
res.rslc1 n5 n51 = 1e-6, tc1=1e-3,tc2=1e-7
res.rslc2 n5 n50 = 1e3
res.rsource n8 n7 = 6.5e-3, tc1=1e-3,tc2=1e-6
res.rvthres n22 n8 = 1, tc1=-5.3e-3,tc2=-1.2e-5
res.rvtemp n18 n19 = 1, tc1=-3.3e-3,tc2=1.3e-6
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc=1
equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/150))** 7))
}
}
©2008 Fairchild Semiconductor Corporation
9
FDB3652_F085 Rev. A1
th
JUNCTION
FDP3652
CTHERM1 TH 6 1e-2
CTHERM2 6 5 1.5e-2
CTHERM3 5 4 2e-2
CTHERM4 4 3 2.1e-2
CTHERM5 3 2 2.2e-2
CTHERM6 2 TL 9e-2
RTHERM1
CTHERM1
6
RTHERM1 TH 6 2.7e-2
RTHERM2 6 5 2.8e-2
RTHERM3 5 4 7.8e-2
RTHERM4 4 3 9e-2
RTHERM5 3 2 2.7e-1
RTHERM6 2 TL 2.87e-1
CTHERM2
RTHERM2
5
SABER Thermal Model
CTHERM3
RTHERM3
SABER thermal model FDP3652
template thermal_model th tl
thermal_c th, tl
{
ctherm.ctherm1 th 6 =1e-2
ctherm.ctherm2 6 5 =1.5e-2
ctherm.ctherm3 5 4 =2e-2
ctherm.ctherm4 4 3 =2.1e-2
ctherm.ctherm5 3 2 =2.2e-2
ctherm.ctherm6 2 tl =9e-2
4
CTHERM4
RTHERM4
3
rtherm.rtherm1 th 6 =2.7e-2
rtherm.rtherm2 6 5 =2.8e-2
rtherm.rtherm3 5 4 =7.8e-2
rtherm.rtherm4 4 3 =9e-2
rtherm.rtherm5 3 2 =2.7e-1
rtherm.rtherm6 2 tl =2.87e-1
}
CTHERM5
RTHERM5
2
CTHERM6
RTHERM6
tl
©2008 Fairchild Semiconductor Corporation
FDB3652_F085 N-Channel PowerTrench® MOSFET
SPICE Thermal Model
REV 23 March 2002
10
CASE
FDB3652_F085 Rev. A1
FRFET®
Global Power ResourceSM
Green FPS™
Green FPS™ e-Series™
GTO™
IntelliMAX™
ISOPLANAR™
MegaBuck™
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MicroFET™
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OPTOPLANAR®
Build it Now™
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EZSWITCH™ *
™
®
Fairchild®
Fairchild Semiconductor®
FACT Quiet Series™
FACT®
FAST®
FastvCore™
FlashWriter® *
FPS™
F-PFS™
Programmable Active Droop™
QFET®
QS™
Quiet Series™
RapidConfigure™
tm
TinyBoost™
TinyBuck™
TinyLogic®
TINYOPTO™
™
TinyPower™
Saving our world, 1mW /W /kW at a time™
TinyPWM™
SmartMax™
TinyWire™
SMART START™
μSerDes™
SPM®
STEALTH™
SuperFET™
UHC®
SuperSOT™-3
Ultra FRFET™
SuperSOT™-6
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VCX™
SupreMOS™
VisualMax™
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XS™
®
®
tm
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Datasheet contains the design specifications for product development. Specifications may
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Semiconductor. The datasheet is for reference information only.
Rev. I37
©2008 Fairchild Semiconductor Corporation
11
FDB3652_F085 Rev. A1
FDB3652_F085 N-Channel PowerTrench® MOSFET
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