ANSALDO Via N. Lorenzi 8 - I 16152 GENOVA - ITALY Tel. int. +39/(0)10 6556549 - (0)10 6556488 Fax Int. +39/(0)10 6442510 Tx 270318 ANSUSE I - Ansaldo Trasporti s.p.a. Unita' Semiconduttori PHASE CONTROL THYRISTOR AT704 Repetitive voltage up to Mean on-state current Surge current 1600 V 640 A 8 kA FINAL SPECIFICATION Feb 97 - ISSUE : 04 Symbol Characteristic Tj [°C] Conditions Value Unit BLOCKING V RRM Repetitive peak reverse voltage 125 1600 V V RSM Non-repetitive peak reverse voltage 125 1700 V V DRM Repetitive peak off-state voltage 125 1600 V I RRM Repetitive peak reverse current V=VRRM 125 50 mA I DRM Repetitive peak off-state current V=VDRM 125 50 mA I T (AV) Mean on-state current 180° sin, 50 Hz, Th=55°C, double side cooled 640 A I T (AV) Mean on-state current 180° sin, 50 Hz, Tc=85°C, double side cooled I TSM Surge on-state current sine wave, 10 ms I² t I² t without reverse voltage V T On-state voltage On-state current = V T(TO) Threshold voltage 125 0.86 V T On-state slope resistance 125 0.790 mohm CONDUCTING r 1000 A 515 A 125 8 kA 25 1.58 320 x1E3 A²s V SWITCHING di/dt Critical rate of rise of on-state current, min. From 75% VDRM up to 720 A, gate 10V 5ohm 125 200 A/µs dv/dt Critical rate of rise of off-state voltage, min. Linear ramp up to 70% of VDRM 125 500 V/µs td Gate controlled delay time, typical VD=100V, gate source 10V, 10 ohm , tr=.5 µs 25 1.3 µs tq Circuit commutated turn-off time, typical dV/dt = 20 V/µs linear up to 75% VDRM Q rr Reverse recovery charge di/dt=-20 A/µs, I= 470 A I rr Peak reverse recovery current VR= 50 V I H Holding current, typical VD=5V, gate open circuit 25 300 mA I L Latching current, typical VD=5V, tp=30µs 25 700 mA 250 125 µs µC A GATE V GT Gate trigger voltage VD=5V 25 3.5 V I GT Gate trigger current VD=5V 25 200 mA V GD Non-trigger gate voltage, min. VD=VDRM 125 0.25 V V FGM Peak gate voltage (forward) 30 V 10 A 5 V 150 W 2 W 52 °C/kW 10 °C/kW I FGM Peak gate current V RGM Peak gate voltage (reverse) P GM Peak gate power dissipation P G Average gate power dissipation R th(j-h) Thermal impedance, DC Junction to heatsink, double side cooled R th(c-h) Thermal impedance Case to heatsink, double side cooled T F j Operating junction temperature Mounting force Mass Pulse width 100 µs MOUNTING -30 / 125 8.4 / 9.4 280 ORDERING INFORMATION : AT704 S 16 standard specification VDRM&VRRM/100 °C kN g ANSALDO AT704 PHASE CONTROL THYRISTOR FINAL SPECIFICATION Feb 97 - ISSUE : 04 DISSIPATION CHARACTERISTICS SQUARE WAVE Th [°C] 130 120 110 100 90 30° 80 60° 70 90° 120° 180° 60 DC 50 0 200 400 600 800 1000 IF(AV) [A] PF(AV) [W] 1400 DC 1200 180° 90° 1000 120° 60° 800 30° 600 400 200 0 0 200 400 600 IF(AV) [A] 800 1000 ANSALDO AT704 PHASE CONTROL THYRISTOR FINAL SPECIFICATION Feb 97 - ISSUE : 04 DISSIPATION CHARACTERISTICS SINE WAVE Th [°C] 130 120 110 100 90 80 30° 70 60° 90° 60 120° 180° 50 0 200 400 600 800 1000 800 1000 IF(AV) [A] PF(AV) [W] 1400 180° 1200 90° 1000 120° 60° 30° 800 600 400 200 0 0 200 400 600 IF(AV) [A] ANSALDO AT704 PHASE CONTROL THYRISTOR FINAL SPECIFICATION Feb 97 - ISSUE : 04 ON-STATE CHARACTERISTIC Tj = 125 °C SURGE CHARACTERISTIC Tj = 125 °C 2000 8 1800 7 6 1400 5 1200 ITSM [kA] On-state Current [A] 1600 1000 800 4 3 600 2 400 1 200 0 0 0.6 1.1 1.6 2.1 2.6 1 On-state Voltage [V] 10 n° cycles TRANSIENT THERMAL IMPEDANCE DOUBLE SIDE COOLED 60.0 Zth j-h [°C/kW] 50.0 40.0 30.0 20.0 10.0 0.0 0.001 0.01 0.1 1 t[s] 10 100 Cathode terminal type DIN 46244 - A 4.8 - 0.8 Gate terminal type AMP 60598 - 1 Distributed by All the characteristics given in this data sheet are guaranteed only with uniform clamping force, cleaned and lubricated heatsink, surfaces with flatness < .03 mm and roughness < 2 µm. In the interest of product improvement ANSALDO reserves the right to change any data given in this data sheet at any time without previous notice. If not stated otherwise the maximum value of ratings (simbols over shaded background) and characteristics is reported. 100