ON Semiconductor MMBT6428LT1 MMBT6429LT1 Amplifier Transistors NPN Silicon 3 MAXIMUM RATINGS 1 Rating 2 Symbol 6428LT1 6429LT1 Unit Collector–Emitter Voltage VCEO 50 45 Vdc Collector–Base Voltage VCBO 60 55 Vdc Emitter–Base Voltage VEBO 6.0 Vdc IC 200 mAdc Symbol Max Unit PD 225 mW 1.8 mW/°C RJA 556 °C/W PD 300 mW 2.4 mW/°C RJA 417 °C/W TJ, Tstg –55 to +150 °C Collector Current — Continuous CASE 318–08, STYLE 6 SOT–23 (TO–236) COLLECTOR 3 THERMAL CHARACTERISTICS Characteristic Total Device Dissipation FR–5 Board(1) TA = 25°C Derate above 25°C Thermal Resistance, Junction to Ambient Total Device Dissipation Alumina Substrate,(2) TA = 25°C Derate above 25°C Thermal Resistance, Junction to Ambient Junction and Storage Temperature 1 BASE 2 EMITTER DEVICE MARKING MMBT6428LT1 = 1KM; MMBT6429LT1 = 1L ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted) Characteristic Symbol Min Max 50 45 — — 60 55 — — — 0.1 — 0.01 — 0.01 Unit OFF CHARACTERISTICS Collector–Emitter Breakdown Voltage (IC = 1.0 mAdc, IB = 0) (IC = 1.0 mAdc, IB = 0) MMBT6428 MMBT6429 V(BR)CEO Collector–Base Breakdown Voltage (IC = 0.1 mAdc, IE = 0) (IC = 0.1 mAdc, IE = 0) MMBT6428 MMBT6429 Vdc V(BR)CBO Collector Cutoff Current (VCE = 30 Vdc) ICES Collector Cutoff Current (VCB = 30 Vdc, IE = 0) ICBO Emitter Cutoff Current (VEB = 5.0 Vdc, IC = 0) IEBO Vdc µAdc µAdc µAdc 1. FR–5 = 1.0 0.75 0.062 in. 2. Alumina = 0.4 0.3 0.024 in. 99.5% alumina. Semiconductor Components Industries, LLC, 2001 November, 2001 – Rev. 2 1 Publication Order Number: MMBT6428LT1/D MMBT6428LT1 MMBT6429LT1 ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted) (Continued) Symbol Min Max MMBT6428 MMBT6429 250 500 — — (IC = 0.1 mAdc, VCE = 5.0 Vdc) MMBT6428 MMBT6429 250 500 650 1250 (IC = 1.0 mAdc, VCE = 5.0 Vdc) MMBT6428 MMBT6429 250 500 — — (IC = 10 mAdc, VCE = 5.0 Vdc) MMBT6428 MMBT6429 250 500 — — — — 0.2 0.6 0.56 0.66 100 700 — 3.0 — 8.0 Characteristic Unit ON CHARACTERISTICS DC Current Gain (IC = 0.01 mAdc, VCE = 5.0 Vdc) hFE Collector–Emitter Saturation Voltage (IC = 10 mAdc, IB = 0.5 mAdc) (IC = 100 mAdc, IB = 5.0 mAdc) VCE(sat) Base–Emitter On Voltage (IC = 1.0 mAdc, VCE = 5.0 mAdc) VBE(on) — Vdc Vdc SMALL–SIGNAL CHARACTERISTICS Current–Gain — Bandwidth Product (IC = 1.0 mAdc, VCE = 5.0 Vdc, f = 100 MHz) fT Output Capacitance (VCB = 10 Vdc, IE = 0, f = 1.0 MHz) Cobo Input Capacitance (VEB = 0.5 Vdc, IC = 0, f = 1.0 MHz) Cibo RS in en IDEAL TRANSISTOR Figure 1. Transistor Noise Model http://onsemi.com 2 MHz pF pF MMBT6428LT1 MMBT6429LT1 NOISE CHARACTERISTICS (VCE = 5.0 Vdc, TA = 25°C) NOISE VOLTAGE 30 IC = 10 mA BANDWIDTH = 1.0 Hz 20 RS ≈ 0 en , NOISE VOLTAGE (nV) 20 en , NOISE VOLTAGE (nV) 30 BANDWIDTH = 1.0 Hz 3.0 mA 10 1.0 mA 7.0 5.0 3.0 300 µA 10 20 50 100 200 RS ≈ 0 f = 10 Hz 10 100 Hz 7.0 10 kHz 3.0 0.01 0.02 500 1k 2k 5k 10k 20k 50k 100k f, FREQUENCY (Hz) Figure 2. Effects of Frequency IC = 10 mA 2.0 1.0 mA 300 µA 100 µA 0.3 0.2 0.1 16 3.0 mA 1.0 0.7 0.5 RS ≈ 0 10 20 10 µA 50 100 200 0.05 0.1 0.2 0.5 1.0 2.0 IC, COLLECTOR CURRENT (mA) 5.0 10 20 BANDWIDTH = 1.0 Hz 3.0 100 kHz Figure 3. Effects of Collector Current NF, NOISE FIGURE (dB) In, NOISE CURRENT (pA) 10 7.0 5.0 1.0 kHz 5.0 BANDWIDTH = 10 Hz to 15.7 kHz 12 500 µA 8.0 IC = 1.0 mA 100 µA 10 µA 4.0 30 µA 0 10 500 1k 2k 5k 10k 20k 50k 100k f, FREQUENCY (Hz) 20 Figure 4. Noise Current 50 100 200 500 1k 2k 5k 10k 20k 50k 100k RS, SOURCE RESISTANCE (OHMS) Figure 5. Wideband Noise Figure 100 Hz NOISE DATA 20 BANDWIDTH = 1.0 Hz 100 µA 100 70 50 3.0 mA 1.0 mA 30 300 µA 20 10 7.0 5.0 3.0 IC = 10 mA 30 µA 10 µA 10 20 NF, NOISE FIGURE (dB) VT, TOTAL NOISE VOLTAGE (nV) 300 200 16 IC = 10 mA 3.0 mA 1.0 mA 12 300 µA 8.0 100 µA 4.0 0 50 100 200 500 1k 2k 5k 10k 20k 50k 100k RS, SOURCE RESISTANCE (OHMS) 30 µA 10 Figure 6. Total Noise Voltage 20 50 100 200 500 1k 2k 5k 10k 20k 50k 100k RS, SOURCE RESISTANCE (OHMS) Figure 7. Noise Figure http://onsemi.com 3 10 µA BANDWIDTH = 1.0 Hz h FE, DC CURRENT GAIN (NORMALIZED) MMBT6428LT1 MMBT6429LT1 4.0 3.0 VCE = 5.0 V 2.0 TA = 125°C 25°C 1.0 -55°C 0.7 0.5 0.4 0.3 0.2 0.01 0.02 0.03 0.05 0.1 0.2 0.3 0.5 IC, COLLECTOR CURRENT (mA) 1.0 2.0 3.0 5.0 10 Figure 8. DC Current Gain 1.0 -0.4 RθVBE, BASE-EMITTER TEMPERATURE COEFFICIENT (mV/ °C) TJ = 25°C V, VOLTAGE (VOLTS) 0.8 0.6 VBE @ VCE = 5.0 V 0.4 0.2 VCE(sat) @ IC/IB = 10 0 0.01 0.02 0.05 0.1 0.2 0.5 1.0 2.0 5.0 10 20 IC, COLLECTOR CURRENT (mA) 50 -0.8 -1.2 TJ = 25°C to 125°C -1.6 -2.0 -55°C to 25°C -2.4 0.01 0.02 0.05 0.1 0.2 0.5 1.0 2.0 5.0 10 IC, COLLECTOR CURRENT (mA) 100 C, CAPACITANCE (pF) TJ = 25°C Cob 4.0 3.0 Ceb Cib Ccb 2.0 1.0 0.8 0.1 0.2 1.0 2.0 5.0 0.5 10 20 VR, REVERSE VOLTAGE (VOLTS) 50 100 f T, CURRENT-GAIN 8.0 6.0 50 100 Figure 10. Temperature Coefficients BANDWIDTH PRODUCT (MHz) Figure 9. “On” Voltages 20 Figure 11. Capacitance 500 300 200 100 VCE = 5.0 V TJ = 25°C 70 50 1.0 2.0 3.0 5.0 7.0 10 20 30 IC, COLLECTOR CURRENT (mA) 50 70 100 Figure 12. Current–Gain — Bandwidth Product http://onsemi.com 4 MMBT6428LT1 MMBT6429LT1 INFORMATION FOR USING THE SOT–23 SURFACE MOUNT PACKAGE MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to insure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process. 0.037 0.95 0.037 0.95 0.079 2.0 0.035 0.9 0.031 0.8 inches mm SOT–23 SOT–23 POWER DISSIPATION SOLDERING PRECAUTIONS The power dissipation of the SOT–23 is a function of the pad size. This can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RθJA, the thermal resistance from the device junction to ambient, and the operating temperature, TA. Using the values provided on the data sheet for the SOT–23 package, PD can be calculated as follows: PD = The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. • Always preheat the device. • The delta temperature between the preheat and soldering should be 100°C or less.* • When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10°C. • The soldering temperature and time shall not exceed 260°C for more than 10 seconds. • When shifting from preheating to soldering, the maximum temperature gradient shall be 5°C or less. • After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. • Mechanical stress or shock should not be applied during cooling. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. TJ(max) – TA RθJA The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values into the equation for an ambient temperature TA of 25°C, one can calculate the power dissipation of the device which in this case is 225 milliwatts. PD = 150°C – 25°C 556°C/W = 225 milliwatts The 556°C/W for the SOT–23 package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 225 milliwatts. There are other alternatives to achieving higher power dissipation from the SOT–23 package. Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Clad. Using a board material such as Thermal Clad, an aluminum core board, the power dissipation can be doubled using the same footprint. http://onsemi.com 5 MMBT6428LT1 MMBT6429LT1 PACKAGE DIMENSIONS SOT–23 (TO–236) CASE 318–08 ISSUE AF NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH THICKNESS. MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL. A L 3 1 V B S 2 G C D H K J STYLE 6: PIN 1. BASE 2. EMITTER 3. COLLECTOR http://onsemi.com 6 DIM A B C D G H J K L S V INCHES MIN MAX 0.1102 0.1197 0.0472 0.0551 0.0350 0.0440 0.0150 0.0200 0.0701 0.0807 0.0005 0.0040 0.0034 0.0070 0.0140 0.0285 0.0350 0.0401 0.0830 0.1039 0.0177 0.0236 MILLIMETERS MIN MAX 2.80 3.04 1.20 1.40 0.89 1.11 0.37 0.50 1.78 2.04 0.013 0.100 0.085 0.177 0.35 0.69 0.89 1.02 2.10 2.64 0.45 0.60 MMBT6428LT1 MMBT6429LT1 Notes http://onsemi.com 7 MMBT6428LT1 MMBT6429LT1 Thermal Clad is a trademark of the Bergquist Company. ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. 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