ICST ICS853052AM Dual lvcmos / lvttl-to-differential 2.5v, 3.3v, 5v lvpecl multiplexer Datasheet

PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS853052
DUAL LVCMOS / LVTTL-TO-DIFFERENTIAL
2.5V, 3.3V, 5V LVPECL MULTIPLEXER
GENERAL DESCRIPTION
FEATURES
The ICS853052 is a Dual LVCMOS / LVTTL-toDifferential 2.5V, 3.3V, 5V LVPECL Multiplexer
HiPerClockS™
and a member of the HiPerClocks™family of High
Performance Clocks Solutions from ICS. The
ICS853052 has two selectable single ended
clock inputs. The single ended clock input accepts LVCMOS
or LVTTL input levels and translates them to 2.5V, 3.3V or 5V
LVPECL levels. The small outline 8-pin TSSOP or 8-pin SOIC
packages make this device ideal for applications where space,
high performance and low power are important.
• 1 differential 2.5V, 3.3V or 5V LVPECL output
ICS
• 2 selectable LVCMOS/LVTTL clock inputs
• Output frequency: TBD
• Additive phase jitter, RMS: 0.06ps (typical)
• Propagation Delay: 370ps (typical)
• 2.5V, 3.3V or 5V operating supply voltage
(operating range 2.375V to 5.5V)
• -40°C to 85°C ambient operating temperature
• Pin compatible with MC100EP58
BLOCK DIAGRAM
Da
PIN ASSIGNMENT
nc
Da
Db
SEL
1
nQ
Q
Db
0
1
2
3
4
8
7
6
5
VCC
Q
nQ
VEE
ICS853052
SEL
8-Lead TSSOP, 118 mil
3mm x 3mm x 0.95mm package body
G Package
Top View
8-Lead SOIC, 150 mil
3.90mm x 4.90mm x 1.37mm package body
M Package
Top View
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
853052AG
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REV. A JULY 1, 2004
1
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS853052
DUAL LVCMOS / LVTTL-TO-DIFFERENTIAL
2.5V, 3.3V, 5V LVPECL MULTIPLEXER
TABLE 1. PIN DESCRIPTIONS
Number
Name
1
nc
Unused
Type
2, 3
Da, Db
Input
4
SEL
Input
Description
No connect.
Pulldown LVCMOS / LVTTL clock inputs.
Select input pin. When HIGH, selects Da input clock.
Pulldown When Low selects Db input clock.
Single-ended 100H LVPECL interface levels.
Negative supply pin.
5
VEE
Power
6, 7
nQ, Q
Output
Differential output pair. LVPECL interface levels.
8
VCC
Power
Positive supply pin.
NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
CIN
Input Capacitance
RPULLDOWN
Input Pulldown Resistor
TABLE 3.
Test Conditions
Minimum
Typical
Maximum
Units
1
pF
75
KΩ
CONTROL INPUT FUNCTION TABLE
Inputs
SEL
Selected Source
0
Db
1
Da
853052AG
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ICS853052
DUAL LVCMOS / LVTTL-TO-DIFFERENTIAL
2.5V, 3.3V, 5V LVPECL MULTIPLEXER
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC
6V (LVPECL mode, VEE = 0)
Negative Supply Voltage, VEE
-6V (ECL mode, VCC = 0)
Inputs, VI (LVPECL mode)
-0.5V to VCC + 0.5 V
Inputs, VI (ECL mode)
0.5V to VEE - 0.5V
Outputs, IO
Continuous Current
Surge Current
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage
to the device. These ratings are stress specifications only. Functional operation of product at
these conditions or any conditions beyond those
50mA
100mA
listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maxi-
Operating Temperature Range, TA -40°C to +85°C
mum rating conditions for extended periods may
affect product reliability.
Storage Temperature, TSTG
-65°C to 150°C
Package Thermal Impedance, θJA
101.7°C/W (0 m/s) TSSOP
112.7°C/W (0 lfpm) SOIC
(Junction-to-Ambient)
TABLE 4A. DC CHARACTERISTICS, VCC = 2.5V; VEE = 0V
Symbol
Parameter
IEE
Power Supply Current
-40°C
Typ
Min
Max
Min
21
25°C
Typ
Max
Min
21
85°C
Typ
Max
21
Units
mA
VOH
Output High Voltage; NOTE 1
1.375
1.475
1.58
1.425
1.495
1.57
1.495
1.53
1.565
V
VOL
Output Low Voltage; NOTE 1
Input High Voltage,
Single-Ended
Input Low Voltage,
Single-Ended
Input High Current
0.605
0.745
0.88
0.625
0.72
0.815
0.64
0.735
0.83
V
1.275
1.56
1.275
1.56
1.275
-0.83
V
0.63
0.965
0.63
0.965
0.63
0.965
V
150
µA
VIH
VIL
IIH
150
IIL
Input Low Current
150
Input and output parameters vary 1:1 with VCC.
NOTE 1: Outputs terminated with 50Ω to VCC - 2V.
150
150
150
µA
TABLE 4B. DC CHARACTERISTICS, VCC = 3.3V; VEE = 0V
Min
-40°C
Typ
Output High Voltage; NOTE 1
2175
Output Low Voltage; NOTE 1
Input High Voltage),
(Single-Ended)
Input Low Voltage,
(Single-Ended)
Input High Current
1405
Symbol
Parameter
IEE
Power Supply Current
VOH
VOL
VIH
VIL
IIH
Max
Min
25°C
Typ
2275
Min
85°C
Typ
2380
2225
2295
2370
2295
2330
2365
mV
1545
1680
1425
1520
1615
1440
1535
1630
mV
2075
2420
2075
2420
2075
2420
mV
1355
1675
1355
1675
1355
1675
mV
21
21
150
Input Low Current
150
IIL
Input and output parameters vary 1:1 with VCC.
NOTE 1: Outputs terminated with 50Ω to VCC - 2V.
853052AG
Max
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3
21
150
150
Max
mA
150
150
Units
µA
µA
REV. A JULY 1, 2004
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ICS853052
DUAL LVCMOS / LVTTL-TO-DIFFERENTIAL
2.5V, 3.3V, 5V LVPECL MULTIPLEXER
TABLE 4C. DC CHARACTERISTICS, VCC = 5V; VEE = 0V
Symbol
Parameter
IEE
Power Supply Current
Min
-40°C
Typ
Max
25°C
Typ
Min
21
Max
Min
21
85°C
Typ
Max
21
Units
mA
VOH
Output High Voltage; NOTE 1
3875
3975
4105
4080
3925
3995
4070
3995
4065
mV
VOL
Output Low Voltage; NOTE 1
Input High Voltage,
Single-Ended
Input Low Voltage,
Single-Ended
Input High Current
3105
3245
3380
3125
3220
3315
3140
3235
3330
mV
3775
4120
3775
4120
3775
4120
mV
3055
3375
3055
3375
3055
3375
mV
150
µA
VIH
VIL
IIH
150
150
Input Low Current
150
IIL
Input and output parameters vary 1:1 with VCC.
NOTE 1: Outputs terminated with 50Ω to VCC - 2V.
150
150
µA
TABLE 4D. ECL DC CHARACTERISTICS, VCC = 0V; VEE = -5.5V TO -2.375V
Min
-40°C
Typ
Output High Voltage; NOTE 1
-1125
Output Low Voltage; NOTE 1
Input High Voltage,
Single-Ended
Input Low Voltage,
Single-Ended
Input High Current
-1895
Symbol
Parameter
IEE
Power Supply Current
VOH
VOL
VIH
VIL
IIH
Max
Min
25°C
Typ
Max
Min
85°C
Typ
-1025
-920
-1075
-1005
-930
-1005
-970
-935
mV
-1755
-1620
-1875
-1780
-1685
-1860
-1765
-1670
mV
-1225
-880
-1225
-880
-1225
-880
mV
-1945
-1625
-1945
-1625
-1945
-1625
mV
150
µA
21
21
21
150
IIL
Input Low Current
150
Input and output parameters vary 1:1 with VCC.
NOTE 1: Outputs terminated with 50Ω to VCC - 2V.
Max
150
150
Units
mA
150
µA
TABLE 5. AC CHARACTERISTICS, VCC = 0V; VEE = -5.5V TO -2.375V OR VCC = 2.375V TO 5.5V; VEE = 0V
-40°C
25°C
85°C
Symbol
Parameter
fMAX
TBD
TBD
TBD
GHz
TBD
370
TBD
ps
TBD
370
TBD
ps
TBD
0.06
TBD
ps
V PP
Output Frequency
Propagation Delay, Low to High;
NOTE 1
Propagation Delay, High to Low;
NOTE 1
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter section
Input Voltage Swing (Differential)
TBD
TBD
TBD
ps
tR/tF
Output Rise/Fall Time
TBD
180
TBD
ps
tPLH
tPHL
tjit
Min
20% to 80%
Typ
Max
Min
Typ
Max
Min
Typ
Max
Units
All parameters are measured ≤ 1GHz unless otherwise noted.
NOTE 1: Measured from VCC/2 of the input crossing point to the differential output crossing point.
853052AG
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ICS853052
DUAL LVCMOS / LVTTL-TO-DIFFERENTIAL
2.5V, 3.3V, 5V LVPECL MULTIPLEXER
ADDITIVE PHASE JITTER
the 1Hz band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value,
which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a
better understanding of its effects on the desired application over
the entire time record of the signal. It is mathematically possible
to calculate an expected bit error rate given a phase noise plot.
The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the
dBc Phase Noise. This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise
power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This
ratio is expressed in decibels (dBm) or a ratio of the power in
0
-10
Input/Output Additive Phase Jitter
-20
@ 155.52MHz (12KHz to 20MHz)
= 0.06ps typical
-30
-40
SSB PHASE NOISE dBc/HZ
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
100
1k
10k
100k
1M
10M
100M
-190
OFFSET FROM CARRIER FREQUENCY (HZ)
As with most timing specifications, phase noise measurements
have issues. The primary issue relates to the limitations of the
equipment. Often the noise floor of the equipment is higher than
the noise floor of the device. This is illustrated above. The de-
853052AG
vice meets the noise floor of what is shown, but can actually be
lower. The phase noise is dependant on the input source and
measurement equipment.
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ICS853052
DUAL LVCMOS / LVTTL-TO-DIFFERENTIAL
2.5V, 3.3V, 5V LVPECL MULTIPLEXER
PARAMETER MEASUREMENT INFORMATION
2V
V CC
Qx
SCOPE
Da Db
nQ
LVPECL
Q
nQx
VEE
tPD
-3.5V to -0.375V
PROPAGATION DELAY
OUTPUT LOAD AC TEST CIRCUIT
80%
80%
VSW I N G
Clock
Outputs
20%
20%
tR
tF
OUTPUT RISE/FALL TIME
853052AG
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ICS853052
DUAL LVCMOS / LVTTL-TO-DIFFERENTIAL
2.5V, 3.3V, 5V LVPECL MULTIPLEXER
APPLICATION INFORMATION
TERMINATION FOR 2.5V LVPECL OUTPUT
Figure 1A and Figure 1B show examples of termination for 2.5V
LVPECL driver. These terminations are equivalent to terminating 50Ω to VCC - 2V. For VCC = 2.5V, the VCC - 2V is very close to
ground level. The R3 in Figure 1B can be eliminated and the
termination is shown in Figure 1C.
2.5V
VCC=2.5V
2.5V
2.5V
VCC=2.5V
R1
250
Zo = 50 Ohm
R3
250
+
Zo = 50 Ohm
+
Zo = 50 Ohm
-
Zo = 50 Ohm
2,5V LVPECL
Driv er
-
R1
50
2,5V LVPECL
Driv er
R2
62.5
R2
50
R4
62.5
R3
18
FIGURE 1B. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
FIGURE 1A. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
2.5V
VCC=2.5V
Zo = 50 Ohm
+
Zo = 50 Ohm
2,5V LVPECL
Driv er
R1
50
R2
50
FIGURE 1C. 2.5V LVPECL TERMINATION EXAMPLE
853052AG
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ICS853052
DUAL LVCMOS / LVTTL-TO-DIFFERENTIAL
2.5V, 3.3V, 5V LVPECL MULTIPLEXER
TERMINATION FOR 3.3V LVPECL OUTPUTS
50Ω transmission lines. Matched impedance techniques should
be used to maximize operating frequency and minimize signal
distortion. Figures 2A and 2B show two different layouts which
are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned
are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must
be used for functionality. These outputs are designed to drive
3.3V
Zo = 50Ω
125Ω
FOUT
125Ω
FIN
Zo = 50Ω
Zo = 50Ω
FOUT
50Ω
FIN
50Ω
Zo = 50Ω
VCC - 2V
1
RTT =
Z
((VOH + VOL) / (VCC – 2)) – 2 o
RTT
84Ω
FIGURE 2A. LVPECL OUTPUT TERMINATION
84Ω
FIGURE 2B. LVPECL OUTPUT TERMINATION
TERMINATION FOR 5V LVPECL OUTPUT
This section shows examples of 5V LVPECL output termination. Figure 3A shows standard termination for 5V LVPECL. The
termination requires matched load of 50Ω resistors pull down to
VCC - 2V = 3V at the receiver. Figure 3B shows Thevenin equivalence of Figure 3A. In actual application where the 3V DC power
supply is not available, this approached is normally used.
5V
5V
5V
5V
R3
84
PECL
PECL
Zo = 50 Ohm
R4
84
Zo = 50 Ohm
+
+
Zo = 50 Ohm
Zo = 50 Ohm
-
R1
50
-
PECL
R1
125
R2
50
PECL
R2
125
3V
FIGURE 3A. STANDARD 5V PECL OUTPUT TERMINATION
853052AG
FIGURE 3B. 5V PECL OUTPUT TERMINATION EXAMPLE
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REV. A JULY 1, 2004
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ICS853052
DUAL LVCMOS / LVTTL-TO-DIFFERENTIAL
2.5V, 3.3V, 5V LVPECL MULTIPLEXER
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS853052.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS853052 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 5.5V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VCC_MAX * IEE_MAX = 5.5V * 21mA = 115.5mW
Power (outputs)MAX = 30.94mW/Loaded Output pair
Total Power_MAX (5.5V, with all outputs switching) = 115.5mW + 30.94mW = 146.4mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a
moderate air flow of 1 meter per second and a multi-layer board, the appropriate value is 90.5°C/W per Table 6A below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.146W * 90.5°C/W = 98.2°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 6A. THERMAL RESISTANCE θJA FOR 8-PIN TSSOP, FORCED CONVECTION
θJA by Velocity (Meters per Second)
Multi-Layer PCB, JEDEC Standard Test Boards
0
1
2
101.7°C/W
90.5°C/W
89.8°C/W
TABLE 6B. THERMAL RESISTANCE θJA FOR 8-PIN SOIC, FORCED CONVECTION
θJA by Velocity (Linear Feet per Minute)
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
0
200
500
153.3°C/W
112.7°C/W
128.5°C/W
103.3°C/W
115.5°C/W
97.1°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
853052AG
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DUAL LVCMOS / LVTTL-TO-DIFFERENTIAL
2.5V, 3.3V, 5V LVPECL MULTIPLEXER
3. Calculations and Equations.
LVPECL output driver circuit and termination are shown in Figure 4.
VCC
Q1
VOUT
RL
50
VCC - 2V
Figure 4. LVPECL Driver Circuit and Termination
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage of V - 2V.
CC
•
For logic high, VOUT = V
OH_MAX
(V
CC_MAX
•
-V
OH_MAX
OL_MAX
CC_MAX
Pd_H = [(V
OH_MAX
-V
OL_MAX
CC_MAX
– 0.935V
) = 0.935V
For logic low, VOUT = V
(V
=V
=V
CC_MAX
– 1.67V
) = 1.67V
– (V
CC_MAX
- 2V))/R ] * (V
CC_MAX
L
-V
OH_MAX
) = [(2V - (V
CC_MAX
-V
OH_MAX
))/R ] * (V
-V
CC _MAX
L
OH_MAX
)=
[(2V - 0.935V)/50Ω] * 0.935V = 19.92mW
Pd_L = [(V
OL_MAX
– (V
CC_MAX
- 2V))/R ] * (V
L
CC_MAX
-V
OL_MAX
) = [(2V - (V
CC_MAX
-V
OL_MAX
))/R ] * (V
L
CC_MAX
-V
OL_MAX
)=
[(2V - 1.67V)/50Ω] * 1.67V = 11.02mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30.94mW
853052AG
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ICS853052
DUAL LVCMOS / LVTTL-TO-DIFFERENTIAL
2.5V, 3.3V, 5V LVPECL MULTIPLEXER
RELIABILITY INFORMATION
TABLE 7A.
θJAVS. AIR FLOW TABLE FOR 8 LEAD TSSOP
θJA by Velocity (Meters per Second)
Multi-Layer PCB, JEDEC Standard Test Boards
TABLE 7B.
0
1
2
101.7°C/W
90.5°C/W
89.8°C/W
θJAVS. AIR FLOW TABLE FOR 8 LEAD SOIC
θJA by Velocity (Linear Feet per Minute)
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
0
200
500
153.3°C/W
112.7°C/W
128.5°C/W
103.3°C/W
115.5°C/W
97.1°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS853052 is: 110
853052AG
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DUAL LVCMOS / LVTTL-TO-DIFFERENTIAL
2.5V, 3.3V, 5V LVPECL MULTIPLEXER
PACKAGE OUTLINE - G SUFFIX FOR 8 LEAD TSSOP
PACKAGE OUTLINE - M SUFFIX FOR 8 LEAD SOIC
TABLE 8A. PACKAGE DIMENSIONS
SYMBOL
TABLE 8B. PACKAGE DIMENSIONS
Minimum
SYMBOL
Maximum
8
--
1.10
A
A1
0
0.15
A2
0.79
0.97
b
0.22
0.38
c
0.08
0.23
D
3.00 BASIC
E
4.90 BASIC
E1
3.00 BASIC
e
0.65 BASIC
e1
1.95 BASIC
aaa
0.40
0°
--
MINIMUN
N
A
α
Millimeters
Millimeters
N
L
ICS853052
MAXIMUM
8
1.35
1.75
A1
0.10
0.25
B
0.33
0.51
C
0.19
0.25
D
4.80
5.00
E
3.80
4.00
e
1.27 BASIC
H
5.80
6.20
h
0.25
0.50
0.80
L
0.40
1.27
8°
α
0°
8°
Reference Document: JEDEC Publication 95, MS-012
0.10
Reference Document: JEDEC Publication 95, MO-187
853052AG
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ICS853052
DUAL LVCMOS / LVTTL-TO-DIFFERENTIAL
2.5V, 3.3V, 5V LVPECL MULTIPLEXER
TABLE 9. ORDERING INFORMATION
Part/Order Number
Marking
Package
Count
Temperature
ICS853052AG
052A
8 lead TSSOP
96 per tube
-40°C to 85°C
ICS853052AGT
052A
8 lead TSSOP on Tape and Reel
2500
-40°C to 85°C
ICS853052AM
853052A
8 lead SOIC
96 per tube
-40°C to 85°C
ICS853052AMT
853052A
8 lead SOIC on Tape and Reel
2500
-40°C to 85°C
The aforementioned trademark, HiPerClockS™ is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
853052AG
www.icst.com/products/hiperclocks.html
13
REV. A JULY 1, 2004
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