TI DAC7811 12-bit, serial input, multiplying digital-to-analog converter Datasheet

DAC7811
www.ti.com
SBAS337 – APRIL 2005
12-Bit, Serial Input, Multiplying
Digital-to-Analog Converter
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2.7 V to 5.5 V Supply Operation
50 MHz Serial Interface
10 MHz Multiplying Bandwidth
±10 V Reference Input
Low Glitch Energy: 2 nV-s
Extended Temperature Range:
–40°C to +125°C
10-Lead SON Package
12-Bit Monotonic
4-Quadrant Multiplication
Power-On Reset with Brownout Detection
Daisy-Chain Mode
Readback Function
Industry-Standard Pin Configuration
APPLICATIONS
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Portable Battery-Powered Instruments
Waveform Generators
Analog Processing
Programmable Amplifiers and Attenuators
Digitally Controlled Calibration
Programmable Filters and Oscillators
Composite Video
Ultrasound
DESCRIPTION
The DAC7811 is a CMOS 12-bit current output
digital-to-analog converter (DAC). This device
operates from a 3.0 V to 5.5 V power supply, making
it suitable to both battery-powered and many other
applications.
This DAC uses a double-buffered 3-wire serial
interface that is compatible with SPI™, QSPI,
MICROWIRE™, and most DSP interface standards.
In addition, a serial data out pin (SDO) allows for
daisy-chaining when multiple packages are used.
Data readback allows the user to read the contents of
the DAC register via the SDO pin. On power-up, the
internal shift register and latches are filled with zeroes
and the DAC outputs are at zero scale.
The DAC7811 offers excellent 4-quadrant multiplication characteristics, with large signal multiplying
bandwidth of 10 MHz. The applied external reference
input voltage (VREF) determines the full-scale output
current. An integrated feedback resistor (RFB) provides temperature tracking and full-scale voltage
output when combined with an external current-to-voltage precision amplifier.
The DAC7811 is available in a 10-lead MSOP package as well as a small 10-lead SON package.
VDD
VREF
R
RFB
DAC7811
12-Bit
R-2R DAC
IOUT1
IOUT2
DAC Register
Power-On
Reset
SYNC
SCLK
SDIN
Input Latch
Control Logic and
Input Shift Register
SDO
GND
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SPI is a trademark of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor.
All trademarks are the property of their respective owners.
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the
right to change or discontinue these products without notice.
Copyright © 2005, Texas Instruments Incorporated
PRODUCT PREVIEW
FEATURES
DAC7811
www.ti.com
SBAS337 – APRIL 2005
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated
circuits be handled with appropriate precautions. Failure to observe proper handling and installation
procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision
integrated circuits may be more susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.
ORDERING INFORMATION (1)
PRODUCT
PACKAGE
PACKAGE
DESIGNATOR
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
MARKING
DAC7811
10-MSOP
DGS
–40°C to +125°C
7811
DAC7811
(1)
10-SON
DRC
–40°C to +125°C
7811
ORDERING NUMBER
TRANSPORT MEDIA,
QUANTITY
DAC7811IDGST
250, Tape and Reel
DAC7811IDGSR
2500, Tape and Reel
DAC7811IDRCT
250, Tape and Reel
DAC7811IDRCR
2500, Tape and Reel
For the most current specifications and package information, see the Package Option Addendum located at the end of this data sheet or
refer to our web site at www.ti.com.
PRODUCT PREVIEW
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted) (1)
VDD to GND
DAC7811
UNIT
–0.3 to +7.0
V
Digital input voltage to GND
–0.3 to VDD + 0.3
V
VOUT to GND
–0.3 to VDD + 0.3
V
Operating temperature range
–40 to +125
°C
Storage temperature range
–65 to +150
°C
Junction temperature (TJ max)
+150
°C
ESD Rating, HBM
1500
V
ESD Rating, CDM
1000
V
(1)
Stresses above those listed under absolute maximum ratings may cause permanent damage to the device. Exposure to absolute
maximum conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
VDD = +2.7 V to +5.5 V; IOUT1 = Virtual GND; IOUT2 = 0V; VREF = 10 V; TA = full operating temperature. All specifications –40°C
to +125°C, unless otherwise noted.
DAC7811
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
±1
LSB
±1
LSB
nA
STATIC PERFORMANCE (1)
Resolution
Relative accuracy
12
Bits
DAC7811
Differential nonlinearity
Output leakage current
Data = 0000h, TA = +25°C
±5
Output leakage current
Data = 0000h, TA = TMAX
±25
nA
Full-scale gain error
All ones loaded to DAC register
±10
mV
Full-scale tempco
Output capacitance
(1)
2
Code dependent
Linearity calculated by using a reduced code range of 48 to 4047; output unloaded.
±5
±5
ppm/°C
50
pF
DAC7811
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SBAS337 – APRIL 2005
ELECTRICAL CHARACTERISTICS (continued)
VDD = +2.7 V to +5.5 V; IOUT1 = Virtual GND; IOUT2 = 0V; VREF = 10 V; TA = full operating temperature. All specifications –40°C
to +125°C, unless otherwise noted.
DAC7811
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
15
V
REFERENCE INPUT
VREF range
–15
Input resistance
8
10
12
kΩ
RFB resistance
8
10
12
kΩ
VIL VDD = +2.7V
0.6
V
VIL VDD = +5V
0.8
V
LOGIC INPUTS AND OUTPUT (2)
Input low voltage
Input high voltage
Input leakage current
Input capacitance
VIH VDD = +2.7V
2.1
V
VIH VDD = +5V
2.4
V
IIL
10
µA
CIL
10
pF
50
MHz
Clock input frequency
fCLK
Clock pulse width high
tCH
8
ns
Clock pulse width low
tCC
8
ns
SYNC falling edge to SCLK
active edge setup time
tCSS
13
ns
SCLK active edge to SYNC
rising edge hold time
tCST
5
ns
Data setup time
tDS
5
ns
Data hold time
tDH
5
ns
SYNC high time
tSH
30
SYNC inactive edge to SDO
valid
tDDS
VDD = +2.7V
25
35
ns
VDD = +5V
20
30
ns
5.5
V
PRODUCT PREVIEW
INTERFACE TIMING
POWER REQUIREMENTS
VDD
2.7
IDD (normal operation)
Logic inputs = 0 V
5
µA
VDD = +4.5 V to +5.5 V
VIH = VDD and VIL = GND
0.8
5
µA
VDD = +2.7 V to +3.6 V
VIH = VDD and VIL = GND
0.4
2.5
µA
Reference multiplying BW
VREF = 7 VPP, Data = FFFh
10
MHz
DAC glitch impulse
VREF = 0 V to 10 V,
Data = 7FFh to 800h to 7FFh
2
nV-s
Feedthrough error VOUT/VREF
Data = 000h, VREF = 100kHz
–70
dB
2
nV-s
AC CHARACTERISTICS
Output voltage settling time
0.2
Digital feedthrough
µs
Total harmonic distortion
–105
dB
Output spot noise voltage
25
nV/√Hz
(2)
Specified by design and characterization; not production tested.
3
DAC7811
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SBAS337 – APRIL 2005
PIN DESCRIPTIONS
SON PACKAGE
3mm x 3mm QFN
(TOP VIEW)
MSOP PACKAGE
(TOP VIEW)
IOUT1
1
10
IOUT2
GND
2
9
RFB
3
8
VREF
VDD
SCLK
SDIN
4
5
7
6
SDO
SYNC
IOUT1 1
10 RFB
IOUT2 2
9 VREF
GND 3
8 VDD
7 SDO
SCLK 4
SDIN 5
6 SYNC
Table 1. TERMINAL FUNCTIONS
TERMINAL
PRODUCT PREVIEW
4
DESCRIPTION
NO.
NAME
1
IOUT1
DAC Current Output
2
IOUT2
DAC Analog Ground. This pin is normally tied to the analog ground of the system.
3
GND
Ground pin.
4
SCLK
Serial Clock Input. By default, data is clocked into the input shift register on the falling edge of the serial clock input.
Alternatively, by means of the serial control bits, the device may be configured such that data is clocked into the shift
register on the rising edge of SCLK.
5
SDIN
Serial Data Input. Data is clocked into the 16-bit input register on the active edge of the serial clock input. By default,
on power-up, data is clocked into the shift register on the falling edge of SCLK. The control bits allow the user to
change the active edge to the rising edge.
6
SYNC
Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes low, it powers
on the SCLK and DIN buffers, and the input shift register is enabled. Data is loaded to the shift register on the active
edge of the following clocks (power-on default is falling clock edge). In stand-alone mode, the serial interface counts
the clocks and data is latched to the shift register on the 16th active clock edge.
7
SDO
Serial Data Output. This allows a number of parts to be daisy-chained. By default, data is clocked into the shift register
on the falling edge and out via SDO on the rising edge of SCLK. Data will always be clocked out on the alternate edge
to loading data to the shift register. Writing the Readback control word to the shift register makes the DAC register
contents available for readback on the SDO pin, clocked out on the opposite edges to the active clock edge.
8
VDD
Positive Power Supply Input. These parts can be operated from a supply of 2.7 V to 5.5 V.
9
VREF
DAC Reference Voltage Input
10
RFB
DAC Feedback Resistor pin. Establish voltage output for the DAC by connecting to external amplifier output.
DAC7811
www.ti.com
SBAS337 – APRIL 2005
TYPICAL CHARACTERISTICS: VDD = +5 V
At TA = +25°C, +VDD = +5 V, unless otherwise noted.
LINEARITY ERROR
vs DIGITAL INPUT CODE
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
1.0
1.0
0.8
TA = +25C
0.8
TA = +25C
0.6
VREF = +10V
0.6
VREF = +10V
0.4
DNL (LSB)
0.2
0
−0.2
−0.4
−0.6
−0.6
−0.8
−0.8
−1.0
0
1.0
512
1024
0.8
TA = −40 C
0.6
VREF = +10V
1536 2048 2560
Digital Input Code
3072
3584
4096
0
512
1024
1536 2048 2560
Digital Input Code
3072
3584
Figure 1.
Figure 2.
LINEARITY ERROR
vs DIGITAL INPUT CODE
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
1.0
0.8
TA = −40 C
0.6
VREF = +10V
4096
0.4
DNL (LSB)
0.4
INL (LSB)
0
−0.2
−0.4
−1.0
0.2
0
−0.2
0.2
0
−0.2
−0.4
−0.4
−0.6
−0.6
−0.8
−0.8
−1.0
−1.0
0
512
1024
1536 2048 2560
Digital Input Code
3072
3584
4096
0
512
1024
1536 2048 2560
Digital Input Code
3072
3584
Figure 3.
Figure 4.
LINEARITY ERROR
vs DIGITAL INPUT CODE
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
1.0
4096
1.0
0.8
TA = +125C
0.8
TA = +125C
0.6
VREF = +10V
0.6
VREF = +10V
0.4
DNL (LSB)
0.4
INL (LSB)
0.2
PRODUCT PREVIEW
INL (LSB)
0.4
0.2
0
−0.2
0.2
0
−0.2
−0.4
−0.4
−0.6
−0.6
−0.8
−0.8
−1.0
−1.0
0
512
1024
1536 2048 2560
Digital Input Code
Figure 5.
3072
3584
4096
0
512
1024
1536 2048 2560
Digital Input Code
3072
3584
4096
Figure 6.
5
DAC7811
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SBAS337 – APRIL 2005
TYPICAL CHARACTERISTICS: VDD = +5 V (continued)
At TA = +25°C, +VDD = +5 V, unless otherwise noted.
SUPPLY CURRENT
vs LOGIC INPUT VOLTAGE
REFERENCE MULTIPLYING BANDWIDTH
1.6
VDD = +5.0V
1.2
Attenuation (dB)
Supply Current (mA)
1.4
6
0
−6
−12
−18
−24
−30
−36
−42
−48
−54
−60
−66
−72
−78
−84
−90
−96
−102
1.0
0.8
0.6
0.4
VDD = +3.0V
0.2
0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
10
100
1k
Logic Input Voltage (V)
100k
1M
Figure 7.
Figure 8.
MIDSCALE DAC GLITCH
MIDSCALE DAC GLITCH
Output Voltage (50mV/div)
PRODUCT PREVIEW
Output Voltage (50mV/div)
10k
10M
100M
Bandwidth (Hz)
Bipolar Configuration: ±10VOUT
Code 2047 to 2048
DAC Update
Bipolar Configuration: ±10VOUT
Code 2048 to 2047
DAC Update
Time (50ns/div)
Time (50ns/div)
Figure 9.
Figure 10.
DAC SETTLING TIME
GAIN ERROR
vs TEMPERATURE
0
−0.2
Small Signal Settling
VREF = +10V
Gain Error (mV)
Output Voltage (20mV/div)
−0.4
DAC Update
−0.6
−0.8
−1.0
−1.2
−1.4
−1.6
−1.8
Time (20ns/div)
−2.0
−40
−20
0
20
40
60
Temperature ( C)
Figure 11.
6
Figure 12.
80
100
120
DAC7811
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SBAS337 – APRIL 2005
TYPICAL CHARACTERISTICS: VDD = +5 V (continued)
At TA = +25°C, +VDD = +5 V, unless otherwise noted.
SUPPLY CURRENT
vs TEMPERATURE
2.0
1.6
VREF = +10V
1.8
VREF = +10V
1.4
1.6
Output Leakage (nA)
1.4
1.2
1.0
VDD = +5.0V
0.8
0.6
VDD = +3.0V
0.4
1.2
1.0
0.8
0.6
0.4
0.2
0.2
0
0
−40
−20
0
20
40
60
80
100
−40
120
−20
0
20
40
60
Temperature (C)
Temperature (C)
Figure 13.
Figure 14.
80
100
120
PRODUCT PREVIEW
Quiescent Current (µA)
OUTPUT LEAKAGE
vs TEMPERATURE
TYPICAL CHARACTERISTICS: VDD = +3 V
At TA = +25°C, +VDD = +3 V, unless otherwise noted.
LINEARITY ERROR
vs DIGITAL INPUT CODE
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
1.0
1.0
0.8
TA = +25C
0.8
TA = +25C
0.6
VREF = +10V
0.6
VREF = +10V
0.4
DNL (LSB)
INL (LSB)
0.4
0.2
0
−0.2
0.2
0
−0.2
−0.4
−0.4
−0.6
−0.6
−0.8
−0.8
−1.0
−1.0
0
512
1024
1536 2048 2560
Digital Input Code
Figure 15.
3072
3584
4096
0
512
1024
1536 2048 2560
Digital Input Code
3072
3584
4096
Figure 16.
7
DAC7811
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SBAS337 – APRIL 2005
TYPICAL CHARACTERISTICS: VDD = +3 V (continued)
At TA = +25°C, +VDD = +3 V, unless otherwise noted.
LINEARITY ERROR
vs DIGITAL INPUT CODE
1.0
0.8
TA = −40 C
0.6
VREF = +10V
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
1.0
0.6
VREF = +10V
DNL (LSB)
0.4
0.2
0
−0.2
0.2
0
−0.2
−0.4
−0.4
−0.6
−0.6
−0.8
−0.8
−1.0
−1.0
0
512
1024
1536 2048 2560
Digital Input Code
3072
3584
4096
0
512
1024
3584
PRODUCT PREVIEW
LINEARITY ERROR
vs DIGITAL INPUT CODE
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
4096
1.0
TA = +125C
0.8
TA = +125C
0.6
VREF = +10V
0.6
VREF = +10V
0.4
DNL (LSB)
0.4
0.2
0
−0.2
0.2
0
−0.2
−0.4
−0.4
−0.6
−0.6
−0.8
−0.8
−1.0
−1.0
0
512
1024
1536 2048 2560
Digital Input Code
3072
3584
4096
0
512
1024
1536 2048 2560
Digital Input Code
3072
Figure 19.
Figure 20.
MIDSCALE DAC GLITCH
MIDSCALE DAC GLITCH
Bipolar Configuration: ±10VOUT
Code 2048 to 2047
3584
Bipolar Configuration: ±10VOUT
Code 2047 to 2048
DAC Update
DAC Update
8
3072
Figure 18.
0.8
Output Voltage (50mV/div)
1536 2048 2560
Digital Input Code
Figure 17.
1.0
INL (LSB)
TA = −40 C
Output Voltage (50mV/div)
INL (LSB)
0.4
0.8
Time (50ns/div)
Time (50ns/div)
Figure 21.
Figure 22.
4096
DAC7811
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SBAS337 – APRIL 2005
TYPICAL CHARACTERISTICS: VDD = +3 V (continued)
At TA = +25°C, +VDD = +3 V, unless otherwise noted.
GAIN ERROR
vs TEMPERATURE
0
−0.2
OUTPUT LEAKAGE
vs TEMPERATURE
1.6
VREF = +10V
VREF = +10V
1.4
Output Leakage (nA)
−0.6
−0.8
−1.0
−1.2
−1.4
−1.6
−1.8
−2.0
−40
1.2
1.0
0.8
0.6
0.4
0.2
−20
0
0
20
40
60
80
100
−40
120
−20
0
20
Temperature ( C)
40
60
80
100
120
Temperature (C)
Figure 23.
Figure 24.
Theory of Operation
The DAC7811 is a single channel current output, 12-bit digital-to-analog converter (DAC). The architecture,
illustrated in Figure 25, is an R-2R ladder configuration with the three MSBs segmented. Each 2R leg of the
ladder is either switched to IOUT1 or the IOUT2 terminal. The IOUT1 terminal of the DAC is held at a virtual GND
potential by the use of an external I/V converter op amp. The R-2R ladder is connected to an external reference
input VREF that determines the DAC full-scale current. The R-2R ladder presents a code independent load
impedance to the external reference of 10 kΩ± 20%. The external reference voltage can vary in a range of –15 V
to +15 V, thus providing bipolar IOUT current operation. By using an external I/V converter and the DAC7811 RFB
resistor, output voltage ranges of -VREF to VREF can be generated.
R
R
R
R
VREF
2R
2R
2R
2R
2R
R FB
IOUT 1
IOUT2
DB11
(MSB)
DB10
DB9
DB0
(LSB)
Figure 25. Equivalent R-2R DAC Circuit
When using an external I/V converter and the DAC7811 RFB resistor, the DAC output voltage is given by
Equation 1:
V OUT VREF CODE
4096
(1)
Each DAC code determines the 2R leg switch position to either GND or IOUT. Because the DAC output
impedance as seen looking into the IOUT1 terminal changes versus code, the external I/V converter noise gain will
also change. Because of this, the external I/V converter op amp must have a sufficiently low offset voltage such
that the amplifier offset is not modulated by the DAC IOUT1 terminal impedance change. External op amps with
large offset voltages can produce INL errors in the transfer function of the DAC7811 due to offset modulation
versus DAC code.
9
PRODUCT PREVIEW
Gain Error (mV)
−0.4
DAC7811
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SBAS337 – APRIL 2005
Theory of Operation (continued)
For best linearity performance of the DAC7811, an op amp (OPA277) is recommended (see Figure 26). This
circuit allows VREF swinging from –10 V to +10 V.
VDD
VDD
DAC7811
VREF
15V
RFB
V+
IOUT1
VOUT
OPA277
I OUT2
GND
V−
−15V
Figure 26. Voltage Output Configuration
Table 2. Control Logic Truth Table (1)
PRODUCT PREVIEW
(1)
CLK
SYNC
SERIAL SHIFT REGISTER
DAC REGISTER
X
H
No effect
Latched
↑+
L
Shift register data advanced one bit
Latched
X
↑+
In daisy-chain mode the function as determined by
C3-C0 is executed.
In daisy-chain mode the contents may chage
as determined by C3-C0.
↑+ Positive logic transition; X = Do not care.
Serial Interface
The DAC7811 has a three-wire serial interface (SYNC, SCLK, and SDIN), which is compatible with SPI, QSPI,
and MICROWIRE interface standards as well as most Digital Signal Processor (DSP) devices. See the Serial
Write Operation timing diagram for an example of a typical write sequence. The write sequence begins by
bringing the SYNC line low. Data from the DIN line is clocked into the 16-bit shift register on the falling edge of
SCLK. The serial clock frequency can be as high as 50MHz, making the DAC7811 compatible with high-speed
DSPs. The SDIN and SCLK input buffers are gated off while SYNC is high which minimizes the power
dissipation of the digital interface. After SYNC goes low, the digital interface will respond to the SDIN and SCLK
input signals and data can now be shifted into the device. If an inactive clock edge occurs after SYNC goes low,
but before the first active clock edge, it will be ignored. If the SDO pin is being used then SYNC must remain low
until after the inactive clock edge that follows the 16th active clock edge.
Input Shift Register
The input shift register is 16 bits wide, as shown in Figure 27. The four MSBs are the control bits C3 – C0; these
bits determine which function will be executed at the rising edge of SYNC in daisy-chain mode or the 16th active
clock edge in stand-alone mode. The remaining 12 bits are the data bits. On a load and update command
(C3–C0 = 0001) these 12 data bits will be transferred to the DAC register; otherwise, they have no effect.
4 CONTROL BITS
C3
C2
C1
12 DATA BITS
C0
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
MSB
DB15
DB2
DB1
DB0
LSB
Figure 27. Contents of the 16-Bit Input Shift Register
10
DB3
DAC7811
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SBAS337 – APRIL 2005
SYNC Interrupt
In a normal write sequence, the SYNC line is kept low for at least 16 falling edges of SCLK and the DAC is
updated on the 16th falling edge. However, if SYNC is brought high before the 16th falling edge, this acts as an
interrupt to the write sequence. The shift register is reset and the write sequence is seen as invalid. Neither an
update of the DAC register contents or a change in the operating mode occurs.
Daisy-Chain
The DAC7811 powers up in the daisy chain mode which must be used when 2 or more devices are connected in
tandem. The SCLK and SYNC signals are shared across all devices while the SDO output of the first device
connects to the SDIN input of the following device, and so forth. In this configuration 16 SCLK cycles for each
DAC7811 in the chain are required. Please refer to the timing diagram of Figure 28.
For n devices in a daisy-chain configuration, 16n SCLK cycles are required to shift in the entire input data
stream. After 16n active SCLK edges are received following a falling SYNC, the data stream becomes complete,
and SYNC can brought high to update n devices simultaneously.
A continuous stream containing the exact number of SCLK cycles may be sent first while the SYNC signal is held
low, and then raise SYNC at a later time. Nothing happens until the rising edge of SYNC, and then each
DAC7811 in the chain will execute the function defined by the four DAC control bits C3-C0 in its input shift
register.
tC
SCLK
tCST
t CC
tCSS
tCH
t9
SYNC
tDH
tDS
SDIN
DB15
(N)
DB0
(N)
DB15
(N + 1)
DB0
(N + 1)
tDDS
SDO
DB15
(N)
DB0
(N)
Figure 28. DAC7811 Timing Diagram
Control Bits C3 to C0
Control Bits C3 to C0 allow control of various functions of the DAC; see Table 3. Default settings of the DAC on
powering up are as follows: Data clocked into shift register on falling clock edges; daisy-chain mode is enabled.
Device powers on with zero-scale loaded into the DAC register and IOUT lines. The DAC control bits allow the
user to adjust certain features as part of an initialization sequence, for example, daisy-chaining may be disabled
if not in use, active clock edge may be changed to rising edge, and DAC output may be cleared to either zero or
midscale. The user may also initiate a readback of the DAC register contents for verification purposes.
11
PRODUCT PREVIEW
When SYNC is brought high, each device will execute the function defined by the four DAC control bits C3-C0 in
its input shift register. For example, C3-C0 must be 0001 for each DAC in the chain that is to be updated with
new data, and C3-C0 must be 0000 for each DAC in the chain whose contents are to remain unchanged.
DAC7811
www.ti.com
SBAS337 – APRIL 2005
Table 3. Serial Input Register Data Format, Data Loaded MSB First
PRODUCT PREVIEW
C3
C2
C1
C0
FUNCTION IMPLEMENTED
0
0
0
0
No operation (power-on default)
0
0
0
1
Load and update
0
0
1
0
Initiate readback
0
0
1
1
Reserved
0
1
0
0
Reserved
0
1
0
1
Reserved
0
1
1
0
Reserved
0
1
1
1
Reserved
1
0
0
0
Reserved
1
0
0
1
Daisy-chain disable
1
0
1
0
Clock data to shift register on rising edge
1
0
1
1
Clear DAC output to 0
1
1
0
0
Clear DAC output to midscale
1
1
0
1
Reserved
1
1
1
0
Reserved
1
1
1
1
Reserved
APPLICATION INFORMATION
Stability Circuit
For a current-to-voltage design (see Figure 29), the DAC7811 current output (IOUT) and the connection with the
inverting node of the op amp should be as short as possible and according to correct printed circuit board (PCB)
layout design. For each code change, there is a step function. If the gain bandwidth product (GBP) of the op amp
is limited and parasitic capacitance is excessive at the inverting node, then gain peaking is possible. Therefore,
for circuit stability, a compensation capacitor C1 (4 pF to 20 pF typ) can be added to the design, as shown in
Figure 29.
VDD
U1
VDD
VREF
VREF
GND
RFB
C1
IOUT1
VOUT
I OUT2
U2
Figure 29. Gain Peaking Prevention Circuit with Compensation Capacitor
Positive Voltage Output Circuit
As Figure 30 illustrates, in order to generate a positive voltage output, a negative reference is input to the
DAC7811. This design is suggested instead of using an inverting amp to invert the output as a result of resistor
tolerance errors. For a negative reference, VOUT and GND of the reference are level-shifted to a virtual ground
and a –2.5 V input to the DAC7811 with an op amp.
12
DAC7811
www.ti.com
SBAS337 – APRIL 2005
APPLICATION INFORMATION (continued)
+2.5V Reference
VDD
VIN
VOUT
GND
RFB
VDD
VREF
OPA277
−2.5V
C1
DAC7811 IOUT1
VOUT
OPA277
IOUT2
GND
0 ≤ VOUT ≤ +2.5V
Figure 30. Positive Voltage Output Circuit
Bipolar Output Section
Some applications require full 4-quadrant multiplying capabilities or bipolar output swing. As shown in Figure 31,
external op amp U4 is added as a summing amp and has a gain of 2X that widens the output span to 5 V. A
4-quadrant multiplying circuit is implemented by using a 2.5 V offset of the reference voltage to bias U4.
According to the circuit transfer equation given in Equation 2, input data (D) from code 0 to full-scale produces
output voltages of VOUT = –2.5 V to VOUT = +2.5 V.
V OUT 0.5 D 2
N
1 V REF
(2)
External resistance mismatching is the significant error in Figure 31.
10kΩ
10kΩ
C2
VDD
VDD
+2.5V
(+10V)
5kΩ
RFB
VREF DAC7811 I OUT1
GND
IOUT2
U4
OPA277
C1
VOUT
U2
OPA277
−2.5V ≤ VOUT ≤ +2.5V
(−10V ≤ VOUT ≤ +10V)
Figure 31. Bipolar Output Circuit
Programmable Current Source Circuit
A DAC7811 can be integrated into the circuit in Figure 32 to implement an improved Howland current pump for
precise voltage to current conversions. Bidirectional current flow and high voltage compliance are two features of
the circuit. With a matched resistor network, the load current of the circuit is shown by Equation 3:
R2R3 R1
IL V REF D
R3
(3)
13
PRODUCT PREVIEW
The DAC7811, as a 2-quadrant multiplying DAC, can be used to generate a unipolar output. The polarity of the
full-scale output IOUT is the inverse of the input reference voltage at VREF.
DAC7811
www.ti.com
SBAS337 – APRIL 2005
APPLICATION INFORMATION (continued)
The value of R3 in the previous equation can be reduced to increase the output current drive of U3. U3 can drive
±20 mA in both directions with voltage compliance limited up to 15 V by the U3 voltage supply. Elimination of the
circuit compensation capacitor C1 in the circuit is not suggested as a result of the change in the output
impedance ZO, according to Equation 4:
R1R3R1R2
ZO R1R2R3 R1R2R3
(4)
As shown in Equation 4, with matched resistors, ZO is infinite and the circuit is optimum for use as a current
source. However, if unmatched resistors are used, ZO is positive or negative with negative output impedance
being a potential cause of oscillation. Therefore, by incorporating C1 into the circuit, possible oscillation problems
are eliminated. The value of C1 can be determined for critical applications; for most applications, however, a
value of several pF is suggested.
R2′
15kΩ
C1
10pF
R1′
150kΩ
VDD
PRODUCT PREVIEW
U2
OPA277
R FB
VDD
U1
IOUT1
DAC7811
I OUT2
GND
VREF
R3′
50kΩ
U2
OPA277
R1
150kΩ
R2
15kΩ
VOUT
R3
50Ω
IL
LOAD
Figure 32. Programmable Bidirectional Current Source Circuit
Cross-Reference
The DAC7811 has an industry-standard pinout. Table 4 provides the cross-reference information.
Table 4. Cross-Reference
14
PRODUCT
INL (LSB)
DNL (LSB)
SPECIFIED
TEMPERATURE
RANGE
DAC7811
±1
±1
–40°C to +125°C
PACKAGE
DESCRIPTION
PACKAGE
OPTION
CROSSREFERENCE PART
10-Lead MicroSOIC
MSOP-10
AD5443YRM
PACKAGE OPTION ADDENDUM
www.ti.com
6-Apr-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
DAC7811IDGSR
PREVIEW
MSOP
DGS
10
2500
TBD
Call TI
Call TI
DAC7811IDGST
PREVIEW
MSOP
DGS
10
250
TBD
Call TI
Call TI
DAC7811IDRCR
PREVIEW
SON
DRC
10
3000
TBD
Call TI
Call TI
DAC7811IDRCT
PREVIEW
SON
DRC
10
250
TBD
Call TI
Call TI
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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Addendum-Page 1
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