Zarlink NJ88C30KADP Vhf synthesiser Datasheet

THIS DOCUMENT IS FOR MAINTENANCE
PURPOSES ONLY AND IS NOT
RECOMMENDED FOR NEW DESIGNS
NJ88C30
NJ88C30 IS FOR MAINTENANCE PURPOSES ONLY AND IS NOT RECOMMENDED FOR NEW DESIGNS
DS3281-1.1
NJ88C30
VHF SYNTHESISER
The NJ88C30 contains all the logic needed for a VHF PLL
synthesiser and is fabricated on the GPS high performance, small
geometry CMOS process. The circuit contains a reference oscillator
and divider, a two-modulus prescaler and 4-bit control register, a
12-bit programmable divider, a phase comparator and the
necessary data input and control logic.
GROUND
1
14
COMP FREQ
DATA TRANSFER
2
13
f UP
CLOCK
3
12
f DN
DATA
4
11
LD
CRYSTAL MON
5
10
VCO
CRYSTAL IN
6
9
P DIV OUT
CRYSTAL OUT
7
8
VDD
FEATURES
■ Low Power CMOS
■
■
■
■
Easy to Use
Low Cost
Single Chip Synthesiser to VHF
NJ88C30
Lock Detect Output
DP14, MP14
APPLICATIONS
Fig.1 Pin connections - top view
■ Mobile Radios
■ Hand Held Portable Radios
■ Sonobuoys
ABSOLUTE MAXIMUM RATINGS
20·3V to 6V
20·3V to VDD10·3V
230°C to 170°C
255°C to 1125°C
Supply voltage, VDD
Voltage on any pin
Operating temperature
Storage temperature
ORDERING INFORMATION
NJ88C30 KA DP Plastic DIL Package
NJ88C30 KA MP Miniature Plastic DIL Package
VDD
CRYSTAL MON
CRYSTAL
OUT
8
5
7
14
0V
0V
6
CRYSTAL
IN
VDD
13
10
VCO
REFERENCE DIVIDER
4 1, 5, 10, 20, 2, 4, 8 OR 16
4 100
REF
SELECT
(DR2-DR0)
4 15/16
12
PHASE
COMP
0V
4-BIT COUNTER
12-BIT PROG DIVIDER
11
DATA
TRANSFER
DATA
CLOCK
12-BIT REGISTER
0V
3-BIT
REGISTER
2
4
3
19-BIT SHIFT REGISTER
1
GROUND
Fig.2 Block diagram
f UP
f DN
LOCK DETECT
(LD)
0V
9
4-BIT REGISTER
COMP FREQ
P DIV OUT
NJ88C30
ELECTRICAL CHARACTERISTICS
Test conditions (unless otherwise stated):
TAMB = –30°C to +70°C, VDD = 5V ±0·5V
Characteristic
Value
Pin
Supply current
Crystal Oscillator
Frequency
External input level
High level
Low level
VCO Input
Input sensitivity
Slew rate
Input impedance
DATA, DATA TRANSFER and
CLOCK Inputs
High level
Low level
Rise, fall time
Data set-up time
Clock frequency
Transfer pulse width
CRYSTAL MONITOR Output
Current sink
COMP FREQ, LD, P DIV
Current sink
f UP / f DN
Current sink
Current source
Units
Conditions
Typ.
Max.
8
4
7
mA
1VRMS VCO input at 200MHz
and fXTAL = 10MHz
6, 7
10
15
MHz
1
Vrms
V
V
Parallel resonant,
fundamental crystal
AC coupled
DC coupled
DC coupled
Min.
6
6
6
1
VDD21
10
10
10
1
4
2, 3, 4
2. 3, 4
2, 3
3, 4
3
2
VDD21
500
V
V
ns
ns
MHz
ns
5
0·8
mA
VOUT = 0·5V
9, 11, 14
1·6
mA
VOUT = 0·5V
12
13
0·8
0·8
mA
mA
VOUT = 0·5V
VOUT = VDD20·5V
Vrms
V/µs
At 200MHz, see Fig. 3
5pF//
10k
1
200
200
2
See Fig. 4
VCO INPUT AMPLITUDE (V RMS)
1·6
1·4
GUARANTEED OPERATING AREA *
1·2
* Tested as
1·0
specified in
Table of
Electrical
Characteristics
0·8
0·6
0·4
TYPICAL
0·2
0
0
50
100
150
FREQUENCY (MHz)
Fig. 3 Input sensitivity
2
200
NJ88C30
CLOCK
DATA
DR1
DR2
DR0
DF15
DF1
DF0
DATA SET-UP TIME
DATA
TRANSFER
TRANSFER PULSE WIDTH
Fig. 4 Input data timing diagram
180
PHASE (DEGREES)
20
GAIN (dB)
10
0
120
60
210
0
100k
1M
FREQUENCY (Hz)
10M
100k
1M
FREQUENCY (Hz)
10M
Fig. 5 Gain and phase characteristics of reference oscillator inverter
CIRCUIT DESCRIPTION
Crystal Oscillator and Reference Divider
The Reference oscillator consists of a Pierce type oscillator
intended for use with a parallel resonant fundamental crystal.
Typical gain and phase characteristics for the oscillator inverter
are shown in Fig 5. An external reference oscillator may be
used by either capacitively coupling a 1V RMS sinewave into
CRYSTAL IN (pin 6) or, if CMOS levels are available, by direct
connection to CRYSTAL IN.
The reference oscillator drives a 4100 prescaler followed
by a reference divider to provide a range of comparison
frequencies which are selected by decoding the first three bits
(DR2, DR1, DR0) of the input data. The possible division ratios
and the comparison frequencies (channel spacing) if a 10MHz
crystal is used are shown in Table 1.
DR2 DR1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
DR0
Total
division
ratio
Comparison frequency
for 10MHz Ref. Osc.
0
1
0
1
0
1
0
1
1600
800
400
200
2000
1000
500
100
6·25kHz
12·5kHz
25kHz
50kHz
5kHz
10kHz
20kHz
100kHz
Table 1 Reference divider division ratios
To assist in trimming the crystal, an open drain output at one
hundredth of the reference oscillator frequency is provided on
CRYSTAL MONITOR pin 5
Programmable Divider
The programmable divider consists of a 415/16 two modulus
prescaler with a 4-bit control register, followed by a 12-bit
programmable divider. A 1V RMS sinewave should be
capacitively coupled from the VCO to the divider input VCO pin
(pin 10).
The overall division ratio is selected by a single 16-bit word
(DF15 to DF0), loaded through the serial data bus. A lower limit
of 240 ensures correct prescaler operation; the upper limit is
65535. The VCO frequency in a locked system will be this
division ratio multiplied by the comparison frequency.
Phase Comparator
The phase comparator consists of a digital type phase
comparator with open drain f UP and f DN outputs and an
open drain LOCK DETECT (LD) output. Open drain outputs
from the reference divider and programmable divider are
provided for monitoring purposes or for use with an external
phase comparator. Waveforms for all these outputs are shown
in Fig.6. The duty cycle of f UP and f DN versus phase
difference are shown in Fig. 7. The phase comparator is linear
over a ±2π range and if the phase gains or slips by more than
2π, the phase comparator outputs repeat with a 2π period.
3
NJ88C30
(a) Phase P DIV output leads
phase COMP FREQ output
COMP FREQ
P DIV
f UP
f DN
LD
(b) Phase P DIV output lags
phase COMP FREQ output
COMP FREQ
P DIV
f UP
f DN
LD
Fig. 6 Phase comparator waveforms
DUTY CYCLE
f UP
100%
0%
0
22π
2π
PHASE DIFFERENCE
2π
PHASE DIFFERENCE
DUTY CYCLE
f DN
100%
0%
22π
0
Fig. 7 Phase comparator output characteristics
4
NJ88C30
to DF0, control the prescaler and programmable divider. Until
the synthesiser receives the DATA TRANSFER pulse, it will
use the previously loaded data; on receiving the pulse it will
switch rapidly to the new data.
Once the phase difference exceeds 2π, the comparator will
gain or slip one cycle and then try to lock on to the new zero
phase difference. Note that very narrow pulses may be seen on
the inactive phase comparator output at the end of the pulse on
the active output, as shown in Fig. 6.
Data Input and Control Register
To control the synthesiser a simple three-line serial input is
used with DATA, CLOCK and DATA TRANSFER signals. The
data consists of 19 bits; the first three, DR2, DR1 and DR0,
control the reference divider while the following sixteen, DF15
APPLICATIONS
A simplified circuit for a synthesiser intended for VHF
broadcast receiver applications is shown in Fig. 8. When the
varicap line drive voltage necessary to tune the required band
is greater than 5V, some form of level shifter such as the
operational amplifier shown in Fig. 8 is required.
LOCK DETECT (LD)
1
14
DATA TRANSFER
2
13
CLOCK
3
12
R1 18k
R1' 18k
4 NJ88C30 11
DATA
5
10
6
9
7
8
112V
1
10k
SL562
R2
10k
2
VARICAP DRIVE
1 -10V
10n
22k
C1
47n
22k
VCO
4·5MHz
112V
22k
10n
5 - 65p
15V
Fig.8. Typical application
PROGRAMMING EXAMPLE
To obtain the maximum VCO frequency of 200MHz the
programmable divider ratio would be:
1.Maximum Frequency
For a channel spacing (comparison frequency, fcomp) of
5kHz when using a 10MHz crystal oscillator, the reference
divider ratio will need to be 2000 (seeTable 1) This is
programmed as binary 100 (= 4HEX) in the most significant
three of the 19 bits (MSB programmed first).
2003106 = 403103 which is 9C40
HEX
53103
The program word would then be as shown in Table 2.
DR
Binary
Hex
DF
2
1
0
1
0
0
15 14 13 12 11 10
1
0
0
1
1
1
9
8
7
6
5
4
3
2
1
0
0
0
0
1
0
0
0
0
0
0
4
9
C
4
0
Table 2 Maximum VCO frequency programming (fXTAL = 10MHz, fcomp = 5kHz)
2. Minimum Frequency
Using the same crystal frequency and channel spacing
(10MHz, 5kHz), the lower limit of programmable divider ratio of
240 = F0HEX gives a minimum programmable VCO frequency
of 240353103 = 1·2MHz. The program word for this frequency
is therefore as shown in Table 3.
DR
Binary
Hex
DF
2
1
0
1
0
0
15 14 13 12 11 10
0
0
0
0
0
0
9
8
7
6
5
4
3
2
1
0
0
0
1
1
1
1
0
0
0
0
4
0
0
F
0
Table 3 MinimumVCO frequency programming (fXTAL = 10MHz, fcomp = 5kHz)
5
NJ88C30
HEADQUARTERS OPERATIONS
GEC PLESSEY SEMICONDUCTORS
Cheney Manor, Swindon,
Wiltshire SN2 2QW, United Kingdom.
Tel: (0793) 518000
Fax: (0793) 518411
GEC PLESSEY SEMICONDUCTORS
P.O. Box 660017
1500 Green Hills Road,
Scotts Valley, California 95067-0017,
United States of America.
Tel: (408) 438 2900
Fax: (408) 438 5576
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 GEC Plessey Semiconductors 1992 Publication No. DS3281 Issue No. 1.1 May 1992
This publication is issued to provide information only which (unless agreed by the Company in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded
as a representation relating to the products or services concerned. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. The Company
reserves the right to alter without prior knowledge the specification, design or price of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute
any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user's responsibility to fully determine the performance and suitability of any equipment using such information
and to ensure that any publication or data used is up to date and has not been superseded. These products are not suitable for use in any medical products whose failure to perform may result in significant injury
or death to the user. All products and materials are sold and services provided subject to the Company's conditions of sale, which are available on request.
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