[AK8456] AK8456 3 channel input 16bit 30MSPS Video ADC with LED driver 1. General Description AK8456 is an AFE for three channels contact image sensor (CIS). AK8456 has offset adjusting DAC, digital programmable gain amplifier (PGA) and LED drivers. AK8456 is suitable for multi-function printer and image scanner. 2. Feature Input Block Channel number 3 channel (1 channel mode is available) Range 1.3Vpp (min.) Gain 0dB/6dB ADC Maximum conversion ratio 30MSPS 10MSPS/ch @ 3-channel mode 30MSPS/ch @ 1-channel mode Resolution 16bit (Straight binary code/Gray code) Black correction DAC Range 369mV (Equivalent input voltage) ＜±250mV(min.)＞ Resolution 6bit Digital PGA Range 0dB~18dB Resolution 8bit Output Format 8bit × 2 LED Current 67.2mA/ch (typ.) @ Maximum setting Adjustable by 12.5% resolution channel independently CPU I/F 3-wire serial interface Supply Voltage AFE: 3.3V0.3V, LED driver: 4.5V~5.7V Power Consumption 190 mW (typ.)：Except LED drive current. Operating Temperature 0C~70C Package 36pin QFN (Exposed Die Pad), 0.4mm pitch, 5mm5mm 014002433-E-00 2014/06 -1- [AK8456] 3. Table of Contents 1. General Description ........................................................................................................................1 2. Feature............................................................................................................................................1 3. Table of Contents............................................................................................................................2 4. Block diagram and Functions ..........................................................................................................3 5. Pin allocation and Functions............................................................................................................5 6. Absolute Maximum Ratings ............................................................................................................7 7. Recommended Operating Conditions ..............................................................................................7 8. Electrical Characteristics .................................................................................................................7 9. Functional Description ..................................................................................................................17 10. Register Map...............................................................................................................................23 11. External Circuit Example ............................................................................................................29 12. Package.......................................................................................................................................31 13. Important Notice .........................................................................................................................32 014002433-E-00 2014/06 -2- [AK8456] 4. Block diagram and Functions OVSS Serial I/F OVDD DVO SDATA POR SDCLK RESETB Clock Gen. SDENB AVO LDO_A AVDD ADCK SHD ISET VRP VDC Reference Voltage LDO_D CMOS Output Analog PGA CISIN0 6 SHD DAC D0 D1 D2 Analog PGA CISIN1 SHD DAC 6 3 to 1 MUX AFE ch0 16bit 16 30MSPS Digital PGA 16 D3 8 Output Control ADC D4 D5 AFE ch1 D6 LED driver LED Cont. Analog PGA CISIN2 6 SHD DAC D7 AFE ch2 LVDD LVSS LVSS LED_B LED_G LEDEN_B LEDEN_G LEDEN_R LED_R LVDD Fig.1 Block diagram Input Block AK8456 is available for CIS whose polarity is positive. The voltage difference between CISIN0~2 input signal and sensor reference voltage VDC is sampled. VDC is input externally and also is able to generate internally. There are three channel mode and one channel mode. In one channel mode, sensor signal input pin is CISIN0. DAC 6bit DAC Offset adjust is excused by adding DAC output voltage to input signal. DAC resolution is six bit and output range is 369mV (typ.). 100mV (max.) out of 369mV is used to cancel LSI internal offset. Therefore effective range for correcting signal offset is 269mV (typ.). Sample and Hold Block S/H The voltage difference between CISIN0~2 input signal and sensor reference voltage VDC is sampled at sample and hold block. Gain at sample and hold block is selected from 0dB and 6dB. Multiplexor MUX Due to process three channels in a time-division, MUX selects one channel out of three channels in order. 014002433-E-00 2014/06 -3- [AK8456] ADC After offset adjust, the ADC convert analog signal level to digital data. The ADC has 16-bit resolution and 30MSPS maximum conversion ratio. The output code is straight binary, 0000h corresponds to black signal and FFFFh corresponds to white signal. Digital PGA The digital PGA amplifies A/D data. Its gain range is 0dB~18dB and gain resolution is 8bit. Output Control Block The output control block converts 16-bit width data to two 8-bit width data. Higher 8-bit is output at ADCK rising edge and lower 8-bit is output at ADCK falling edge. Gray code output is possible too by register setting. Reference Voltage Generation Block Reference Voltage This block generates internal reference voltage VRP, sensor reference voltage VDC and LDO reference voltage. Internal Clock Generation Block Clock Gen This block generates internal pulses using A/D clock ADCK and sampling pulse SHD. LED Driver Control Block LED Control This block controls LED switching and LED current. LED current is adjustable from 100% to12.5% by 12.5% step channel independently. 100% current is 67.2mA per channel. Serial Interface Block Serial I/F Control registers are written and read through 3-wire serial interface. Low Dropout Voltage Regulator LDO The LDO generate 1.8V supply from 3.3V of AVDD. The 1.8V is used for internal circuit. There are two LDO for analog circuit and digital circuit. 014002433-E-00 2014/06 -4- [AK8456] 5. Pin allocation and Functions D7 19 D6 20 D5 21 D4 22 OVDD 23 OVSS 24 D3 25 D2 26 D1 27 18 LED_B D0 28 DVO 29 17 LVSS ADCK 30 16 LED_G SHD 31 AVDD 15 LVSS AK8456 Top View 32 14 LED_R AVO 33 13 LVDD VRP 34 12 LEDEN_B ISET 35 11 LEDEN_G VDC 36 10 LEDEN_R 9 SDATA SDENB 8 SCLK 7 6 RESETB 5 CISIN2 4 AVDD 3 CISIN1 2 AVDD 1 CISIN0 Note) Connect under side thermal exposed PAD with AVSS. Fig.2 Pin Layout Pin Functions No. Name IO 1 CISIN0 I --- Sensor Signal Input 2 AVDD P --- Analog Supply 3 CISIN1 I --- Sensor Signal Input 4 AVDD P --- Analog Supply 5 CISIN2 I --- Sensor Signal Input 6 RESETB I --- Reset Input, Active Low Include Pull-up Resistance 100k (typ.) 7 SDENB I --- Serial Interface Data Enable 8 SCLK I --- Serial Interface Clock Input 9 SDATA 10 LEDEN_R IO I Standby Description (note 2) High-Z Serial Interface Data Input and Output --- LED_R Control Signal Input Include Pull-down Resistance 50k (typ.) 014002433-E-00 2014/06 -5- [AK8456] 11 LEDEN_G I --- LED_G Control Signal Input Include Pull-down Resistance 50k (typ.) 12 LEDEN_B I --- LED_B Control Signal Input Include Pull-down Resistance 50k (typ.) 13 LVDD P --- LED Driver Supply (5V) 14 15 LED_R LVSS O P High-Z LED Driver Output R --LED Driver Ground 16 LED_G O High-Z LED Driver Output G 17 LVSS P 18 LED_B O 19 D7 O Low A/D Data Output (note 1) (Upper bit) 20 D6 O Low A/D Data Output (note 1) 21 D5 O Low A/D Data Output (note 1) 22 D4 O Low A/D Data Output (note 1) 23 OVDD P --- 24 25 OVSS D3 P O --Low A/D Data Output Buffer Ground A/D Data Output (note 1) 26 D2 O Low A/D Data Output (note 1) 27 D1 O Low A/D Data Output (note 1) 28 D0 O Low A/D Data Output (note 1) (Lower bit) 29 DVO O 1.8V Digital LDO Output pin (1.8V) Keep DVO open. 30 ADCK I --- ADC Clock 31 SHD I --- Sampling Clock 32 AVDD P --- Analog Supply (LDO Supply) 33 AVO O Low Analog Block LDO Output Voltage Monitor (1.8V) Connect 1μF capacitor between AVO and AVSS. 34 VRP O Low ADC Reference Voltage Connect stabilize capacitor 1F via AVSS 35 ISET I --- Resistance for Reference Current Setting 36 VDC IO Tab AVSS P --- LED Driver Ground High-Z LED Driver Output B A/D Data Output Buffer Supply (3.3V) High-Z CIS Reference Voltage Connect stabilize capacitor 1F via AVSS --- Analog Ground (note 1) Open drain output in cascade output mode (note 2) Standby is defined as the condition that power down bit NPD=0 after reset. (note 3) I:Input / O:Output / P:Power supply 014002433-E-00 2014/06 -6- [AK8456] 6. Absolute Maximum Ratings AVSS=OVSS=LVSS=0V. All voltages are based on ground. Item Symbol Min. Max. Unit Analog Supply Digital Output Buffer Supply LED Driver Supply AVDD OVDD LVDD -0.3 -0.3 4.6 4.6 6.2 V V V Input Voltage VINA -0.3 AVDD+0.3 V Storage Temperature Tstg 65 150 C -0.3 Remarks Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. 7. Recommended Operating Conditions AVSS=OVSS=LVSS=0V. All voltages are based on ground. Item Symbol Min. Typ. Max. Unit Analog Supply Digital Output Buffer Supply LED Driver Supply AVDD OVDD LVDD 3.0 3.0 4.5 3.3 3.3 5.0 3.6 3.6 5.7 V V V Operational Temperature Ta 0 70 C Remarks Normal operation is guaranteed at AVDD voltage = OVDD voltage. All supplies must be power-up. Don’t power off partial supplies for saving consumption. If LEDD function is unnecessary. LVDD pins can connect VSS level. 8. Electrical Characteristics Reset timing Fig.3 In case of internal power on reset Prise Prise Poff 0.9×AVDD Power 0.1×AVDD Rtime Internal Reset signal (note) When using a power on reset circuit, the RESETB pin must connect the capacity of 0.33μF to AVSS. (VDD：AVDD=OVDD =3.0~3.6V, Ta=0~70C) Item Symbol Min. Typ. Max. unit Condition VDD rise time Prise 0.01 10 ms VDD 0V period Poff 300 ms 0V peripd The waiting time of the Rtime 100 ms reset cancellation * Start all powers at the same time. * When VDD_0V_period can not meet this condition, Because a register isn't reset, this 014002433-E-00 2014/06 -7- [AK8456] doesn't work normally. And the over-current may flow through VDD. It is same when using an external reset pin, too. Fig.4 In case of external power on reset pin Trst1 0.9×AVDD Power 0.1×AVDD Trst2 Prise RESETB Item VDD rise time Reset period 1 Reset period2 0.1AVDD Symbol Prise Trst1 Trst2 (VDD：AVDD=OVDD=3.0~3.6V, Ta=0~70C) Typ. Max. unit Condition ms μs μs Min. 0.01 100 100 *When RESETB:Low, LDO for AFE power and LDO for digital power are power downed. The time of digital LDO power-off is 6μs. (The time which becomes lower than 20% of 1.8 V) DC Characteristics (AVDD=OVDD=3.0V~3.6V, Ta= 0~70C) Item Symbol Pin High Input Voltage VIH Note 1,2,3 Low Input Voltage VIL Min. Max. 0.7×AVDD Unit Remarks V High Level output resister Low Level output resister ROH1 ROL1 Note 1,2,3 Note 4 Note 4 0.3×AVDD V 100 100 Ω Ω High Output Voltage Low Output Voltage VOH VOL Note 5 Note 5 0.8×AVDD 0.2×AVDD V V Input Leakage ILKG1 Note 1 10 10 A Input Leakage ILKG2 Note 2 45 10 A Input Leakage ILKG3 Note 3 10 90 A Input Leakage ILKG4 Note 4 10 10 A Input Leakage ILKG5 Note 6 10 10 A Output Leakage OLKG Note 7 10 10 A IOH=-1mA IOL=1mA High-Z (Note1) ADCK, SHD, SCLK, SDATA (Input), SDENB, (Note2) RESETB (Note3) LEDEN_R, LEDEN_G, LEDEN_B (Note4) D0~D7 (Note5) SDATA (Output) 014002433-E-00 2014/06 -8- [AK8456] (Note6) CISIN0~2 (Note7) LED_R/G/B (LED Driver OFF) AFE Block Analog Characteristics 1 (Unless other specified, AVDD=OVDD=3.3V, LVDD=5.0V, Ta=25C, ADCK=30MHz) Item Sensor Reference Level ADC Voltage Symbol VDCE VDCI1 VDCI2 Reference VRP Conditions Reference Voltage External Input Range Internal Voltage Internal Voltage min typ max 0.8 0.9 1.0 1.0 1.1 1.2 1.1 1.2 1.4 1.5 1.6 1.3 1.5 5.5 6.0 Unit V V V V Sample and Hold Input Range VI Gain GSH Resolution DRES Range DRNG Differential nonlinearity DDNL S/H Gain=0dB Digital PGA Gain=0dB S/H Gain=6dB setting Offset Adjust DAC Equivalent Input Level Positive Direction Negative Direction DAC code conversion 300 -440 369 -369 -1 Vpp 6.5 dB 6 bit 440 -300 +1 mV mV LSB Digital PGA Maximum Gain GMAX Relative to 0dB setting Step Width GSTA Monotonicity Guaranteed 0.001 18 dB 0.07 dB ADC Resolution Differential Non-Linearity RES DNL Integral Non-linearity INL CISIN~ADC No missing code guaranteed at 12bit accuracy (PGA=0dB) CISIN~ADC 12bit accuracy -1 16 +1 -16 16 bit LSB LSB Noise, Internal Offset, Cross Talk No Signal Noise (Note 1) NI Gain=0dB Gain=18dB (S/H=6dB, PGA=12dB) Internal Offset (Note 2) Cross Talk VOFST Gain=0dB 50 XTALK (Note 3) PGA=0dB -256 014002433-E-00 14 67 32 LSBrms 50 mV 256 LSB 2014/06 -9- [AK8456] AFE Block Analog Characteristics 2 These specifications are defined under the condition external parts and their constants are in External Circuit Example. (AVDD=OVDD=3.0～3.6V, LVDD=4.5～5.7V, Ta=25C, ADCK=30MHz) Current consumption (note 4) Normal operation AVDD 37.4 51.2 mA (note 5) OVDD 8.6 25.5 mA (note 6) LVDD 6.2 8.4 mA Stand By ISTB 2.2 3 mA These specifications are defined under the condition external parts and their constants are in External Circuit Example. (Note1) No signal noise is defined as sigma(σ) of ADC code deviation under no input signal. (Note2) When no input signal is applied, ADC code changes from 0000h to 0001h between offset DAC 50mV and offset DAC 50mV. The offset DAC cancels this internal offset as well as signal offset. Thus adjust range for input signal offset is reduced by the internal offset. (Note3) ADCK=30MHz, 3ch, PGA Gain of all channel is minimum. Cross talk is defined, as change of output code when measured channel input is fixed and all other channel inputs is full-scale 2dB step signal. (Note4) ADCK=30MHz, Input -2dB of 1.5Vpp sine wave, 1MHz signal to three channels. (Note5) Load Capacitance10pF (Note6) @ LED_R=100%, LED_G=25%, LED_B=25% setting (except LED drive current) LED Driver Analog Characteristics (Unless otherwise specified, AVDD=OVDD=3.3V, LVDD=5.0V, Ta=0C~70C, ADCK=30MHz) Item Min. Maximum LED Current per Channel Total Maximum Current 60.5 LED Typ. 67.2 Max. 73.9 100.8 Unit Remarks mA/ch ISET Resistance=8.2kΩ LED_R/G/B Pin Voltage=2.0V mA 5 5 % LED_R/G/B Pin Voltage=2.0V Dependence of LED Current on LED_R/G/B Pin Voltage 2.5 2.5 % LED_R/G/B Pin’s Reference Voltage = 2.0V LED_R/G/B Pin Voltage 0.3 LVDD 1.1 V Driving Current LED Current Accuracy Setting 014002433-E-00 2014/06 - 10 - [AK8456] Switching Characteristics No. 1 2 Item ADCK Cycle (T) ADCK Low Width 3 ADCK High Width (Unless otherwise specified, AVDD=OVDD=3.0V~3.6V, Ta=0~70C) Pin Min. Typ. Max. Unit Remarks ADCK 33.3 2000 ns ADCK 15 ns ADCK 15 ns 3 6 1 3ch Normal Output clocks 3ch Cascade Output 1ch Mode ns 4 SHD Cycle SHD 5 SHD Pulse Width SHD 8 6 SHD Setup Time （to ADCK） SHD 2 ns 7 SHD Delay Time （to ADCK） SHD 10 ns 8 9 10 SHD Aperture Delay D0~7 Delay （to ADCK） Pipeline Delay (ADCK unit) SHD D7~D0 2.5 2 D7~D0 ns 10 11 Hold, Setup ns CL=10pF (Note 1) 3ch Mode clocks 1ch Mode SHD=”H” Prohibited 1T+10 3ch Normal Output 11 Region (to First SHD 4T+10 ns 3ch Cascade Output ADCK after SHD) 10 1ch Mode 0 8.2 12 D0~7 Enable Time D7~D0 ns Cascade Output 2.4 7.2 13 D0~7 Disable Time D7~D0 ns Cascade Output These specifications refer to point crossing levels that defined in DC characteristics. (Note1) Refer to points ADCK, D7~D0 cross 50% of supply voltage. This delay is under ADCK rise time tr and fall time tf are 1.65ns. 014002433-E-00 2014/06 - 11 - [AK8456] 3ch Input, Normal Output CISIN0~2 0 1 2 SHD 4 10 clock ADCK D7~D0 3 1 2 4 3 5 7 6 8 9 1 1 L ML ML ML ML ML ML ML ML ML ML ML ML ML ML CISIN0 CISIN1 CISIN2 CISIN0 CISIN1 CISIN2 In D7~D0, L means lower 8 bits, M means upper 8bits. Fig. 5 0 Whole Timing Sampling Point 8 CISIN0(n) CISIN1(n) CISIN0~2 CISIN0(n+1) CISIN1(n+1) 5 6 SHD 1 3 4 7 2 11 ADCK 9 D7~D0 9 MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB CISIN2(n5) CISIN0(n4) CISIN1(n4) Fig.6 CISIN0(n3) CISIN1(n3) CISIN2(n3) Details tf tr ADCK CISIN2(n4) 0.7AVDD 0.3AVDD 9 D7~D0 9 0.5OVDD Fig.7 D0~D7 Delay 014002433-E-00 2014/06 - 12 - [AK8456] 3ch Input, Cascade Output CISIN0~2 1 0 2 3 SHD ADCK D7~D0 #0 D7~D0 #1 M L M L M L M L M L M L CISIN0 M L M L M L M L M L M L M L CISIN2 CISIN1 M L M L M L CISIN0 2 1 M L M L M L CISIN2 CISIN1 0 In D7~D0, L means lower 8 bits, M means upper 8bits. Fig.8 Whole Timing Sampling Point 8 CISIN0(n) CISIN1(n) CISIN2(n) CISIN0~2 CISIN0(n+1) CISIN1(n+1) CISIN2(n+1) 6 5 SHD 1 2 ADCK 3 9 D7~D0 M 4 7 L 11 9 M L M L M L M L M L M L CISIN0 CISIN1 CISIN2 (n4) (n4) (n4) Fig.9 tr ADCK Details tf 0.7AVDD 0.3AVDD 12 9 D7~D0 9 13 0.5OVDD Fig.10 D0~D7 Delay 014002433-E-00 2014/06 - 13 - [AK8456] 1ch Input CISIN0 0 1 2 3 4 5 6 7 8 9 10 11 12 SHD ADCK D7~D0 L M L M L M 10 L 9 M L M 8 L M 7 L M 6 L M 5 L M 4 L 3 M L M 2 L M 1 L 0 M L 1 In D7~D0, L means lower 8 bits, M means upper 8bits. Fig.11 Whole Timing Sampling Point CISIN0(n+1) 8 CISIN0(n) CISIN0 5 6 SHD 4 7 11 ADCK 9 D7~D0 3 9 MSB 2 1 LSB MSB CISIN0(n11) LSB CISIN0(n10) Fig.12 Details tr ADCK tf 0.7AVDD 0.3AVDD 9 D7~D0 9 0.5OVDD Fig.13 D0~D7 Delay 014002433-E-00 2014/06 - 14 - [AK8456] Serial Interface Switching Characteristics Sf SDENB Sr Sdenh 0.7AVDD 0.3AVDD Sf Ssu Sr Shi Slo Sh2 0.7AVDD 0.3AVDD SCLK Ssu SDATA 0.7AVDD 0.3AVDD Sh Scyc input Ssp input output Sst Fig.14 output 0.8AVDD 0.2AVDD Sdl Serial Interface Timing (Unless otherwise specified, AVDD=OVDD=3.0V~3.6V, Ta=0~70C, CL=10pF) Item Clock Cycle Symbol Scyc Condition min. Clock High Width Shi Above 70% of AVDD 40 ns Clock Low Width Slo Under 30% of AVDD 40 ns Setup Time (to SCLK) Ssu 40 ns Hold Time (to SCLK) Sh 40 ns SDENB Hold Time (to SCLK) Sh2 80 ns Data Enable Delay (to SCLK) Sst Data Output Delay (to SCLK) Sdl Data Disable Delay (to SDENB) SDENB High Width Ssp High-Z→Data Out typ. max. 10 Unit MHz 0 30 ns 0 30 ns Data Out→High-Z 0 30 ns Sdenh Above 70% of AVDD 40 Rise Time Sr 30%70% of AVDD 10 ns Fall Time Sf 70%30% of AVDD 10 ns 014002433-E-00 ns 2014/06 - 15 - [AK8456] LED Driver Switching Characteristics (Unless otherwise specified, AVDD=OVDD=3.0V~3.6V, LVDD=4.5V~5.7V, Ta=0~70C) Item Symbol LEDEN_R/G/B Setup Time (to SHD) tlens 15 ns LEDED_R/G/B Hold Time (to SHD) tlenh 15 ns min. typ. max. 0.7AVDD LEDEN_R/G/B tlenh SHD Conditions 0.3AVDD tlens tlenh tlens 0.7AVDD 0.3AVDD Fig. 15 Unit LED driver switching characteristics (Unless otherwise specified, AVDD=OVDD=3.0V~3.6V, LVDD=4.5V~5.7V, Ta=0~70C) Item Symbol Conditions min. typ. max. Unit LED Current Rise Time tlon 10 s LED Current Fall Time tloff 10 s LEDEN_R/G/B SHD 0.3AVDD 0.3AVDD 90% LED_R/G/B Current 10% tlon Fig. 16 tloff LED current timing LED drivers are switched in LEDEN_R/G/B those are synchronized with SHD falling edge. Therefore, if it can’t meet setup time or hold time of LEDEN_R/G/B, LED lighting time will be 1~2 pixels change. 014002433-E-00 2014/06 - 16 - [AK8456] 9. Functional Description Start Up There is no restriction on order of turning on AVDD, OVDD and LVDD. Please take a reset by hold RESETB low level when the power AVDD is turned on. LEDEN_R/G/B must be low level during RESETB rises. User can access to the registers after wait time that are shown in followed figures from power-up. Fig.17 Not Use Power on Reset AVDD (3.3V) Internal Reference circuits (related to LDO) are activated immediately. A few mA consumption RESETB LDO start DVO (LDO Output) (1.8V) Access to Register Not available (Reset) a few ms Available ~1ms LEDEN_R/G/B LEDEN_R/G/B are must be all low when RESETB rise to high. 014002433-E-00 2014/06 - 17 - [AK8456] Fig.18 Use Power on Reset AVDD 100k RESETB 0.33F AK8456 Power on reset circuit is composed by pull-up resistance of RESETB and external capacitor. When external capacitor is 0.33F, AVDD rise time must be less than 10ms to reset exactly. Staircase-like supply voltage rising is not allowed. Fig.19 Power on Reset timing AVDD (3.3V) Internal Reference circuits (related to LDO) are activated immediately. A few mA consumption occurs. RESETB LDO start DVO (LDO Output) (1.8V) Access to Register Not available (Reset) Available ~100ms LEDEN_R/G/ LEDEN_R/G/B are must be all low when RESETB rise to high. When down AVDD to 0V, RESETB level does not became 0V immediately because of charge remaining in RESETB external capacitor. If up AVDD again before RESETB becoming 0V, power on reset does not carry out. The time AVDD is 0V must be longer than 300ms for exact power on reset at re-power up AVDD. Please control the RESETB from outside without the use of a power-on reset if the above conditions are not met. During power up AVDD, hold RESETB low level. Then raise RESETB to high level. 014002433-E-00 2014/06 - 18 - [AK8456] Serial Interface Control registers are accessed through serial interface. The control registers are readable. If SDENB is low, it is possible to access registers. Input address and data into SDATA. SDATA is captured by SCLK rising edge. Write The first bit of SDATA is 0, data is written to register. From second bit to fourth bit must be 0. From fifth bit to eighth bit are address bits. The fifth bit is most significant bit of address. From ninth bit to sixteenth bit are data bit. Data is written into register by rising edge of SDENB. If rising edge of SCLK is less than sixteen, data isn't written into register. If rising edge of SCLK is more than seventeen, front sixteen bits are effective. SDENB SCLK SDATA Fig.20 0 0 0 0 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 Write to Register Read The first bit of SDATA is 1, data is read from register. From second bit to fourth bit must be 0. From fifth bit to eighth bit are address bits. The fifth bit is most significant bit of address. Data is output from the SCLK falling after SCLK rising incorporating an eighth bit. SDATA pin is used as an input again if SDENB become high level. If there is a SCLK 17 or more times, read data after the B0 is output is 0. SDENB SCLK SDATA 1 0 0 0 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 Input Fig.21 Output Input Read from Register 014002433-E-00 2014/06 - 19 - [AK8456] CIS Signal Input Channel Number Select There are 3-channel mode and 1-channel mode as input channel number. Input channel number is selected by register. In 1-channel mode, signal is input to CISIN0. At this time, CISIN1 and CISIN2 can be connected to AVSS, or opened, or input dummy signal. Sample and hold circuit and DAC of not used channels are power down. Frequency of ADCK in 3-channel mode is three times the pixel frequency per channel. In 1-channel mode, ADCK frequency is equal the pixel frequency. CIS Reference Voltage It is able to select to use internal voltage or to use externally input voltage as sensor reference voltage by register. Input range of external voltage is from 0.8V to 1.2V. Internal voltage is 1.0V (typ.) or 1.1V (typ.). Offset Adjustment Offset adjustment is done by adding DAC output voltage to sensor signal. Resolution of DAC is six bit, range is 369mV(typ.)/300mV(min.) in equivalent input voltage. 50mV (max.) out of 369mV is used to cancel LSI internal offset. Therefore effective range for correcting signal offset is 319mV(typ.)/250mv(min.). The equivalent input voltage does not change even if set 6dB gain at sample and hold block. VDC Offset DAC Vref S/H CISINn Signal Vsig Reference Vref GND Vsig Internal Reference Level Fig.22 +Max.(011111b) 369mV 369mV Max.(100001b) Offset adjustment Sampling Sensor signal are sampled at SHD falling edge. Gain Adjustment It is possible to amplify signals at sample and hold block. And it is possible to amplify A/D output code by digital PGA. Gain of digital PGA is from 0dB to 18dB. Its resolution is 8bit. Output Format Output Formal is straight binary. Gray code output is possible too. 014002433-E-00 2014/06 - 20 - [AK8456] A/D 16 Digital PGA 16 16 Gray Code D15 G15 D14 G14 D13 G13 Gray code conversion D12 G11 D10 G10 D8 Forward Backward 8 D7~D0 G12 D11 D9 16bit Upper 8bit Lower 8bit G9 G8 Forward Backward D7 D15 D7 G7 G15 G7 D6 D14 D6 G6 G14 G6 D5 D13 D5 G5 G13 G5 D4 D12 D4 G4 G12 G4 D3 D11 D3 G3 G11 G3 D2 D10 D2 G2 G10 G2 D1 D9 D1 G1 G9 G1 D0 D8 D0 G0 G8 G0 Normal Fig.23 Gray Code Output format LED Driver LED Driver controls LED current RGB independently. LED must be connected as anode common. If LEDEN_R/G/B are high level, LED current are driven. If LEDEN_R/G/B are low level, LED current are stopped. LEDEN_R/G/B are synchronized once by SHD internally. Therefore if SHD is not input, LEDEN_R/G/B are not effective. LED Current Adjustment The LED current can be adjusted in increments of 8.4mA to 67.2mA from 8.4mA channel independently. LED Current Limit AK8456 LED driver current limitation is 100.8mA (total:150% setting). With the combination with “LEDEN_R/G/B pin logic” and LED drive current setting register value, in case of the combination that the total of the current amount to flow through at the same time exceeds 150%(100.8 mA), the LED drive current doesn't flow. For example, when making "LEDEN_R/G/B" active at the same time and when the total of the LED drive current set value exceeds 150%(100.8 mA), the LED drive current doesn't flow. On the other hand, when making "LEDEN_R/G/B" active individually, the current flows. 014002433-E-00 2014/06 - 21 - [AK8456] Cascade Output Mode It is possible that connect two AK8456’s output pins to same 8bit bus by cascade output mode. The cascade output mode is available only in 3-channle input mode. It becomes the normal output regardless of the cascade mode register setting when the channel 1 input. If use cascade mode, please release the power-down after setting the device ID and cascade mode register. Select the cascade mode in the register and set 0 in ID register of one and set 1 in ID register of the other. Device of ID0 outputs the data before, ID1 devices will output the data then refer to SHD pulse. D7~D0 become high impedance when these pins don’t output A/D data. D7~D0 are open drain output in cascade mode. Please connect pull-up resistance to each data output pin. Maximum sampling rate in cascade mode is 5MSPS/ch. AK8456 #0 D7~D0 8 SCLK, SDATA 2 SDENB1 8 Control IC AK8456 #1 D7~D0 8 SCLK, SDATA 2 SDENB2 CISIN0~2 0 1 3 2 SHD ADCK D7~D0 #0 D7~D0 #1 M L M L M L M L M L M L CISIN0 M L M L M L M L M L M L M L CISIN2 CISIN1 M L M L M L CISIN0 Fig.24 M L M L M L CISIN2 CISIN1 Cascade mode explanation 014002433-E-00 2014/06 - 22 - [AK8456] 10. Register Map 0h Register Name CNTRL1 1h 2h OFST0 OFST1 CISIN0 Offset Setting CISIN1 Offset Setting 3h 4h OFST2 GAIN0 CISIN2 Offset Setting CISIN0 Gain Setting 5h 6h GAIN1 GAIN2 CISIN1 Gain Setting CISIN2 Gain Setting 7h 8h CNTRL2 ISELR Operation Control 2 (Related to Output Stage) LED_R Current Setting 9h 0Ah ISELG ISELB LED_G Current Setting LED_B Current Setting Adrs Function Operation Control 1 (Related to Input Stage) ** Register-address 0Bh-0Fh is an access-inhibit. ** When writing an undefined bit, write 0. 014002433-E-00 2014/06 - 23 - [AK8456] Adrs Name B7 B6 B5 B4 B3 B2 B1 0h CNTRL1 Default NPD 0 SHG0 0 SHG1 0 SHG2 0 --0 VDCO 0 VDCSEL CHN 0 0 Address 0h B7 NPD B0 Power-down Setting Operation 0 Power-down 1 Normal Operation Both of AFE block and LED driver power-down. LDO for analog block does not power –down. Address 0h B6 CISIN0 Sample and Hold Gain Address 0h B5 CISIN1 Sample and Hold Gain Address 0h B4 CISIN2 Sample and Hold Gain SHG0/1/2 0 1 Gain at Sample and Hold Block 0dB 6dB Address 0h B2 CIS Reference Voltage Source Select VDCO CIS Reference Voltage Source 0 1 External Internal (Output to VDC pin) Address 0h B1 CIS Internal Reference Voltage Select VDCSEL 0 CIS Reference Voltage 1.0V 1 1.1V Address 0h B0 CHN Input Channel Number Select Channel Number 0 3 Channels 1 1 Channel (Input to CISIN0) ** When writing an undefined bit, write 0. 014002433-E-00 2014/06 - 24 - [AK8456] Adrs Name B7 B6 B5 1h 2h Offset 0 Offset 1 － － － － OFST0 OFST1 3h Offset 2 Default － － 0 0 OFST2 0 Address 1h B5~B0 CISIN0 Offset Setting Address 2h B5~B0 CISIN1 Offset Setting Address 3h B5~B0 CISIN2 Offset Setting OFST0/1/2 01 1111 01 1110 : 00 0001 00 0000 11 1111 : 10 0010 10 0001 10 0000 B4 B3 B2 B1 B0 0 0 0 0 0 Offset Voltage +369mV +357.1mV +11.9mV 0mV 11.9mV 357.1mV 369mV Inhibit When set minus value, signal magnitude becomes smaller. When set plus value, signal magnitude becomes larger. When 11.9mV setting, image signal decrease 11.9mV. ** When writing an undefined bit, write 0. 014002433-E-00 2014/06 - 25 - [AK8456] Adrs Name B7 4h 5h DPGA 0 DPGA 1 DGAIN0 DGAIN1 6h DPGA 2 Default DGAIN2 0 0 B6 0 B5 B4 0 0 B3 Address 4h B7~B0 CISIN0 Digital PGA Gain Setting Address 5h B7~B0 CISIN1 Digital PGA Gain Setting Address 6h B7~B0 CISIN2 Digital PGA Gain Setting DGAIN0/1/2 0000 0000 0000 0001 : 1111 1110 1111 1111 B2 B1 B0 0 0 0 Digital PGA Gain 0dB 18dB Inhibit Gain( x) 18 x / 254 [dB] x=0~254 014002433-E-00 2014/06 - 26 - [AK8456] Adrs Name B7 B6 B5 B4 B3 B2 B1 B0 7h CNTRL2 Default --0 --0 CASC 0 DEVID 0 --0 DRV 0 --0 FORMAT 0 Address 7h B5 CASC Cascade Output Mode Select Data Output 0 Normal Output 1 Cascade Output If use cascade output mode, power down mode must be released after setting cascade output mode select register and device ID select register. Address 7h B4 DEVID 0 1 Address 7h B2 DRV 0 Device ID for Cascade Output Mode Device ID 0 1 Output Buffer Ability Select Output Buffer Ability Normal 1 1/3 If set DRV=1 then output buffer ability of D7~D0 became 1/3 of normal. Address 7h B0 FORMAT 0 1 Output Format Select Output Format Straight Binary Code Gray Code ** When writing an undefined bit, write 0. 014002433-E-00 2014/06 - 27 - [AK8456] Adrs Name B7 B6 8h 9h Current R Current G ----- ----- ----- ----- ----- ISELR ISELG Ah Current B Default --- --- --- --- --- ISELB 0 0 0 B5 B4 0 0 Address 8h B2~B0 LED_R Current Setting Address 9h B2~B0 LED_G Current Setting Address Ah B2~B0 LED_B Current Setting ISELR/G/B 000 001 : 110 111 I ( x ) 8.4( x 1) [mA] B3 0 B2 B1 B0 0 0 LED Current 8.4mA 16.8mA : 58.8mA 67.2mA x=0~7 ** When writing an undefined bit, write 0. 014002433-E-00 2014/06 - 28 - [AK8456] 11. External Circuit Example 8.2k(note1,4) ISET 1F(note3,4) VDC 1F(note2,3,4) VRP 0.33F(note4,5) RESETB 1F(note3,4) AVO (note6) LED_R/G/B AVSS AVSS AVSS AVSS AVSS LVSS OVDD min. 300 Pull-up(only cascade mode) D0～7 SDATA min. 10k Pull-down or pull-up AVSS Fig.25 Reference voltage:D0~ 7,SDOUT,AVO,LED_R/G/B note1）The resistance precision is ±3 % (including thermal-characteristic) note2）The capacitance precision is ±50 % (including thermal-characteristic) note3）Connect them near the pin. note4）Keep off them from clock line(noise source) and so on. note5）When not using a power on reset, it is unnecessary, connecting. note6) Be careful that the voltage of the LED_R/G/B-pin doesn't exceed "LVDD+0.3V" , by the influence of the overshoot. In case of ,the overshoot is big and the LED wiring is long, put a capacitor between " the LED_R/G/B terminal " and the grand. *VDD：OVDD, AVDD, LVDD *VSS：OVSS, AVSS, LVSS Note7） Each power pin need this Cap. *VDD VDD 0.1F(note7) 10F (note7) *VSS Fig.26 Power pins 014002433-E-00 2014/06 - 29 - [AK8456] Connection of Cascade Output Mode 3.3V 3.3V R R R R R R R R D7 D6 D5 D4 OVDD 19 20 21 22 23 24 25 29 OVSS D3 Fig.27 26 17 28 27 19 D0 18 D2 D1 D7 20 21 22 23 24 25 29 D6 D5 D4 OVDD OVSS D3 26 27 28 D2 D1 D0 R: min.300 18 17 Cascade mode connection example 014002433-E-00 2014/06 - 30 - [AK8456] 12. Package Dimensions (36pin QFN 5mm×5mm, Pin Pitch 0.4mm) Fig.28 Package dimensions Marking 1. 2. Marketing Code Date Code :XXX :Y :AK8456 Week Number Control Code AK8456 XXXY Note) Marking is preliminary Fig.29 AK8456 Marking 014002433-E-00 2014/06 - 31 - [AK8456] 13. Important Notice IMPORTANT NOTICE 0. Asahi Kasei Microdevices Corporation (“AKM”) reserves the right to make changes to the information contained in this document without notice. When you consider any use or application of AKM product stipulated in this document (“Product”), please make inquiries the sales office of AKM or authorized distributors as to current status of the Products. 1. All information included in this document are provided only to illustrate the operation and application examples of AKM Products. AKM neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of AKM or any third party with respect to the information in this document. You are fully responsible for use of such information contained in this document in your product design or applications. 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This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written consent of AKM. 014002433-E-00 2014/06 - 32 -