M61140FP
Tuner Single Chip
REJ03F0023-0130
Rev.1.3
Jun 14, 2004
Description
The M61140FP is a semiconductor integrated circuit consisting of Tuner signal processing for NTSC color TV and
VCRs.
The circuit includes Mixer circuit in Tuning system, Oscillator circuit, PLL frequency synthesizer and VIF/SIF, which
permits a smaller tuner system.
Features
• VIF/SIF
Inter carrier type for NTSC
Coil-less VCO
Adjustment free AFT
High-speed IF AGC
• PLL
Low phase noise and High-speed lock-up
Built-in band switch driver (4 port)
I2C bus control
Available for both XO and external reference
• Mixer/Oscillator
Built-in U&V Oscillator and mixer
Built-in IF Amplifier (Unbalanced Output)
Application
TV, VCR
Recommended Operating Conditions
Supply voltage range --- 4.75 to 5.25V
Recommended supply voltage --- 5.0V
Rev.1.3 Jun 14, 2004 page 1 of 27
M61140FP
2
3
4
5
6
7
8
9
Video det OUT
Vreg
RF AGC Delay
IF AGC 2
EQ F/B
OSC GND
V OSC IN 1
V OSC OUT 1
V OSC OUT 2
M/O Vcc
OSC GND
1
Rev.1.3 Jun 14, 2004 page 2 of 27
10
11
12
24
48
EQ
AMP
Vreg
UHF
OSC
VHF
OSC
23
LPF
22
U
MIX
21
47
IF AGC
DET
20
46
PSC
1/32, 1/33
19
V
MIX
PVHFH
Mix Filter 1
18
Band driver
15bit
P.G divider
RF GND
APC
PVHFL
Mix Filter 2
17
ADS
RF
AGC
PFMST
RF GND
16
AFT
IF
AMP
RF AGC OUT
V Band IN
15
QIF
AMP
MO Vcc
PUHF
14
SCL
Ref IN
SDA
Logic Vcc
Logic GND
Bus
receiver
Phase
det
45
VCO F/B
EQ IN
Coil-less
VCO
44
Video OUT
25
U Band IN 1
13
43
APC Filter
26
Ref
divider
LIM
AMP
VIF GND
IF AGC 1
27
FM
det
42
VIF GND
28
Logic Vcc
XO
Charge
pump
41
AFT OUT
29
U OSC 2
40
QIF OUT
30
Logic GND
U OSC 1
39
Audio OUT
31
V OSC IN 2
38
AF Bypass
32
Video
det
VIF IN 1
33
VIF Vcc
IF amp
37
VIF IN 2
Vt Drive
34
CP
35
IF2 GND
VIF Vcc
IF2 Vcc
36
IF OUT
IF2 GND
Pin Configuration and Block Diagram
U Band IN 2
M61140FP
Absolute Maximum Ratings
(Ta=25ºC, unless otherwise noted)
Parameter
Supply Voltage
Symbol
Vcc
Ratings
6
Unit
V
MO Block
PLL Block
Maximum Allowable Input
Input Voltage
Note
Vin
Vimax
126
6
dBµV
V
Port Output Voltage
Port Output Current (1)
Vo
Iopmax1
6
26
V
mA
Pin20 to 22,15
Pin20, 21
Port Output Current (2)
Port Output Current (3)
Iopmax2
Iopmax3
7
33
mA
mA
Pin15, 22
2 circuits are on at same time
SDA Output Current
Power Consumption
Iosdamax
Pd
10
750
mA
mW
Operating Temperature
Topr
–20 to +75
°C
Storage Temperature
Tstg
–40 to +150
°C
Pin25 to 27
Recommended circuit board.
When Cu occupancy area is 50%.
Temperature Characteristics (maximum ratings)
Mounting in standard circuit board (70mm × 70mm × 1.6mmt Epoxy board of one side copper)
Allowable power consumption Pd
1500
1250
1000
750
500
250
0
-20
0
25
50
75
100
Ambient temperature Ta (˚C)
125
150
Recommended Operating Condition
(Ta=25ºC, unless otherwise noted)
Parameter
Guarantee Operating Voltage
Symbol
Vcc
Supply Voltage Range
Operating frequency of Crystal oscillator
Vcc
fopr
Port output current (1)
Port output current (2)
Ioprt1
Ioprt2
Rev.1.3 Jun 14, 2004 page 3 of 27
Ratings
4.5~5.3
Unit
V
4.75~5.25
4.0
V
MHz
0~25
0~5
mA
mA
Note
Refer to Data
Pin 20,21
Pin 15,22
M61140FP
Pin Description
Pin No.
1
2
Pin name
VIDEO DET
OUT
Vreg
Function
Circuit Diagram
Video detected output terminal. SIF
trap and SIF B.P.F. are connected to
this terminal. Because of open
emitter configuration, an externally
connected drive resistor is
necessary.
33
Regulated voltage output.
Approximately 3V output.
33
50
1
50
2
9.9K
6.2K
3
RF AGC
DELAY
RF AGC terminal. This terminal
combine 4.5MHz SIF signal input
with set up the RF AGC delay point.
The RF AGC delay point is set up by
the DC component of input signal.
AC component is FM detection threw
the limiter amplifier.
33
40
3
5.1K
40p
43K
15p
4
44
IF AGC 2
IF AGC 1
IF AGC 2 terminal
IF AGC 2 terminal. External
capacitor effects AGC speed. When
this terminal is grounded, the effect
of VIF amp gain becomes minimum.
33
10K
2.5K
4
44
5
EQ F/B
Equalizer feedback terminal. It is
possible to change the frequency
characteristic of the video signal by
attaching L,C,R to this terminal.
33
2.2K
500
5
6
OSC GND
OSC ground terminal.
Rev.1.3 Jun 14, 2004 page 4 of 27
7K
50
M61140FP
Pin No.
7
Pin name
V OSC IN 1
8
9
V OSC OUT 1
V OSC OUT 2
10
V OSC IN 2
Function
VHF oscillator circuit is connected
externally. When band byte bit PUHF
is set "1", bias current of oscillator
transistor turns OFF.
Circuit Diagram
24
600
400
600
400
7
9
8
11
12
U OSC 1
U OSC 2
UHF oscillator circuit is connected
externally. When band byte bit PUHF
is set "1", bias current of oscillator
transistor turns ON.
36
400
3p
11
400
3p
12
2.5p
2.5p
13
14
U BAND
IN 1
U BAND
IN 2
UHF RF input terminal. Input type is
balance input. In the case of
unbalance input, grounding of either
pin 13 or 14 with capacitor is
required, while input to the other pin.
24
13
1.8K
14
1.8K
15
PUHF
Band change drive terminal. Output
configuration is PNP open collector.
When band selection bit PUHF is set
"1", current is output.
24
47K
15
16
V BAND IN
VHF RF input terminal.
Input type is unbalance.
24
2.2K
16
2.2K
17
RF GND
RF (Mixer) GND terminal.
Rev.1.3 Jun 14, 2004 page 5 of 27
2.2K
2.2K
10
M61140FP
Pin No.
18
19
20
21
Pin name
MIX
FILTER 1
MIX
FILTER 2
PVHFH
PVHFL
Function
Mixer output terminal. The output
terminal is open collector type,
single-tuned filter is connected. This
pin is pull-up through power supply in
order for voltage to be above 4.2V.
Band change drive terminal. Output
configuration is PNP open collector.
When band selection bit PVHFL or
PVHFH is set "1", current is output.
Circuit Diagram
24
200 20p
19
200 20p
28
47K
20
21
22
23
PFMST
RF AGC
OUT
Band change drive terminal. Output
configuration is PNP open collector.
When band selection bit PFMST is
set "1", current is output. Reference
frequency or divided frequency of
local are output by test mode
condition.
28
RF AGC output terminal. It is current
drive type.
33
47K
22
24
50
23
24
MO Vcc
25
ADS
Mixer and oscillator block power
supply.
Address setting input terminal.
Address bit "MA1","MA2" is selected
by the potential at this terminal.
28
40K
1K
25
13K
Rev.1.3 Jun 14, 2004 page 6 of 27
4K
18
4K
M61140FP
Pin No.
26
Pin name
SCL
Function
SCL input terminal.
Circuit Diagram
28
1K
26
27
SDA
SDA input terminal. Reading and
2
writing of data confirm to I C bus of
Philips.
28
1K
27
ACK
28
Logic Vcc
Logic block power supply.
29
REF IN
Reference frequency input terminal.
Connect crystal oscillator at this
terminal, or external signal (Sine
wave).In this case of using external
sine wave signal, pull down this
terminal with 1.5k to 3.3kΩ.
28
1.3K
Logic GND
Logic block power supply.
31
VT DRIVE
Filter transistor drive terminal. As for
drive output, control bit "OS" controls
it On or OFF
28
32
CP
Charge pump output terminal.
When the phase of the divide
frequency of local is lead compared
with the reference frequency, the
"source" current state becomes
active. If it is lag, the "sink" current
becomes active. If the phase are the
same, the high impedance state
becomes active.
32
VIF Vcc
VIF block power supply.
34
IF2 Vcc
Power supply terminal exclusively for
IF amp output (pin 34) circuit.
35
IF OUT
IF amp output terminal. This terminal
is a low impedance and output IF
frequency.
D
1K
31
150
OS
34
20
35
Rev.1.3 Jun 14, 2004 page 7 of 27
1.3K
29
30
33
500
500
50
U
M61140FP
Pin No.
36
37
38
Pin name
IF2 GND
Function
IF2 grand terminal. This grand is
exclusively used by circuit of IF
amplifier
VIF IN 1
VIF IN 2
IF signal thew SAW filter is input. It is
a balance type input.
Circuit Diagram
33
2K
37
38
2K
14K
39
40
AF BYPASS
AUDIO OUT
AF bypass terminal. It is connected
to one of the input of a differential
amplifier, external capacitor provides
AC filtering. When resistor is
connected in series with capacitor, it
is possible to lows the amplitude of
the audio output. When audio output
terminal is not used, please connect
pin 22 to GND.
33
Sound output terminal. De-emphasis
is achieved by external components.
33
30K
39
1K
100
30K
1K
200
40
41
QIF OUT
QIF output terminal. FM signal which
is converted to 4.5MHz is output.
Additionally, this pin has dual
function of being VIF VCO type
selection. Connected to GND via
1.2kΩ
33
400
30K
6p
41
42
AFT OUT
AFT output terminal. Because of
pulse-like signal output, a smoothing
capacitor is connected externally. In
addition, AFT detection sensitivity is
set by external resistor.
33
300u
50
42
300u
43
VIF GND
VIF GND terminal.
Rev.1.3 Jun 14, 2004 page 8 of 27
M61140FP
Pin No.
45
Pin name
APC FILTER
Function
APC filter terminal. It is the loop filter
terminal which a VIF signal is made
to lock VCO and keeps frequency
constant.
Circuit Diagram
28
33
21K
17
45
46
VIDEO OUT
Video output terminal. The signal
inputted into the EQI terminal is
outputted.
21K
33
200
46
47
VCO F/B
VCO feedback terminal. The
feedback is to keep the free-running
frequency of the built-in VCO.
33
20K
47
48
EQ IN
The video signal threw the SIF trap is
input to this terminal. DC impression
from pin 1 is required for the input to
48 pins.
33
100
48
Rev.1.3 Jun 14, 2004 page 9 of 27
10K
300
300
M61140FP
Setting Data
M61140FP's bus format is based on Philips's I2C-bus.
Bidirectional bus communication control can be performed. It consists of WRITE mode which receives various data,
and READ mode which transmits data. Recognition in WRITE mode and READ mode is performed by specification of
the last bit on Address Byte (R/W bit). When the setup of a R/W bit is "0", it is set as WRITE mode and, in the case of
"1", is set as READ mode. Furthermore, it has the address in which four programs are possible.
It enables this to use two or more devices on the same I2C bus.
Moreover, four programmable addresses are possible. Therefore, two or more devices become usable on I2C bus.
A setup of an address is chosen by the voltage impressed to an address setting terminal (ADS:25 pin).
If the address Byte in agreement is received, a data line will be set to "L" between knowledge, and at the time of
WRITE mode, if Data Byte is received, SDA line between knowledge will be set to "L."
It shows a definition of bus protocol admitted in the following.
Mode_1 STA
CA DB1 DB2 CB1 CB2 STO
Mode_2 STA
CA CB1 CB2 DB1 DB2 STO
Mode_3 STA
CA DB1 DB2 STO
Mode_4 STA
CA CB1 CB2 STO
STA : Start condition
STO : Stop condition
CA : Chip address
DB1 : Divider data byte 1
DB2 : Divider data byte 2
CB1 : Control data byte 1
CB2 : Band data byte 2
Rev.1.3 Jun 14, 2004 page 10 of 27
M61140FP
(1) WRITE mode
The information of 5 bytes required for circuit operational chip address, control data and band SW data of 2 bytes
and divider data of 2 bytes. after the chip address input, 2 or 4 bytes can be received. Function bit is contained in the
first and the third data byte to distinguish between divider and 'control data/band SW data', with "0" going ahead of
divider data, and "1" going ahead of 'control data/band SWdata'.
The timing of Writing data for bus protocol Mode is shown in the figure below. Divider data uses 15 bits and is read
in at the rise of the eighth clock bit of the second byte divider data (DB2). Control data (CB1) and band SW-data
(BB) are each read in at the rise of their eighth clock bit.
Timing Chart
SDA
address
DB1
DB2
CB2
CB1
SCL
Read into latch
Read into latch
Read into latch
Write mode data format
Byte
MSB
LSB
Address Byte (CA)
1
1
0
0
0
MA1
MA0
R/W=0
A
Divider Byte1 (DB1)
Divider Byte2 (DB2)
0
N7
N14
N6
N13
N5
N12
N4
N11
N3
N10
N2
N9
N1
N8
N0
A
A
Control Byte (CB1)
Band Byte (CB2)
1
X
CP
X
T2
X
T1
X
T0
PUHF
Rsa
PFMST
Rsb
PVHFH
OS
PVHFL
A
A
Programmable Address Bit
Address input voltage applied to ADS [V]
MA1
MA0
0 to 0.1xVcc
0
0
Open or 0.2 to 0.3xVcc
0
1
0.4xVcc to 0.6xVcc
0.9xVcc to Vcc
1
1
0
1
N14 to N0 : Set up for division ratio of the programmable divider
Frequency of VCO fvco: fvco=fref x N
Division ratio N: N=N14(2^14 )+N13(2^13 )+ --- +N0(2^0)
Range of division ratio N: N=1,024 to 32,767
fref: Reference frequency of phase comparator
CP: Set up the charge pump current
CP
Charge pump current *
0
70µA
1
300µA
Note:* Current of charge pump is typ current
In the case of setting current 270µA,when PLL is locked, charge pump current is automatically switched to CP=O
(70µA).
Rev.1.3 Jun 14, 2004 page 11 of 27
M61140FP
T2, T1, T0 : Set up for test mode
CP
T2
T1
T0
Charge pump
Test output
Test SW
Mode
0
0
0
X
CP switched off
-
OFF
Normal mode
1
0
0
X
CP switched on
-
OFF
Normal mode
X
X
0
1
1
1
X
0
High impedance
Sink
-
OFF
OFF
Test mode
Test mode
X
0
1
1
1
0
1
0
Source
High impedance
fREF
OFF
OFF
Test mode
Test mode
1
0
1
1
0
0
X
1
CP switched on
High impedance
f1/N
ON
OFF
TV test mode
Test mode
Note : fREF and f1/N is available on pin PFMST(pin 22). Test SW is for the mix filter damping switch
Rsa : Set up tuning step
Rsa
Rsb
tuning step frequency
@4MHz X'tal
Division ratio
0
1
1
1
1/128
1/64
31.25kHz
62.5kHz
X
0
1/80
50.0kHz
OS : Set up drive output
OS
Drive output
Mode
0
ON
Normal mode
1
OFF("L")level
Test mode
PFMST, PUHF , PVHFL,PVHFH : PORT setting
PFMST,PUHF,PVHFL,PVHFH
Output
0
1
OFF
ON
PNP open collector output. When PUHF is "OFF", Mixer and Oscillator active VHF mode.
(2) READ mode data format
At the time of READ mode, a power-on reset state, a phase comparison machine lock detector output state, and the
state of the charge pump current change SW are outputted to a master device.
Read mode data format
Byte
Address Byte
Status Byte
MSB
1
POR
LSB
1
FL
0
ACPS
0
X
0
X
MA1
X
MA0
X
R/W=1
X
A
A
X: 0 or 1 Don't care
POR: Power on reset flag. Output is "1" at power-on
Set to "1" when the time of a power supply voltage injection or power supply voltage falls
in about 3V or less.
Reset by "0", if a Request to Send is carried out in READ mode and a flag is returned.
Power supply voltage is about 3v or more, Reset by "0", after returning a flag in READ
mode.
FL: Lock detector flag. Output is "1" at locked, output is "0" at unlocked.
ACPS: Automatic charge pump current flag. Output is "0" at charge pump current automatically
switched mode, output is "1" at other mode.
Rev.1.3 Jun 14, 2004 page 12 of 27
M61140FP
(3) Power on reset
The initial status is shown as below when supply voltage is turned on. If supply voltage becomes less than about
3.0V, the initial status is set.
Byte
MSB
LSB
Divider Byte1 (DB1)
0
X
X
X
X
X
X
X
Divider Byte2 (DB2)
Control Byte (CB1)
X
1
X
1
X
0
X
1
X
X
X
1
X
1
X
1
Band Byte (CB2)
X
X
X
X
0
0
0
0
(4) Data format example
Ex1.US-TV-ch2 (fRF=55.25MHz,fosc=101MHz),CP sw=ON, Reference Frequency=4MHz,31.25kHzstep,
PUHF="ON"
Byte
MSB
LSB
Address Byte
Divider Byte1 (DB1)
1
0
1
0
0
0
0
0
0
1
MA1
1
MA0
0
R/W=0
0
A
A
Divider Byte2 (DB2)
Control Byte (CB1)
1
1
0
1
1
0
0
0
0
0
0
0
0
1
0
0
A
A
X
X
X
0
0
0
1
A
Band Byte (CB2)
X
6
Divide ratio N =101*10 /31.25*10
= 3232
11
10
7
5
= 2 +2 +2 +2
3
2
Purchase of Renesas Technology electric corporation's I C components conveys a license under the Philips
2
2
2
I C Patent Rights to use these components in an I C system, provided that the system conforms to the I C
Standard Specification as defined by Philips
Rev.1.3 Jun 14, 2004 page 13 of 27
M61140FP
Electrical Characteristics
DC characteristics
(Ta=25°C, Vcc=5.0V otherwise noted.)
Symbol
Measure
point
Input
SG
Condition switches set
to position "1" unless
otherwise noted
IF Vcc current
IF2 Vcc current
IccIF
IccIF2
33
34
-
SW33=2
SW34=2
40
14
53
19
66
24
mA
mA
M/O Vcc current
Logic Vcc
current(1)
IccRF
IccLo1
24
28
-
SW24=2
SW28=2 Port OFF
14
11
18
14
23
18
mA
mA
Logic Vcc
current(2)
Logic Vcc
current(3)
IccLo2
28
-
27
37
46
mA
IccLo3
28
-
SW28=2, Io(PVHFL) or
Io(PVHFH)=20mA
SW28=2, Io(PFMST) or
Io(PUHF)=5mA
15
20
25
mA
Item
Rev.1.3 Jun 14, 2004 page 14 of 27
min
Limits
typ max
Unit
Note
M61140FP
Mixer and OSC Block
(Ta=25°C, Vcc=5.0V otherwise noted.)
Symbol
Measure
point
Input
SG
Condition switches set
to position "1" unless
otherwise noted
Conversion gain1
Conversion gain2
GvcV1
GvcV2
35,16
35,16
-
fRF=55.25MHz, CW
fRF=361.25MHz, CW
20
20
23
23
26
26
dB
dB
NF1
NF2
NFV1
NFV2
35
35
-
fRF=55.25MHz, CW
fRF=361.25MHz, CW
-
16.5
17.5
18
20
dB
dB
Cross modulation1
CMV1
35
-
-28
-25
-
dBm
Cross modulation2
CMV2
35
-
fd=55.25MHz, CW
fud=fd6MHz,
AM100kHz, 30%
fd=361.25MHz, CW
fud=fd6MHz,
AM100kHz, 30%
-28
-25
-
dBm
CS beat1
CS1
35
-
55
60
-
dBc
CS beat1
CS2
35
-
fp=241.25MHz,
fs=245.75MHz
fc=244.83MHz,
AM100kHz, 30%
fp=241.25MHz,
fs=245.75MHz
fc=244.83MHz,
AM100kHz,30%
55
60
-
dBc
Conversion gain3
Conversion gain4
GvcU3
GvcU4
35
35
-
fRF=367.25MHz, CW
fRF=801.25MHz, CW
27
27
30
30
33
33
dB
dB
NF1
NF2
NFU1
NFU2
35
35
-
fRF=367.25MHz, CW
fRF=801.25MHz, CW
-
11.5
13
13
15
dB
dB
cross
modulation1(-)
CMU1(-)
35
-
-31
-28
-
dBm
cross
modulation1(+)
CMU1(+)
35
-
fd=367.25MHz, CW
fud=fd-6MHz,
AM100kHz, 30%
fd=367.25MHz, CW
fud=fd+6MHz,
AM100kHz, 30%
-37
-34
-
dBm
cross
modulation2(-)
CMU2(-)
35
-
-31
-28
-
dBm
cross
modulation2(+)
CMU2(+)
35
-
fd=801.25MHz, CW
fud=fd-6MHz,
AM100kHz, 30%
fd=801.25MHz, CW
fud=fd+6MHz,
AM100kHz, 30%
-37
-34
-
dBm
CS beat3
CS3
35
-
fp=615.25MHz,
fs=627.75MHz
fc=618.83MHz,
VoIF=-10dBm
55
60
-
dBc
Item
V
H
F
U
H
F
Rev.1.3 Jun 14, 2004 page 15 of 27
min
Limits
typ max
Unit
Note
M61140FP
Mixer and OSC Block
(Ta=25°C,Vcc=5.0V otherwise noted.)
Symbol
Measure
point
Input
SG
6ch beat
INT6ch
35
-
A5ch beat
INTA5ch
35
-
5ch beat
INT5ch
35
-
PSC beat1
PSC183
35
PSC beat2
PSC beat3
PSC366
PSC732
35
35
VHF OSC Power
supply shift
VHF OSC Swon
Drift
∆fosc_v
Item
B
e
a
t
O
S
C
Condition switches set
to position "1" unless
otherwise noted
min
Limits
typ
max
Unit
fp=83.25MHz,
fs=87.75MHz
VoIF=-10dBm
fp=91.25MHz,
VoIF=-10dBm
55
60
-
dBc
60
65
-
dBc
60
65
-
dBc
-
fp1=83.25MHz,
fp=77.25MHz
VoIF=-10dBm
fosc=183MHz
-
-
-85
dBm
-
fosc=366MHz
fosc=732MHz
-
-
-85
-85
dBm
dBm
35
-
∆Vcc=10%
-
-
±500
kHz
∆foscv_t
35
-
VccOn 3sec to 5min
-
-
±500
kHz
VHF OSC C/N1
C/N(V1)
35
-
65
-
-
dBc
VHF OSC C/N2
C/N(V2)
35
-
fp=83.25MHz,
VoIF=-10dBm +/-50kHz
offset
fp=241.25MHz,
VoIF=-10dBm +/-50kHz
offset
65
-
-
dBc
UHF OSC Power
supply shift
UHF OSC Swon
Drift
∆fosc_u
35
-
∆Vcc =10%
-
-
±500
kHz
∆foscu_t
35
-
VccOn 3sec to 5min
55
-
-
kHz
UHF OSC C/N
C/N(U)
35
-
fp=615.25MHz,
VoIF=-10dBm +/-50kHz
offset
65
-
-
dBc
Rev.1.3 Jun 14, 2004 page 16 of 27
Note
M61140FP
PLL Block
(Ta=25°C,Vcc=5.0V otherwise noted.)
Condition switches
set to position "1"
unless otherwise
noted
Symbol
Measure
point
Input
SG
High input voltage
Low input voltage
ViH
ViL
26,27
26,27
-
SW26,27=2
SW26,27=2
High input current
IiH
26,27
-
Low input current
IiL
26,27
-
Low output
voltage
VoSL
27
Leakage current
High input current
IoSLK
ViAH
Low input current
P
O
R
T
C
P
Item
S
D
A
/
S
C
L
S
D
A
A
D
S
V
T
X
i
n
min
Limits
typ
max
Unit
2.3
-
-
Vcc
1.0
V
V
SW25A,26,27=2
Vi=4.0V
SW25A,26,27=2
Vi=0.4V
-
-
10
µA
-
-1
-10
µA
-
SW25A,27=2 Io=3mA
-
-
0.4
V
27
25
-
SW25A,27=2 Vo=5.0V
SW25,25A=2 Vi=5.0V
-
-
10
600
µA
µA
IiAL
25
-
SW25,25A=2 Vi=0.4V
-
-
-200
µA
Output voltage1
Output voltage2
Vop1
Vop2
20,21
15,22
-
SW20,21=2 Io=-25mA
SW15,22=2 Io=-5mA
4.6
4.6
4.8
4.8
-
V
V
Leakage current
IopLK
15 20~22
-
-
-
10
µA
High output
current
IcpH
32
-
SW15,20,21,22=2
output "OFF"
SW32=2 Vo=2.5V
±170
±300
±400
µA
Low output
current
Leakage current
IcpL
32
-
SW32=2 Vo=2.5V
±55
±75
±115
µA
IcpLK
32
-
SW32=2
Vo=2.5V,output "OFF"
-
-
50
nA
Iovt
31
-
SW31=2 Vo=0.5V
-
-
2.0
mA
fxin
29
-
3.2
4.0
4.4
MHz
Rxin
Vixin
29
29,22
SG17
2.0
50
-
600
kΩ
mVp
-p
Tuning drive
output
Operational
frequency of
Crystal OSC
Absolute Value
Sensitivity of
External signal
Rev.1.3 Jun 14, 2004 page 17 of 27
SW29=2,Sine wave
signal input
Data(T2,T1,T0)="01X"
Note
*14
M61140FP
Data input Block
(Ta=25°C,Vcc=5.0V otherwise noted.)
Condition switches set
to position "1" unless
otherwise noted
Input
SG
Symbol
Measure
point
Clock frequency
Bus free time
fSCL
tBUF
26
27
0
1.3
100
-
400
-
kHz
µsec
Data hold time
SCL LOW hold
time
tHDSTA
tLOW
27
26
0.6
1.3
-
-
µsec
µsec
SCL HIGH hold
time
Set up time
tHIGH
26
0.6
-
-
µsec
tSUSTA
26,27
0.6
-
-
µsec
Data hold time
Data set up time
tHDDAT
tSUDAT
26,27
26,27
0
100
-
-
µsec
nsec
Rise time
Fall time
tR
tF
26,27
26,27
-
-
300
300
nsec
nsec
Set up time
tSUSTO
26
0.6
-
-
µsec
Item
min
Limits
typ max
Unit
Note
Timing chart
SDA
tLOW
tBU
tf
tr
tHDSTA
SCL
tHDSTA
[STOP] [START]
condition condition
Rev.1.3 Jun 14, 2004 page 18 of 27
tHDDAT
tHIGH
tSUDAT
tSUSTA
[START]
condition
tSUSTO
[STOP]
condition
M61140FP
VIF Block1
(Ta=25°C, Vcc=5.0V otherwise noted.)
Symbol
Measure
point
Input
SG
Video output level
Sync tip voltage
Vodet
VoSNK
46
46
SG1
SG2
Video S/N
VideoS/
N
BW
46
SG2
1
SG3
Input sensitivity
Max. IF input
VinMIN
VinMAX
1,37,38
1,37,38
SG4
SG5
AGC range
Capture range U
GR
CR-U
46,37,38
Capture range L
Inter modulation
CR-L
IM
D/G
D/P
Item
Condition switches set
to position "1" unless
otherwise noted
min
Limits
typ max
Unit
Note
0.85
1.1
1.15
1.3
1.35
1.5
Vp-p
V
48
50
-
dB
*1
6
7
-
MHz
*2
Vo=-3dB point
Vo=-3dB point
101
45
105
52
-
dBµV
dBµV
*3
*4
GR = VinMAX - Vin MIN
SG9
52
0.6
60
0.8
-
dB
MHz
*5
*6
46,37,38
1
SG9
SG11
1.1
32
1.5
40
-
MHz
dB
*7
*8
DG
DP
1
1
SG12
SG12
-
3
3
5
5
%
deg
Input impedance
Input capacitance
Zin
Yin
37,38
37,38
-
-
2k
5
-
Ω
pF
RF AGC max
voltage
RF AGC min
voltage
V23H
23
SG6
4
4.3
4.6
V
V23L
23
SG7
0
0.3
0.6
V
RFAGC Delay
point
Vi23
23,37,38
SG8
82
85
88
dBµV
Video out freq.
response
5MHz LPF
DC
40MHz
@3pin open
*9
VIF Block2
(Ta=25°C,Vcc=5.0V otherwise noted.)
Condition switches set
to position "1" unless
otherwise noted
Symbol
Measure
point
Input
SG
Freerun frequency
fvco
42
SG17
SW42,29=2,44pin
"GND" Data
(T2,T1,T0="01X")
AFT Sensitivity
µ
42
SG10
AFT high output
voltage
V42H
42
AFT Low output
voltage
AFT center
voltage
V42L
AFT center
voltage
Item
Limits
min
-500
typ
-
max
500
Unit
Note
kHz
*15
@360k/360k 0.1µF
12
24
36
mV/
kHz
*10
SG10
4.3
4.7
5
V
42
SG10
0
0.3
0.7
V
V42C1
42
SG18
frequency=58.75MHz
2.4
2.5
2.6
V
V42C2
42
SG2
frequency=45.75MHz
2.4
2.5
2.6
V
Rev.1.3 Jun 14, 2004 page 19 of 27
M61140FP
SIF Block
(Ta=25°C,Vcc=5.0V otherwise noted.)
Symbol
Measure
point
Input
SG
Condition switches set
to position "1" unless
otherwise noted
min
Audio out level
Audio out THD
VoAF
THDAF
40
40
SG13
SG13
SW3=2 @Pin39:0.22µF
SW3=2 @Pin39:0.22µF
500
-
770
0.4
1040
0.9
mVrms
%
AF S/N
Limiting
sensitivity
AF S/N
LIM
40
3,40
SG16
SG14
SW3=2 @Pin39:0.22µF
SW3=2 S/N=30dB Point
51
-
56
50
55
dB
dBµV
*11
*12
AMR
QIF output
AMR
VoQIF
40
41
SG15
SG16
SW3=2
SW3=2
44
86
50
92
-
dB
dBµV
*13
Item
Limits
typ
max
Note
Unit
Measurement Diagram
Vt
33V
22K
100p
10p
0. 01u
01µ
18K
2200p
0. 1u
1µ
I2C BUS
4MHz
5V
2 1
1
2
2
1
2
2
1
A
SW 29
SW 31
SW 32
1
2
0. 01µ
01u
SW 28
SW 33
1
35
IF 2 GN D
33
IF 2 V cc
VI F Vc c
31
30
29
28
10p
Log ic G N D
27
26
A
Log ic Vcc
38
Bu s
rec eiv er
XO
Char ge
pump
SW 24
0. 01µ
01u
43
0. 1µ
1u
1000p
2
22
APC
SW 46
47p
PS C
1/32, 1/33
IF A G C
DE T
27p
V ba nd in
1n
U
MIX
SW 15
1n
0. 1µ
1u
47
LP F
48
Vr eg
1
UH F
OS C
VH F
OS C
EQ
AMP
15 µ
u
1
2
1n
14
2
21
V
MIX
1
LP F
20
15bit
P. G d ivider
46
V4 6B
50
2.2K
0. 22 µ
200
27p
19
IF
AMP
45
V4 6A
1
0. 01µ
01u 2
RF
AG C
44
SW 44
SW 22
1n
U band in
13
1
AF T
VI F G N D
SW 42
Ph as e
det
QI F
AMP
42
0. 1µ
1u
360K
1
V
2
18
360K
TP 42
2
10K
SW 21 2
0. 01µ
01u
16
5V
1
Coil-les s
VC O
41
1n
Re f
divider
LI M
AMP
7.5K
15
0. 01µ
01u
0. 01u
01µ SW 22
17
40
TP 40
B and driver
0
RF G N D
39
0. 22µ
TP 41
TP 23
0. 1µ
1u
1
FM
det
2
1
25
1n
50
5V
SW 26
32
Video
det
IF a mp
37
VIF in
34
A
V
SW 25
10 n
36
2
2
2
SW 27
47u
47µ
SW 34
0. 01µ
01u
S W25A
2
24
1
TP 35
1
1
M/O Vcc
1
A
1n
5V
A
A
23
5V
OS C GN D
2
3
4
5
6
7
8
9
10
11
12
330
5p
0. 01µ
01u
10K
5p
5p
68
56p
0. 022µ
022u
SW 3
2200p
1n
10p
TP 4
240
22K
5p
5. 6K
1K
2p
1
0. 5p
10 K
2
100K
2. 7K
1n
2200p
56p
2200p
100K
TP 1
7. 5K
22 µ
u
50
Vt
Rev.1.3 Jun 14, 2004 page 20 of 27
2200p
6800p
27K
100K
27K
M61140FP
Input Signal
SG
50ohm termination
1
2
f0=45.75MHz
f0=45.75MHz
Vi=90dBµV
Vi=90dBµV
fm=20kHz
CW
3
4
f1=45.75MHz
f2=Frequency Variable
f0=45.75MHz
Vi=90dBµV
Vi=70dBµV
Level Variable
CW
CW
fm=20kHz
5
6
f0=45.75MHz
f0=45.75MHz
Level Variable
Vi=80dBµV
fm=20kHz
CW
7
8
f0=45.75MHz
f0=45.75MHz
Vi=110dBµV
Level Variable
CW
CW
9
10
f0=Frequency Variable
f0=Frequency Variable
Vi=90dBµV
Vi=90dBµV
fm=20kHz
CW
11
f1=45.75MHz
f2=42.17MHz
f3=41.25MHz
Vi=90dBµV
Vi=80dBµV
Vi=80dBµV
CW
CW
CW
12
f0=45.75MHz
TV moduration=87.5%
13
f0=4.5MHz
Sync Tip Level 90dBµ
10 stair-steps waveform
Vi=90dBµV
fm=1kHz
+/- 25kHz dev
14
15
f0=4.5MHz
f0=4.5MHz
Level Variable
Vi=90dBµV
fm=1kHz
fm=1kHz
+/- 25kHz dev
AM=30%
16
17
f0=4.5MHz
f0=4.0MHz
Vi=90dBµV
Level Variable
CW
CW
18
f0=58.75MHz
Vi=90dBµV
CW
Rev.1.3 Jun 14, 2004 page 21 of 27
AM=77.8%
mixed signal
AM=77.8%
AM=14.0%
AM=77.8%
mixed signal
M61140FP
Measurement of Electrical Characteristic Notes
1. Video S/N
Input SG2 to VIF IN and measure the video out (Pin 46) noise in r.m.s. at TP46B through a 5MHz (-3dB) L.P.F.
S/N=20log
0.7xVodet
NOISE
(dB)
2. Video Band Width
1. Measure the 1MHz component level of Video output TP1 with a spectrum analyzer when SG3 (f2=44.75MHz)
is input to VIF IN. At that time, measure the voltage at TP44 with SW8, set to position 2, and then fix V8 at that
voltage.
2. Reduce f2and measure the value of (f2-f1) when the (f2-f1) component level reaches -3dB from the 1MHz
component level as shown below.
Video det out
-3dB
1MHz
BW
(f2-f1)
3. Input sensitivity
Input SG4 (Vi=90dBµ) to VIF IN , and then gradually reduce Vi and measure the input level when the 20kHz
component of Video output TP46A reaches -3dB from Vo det level.
4. Maximum Allowable Input
1. Input SG5 (Vi=90dBµ) to VIF IN, and measure the level of the 20kHz component of Video output.
2. Gradually increase the Vi of SG and measure the input level when the output reaches -3dB.
5. AGC control Range
GR=VinMAX-VinMIN (dB)
6. Capture range U
1. Increase the frequency of SG9 until the VCO is out of locked-oscillation
2. And decrease the frequency of SG9 and measure the frequency fU when the VCO is locked.
CR-U=fU-45.75 (MHz)
7. Capture range L
1. Decrease the frequency of SG9 until the VCO is out of locked-oscillation.
2. And increase the frequency of SG9 and measure the frequency fL when the VCO is locked.
CR-L=45.75-fL (MHz)
8. Inter modulation
1. Input SG11 to VIF IN, and measure video output TP9 with an oscilloscope.
2. Adjust AGC filter voltage V44 so that the minimum DC level of the output waveform is 1.5V.
3. At that time, measure TP1 with a spectrum analyzer The inter modulation is defined as a difference between
0.92MHz and3.58 MHz frequency components.
9. RF AGC Operating Voltage:
Input SG8 to VIF IN and gradually reduce Vi and then measure the input level when RF AGC output reaches
1/2Vcc, as shown below.
V23
V23H
1/2Vcc
V23L
Vi
Rev.1.3 Jun 14, 2004 page 22 of 27
M61140FP
10. AFT sensitivity, Maximum AFT voltage, Minimum AFT voltage
1. Input SG10 to VIF IN, and set the frequency of SG10 so that the voltage of AFT output TP42 is 3(V).
This frequency is named f(3).
2. Set the frequency of SG10 so that the AFT output voltage is 2(V). This frequency is named f(2).
3. IN the graph shown below, maximum and minimum DC voltage are V42H and V42L, respectively.
V42
µ=
1000mV
f(2)-f(3) (KHz)
V42H
3V
(mV/KHz)
2V
V42L
f(2)
f(3)
11. AF S/N
1. Input SG19 to LIM IN, and measure the output noise level of Audio output (TP40). This level is named VN.
S/N=20log
VoAF
VN
(dB)
12. Limiting Sensitivity
1. Input SG14 to LIM IN, and measure the 1kHz component level of AF output TP40.
2. Input SG17 to LIM IN, and measure the noise level of AF output TP40 .
3. The input limiting sensitivity is defined as the input level when the difference between each 1kHz components of
audio output (TP40) is 30dB, as shown below.
AF
Audio output while SG14 is input.
30dB
Audio output while SG17 is input.
13. AM Rejection
1. Input SG15 to LIM IN, and measure the output level of Audio output (TP40). This level is named VAM.
2. AMR is
AMR=20Log
Vo AF (mVrms)
VAM (mVrms)
(dB)
14. Xin sensitivity of external signal
1. Input data that Control byte data CP,T2,T1,T0 is "0100" and Rsa,Rsa is"01"
2. The Reference frequency is output to Pin 22, measure the frequency with counter.
3. Input sensitivity is defined as the input level when the frequency is less than plus-or-minus 1ppm of 31.25kHz.
15. Freerun frequency
1. Input data that Control byte data CP,T2,T1,T0 is "01X".
2. The Reference frequency is output to Pin 42, measure the frequency with counter.
This frequency is named fmoni.
Freerun frequency (foUS) is 52.9524[MHz] - fmoni x 9 [MHz]
Freerun frequency (foJP) is 65.9512[MHz] - fmoni x 9 [MHz]
Rev.1.3 Jun 14, 2004 page 23 of 27
0. 01µ
Rev.1.3 Jun 14, 2004 page 24 of 27
46
47
48
22µ
3
*4
*21
0.022µ
4
5
Vt
10K
6
7.5K
68
5p
OS C GN D
2200p
2p
8
*6
5p
6800p
2200p
7
*12
9
*8
56p
5p
10
100K
*11
5p
1n
27K
0.5p
10p
11
*7
12
*10
100K
*7
13
56p
2
UH F
OS C
U
MIX
V
MIX
25
14
RF A GC
delay
0. 1µ
V ideo
det
Vr eg
VH F
OS C
Bu s
rec eiv er
26
RF GND
*3
VI F G N D
240
IF a mp
1
LP F
PS C
1/32, 1/33
15bit
P.G d ivider
IF
AMP
27
A DS
15
330
45
15µ
44
16
EQ
AMP
IF A G C
DE T
28
Log ic V cc
B and dr iver
0. 1µ
27K
43
0.22 µ
RF
AG C
Ph as e
det
Re f
divider
XO
29
S CL
17
47p
30
Log ic G ND
SD A
*13
5V
to MO D
18
200
0. 1µ
42
APC
AF T
Co il-les s
VC O
31
Ch arge
pump
32
0. 01µ
10 p
19
1000p
41
360K
33
VI F V cc
*5
M/ O V cc
V ideo out
0. 1µ
40
QI F
AMP
34
0. 1µ
*1
20
AF T out
39
LI M
AMP
FM
det
35
0. 01µ
47 µ
2200p
Re f in ( 4MHz )
21
360K
38
5V
7.5K
36
IF 2 G ND
0. 01µ
*14
18K
5V
100p
22
0. 01µ
37
23
0.22µ
1n
*15
1n
0. 01µ
5V
Vt
22K
*20
24
1. 5K for J AP A N mode
A udio out
QI F out
1n
*2
SA W
33 V
0. 01µ
27K
27p
27p
5. 6K 1K
2200p
0. 01µ
*9
50
*17
*18
2200p
2. 7K
1n
1n
*16
1n
0. 01µ
2.2K
0. 01µ
0. 01µ
*19
5V
0. 1µ
100K
U ban d in
PU H F
V ba nd in
PV HF H
PV HFL
PF MS T
RF A GC o ut
M61140FP
Application Example
M61140FP
Application Note
*1
*2
*3
*4
*5
*6,7
*8
*9
*10
*11
*12
*13,14
*15
*16-19
*21
2SC2643 equivalent made by Renesas
45.75MHz SAW Filter made by EPCOS
4.5MHz Trap: TPSRA4M50B00 made by Murata
4.5MHz B.P.F.: SFSRA4M50EF00 made by Murata
HC-49/U equivalent made by Daishinku. Load capacitance=20pF,Motinal resistance: Less 300 Ω
HVC306B, HVC306C equivalent made by Renesas
HSC277 equivalent made by Renesas
0.1mm 3mm φ 6t x2 P886ANS-0194VN made by TOKO
0.5mm 2.4mm φ 1.5t
0.5mm 2.4mm φ 2.5t
0.5mm 2.4mm φ 8.5t
The bypass capacitor of Vcc is arranged near the LogicGND pin.
In order to mitigate the surroundings lump by the VIF input, the balanced connection from a SAW filter to
the VIF input pin of 37.38 recommends a putter which serves as a 1t coil by Tip C or the jumper.
In order to stop digital beat which goes via the port output from Logic Vcc, bypass capacitor arranged near
the port output pin.
It is high impedance. keep away from VideodetOUT and EQ F/B pin.
Notes about the handling of IC
*20
*
The direct power supply impression to Vt terminal is forbidden. When power supply impression is required,
please impress through the resistance for current restrictions. Depending on the case, it is drive current from
31 pin, and excessive collector current flows and breaks to an external transistor.
Because there is a possibility of also destroying IC by the destruction.
Since this IC is using the detailed process, be careful of serge enough.
Especially careful 1,7,8,9,10,25,26,27,32,48 pins.
Rev.1.3 Jun 14, 2004 page 25 of 27
M61140FP
Application Board Example
Rev.1.3 Jun 14, 2004 page 26 of 27
M61140FP
Package Dimensions
JEITA Package Code
RENESAS Code
Previous Code
P-LQFP48-7x7-0.50
PLQP0048KB-A
48P6Q-A
MASS[Typ.]
0.2g
HD
*1
D
36
25
37
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
24
bp
c
c1
*2
E
HE
b1
Reference
Symbol
48
13
1
ZE
Terminal cross section
Nom
D
6.9
7.0
7.1
E
6.9
7.0
7.1
A2
12
c
A
A2
F
1.4
8.8
9.0
9.2
HE
8.8
9.0
9.2
A1
0
0.1
0.2
bp
0.17
0.22
0.27
0.09
0.145
A1
1.7
0.20
b1
c
L
0°
e
y
*3
bp
Detail F
x
0.08
y
0.10
0.75
ZD
0.75
ZE
L1
Rev.1.3 Jun 14, 2004 page 27 of 27
8°
0.5
x
L
0.20
0.125
c1
L1
e
Max
HD
A
Index mark
ZD
Dimension in Millimeters
Min
0.35
0.5
1.0
0.65
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