GENLINX ™II GS9035A Serial Digital Reclocker DATA SHEET DESCRIPTION • adjustment-free operation The GS9035A is a high performance clock and data recovery IC designed for serial digital data. The GS9035A receives either single-ended or differential PECL data and outputs differential PECL clock and retimed data signals. • auto-rate selection for 5 SMPTE data rates: 143, 177, 270, 360, 540Mb/s • data rate indication output The GS9035A can operate in either auto or manual rate selection mode. In auto mode the GS9035A is ideal for multi-rate serial data protocols such as SMPTE 259M. In this mode the GS9035A automatically detects and locks onto the incoming data signal. For single rate data systems, the GS9035A can be configured to operate in manual mode. In both modes, the GS9035A requires only one external resistor to set the VCO centre frequency and provides adjustment-free operation. • serial data output mute when PLL is not locked • immune to harmonic locking • operation independent of SAV/EAV sync signals • low jitter, low power • single external VCO resistor for operation with five input data rates • large input jitter tolerance: typically 0.45 UI beyond loop bandwidth • power savings mode (output serial clock disable) The GS9035A has dedicated pins to indicate LOCK and data rate. In addition, an internal muting function forces the serial data outputs to a static state when input data is not present or when the PLL is not locked. The serial clock outputs can also be disabled resulting in a 10% power savings. • system friendly: serial clock remains active when data outputs muted • robust lock detect • Pb-free and Green APPLICATIONS The GS9035A is packaged in a 28 pin PLCC and operates from a single +5 or -5 volt power supply. The GS9035A is used for Clock and Data recovery, and Jitter elimination for all high speed serial digital interface applications involving SMPTE 259M and other data standards. ORDERING INFORMATION PART NUMBER PACKAGE TEMPERATURE Pb-FREE AND GREEN GS9035ACPJ 28 pin PLCC 0°C to 70°C No GS9035ACTJ 28 pin PLCC Tape 0°C to 70°C No GS9035ACPJE3 28 pin PLCC 0°C to 70°C Yes GS9035ACTJE3 28 pin PLCC Tape 0°C to 70°C Yes COSC LOCK CARRIER DETECT PHASELOCK LOGIC HARMONIC SDO FREQUENCY ACQUISITION SDO 2 DDI/DDI CLK_EN PHASE DETECTOR SCO SCO 3 BIT COUNTER DIVISION SMPTE AUTO/MAN CHARGE PUMP DECODER VCO SSO SS1 SS2 LF+ LFS LF- CBG RVCO BLOCK DIAGRAM Revision Date: June 2004 Document No. 522 - 41 - 08 GENNUM CORPORATION P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3 Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946 E-mail: [email protected] www.gennum.com GS9035A FEATURES ABSOLUTE MAXIMUM RATINGS PARAMETER VALUE Supply Voltage (VS) 5.5V VCC + 0.5 to VEE - 0.5V Input Voltage Range (any input) 0°C ≤ TA ≤ 70°C Operating Temperature Range Lead Temperature (soldering, 10 sec) GS9035A -65°C ≤ TS ≤ 150°C Storage Temperature Range 260°C DC ELECTRICAL CHARACTERISTICS VCC = 5.0V, VEE = 0V, TA = 0° – 70°C unless otherwise stated, RLF = 1.8K, CLF1 = 15nF, CLF2 = 3.3pF. PARAMETER CONDITION MIN TYPICAL 4.75 CLK_EN = 0 CLK_EN = 1 1 UNITS 5.00 5.25 V 3 - 90 110 mA 3 - 105 120 mA 3 VEE + (VDIFF/2) 0.4 to 4.6 VCC - (VDIFF/2) V 200 800 2000 mV 3 High 2.0 - - V 3 Low - - 0.8 High 2.5 - - V 3 Low - - 0.8 LOCK Output Low Voltage ΙOH = 500µA - 0.25 0.4 V SS{2:0} Output Voltage HIGH, ΙOH = -180µA, Auto Mode 4.4 4.8 - V 1 - 0.3 0.4 HIGH, Manual Mode 2 - - V 3 LOW, ManualMode - - 0.8 Low, VIL = 0V - 26 55 µA 1 Supply Voltage Supply Current DDI/DDI Common Mode Input Voltage Range DDI/DDI Differential Input Drive AUTO/MAN, SMPTE CLK_EN Input Voltage LOW, ΙOL = 600µA, NOTES TEST LEVEL MAX 2 3 3 1 Auto Mode SS{2:0} Input Voltage CLK_EN Source Current NOTES TEST LEVELS 1. TYPICAL - measured on EB-RD35A board. 1. Production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges. 2. VDIFF is the differential input signal swing. 3. LOCK is an open collector output and requires an external pull-up resistor. 4. Pins SS[2:0] are outputs in AUTO mode and inputs in MANUAL mode. 2. Production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges using correlated test. 3. Production test at room temperature and nominal supply voltage. 4. QA sample test. 5. Calculated result based on Level 1,2, or 3. 6. Not tested. Guaranteed by design simulations. 7. Not tested. Based on characterization of nominal parts. 2 of 14 GENNUM CORPORATION 522 - 41 - 08 AC ELECTRICAL CHARACTERISTICS VCC = 5.0V, VEE = 0V, TA = 0° – 70°C unless otherwise stated, RLF = 1.8K, CLF1 = 15nF, CLF2 = 3.3pF PARAMETER CONDITION Serial Data Rate SDI Intrinsic Jitter TYPICAL1 MAX UNITS 143 - 540 Mb/s See Figure 6 ps p-p 2 4 See Figure 7 ps p-p 2 3 UI p-p 3 9 4 7 - 185 540Mb/s - 164 Intrinsic Jitter 270Mb/s - 462 Pathological (SDI checkfield) 360Mb/s - 308 540Mb/s - 260 270Mb/s 0.40 0.56 - 540Mb/s - 1) Input Jitter Tolerance NOTES 3 0.35 0.43 - tSWITCH < 0.5µs, 270Mb/s - 1 - µs 0.5µs < tSWITCH < 10ms - 1 - ms tSWITCH > 10ms - 4 - ms Loop Bandwidth = 6MHz at 540 Mb/s - 10 - ms 5 7 SDO MUTE Time 0.5 1 2 µs 6 7 SDO to SCO Synchronization -200 0 200 ps 7 Lock Time Synchronous Switch Lock Time Asynchronous Switch SDO, SCO Output Signal Swing 75Ω DC load 600 800 1000 mV p-p 1 SDO, SCO Rise and Fall Times 20% - 80% 200 300 400 ps 7 NOTES 1. TYPICAL - measured on EB-RD35A board, TA = 25°C. 2. Characterized 6 sigma rms. 3. IJT measured with sinusoidal modulation beyond Loop Bandwidth (at 6.5MHz). 4. Synchronous switching refers to switching the input data from one source to another source which is at the same data rate (ie: line 10 switching for component NTSC). 5. Asynchronous switching refers to switching the input data from one source to another source which is at a different data rate. 6. SDO MUTE Time refers to the response of the SDO output from valid re-clocked input data to mute mode when the input signal is removed. TEST LEVEL 1. Production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges. 2. Production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges using correlated test. 3. Production test at room temperature and nominal supply voltage. 4. QA sample test. 5. Calculated result based on Level 1,2, or 3. 6. Not tested. Guaranteed by design simulations. 7. Not tested. Based on characterization of nominal parts. 8. Not tested. Based on existing design/characterization data of similar product. 9. Indirect test 3 of 14 GENNUM CORPORATION 522 - 41 - 08 GS9035A 270Mb/s 23 Psuedorandom (2 TEST LEVEL MIN TEKTRONIX GIGABERT 1400 CLK GENNUM TEST BOARD DI TEKTRONIX CH-1 TRIG CSA803 SDO DATA DI GS9035A PATTERN 223-1 Fig. 1 Jitter Measurement Test Setup LOCK COSC VEE CLK_EN VEE 4 3 2 1 28 27 VCC3 SMPTE PIN CONNECTIONS 26 DDI 5 25 SDO DDI 6 24 SDO VEE 7 23 SCO VEE 8 22 SCO VCC1 9 21 SSO 10 20 SS1 19 SS2 13 14 15 16 17 LF- RVCO_RTN RVCO CBG 18 VCC2 11 12 LFS VEE LF+ AUTO/MAN GS9035A TOP VIEW PIN DESCRIPTIONS NUMBER SYMBOL TYPE DESCRIPTION 1,7,8,11,27 VEE I Most negative power supply connection. 2 COSC I Timing control capacitor for internal system clock. 3 LOCK O Lock indication. When HIGH, the GS9035A is locked. LOCK is an open collector output and requires an external 10k pullup resistor. 4 SMPTE I SMPTE/Other rate select. 5, 6 DDI/DDI I Digital data input (Differential ECL/PECL). 9 VCC1 I Most positive power supply connection. 10 AUTO/MAN I Auto or Manual mode select. TTL/CMOS compatible input. 12 LF+ I Loop filter component connection. 13 LFS I Loop filter component connection. 14 LF- I Loop filter component connection. 15 RVCO_RTN I RVCO return. 4 of 14 GENNUM CORPORATION 522 - 41 - 08 PIN DESCRIPTIONS (continued) SYMBOL TYPE DESCRIPTION 16 RVCO I Frequency setting resistor. 17 CBG I Internal bandgap voltage filter capacitor. 18 VCC2 I Most positive power supply connection. 19 - 21 SS[2:0] I/O Data rate indication (Auto mode) or data rate select (Manual mode). TTL/CMOS compatible I/O. In auto mode these pins can be left unconnected. 22, 23 SCO/SCO O Serial clock output. SCO/SCO are differential current mode outputs and require external 75Ω pullup resistors. 24, 25 SDO/SDO O Serial data output. SDO/SDO are differential current mode outputs and require external 75Ω pullup resistors. 26 VCC3 I Most positive power supply connection. 28 CLK_EN I Clock enable. When HIGH, the serial clock outputs are enabled. TYPICAL PERFORMANCE CURVES (VS = 5V, TA = 25°C unless otherwise shown.) 23 23 Fig. 4 Intrinsic Jitter (2 -1 Pattern) 270Mb/s Fig. 2 Intrinsic Jitter (2 -1 Pattern) 30Mb/s Fig. 5 Intrinsic Jitter (223-1 Pattern) 540Mb/s 23 Fig. 3 Intrinsic Jitter (2 -1 Pattern) 143Mb/s 5 of 14 GENNUM CORPORATION 522 - 41 - 08 GS9035A NUMBER 2000 0.600 143Mb/s 1800 0.550 177Mb/s 1600 360Mb/s 0.450 1200 IJT (UI) 1000 800 0.400 540Mb/s GS9035A JITTER (ps) 270Mb/s 0.500 1400 0.350 600 Typical Range, Characterized 0.300 400 Max Typical Min 200 0 100 200 300 400 500 0.250 0.200 600 SDI DATA RATE (Mb/s) 0 10 20 30 40 50 60 70 TEMPERATURE (C˚) TA=0 to 70˚C, VCC=4.75 to 5.25V for the typical range Fig. 6 Intrinsic Jitter - Pseudorandom (2 23 Fig. 9 Typical IJT vs. Temperature (VCC=5.0V) (Characterized) -1) DETAILED DESCRIPTION 2000 The GS9035A receives either a single-ended or differential PECL serial data stream at the DDI and DDI inputs. It locks an internal clock to the incoming data and outputs the differential PECL retimed data signal and recovered clock on outputs SDO/SDO and SCO/SCO respectively. The timing between the input, output, and clock signals is shown below. 1800 1600 JITTER (ps p-p) 1400 1200 1000 800 600 400 Max Typical Min DDI 200 Typical Range, Characterized 0 100 200 300 400 500 SDO 600 SDI DATA RATE (Mb/s) TA = 0 to 70˚C, VCC = 4.75 to 5.25V for the typical range SCO 50% Fig. 7 Intrinsic Jitter - Pathological SDI Checkfield Fig. 10 Input/Output Clock Signal Timing 0.6 0.4 The GS9035A reclocker contains four main functional blocks: the Phase Locked Loop, Auto/Manual Data Rate Select, Frequency Acquisition, and Logic Circuit. 0.3 1. PHASE LOCKED LOOP (PLL) IJT (UI) 0.5 The Phase Locked Loop locks the internal PLL clock to the incoming data rate. A simplified block diagram of the PLL is shown below. The main components are the VCO, the phase detector, the charge pump, and the loop filter. 0.2 0.1 0 100 200 300 400 500 600 DATA RATE (Mb/s) TA = 0 to 70˚C, VCC = 4.75 to 5.25V Fig. 8 Typical Input Jitter Tolerance (Characterized) 6 of 14 GENNUM CORPORATION 522 - 41 - 08 DDI/DDI VCO When the input data stream is removed for an excessive period of time (see AC electrical characteristics table), the VCO frequency can drift from the previously locked frequency up to the maximum shown in Table 1. PHASE DETECTOR INTERNAL PLL CLOCK CHARGE PUMP LFS LF+ LF- TABLE 1: Frequency Drift Range (when PLL loses lock) RVCO LOOP FILTER RLF CLF1 CLF2 LOSES LOCK FROM MIN (%) MAX(%) 143Mb/s lock -21 21 177Mb/s lock -12 26 270Mb/s lock -13 28 360 Mb/s lock -13 24 540 Mb/s lock -13 28 Fig. 11 Simplified Diagram of the PLL 1.1 VCO The VCO is a differential low phase noise, factory trimmed design that provides increased immunity to PCB noise and precise control of the VCO center frequency. The VCO operates between 30 and 540Mb/s and has a pull range of -13 +25% about the center frequency depending on the signal data rate. A single low impedance external resistor, RVCO, sets the VCO center frequency (see Figure 12). The low impedance RVCO minimizes thermal noise and reduces the PLL's sensitivity to PCB noise. For a given RVCO value, the VCO can oscillate at one of two frequencies. When SMPTE = SS0 = logic 1, the VCO center frequency corresponds to the ƒL curve. For all other SMPTE/SS0 combinations, the VCO center frequency corresponds to the ƒH curve (ƒH is approximately 1.5 x ƒL). 800 VCO FREQUENCY (MHz) 700 1.2 Phase Detector The phase detector compares the phase of the PLL clock with the phase of the incoming data signal and generates error correcting timing pulses. The phase detector design provides a linear transfer function between the input phase and output timing pulses maximizing the input jitter tolerance of the PLL. 1.3 Charge Pump The charge pump takes the phase detector output timing pulses and creates a charge packet that is proportional to the system phase error. A unique differential charge pump design ensures that the output phase does not drift when data transitions are sparse. This makes the GS9035A ideal for SMPTE 259M applications where pathological signals have data transition densities of 0.05. 600 1.4 Loop Filter 500 400 The loop filter integrates the charge pump packets and produces a VCO control voltage. The loop filter is comprised of three external components which are connected to pins LF+, LFS, and LF-. The loop filter design is fully differential giving the GS9035A increased immunity to PCB board noise. ƒH 300 200 ƒL 100 SMPTE=1 SSO=1 0 0 200 400 600 800 1000 1200 1400 1600 1800 RVCO (Ω) Fig. 12 VCO Frequency vs. RVCO The recommended RVCO value for auto rate SMPTE 259M applications is 365Ω. The loop filter components are critical in determining the loop bandwidth and damping of the PLL. Choosing these component values is discussed in detail in the PLL Design Guidelines section. Recommended values for SMPTE 259M applications are shown in the Typical Application Circuit diagram. 7 of 14 GENNUM CORPORATION 522 - 41 - 08 GS9035A DIVISION The VCO and an internal divider generate the PLL clock. Divider moduli of 1, 2, and 4 allow the PLL to lock to data rates from 143Mb/s to 540Mb/s. The divider modulus is set by the AUTO/MAN, SMPTE, and SS[2:0] pin (see Auto/Manual Data Rate Select section for further details). In addition, a manually selectable modulus 8 divider allows operation at data rates as low as 30Mb/s. 2 2. FREQUENCY ACQUISITION 4. AUTO/MANUAL DATA RATE SELECT The core PLL is able to lock if the incoming data rate and the PLL clock frequency are within the PLL capture range (which is slightly larger than the loop bandwidth). To assist the PLL to lock to data rates outside of the capture range, the GS9035A uses a frequency acquisition circuit. The GS9035A can operate in either auto or manual data rate select mode. The mode of operation is selected by a single input pin (AUTO/MAN). tsys tswp VLF In auto mode, the GS9035A uses a 3-bit counter to automatically cycle through five (SMPTE=1) or three (SMPTE=0) different divider moduli as it attempts to acquire lock. In this mode, the SS[2:0] pins are outputs and indicate the current value of the divider moduli according to Table 2. Note that for SMPTE = 0 and divider moduli of 2 and 4, the PLL can correctly lock for two values of SS[2:0]. TABLE 2: Data Rate Indication in Auto Mode AUTO/MAN = 1 (Auto Mode) ƒH, ƒL = VCO center frequency as per Figure 12 A Tcycle SMPTE SS[2:0] DIVIDER MODULI PLL CLOCK Fig. 13 Typical Sweep Form 1 000 4 ƒH/4 The VCO frequency starts at point A and sweeps up attempting to lock. If lock is not established during the up sweep, the VCO is then swept down. The system is designed such that the probability of locking within one cycle period is greater than 0.999. If the system does not lock within one cycle period, it will attempt to lock in the subsequent cycle. In manual mode, the divider modulus is fixed for all cycles. In auto mode, each subsequent cycle is based on a different divider moduli as determined by the internal 3-bit counter. 1 001 2 ƒL/2 1 010 2 ƒH/2 1 011 1 ƒL 1 100 1 ƒH 1 101 - - 1 110 - - 1 111 - - 0 000 4 ƒH/4 The average sweep time, tswp, is determined by the loop filter component, CLF1, and the charge pump current, ΙCP: 0 001 4 ƒH/4 0 010 2 ƒH/2 0 011 2 ƒH/2 0 100 1 ƒH 0 101 - - 0 110 - - 0 111 - - tswp 4 CLF1 = 3 Ι LF1 Tcycle = tswp + tsys [seconds] The nominal sweep time is approximately 121µs when CLF1 = 15nF and ΙCP = 165µA (RVCO = 365Ω). An internal system clock determines tsys (see section 7, Logic Circuit). 3. LOGIC CIRCUIT The GS9035A is controlled by a finite state logic circuit which is clocked by an asynchronous system clock. That is, the system clock is completely independent of the incoming data rate. The system clock runs at low frequencies, relative to the incoming data rate, and thus reduces interference to the PLL. The period of the system clock is set by the COSC capacitor and is tsys = 9.6 x 104 x COSC 4.2 Manual Mode (AUTO/MAN = 0) In manual mode, the GS9035A divider moduli is fixed. In this mode, the SS[2:0] pins are inputs and set the divider moduli according to Table 3. [seconds] The recommended value for tsys is 450µs (COSC = 4.7nF). 8 of 14 GENNUM CORPORATION 522 - 41 - 08 GS9035A The frequency acquisition circuit sweeps the VCO control voltage such that the VCO frequency changes from -10% to +10% of the center frequency. Figure 13 shows a typical sweep waveform. 4.1 Auto Mode (AUTO/MAN = 1) 5.1 Lock Time TABLE 3: Data Rate Select in Manual Mode AUTO/MAN = 0 (Manual Mode) ƒH, ƒL = VCO center frequency as per Figure 8 SS[2:0] DIVIDER MODULI PLL CLOCK 1 000 4 ƒH/4 1 001 2 ƒL/2 1 010 2 ƒH/2 1 011 1 ƒL 1 100 1 ƒH 1 101 8 ƒL/8 1 110 8 ƒH/8 1 111 - - 0 000 4 ƒH/4 0 001 4 ƒH/4 0 010 2 ƒH/2 0 011 2 0 100 0 When input data to the GS9035A is removed, the GS9035A latches the current state of the counter (divider modulus). Therefore, when data is reapplied, the GS9035A begins the lock procedure at the previous locked data rate. As a result, in synchronous switching applications, the GS9035A locks very quickly. The nominal lock time depends on the switching time and is summarized in the table below: TABLE 4: Lock Time Relative to Switching Time SWITCHING TIME LOCK TIME <0.5µs 10µs ƒH/2 0.5µs - 10ms 2tsys 1 ƒH > 10ms 2Tcycle + 2tsys 101 1 ƒH 0 110 8 ƒH/8 0 111 - - 5. LOCKING The GS9035A indicates lock when three conditions are satisfied: 1. Input data is detected. 2. The incoming data signal and the PLL clock are phase locked. 3. The system is not locked to a harmonic. The GS9035A defines the presence of input data when at least one data transition occurs every 1µs. The GS9035A assumes that it is NOT locked to a harmonic if the pattern ‘101’ or ‘010’ (in the reclocked data stream) occurs at least once every tsys/3 seconds. Using the recommended component values, this corresponds to approximately 150µs. (In an harmonically locked system, all bit cells are double clocked and the above patterns become ‘110011’ and ‘001100’, respectively.) In asynchronous switching applications (including power up) the lock time is determined by the frequency acquisition circuit as described in section 2, Frequency Acquisition. In manual mode, the frequency acquisition circuit may have to sweep over an entire cycle (depending on initial conditions) to acquire lock resulting in a maximum lock time of 2Tcycle + 2tsys. In auto tune mode, the maximum lock time is 6Tcycle + 2tsys since the frequency acquisition circuit may have to cycle through 5 possible counter states (depending on initial conditions) to acquire lock. The nominal value of Tcycle for the GS9035A operating in a typical SMPTE 259M application is approximately 1.3ms. The GS9035A has a dedicated LOCK output (pin 3) indicating when the device is locked. It should be noted that in synchronous switching applications where the switching time is less than 0.5µs, the LOCK output will NOT be de-asserted and the data outputs will NOT be muted. 5.2 DVB-ASI Design Note: For DVB-ASI applications having significant instances of few bit transitions or when only K28.5 idle bits are transmitted, the wide-band PLL in the GS9035A may lock at 243MHz being the first 27MHz sideband below 270MHz. In this case, when normal bit density signals are transmitted, the PLL will correctly lock onto the proper 270MHz carrier. 9 of 14 GENNUM CORPORATION 522 - 41 - 08 GS9035A SMPTE The lock time of the GS9035A depends on whether the input data is switching synchronously or asynchronously. Synchronous switching refers to the case where the input data is changed from one source to another source which is at the same data rate (but different phase). Asynchronous switching refers to the case where the input data to the GS9035A is changed from one source to another source which is at a different data rate. 6. OUTPUT DATA MUTING PHASE DETECTOR The GS9035A internally mutes the SDO and SDO outputs when the device is not locked. When muted, SDO/SDO are latched providing a logic state to the subsequent circuit and avoiding a condition where noise could be amplified and appear as data. The output data muting timing is shown in Figure 14. Øi + KPD ΙCP VCO 2πKf - Øo Ns RLF CLF1 CLF2 GS9035A LOOP FILTER NO DATA TRANSITIONS DDI Fig. 15 PLL Model LOCK 9.1 Transfer Function SDO VALID DATA OUTPUTS MUTED VALID DATA The transfer function of the PLL is defined as Øo/Øi and can be approximated as sC LF1 R LF + 1 Øo 1 ------- = ---------------------------------------------------------------- --------------------------------------------------------L L 2 Øi s C LF1 R LF – ---------- + 1 s C LF2 L + s --------- + 1 R LF R LF Fig. 14 Output Data Muting Timing 7. CLOCK ENABLE When CLK_EN is high, the GS9035A SCO/SCO outputs are enabled. When CLK_EN is low, the SCO/SCO outputs are set to a high Z state and float to VCC. Disabling the clock outputs results in a power savings of 10%. It is recommended that the CLK_EN input be hard wired to the desired state. For applications which do not require the clock output, connect CLK_EN to Ground and connect the SCO/SCO outputs to VCC. Equation 1 where N L = ------------------DI CP K ƒ N is the divider modulus D is the data density (=0.5 for NRZ data) 8. STRESSFUL DATA PATTERNS All PLL's are susceptible to stressful data patterns which can introduce bit errors in the data stream. PLL's are most sensitive to patterns which have long run lengths of zeros or ones (low data transition densities for a long period of time). The GS9035A is designed to operate with low data transition densities such as the SMPTE 259M pathological signal (data transition density = 0.05). ΙCP is the charge pump current in Amps Kƒ is the VCO gain in Hz/V This response has 1 zero (wZ) and three poles (wP1, wBW, wP2) where 1 w Z = ----------------------C LF1 R LF 9. PLL DESIGN GUIDELINES 1 w P1 = -------------------------------------L C LF1 R LF – --------R LF The performance of the GS9035A is primarily determined by the PLL. Thus, it is important that the system designer is familiar with the basic PLL design equations. R LF w BW = --------L A model of the GS9035A PLL is shown below. The main components are the phase detector, the VCO, and the external loop filter components. 1 w P2 = ---------------------C LF2 R LF The bode plot for this transfer function is plotted in Figure 16. 10 of 14 GENNUM CORPORATION 522 - 41 - 08 The second is the zero-pole combination: 0 AMPLITUDE (dB) s ------- + 1 sC LF1 R LF + 1 wZ ----------------------------------------------------------- = -------------------s-+1 L - + 1 --------s C LF1 R LF – --------- w P1 R LF GS9035A This causes lift in the transfer function given by w P1 1 20 LOG ---------- = 20 LOG --------------------wZ wZ 1 – ----------w BW WZ WBW WP1 WP2 To keep peaking to less than 0.05dB, FREQUENCY wZ < 0.0057 wBW Fig. 16 Bode Plot for PLL Transfer Function The 3dB bandwidth of the transfer function is approximately w 3dB 9.3 Selection of Loop Filter Components Based on the above analysis, select the loop filter components for a given PLL bandwidth, ƒ3dB, as follows: w BW w BW = ---------------------------------------------------------------------- ≈ -----------0.78 w BW ( w BW ⁄ w P2 ) 2 1 – 2 ------------ + --------------------------------w P2 w BW 1 – 2 -----------w P2 1. Calculate where ΙCP is the charge pump current and is a function of the RVCO resistor and is obtained from Figure 17. 9.2 Transfer Function Peaking There are two causes of peaking in the PLL transfer function given by Equation 1. Kƒ = 90MHz/V for VCO frequencies corresponding to the ƒL curve. The first is the quadratic Kƒ = 140MHz/V for VCO frequencies corresponding to the ƒH curve. L s C LF2 L + s --------- + 1 R LF 2 N is the divider modulus. which has (ƒL, ƒH and N can be obtained from Table 2 or Table 3). 1 w O = -------------------C LF2 L C LF2 Q = R LF -----------L and 2. Choose RLF = 2(3.14) ƒ3dB (0.78)L 3. Choose CLF1 = 174 L / (RLF) 2 This response is critically damped for Q = 0.5. 4. Choose CLF2 = L/4(RLF)2 Thus, to avoid peaking: 400 CHARGE PUMP CURRENT (µA) C LF2 1 R LF ------------ < --2 L or 1 - -------L--------------------->4 R LF C LF2 R LF Therefore, wP2 > 4 wBW L= 2N ΙCPKƒ However, it is desirable to keep wP2 as low as possible to reduce the high frequency content on the loop filter. 350 300 250 200 150 100 50 0 0 200 400 600 800 1000 1200 1400 1600 1800 RVCO (Ω) Fig. 17 Charge Pump Current vs. RVCO 11 of 14 GENNUM CORPORATION 522 - 41 - 08 1. Input signal amplitudes are between 200 and 2000mV 9.4 Spice Simulations More detailed analysis of the GS9035A PLL can be done using SPICE. A SPICE model of the PLL is shown below: PHII G1 IN+ PHIO E1 Ns RLF 1 CLF1 R2 examples are shown in Figure 19 illustrates the simplest interface to the GS9035A. In this example, the driving device generates the PECL level signals (800mV amplitudes) having a common mode input range between 0.4 and 4.6V. This scheme is recommended when the trace lengths are less than 1in. The value of the resistors and the DC connection (VCC or Ground), depends on the output driver circuitry of the previous device. 2πKƒ IN- Commonly used interface Figures 19 and 20. CLF2 NOTE: PHII, PHIO, LF and 1 are node names in the SPICE netlist. Fig. 18 SPICE Model of PLL VCC or GND The model consists of a voltage controlled current source (G1), the loop filter components (RLF, CLF1, and CLF2), a voltage controlled voltage source (E1), and a voltage source (V1). R2 is necessary to create a DC path to ground for Node 1. V1 is used to generate the input phase waveform. G1 compares the input and output phase waveforms and generates the charge pump current, ΙCP. The loop filter components integrate the charge pump current to establish the loop filter voltage. E1 creates the output phase waveform (PHIO) by multiplying the loop filter voltage by the value of the Laplace transform (2pKƒ/Ns). The netlist for the model is given below. The .PARAM statements are used to set values for ΙCP, Kƒ, N, and D. ΙCP is determined by the RVCO resistor and is obtained from Figure 17. SPICE NETLIST * GS9035A PLL Model .PARAM ICP = 165E-6 KF= 90E+6 .PARAM N = 1 D = 0.5 .PARAM PI = 3.14 .IC V(Phio) = 0 .ac dec 30 1k 10meg RLF 1 LF 1000 CLF1 1 0 15n CLF2 0 LF 15p E_LAPLACE1 Phio 0 LAPLACE {V(LF)} {(2*PI*KF)/(N*s)} G1 0 LF VALUE{D * ICP/(2*pi)*V(Phii, Phio)} V1 2 0 DC 0V AC 1V R2 0 1 1g .END DDI GS9035A DDI VCC or GND Fig. 19 Simple Interface to the GS9035A When trace lengths become greater than 1in, controlled impedance traces should be used. The recommended interface for differential signals is shown in Figure 20. In this case, a parallel resistor (RLOAD) is placed near the GS9035A inputs to terminate the controlled impedance trace. The value of RLOAD should be twice the value of the characteristic impedance of the trace. Both traces should be in a symmetric arrangement and same physical transmission line dimensions since common-mode signals or common-mode noise is not terminated. In addition, series resistors, RSOURCE, can be placed near the driving chip to serve as source terminations. They should be equal to the value of the trace impedance. Assuming 800mV output swings at the driver, RLOAD =100Ω, RSOURCE =50Ω and ZO = 50Ω. RSOURCE ZO DDI RLOAD RSOURCE GS9035A DDI ZO Fig. 20 Recommended Interface for Differential Signals 10. I/O DESCRIPTION 10.1 High Speed Inputs (DDI/DDI) DDI/DDI are high impedance inputs which accept differential or single-ended input drive. Two conditions must be observed when interfacing to these inputs: Figure 21 shows the recommended interface when the GS9035A is driven single-endedly. In this case, the input must be AC-coupled and a matching resistor (ZO) must be used. 12 of 14 GENNUM CORPORATION 522 - 41 - 08 GS9035A V1 LF 2. The common mode input voltage range is as specified in the DC Characteristics table. DDI ZO GS9035A VCC DDI Fig. 21 Recommended Interface for Single-Ended Driver SDO/SDO and SCO/SCO are current mode outputs that require external pullup resistors (see Figure 22). To calculate the output sink current use the following relationship: GS9035A 75Ω 75Ω 75Ω 75Ω GS9035A 10.2 High Speed Outputs (SDO/SDO and SCO/SCO) SDO SDO SCO SCO Output Sink Current = Output Signal Swing / Pullup Resistor A diode can be placed between Vcc and the pullup resistors to reduce the common mode voltage by approximately 0.7 volts.When the output traces are longer than 1in, controlled impedance traces should be used. The pullup resistors should be placed at the end of the output traces as they terminate the trace in its characteristic impedance (75Ω). VCC Fig. 22 High Speed Outputs with External Pullups TYPICAL APPLICATION CIRCUIT The figure below shows the GS9035A connected in a typical auto rate select SMPTE 259M application. Table 4 summarizes the relevant system parameters. VCC VCC 10k 6 DDI 28 27 26 VEE VEE 1 VCC3 DDI LOCK 5 2 CLK_EN From GS9024 3 SMPTE 4 VCC VCC 4.7n VCC COSC VCC 4 x 75 SDO 25 SDO 24 To GS90201 7 VEE 8 VEE VCC 9 VCC1 SSO 21 VCC 10 AUTO/MAN SS1 20 11 VEE CLF1 1800 15n CBG VCC2 13 RLF RVCO 12 SCO 22 RVCO_RTN LF+ LFS GS9035A TOP VIEW LF- All resistors in ohms, all capacitors in farads, unless otherwise shown. Power supply decoupling capacitors are not shown. See application note "EB9035A" for details on PCB artwork. SCO 23 14 15 16 17 18 RVCO 365 (1%) 0.1µ SS2 19 } To LED Driver (optional) NOTE 1. The 75Ω pullup resistors on SDO/SDO and SCO/SCO are not required when interfacing the GS9035A to the GS9020 since the GS9020 has internal 75Ω resistors. 0.1µ CLF2 3.3p VCC 13 of 14 GENNUM CORPORATION 522 - 41 - 08 TABLE 5: System Parameters RVCO = 365Ω, ƒH = 540MHz, ƒL = 360MHz SS[2:0] DATA RATE (Mb/s) LOOP BANDWIDTH 1 000 143 1.2MHz 1 001 177 1.9MHz 1 010 270 3.0MHz 1 011 360 4.5MHz 1 100 540 6.0MHz GS9035A SMPTE PACKAGE DIMENSIONS 12.573 MAX 12.319 MIN 1.219 x 45 1.067 SEATING PLANE 11.582 MAX 11.430 MIN 1.270 MIN 0.508 12.573 MAX 12.319 MIN 11.582 MAX 11.430 MIN 10.922 MAX 9.906 MIN 3.048 MAX 2.286 MIN 4.572 MAX 4.115 MIN All dimensions in millimetres. 28 pin PLCC (QM) CAUTION ELECTROSTATIC SENSITIVE DEVICES DO NOT OPEN PACKAGES OR HANDLE EXCEPT AT A STATIC-FREE WORKSTATION DOCUMENT IDENTIFICATION REVISION NOTES: DATA SHEET The product is in production. Gennum reserves the right to make changes at any time to improve reliability, function or design, in order to provide the best product possible. Added lead-free and green information. GENNUM CORPORATION MAILING ADDRESS: P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3 Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946 SHIPPING ADDRESS: 970 Fraser Drive, Burlington, Ontario, Canada L7L 5P5 For latest product information, visit www.gennum.com GENNUM JAPAN CORPORATION Shinjuku Green Tower Building 27F, 6-14-1, Nishi Shinjuku, Shinjuku-ku, Tokyo, 160-0023 Japan Tel. +81 (03) 3349-5501, Fax. +81 (03) 3349-5505 GENNUM UK LIMITED 25 Long Garden Walk, Farnham, Surrey, England GU9 7HX Tel. +44 (0)1252 747 000 Fax +44 (0)1252 726 523 Gennum Corporation assumes no responsibility for the use of any circuits described herein and makes no representations that they are free from patent infringement. © Copyright July 1999 Gennum Corporation. All rights reserved. Printed in Canada. 14 of 14 522 - 41 - 08