ICSI IS61C64AH-20J 8k x 8 high-speed cmos static ram Datasheet

IS61C64AH
8K x 8 HIGH-SPEED CMOS STATIC RAM
FEATURES
DESCRIPTION
The ICSI IS61C64AH is a very high-speed, low power,
8192-word by 8-bit static RAM. It is fabricated using ICSI's
• High-speed access time: 15, 20, 25 ns
• Automatic power-down when chip is
deselected
• CMOS low power operation
— 450 mW (typical) operating
— 250 µW (typical) standby
• TTL compatible interface levels
• Single 5V power supply
• Fully static operation: no clock or refresh
required
• Three state outputs
• Two Chip Enables (CE1 and CE2) for
simple memory expansion
high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields
access times as fast as 15 ns with low power consumption.
When CE1 is HIGH or CE2 is LOW (deselected), the device
assumes a standby mode at which the power dissipation can
be reduced down to 250 µW (typical) with CMOS input levels.
Easy memory expansion is provided by using two Chip Enable
inputs, CE1 and CE2. The active LOW Write Enable (WE)
controls both writing and reading of the memory.
The IS61C64AH is packaged in the JEDEC standard 28-pin,
300mil SOJ and 330mil SOP.
FUNCTIONAL BLOCK DIAGRAM
A0-A12
DECODER
256 X 256
MEMORY ARRAY
I/O
DATA
CIRCUIT
COLUMN I/O
VCC
GND
I/O0-I/O7
CE2
CE1
OE
CONTROL
CIRCUIT
WE
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.
Integrated Circuit Solution Inc.
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1
IS61C64AH
PIN CONFIGURATION
28-Pin SOJ and SOP
PIN DESCRIPTIONS
A0-A12
Address Inputs
WE
CE1
Chip Enable 1 Input
26
CE2
CE2
Chip Enable 2 Input
4
25
A8
OE
Output Enable Input
5
24
A9
A4
6
23
A11
WE
Write Enable Input
A3
7
22
OE
I/O0-I/O7
Input/Output
A2
8
21
A10
Vcc
Power
A1
9
20
CE1
GND
Ground
A0
10
19
I/O7
I/O0
11
18
I/O6
I/O1
12
17
I/O5
I/O2
13
16
I/O4
GND
14
15
I/O3
NC
1
28
VCC
A12
2
27
A7
3
A6
A5
TRUTH TABLE
Mode
Not Selected
(Power-down)
Output Disabled
Read
Write
WE
CE1
CE2
OE
I/O Operation
Vcc Current
X
X
H
H
L
H
X
L
L
L
X
L
H
H
H
X
X
H
L
X
High-Z
High-Z
High-Z
DOUT
DIN
ISB1, ISB2
ISB1, ISB2
ICC
ICC
ICC
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
VTERM
TBIAS
TSTG
PT
IOUT
Parameter
Terminal Voltage with Respect to GND
Temperature Under Bias
Storage Temperature
Power Dissipation
DC Output Current (LOW)
Value
–0.5 to +7.0
–55 to +125
–65 to +150
1.0
20
Unit
V
°C
°C
W
mA
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
OPERATING RANGE
Range
Commercial
Industrial(1)
Ambient Temperature
0°C to +70°C
–40°C to +85°C
VCC
5V ± 10%
5V ± 10%
Notes:
1. Industrial supplement specification available upon request.
2
Integrated Circuit Solution Inc.
SR001-B
IS61C64AH
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Symbol
Parameter
Test Conditions
Min.
Max.
Unit
VOH
Output HIGH Voltage
VCC = Min., IOH = –4.0 mA
2.4
—
V
VOL
Output LOW Voltage
VCC = Min., IOL = 8.0 mA
—
0.4
V
VIH
Input HIGH Voltage
2.2
VCC + 0.5
V
VIL
Input LOW Voltage(1)
–0.5
0.8
V
ILI
Input Leakage
GND ≤ VIN ≤ VCC
–2
2
µA
ILO
Output Leakage
GND ≤ VOUT ≤ VCC, Outputs Disabled
–2
2
µA
1
2
3
Note:
1. VIL = –3.0V for pulse width less than 10 ns.
4
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
-15 ns
Min. Max.
-20 ns
Min. Max.
-25 ns
Min. Max.
5
Symbol Parameter
Test Conditions
ICC
Vcc Dynamic Operating
Supply Current
VCC = Max.,
IOUT = 0 mA, f = fMAX
—
135
—
120
—
110
mA
ISB1
TTL Standby Current
(TTL Inputs)
VCC = Max.,
VIN = VIH or VIL
CE1 ≥ VIH or
CE2 ≥ VIL, f = 0
—
20
—
20
—
20
mA
VCC = Max.,
CE1 ≥ VCC – 0.2V,
CE2 ≤ 0.2V,
VIN ≥ VCC – 0.2V, or
VIN ≤ 0.2V, f = 0
—
ISB2
CMOS Standby
Current (CMOS Inputs)
Unit
6
7
6
—
6
—
6
mA
8
Note:
1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
9
10
CAPACITANCE(1,2)
Symbol
Parameter
CIN
Input Capacitance
COUT
Output Capacitance
Conditions
Max.
Unit
VIN = 0V
5
pF
VOUT = 0V
7
pF
11
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: TA = 25°C, f = 1 MHz, Vcc = 5.0V.
Integrated Circuit Solution Inc.
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12
3
IS61C64AH
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
Symbol
-15 ns
Min. Max.
Parameter
-20 ns
Min. Max.
-25 ns
Min. Max.
Unit
tRC
Read Cycle Time
15
—
20
—
25
—
ns
tAA
Address Access Time
—
15
—
20
—
25
ns
tOHA
Output Hold Time
3
—
3
—
3
—
ns
tACE1
CE1 Access Time
—
15
—
20
—
25
ns
tACE2
CE2 Access Time
—
15
—
20
—
25
ns
tDOE
OE Access Time
—
7
—
7
—
9
ns
(2)
OE to Low-Z Output
0
—
0
—
0
—
ns
(2)
OE to High-Z Output
—
6
—
7
—
9
ns
tLZCE1(2) CE1 to Low-Z Output
3
—
3
—
3
—
ns
CE2 to Low-Z Output
3
—
3
—
3
—
ns
CE1 or CE2 to High-Z Output
—
8
—
10
—
12
ns
tPU
CE1 or CE2 to Power-Up
0
—
0
—
0
—
ns
tPD(3)
CE1 or CE2 to Power-Down
—
15
—
20
—
20
ns
tLZOE
tHZOE
(2)
tLZCE2
(2)
tHZCE
(3)
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V
and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. Not 100% tested.
AC TEST CONDITIONS
Parameter
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
and Reference Level
Output Load
Unit
0V to 3.0V
3 ns
1.5V
See Figures 1 and 2
AC TEST LOADS
480 Ω
480 Ω
5V
5V
OUTPUT
OUTPUT
30 pF
Including
jig and
scope
Figure 1.
4
255 Ω
5 pF
Including
jig and
scope
255 Ω
Figure 2.
Integrated Circuit Solution Inc.
SR001-B
IS61C64AH
AC WAVEFORMS
READ CYCLE NO. 1(1,2)
1
t RC
ADDRESS
2
t AA
t OHA
t OHA
DOUT
3
DATA VALID
PREVIOUS DATA VALID
4
READ CYCLE NO. 2(1,3)
5
t RC
ADDRESS
t AA
t OHA
6
OE
t HZOE
t DOE
7
t LZOE
CE1
8
CE2
t ACE1
t ACE2
t LZCE1
t LZCE2
DOUT
HIGH-Z
t HZCE1
t HZCE2
9
DATA VALID
10
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CE1 = VIL, CE2 = VIH.
3. Address is valid prior to or coincident with CE1 LOW and CE2 HIGH transitions.
11
12
Integrated Circuit Solution Inc.
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5
IS61C64AH
WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range)
Symbol
-12 ns
Min. Max.
Parameter
-15 ns
Min. Max.
Min.
-20 ns
Max.
-25 ns
Min. Max.
Unit
tWC
Write Cycle Time
12
—
15
—
20
—
25
—
ns
tSCE1
CE1 to Write End
10
—
12
—
17
—
22
—
ns
tSCE2
CE2 to Write End
10
—
12
—
17
—
22
—
ns
tAW
Address Setup Time to Write End
10
—
12
—
15
—
20
—
ns
tHA
Address Hold from Write End
0
—
0
—
0
—
0
—
ns
tSA
Address Setup Time
0
—
0
—
0
—
0
—
ns
tPWE(4)
WE Pulse Width
8
—
10
—
12
—
15
—
ns
tSD
Data Setup to Write End
8
—
9
—
10
—
12
—
ns
Data Hold from Write End
0
—
0
—
0
—
0
—
ns
WE LOW to High-Z Output
—
6
—
8
—
10
—
12
ns
tLZWE(2) WE HIGH to Low-Z Output
0
—
0
—
0
—
0
—
ns
tHD
(2)
tHZWE
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V
and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of CE1 LOW, CE2 HIGH and WE LOW. All signals must be in valid states to
initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the
rising or falling edge of the signal that terminates the write.
AC WAVEFORMS
WRITE CYCLE NO. 1 (CE Controlled, OE is HIGH or LOW) (1 )
t WC
VALID ADDRESS
ADDRESS
t SCE1
t SCE2
t SA
t HA
CE1
CE2
t AW
t PWE1
t PWE2
WE
t HZWE
DOUT
DATA UNDEFINED
t LZWE
HIGH-Z
t SD
DIN
6
t HD
DATAIN VALID
Integrated Circuit Solution Inc.
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IS61C64AH
AC WAVEFORMS
WRITE CYCLE NO. 2 (OE is HIGH During Write Cycle) (1,2)
1
t WC
ADDRESS
VALID ADDRESS
2
t HA
OE
CE1
3
LOW
HIGH
CE2
t AW
4
t PWE1
WE
t HZWE
t SA
DOUT
t LZWE
5
HIGH-Z
DATA UNDEFINED
t SD
t HD
6
DATAIN VALID
DIN
WRITE CYCLE NO. 3 (OE is LOW During Write Cycle) (1)
7
t WC
ADDRESS
VALID ADDRESS
OE
LOW
CE1
LOW
8
t HA
9
HIGH
CE2
t AW
10
t PWE2
WE
t SA
DOUT
DATA UNDEFINED
t HZWE
t LZWE
HIGH-Z
t SD
DIN
11
t HD
DATAIN VALID
12
Notes:
1. The internal write time is defined by the overlap of CE1 LOW, CE2 HIGH and WE LOW. All signals must be in valid states to
initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the
rising or falling edge of the signal that terminates the write.
2. I/O will assume the High-Z state if OE = VIH.
Integrated Circuit Solution Inc.
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7
IS61C64AH
ORDERING INFORMATION
Commercial Range: 0°C to +70°C
Speed (ns)
Order Part No.
Package
15
IS61C64AH-15J
IS61C64AH-15U
300mil SOJ
330mil SOP
20
IS61C64AH-20J
IS61C64AH-20U
300mil SOJ
330mil SOP
25
IS61C64AH-25J
IS61C64AH-25U
300mil SOJ
330mil SOP
Integrated Circuit Solution Inc.
HEADQUARTER:
NO.2, TECHNOLOGY RD. V, SCIENCE-BASED INDUSTRIAL PARK,
HSIN-CHU, TAIWAN, R.O.C.
TEL: 886-3-5780333
Fax: 886-3-5783000
BRANCH OFFICE:
7F, NO. 106, SEC. 1, HSIN-TAI 5TH ROAD,
HSICHIH TAIPEI COUNTY, TAIWAN, R.O.C.
TEL: 886-2-26962140
FAX: 886-2-26962252
http://www.icsi.com.tw
8
Integrated Circuit Solution Inc.
SR001-B
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