19-4557; Rev 1; 3/11 76V, APD, Bias Output Stage with Current Monitoring The DS1842 integrates the discrete high-voltage components necessary for avalanche photodiode (APD) bias and monitor applications. A switch FET is used in conjunction with an external DC-DC controller to create a boost DC-DC converter. A current clamp limits current through the APD and also features an external shutdown. The device also includes a dual current mirror to monitor the APD current. Applications Features ♦ 76V Maximum Boost Voltage ♦ Switch FET ♦ Current Monitor with a Wide 1µA to 2mA Range, Fast 50ns Time Constant, and 10:1 and 5:1 Ratio ♦ 2mA Current Clamp with External Shutdown ♦ Multiple External Filtering Options ♦ 3mm x 3mm, 14-Pin TDFN Package with Exposed Pad APD Biasing Ordering Information GPON Optical Network Unit and Optical Line Transmission PART TEMP RANGE PIN-PACKAGE DS1842N+ -40°C to +85°C 14 TDFN-EP* DS1842N+T&R -40°C to +85°C 14 TDFN-EP* +Denotes a lead(Pb)-free/RoHS-compliant package. T&R = Tape and reel. *EP = Exposed pad. Pin Configuration appears at end of data sheet. Typical Application Circuit 3.3V LX CBULK DS1842 MIRIN GATE SW GND FB CURRENT MIRROR MIR1 CCOMP R COMP COMP D2 CLAMP CURRENT LIMIT MIR2 EXTERNAL MONITOR MIROUT ROSA DS1875 APD TIA MON3 ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 DS1842 General Description DS1842 76V, APD, Bias Output Stage with Current Monitoring ABSOLUTE MAXIMUM RATINGS Voltage Range on GATE and CLAMP Relative to GND...................................................-0.3V to +12V Voltage Range on MIRIN, MIROUT, MIR1, and MIR2 Relative to GND........................-0.3V to +80V Voltage Range on LX Relative to GND...................-0.3V to +85V Continuous Power Dissipation (TA = +70°C) TDFN (derate 24.4mW/°C above +70°C).................1951.2mW Operating Junction Temperature Range ...........-40°C to +150°C Storage Temperature Range .............................-55°C to +135°C Lead Temperature (soldering, 10s) .................................+300°C Soldering Temperature (reflow) .......................................+260°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. PACKAGE THERMAL CHARACTERISTICS (Note 1) TDFN Junction-to-Ambient Thermal Resistance (θJA) ............41°C/W Junction-to-Case Thermal Resistance (θJC) ...................8°C/W Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial. ELECTRICAL CHARACTERISTICS (TA = -40°C to +85°C, unless otherwise noted.) PARAMETER Switching Frequency FET Capacitance FET Gate Resistance FET On-Resistance SYMBOL f SW C GATE CLX RDSON VGS Switching Current ILX LX Voltage VLX LX Leakage I IL(LX) CLAMP Threshold Maximum MIROUT Current MIR1 to MIROUT Ratio MIR2 to MIROUT Ratio MIR1, MIR2 Rise Time (20%/80%) Shutdown Temperature Leakage on GATE and CLAMP MIN 0 KMIR2 tRC T SHDN 1.2 MHz 90 VGS = 3V, ID = 170mA VGS = 10V, ID = 170mA 4.6 10 3.7 8 pF 22 0 Duty cycle = 10%, f SW = 100kHz VGATE = 0V, VLX = 76V CLAMP = low 11 V 680 mA 80 V +1 μA 0 11 V 2 4 7 V 1.75 2.6 4 mA 10 μA CLAMP = high IMIROUT = 1mA 0.095 0.100 0.105 IMIROUT = 1μA 0.094 0.100 0.106 15V < VMIRIN < 76V IMIROUT = 1mA 0.190 0.200 0.210 IMIROUT = 1μA 0.188 0.200 0.212 15V < VMIRIN < 76V (Note 2) 30 (Note 3) IIL -1 -1 _______________________________________________________________________________________ A/A A/A ns +150 Note 2: Rising MIROUT transition from 10µA to 1mA; VMIRIN = 40V, 2.5kΩ load. Note 3: Guaranteed by design; not production tested. 2 UNITS f SW = 1MHz VCLT KMIR1 MAX 40 VCLAMP IMIROUT TYP VGS = 0V, VDS = 25V RG GATE Voltage CLAMP Voltage CONDITIONS °C +1 μA 76V, APD, Bias Output Stage with Current Monitoring MIRIN CURRENT vs. TEMPERATURE (VMIRIN = 40V, IMIROUT = 250nA) 90 100 4 MIRIN CURRENT (mA) 80 1000 5 DS1842 toc02 DS1842 toc01 100 MIRIN CURRENT (μA) MIRIN CURRENT (μA) 10,000 MIRIN CURRENT vs. TEMPERATURE (VMIRIN = 40V, IMIROUT = 2mA) 70 60 50 40 30 DS1842 toc03 MIRIN vs. MIROUT CURRENT (VMIRIN = 40V) 20 3 2 1 10 0 1 10 100 10,000 1000 -20 0 20 40 60 80 MIROUT CURRENT (μA) TEMPERATURE (°C) MIR ERROR vs. TEMPERATURE (IMIROUT = 1μA) MIR ERROR vs. TEMPERATURE (IMIROUT = 1mA) 100 0 DS1842 toc05 MIR2 0 0 20 80 100 MIR2 0 -1 -2 -2 40 60 80 MIR1 -2 -40 100 -20 0 20 40 60 80 100 10 1 TEMPERATURE (°C) TEMPERATURE (°C) 10,000 DS1842 toc08 5 4 MIR2 1mA 1 1000 MIROUT CLAMP CURRENT vs. TEMPERATURE DS1842 toc07 2 100 MIROUT CURRENT (μA) MIR ERROR vs. MIRIN VOLTAGE IMIROUT (mA) MIR2 1μA ERROR (%) -20 60 MIR1 MIR1 -40 40 1 -1 -1 20 MIR ERROR vs. MIROUT CURRENT ERROR (%) ERROR (%) MIR2 0 2 1 1 -20 -40 TEMPERATURE (°C) 2 DS1842 toc04 2 ERROR (%) 0 -40 DS1842 toc06 10 0 3 2 MIR1 1μA -1 1 MIR1 1mA 0 -2 10 20 30 40 50 60 MIRIN VOLTAGE (V) 70 80 -40 -20 0 20 40 60 80 100 TEMPERATURE (°C) _______________________________________________________________________________________ 3 DS1842 Typical Operating Characteristics (TA = +25°C, unless otherwise noted.) Typical Operating Characteristics (continued) (TA = +25°C, unless otherwise noted.) FET ON-RESISTANCE vs. DRAIN CURRENT FET DRAIN CURRENT vs. DRAIN VOLTAGE VGS = 2.5V VGS = 10V 600 6 VGS = 5V 500 IDS (mA) VGS = 3.0V 5 VGS = 3.6V DS1842 toc10 700 DS1842 toc09 7 RDSON (Ω) DS1842 76V, APD, Bias Output Stage with Current Monitoring VGS = 3.6V 400 VGS = 3.0V 300 200 4 100 VGS = 5V VGS = 2.5V VGS = 10V 3 0 1 10 100 1000 0 IDS (mA) 1 2 3 Pin Description 4 PIN NAME FUNCTION 1 MIR1 Current Mirror Monitor Output, 10:1 Ratio 2 MIR2 Current Mirror Monitor Output, 5:1 Ratio 3 N.C. No Connection. Can be connected to GND for compatibility with the DS1842A. 4, 9–12 N.C. No Connection. Not internally connected. 5 CLAMP 6 GATE FET Gate Connection 7 GND Ground 8 LX 13 MIRIN 14 MIROUT — EP Clamp Input. Disables the current mirror output (MIROUT). 4 DRAIN VOLTAGE (V) Block Diagram LX MIRIN DS1842 CURRENT MIRROR GATE MIR1 MIR2 GND CLAMP CURRENT LIMIT THERMAL SHUTDOWN MIROUT FET Drain Connection. Connect to switching inductor. Current Mirror Input Current Mirror Output. Connect to APD bias pin. Exposed Pad. Connect to ground. _______________________________________________________________________________________ 76V, APD, Bias Output Stage with Current Monitoring CLAMP REF The mirror response time is dominated by the amount of capacitance placed on the output. For burst-mode Rx systems where the fastest response times are required (approximately a 50ns time constant), a 3.3pF capacitor and external op amp should be used to buffer the signal sent to the ADC. For continuous mode applications, a 10nF capacitor is all that is required on the output. Current Clamp Figure 1. Current Clamp from Current Feedback Detailed Description The DS1842 contains discrete high-voltage components required to create an APD bias voltage and to monitor the APD bias current. The device’s mirror outputs are a current that is a precise ratio of the output current across a large dynamic range. The mirror response time is fast enough to comply with GPON Rx burst-mode monitoring requirements. The device has a built-in current-limiting feature to protect APDs. The APD current can also be shut down by CLAMP or thermal shutdown. The internal FET is used in conjunction with a DC-DC boost controller to precisely create the APD bias voltage. Current Mirror The DS1842 has two current mirror outputs. One is a 10:1 mirror connected at MIR1, and the other is a 5:1 mirror connected to MIR2. The mirror output is typically connected to an ADC using a resistor to convert the mirrored current into a voltage. The resistor to ground should be selected such that the maximum full-scale voltage of the ADC is reached when the maximum mirrored current is reached. For example, if the maximum monitored current through the APD is 2mA with a 1V ADC full scale, The DS1842 has a current clamping circuit to protect the APD by limiting the amount of current from MIROUT. There are three methods of current clamping available. 1) Internally Defined Current Limit The device’s current clamp circuit automatically clamps the current when it exceeds ICLAMP. 2) External Shutdown Signal The CLAMP pin can completely shut down the current from MIROUT. The CLAMP pin is active high. 3) Precise Level Set by External Feedback Circuit A feedback circuit is used to control the level applied to the CLAMP pin. Figure 1 shows an example feedback circuit. Thermal Shutdown As a safety feature, the DS1842 has a thermal-shutdown circuit that turns off the MIROUT and MIRIN currents when the internal die temperature exceeds TSHDN. These currents resume after the device has cooled. Switch FET and Diode The DS1842 switching FET is designed to complement the DS1875 controller’s built-in DC-DC boost controller. Other DC-DC converters are also compatible, including the MAX1932. APD biasing of 16V to 76V can be achieved using the DS1842. _______________________________________________________________________________________ 5 DS1842 and the 10:1 mirror is used, then the correct resistor is approximately 5kΩ. If both MIR1 and MIR2 are connected together, the correct resistor is 1.6kΩ. MIR1 76V, APD, Bias Output Stage with Current Monitoring DS1842 Pin Configuration TOP VIEW 1 MIR2 2 N.C. 3 N.C. 4 CLAMP 5 GATE 6 14 MIROUT + MIR1 13 MIRIN 12 N.C. DS1842 11 N.C. Package Information For the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO. 14 TDFN-EP T1433+2 21-0137 90-0063 10 N.C. 9 N.C. 8 LX *EP GND 7 TDFN *EXPOSED PAD. 6 _______________________________________________________________________________________ 76V, APD, Bias Output Stage with Current Monitoring REVISION NUMBER REVISION DATE 0 4/09 Initial release 3/11 Updated the Absolute Maximum Ratings section; added the Package Thermal Characteristics section; changed pin 3 from GND to N.C. in the Pin Description and Pin Configuration 1 DESCRIPTION PAGES CHANGED — 2, 4, 6 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 _____________________ 7 © 2011 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc. DS1842 Revision History