C8051F063 25 MIPS, 64 kB Flash, 16-Bit ADC, 64-Pin Mixed-Signal MCU Analog Peripherals High-Speed 8051 µC Core - Two 16-Bit ADCs - ±1.5 LSB INL; guaranteed no missing codes Programmable throughput up to 1 Msps (each ADC) Configurable as two single-ended or one differential ADC DMA to XRAM or external memory interface Data-dependent windowed interrupt generator - Memory - 10-Bit ADC - Programmable throughput up to 200 ksps 8 external inputs Built-in temperature sensor (±3 °C) - Can synchronize outputs to timers for jitter-free waveform generation Three Comparators Internal Voltage Reference Precision VDD Monitor/Brown-out Detector - On-chip debug circuitry facilitates full speed, non-intrusive in-system debug (no emulator required) Provides breakpoints, single stepping, watchpoints, stack monitor Inspect/modify memory and registers Superior performance to emulation systems using ICE-chips, target pods, and sockets IEEE1149.1 compliant boundary scan Supply Voltage: 2.7 to 3.6 V - TCK TMS TDI TDO Digital Power Boundary Scan Debug HW Reset RST MONEN XTAL1 XTAL2 8 0 5 1 Analog Power JTAG Logic VDD Monitor DAC0 DAC1 VREF VREF2 DAC0 (12-Bit) AVDD ADGND AV+ AGND VREF0 VRGND0 ADC0 1 Msps (16-Bit) AIN0G VBGAP0 CNVSTR0 AVDD ADGND AIN1G CAN 2.0B - Internal programmable 2% oscillator: up to 24.5 MHz External oscillator: Crystal, RC, C, or Clock SMBus SPI Bus PCA Timers 0, 1, 2,3,4 SFR Bus P0, P1, P2, P3 Latches 64 kB FLASH C R O S S B A R ADC1 1 Msps (16-Bit) R E S U L T 1 P1.0/AIN2.0 P2 Drv P2.0 P1.7/AIN2.7 P2.7 CTX CRX 256 byte RAM VREF2 A M 8:1 U X ADC 200 ksps (10-Bit) 4 kB RAM CP0 + - D I F F + + - P4 Latch DMA EMIF Cntrl P5 Latch Addr15-8 P6 Latch Addr7-0 P7 Latch Data Latch Copyright © 2004 by Silicon Laboratories Temp Sensor P2.6 P2.7 P2.2 P2.3 Ctrl Latch - P1 Drv P0.7 CAN 2.0B External Data Memory Bus Σ P0.0 (32 Message Objects) R E S U L T 0 + P0 Drv P3 Drv CP2 AV+ AGND VREF1 VRGND1 VBGAP1 CNVSTR1 Clock Sources CP1 AIN0 AIN1 - 24 port I/O; all are 5 V tolerant Hardware SMBus™ (I2C™ compatible), SPI™, and two UART serial ports available concurrently Programmable 16-bit counter array with 6 capture/compare modules 5 general-purpose 16-bit counter/timers Dedicated watchdog timer; bidirectional reset Real-time clock mode using timers or PCA UART1 C o r e System Clock 25 MHz 2% Internal Oscillator VREF Digital Peripherals UART0 WDT External Oscillator Circuit 32 message objects ”Mailbox" implementation only interrupts CPU when needed 64-Pin TQFP - Temperature Range: –40 to +85 °C Typical operating current: 10 mA at 25 MHz Multiple power saving sleep and shutdown modes VDD VDD VDD DGND DGND DGND AV+ AGND - On-Chip JTAG Debug & Boundary Scan - 4352 bytes data RAM 64 kB Flash; in-system programmable in 1024-byte sectors (1024 bytes are reserved) External parallel data memory interface CAN Bus 2.0B Two 12-Bit DACs - Pipelined instruction architecture; executes 70% of instructions in 1 or 2 system clocks Up to 25 MIPS throughput with 25 MHz system clock Expanded interrupt handler P2.4 P2.5 P4 DRV P5 DRV P6 DRV P7 DRV 6.15.2004 C8051F063 25 MIPS, 64 kB Flash, 16-Bit ADC, 64-Pin Mixed-Signal MCU Selected Electrical Specifications (TA = –40 to +85 C°, VDD = 2.7 V unless otherwise specified) PARAMETER CONDITIONS GLOBAL CHARACTERISTICS Supply Voltage Supply Current (CPU Clock = 25 MHz active) Clock = 1 MHz Clock = 32 kHz; VDD Monitor Enabled Supply Current Oscillator not running; VDD Monitor (shutdown) Disabled Clock Frequency Range 16-BIT A/D CONVERTERS Resolution Integral Nonlinearity Single-ended Mode Differential Mode Differential Nonlinearity Guaranteed Monotonic Signal-to-Noise Plus Fin = 10 kHz, Single-ended Distortion Fin = 10 kHz, Differential Total Harmonic Distortion Fin = 10 kHz, Single-ended Fin = 10 kHz, Differential Spurious-Free Dynamic Fin = 10 kHz, Single-ended Range Fin = 10 kHz, Differential Throughput Rate Input Voltage Range Single-ended (AINn–AINnG) Differential (AIN0–AIN1) Power Supply Current Operating Mode, 1 Msps (each ADC) (AVDD + AV+) Shutdown Mode D/A CONVERTERS Resolution Differential Nonlinearity Output Settling Time MIN TYP 2.7 MAX UNITS 3.6 V mA mA µA µA 25 MHz 18 0.7 20 0.1 DC 16 ±1.5 ±1 ±0.5 86 89 96 103 97 104 ±4 ±2 ±1 1 VREF VREF 0 –VREF 5.5 1 bits LSB LSB LSB dB dB dB dB dB dB Msps V V mA µA 12 ±1 10 LSB LSB µs C8051F060DK Development Kit Package Information D D1 MIN NOM MAX (mm) (mm) (mm) A E1 E - 1.20 A1 0.05 - 0.15 A2 0.95 - 1.05 b 64 PIN 1 DESIGNATOR 1 e A2 A b CAN 2.0B - 0.17 0.22 0.27 D - 12.00 - D1 - 10.00 - e - 0.50 - E - 12.00 - E1 - 10.00 - A1 Copyright © 2004 by Silicon Laboratories 6.15.2004 Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc. Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders