Product Folder Sample & Buy Support & Community Tools & Software Technical Documents LM34926 SNVS847E – JUNE 2012 – REVISED DECEMBER 2014 LM34926 Integrated Secondary-Side Bias Regulator for Isolated DC-DC Converters 1 Features 3 Description • • The LM34926 regulator features all of the functions needed to implement a low-cost, efficient, isolated bias regulator. This high-voltage regulator contains two 100-V N-channel MOSFET switches — a highside buck switch and a low-side synchronous switch. The constant on-time (COT) control scheme employed in the LM34926 requires no loop compensation and provides excellent transient response. The regulator operates with an on-time control that is inversely proportional to the input voltage. This feature allows the operating frequency to remain relatively constant. An intelligent peak current limit is implemented with integrated sense circuit. Other features include a programmable input undervoltage comparator to inhibit operation during low-voltage conditions. Protection features include thermal shutdown and VCC Undervoltage Lockout (UVLO). The LM34926 device is offered in WSON-8 and SO PowerPAD-8 plastic packages. 1 • • • • • • • • • • • • • Wide 7.5-V to 100-V Input Range Integrated 300-mA High-Side and Low-Side Switches No Schottky Required Constant On-Time Control No Loop Compensation Required Ultra-Fast Transient Response Nearly Constant Operating Frequency Intelligent Peak Current Limit Adjustable Output Voltage From 1.225 V Precision 2% Feedback Reference Frequency Adjustable to 1 MHz Adjustable Undervoltage Lockout (UVLO) Remote Shutdown Thermal Shutdown Packages: – WSON-8 – SO PowerPAD™-8 Packages Device Information(1) PART NUMBER LM34926 2 Applications • • PACKAGE BODY SIZE (NOM) HSOP (8) 4.89 mm x 3.90 mm WSON (8) 4.00 mm x 4.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Isolated Telecom Bias Supply Isolated Automotive and Industrial Electronics Typical Application VOUT2 D1 + LM34926 VIN 7.5V-100V CIN 2 + 4 RUV2 RON 3 BST VIN SW RON VCC UVLO FB RUV1 RTN 1 NS COUT2 7 + 8 X1 CBST VOUT1 NP 6 D2 5 + CVCC Rr RFB2 + RFB1 COUT1 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. LM34926 SNVS847E – JUNE 2012 – REVISED DECEMBER 2014 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 4 6.1 6.2 6.3 6.4 6.5 6.6 6.7 4 4 4 4 5 6 6 Absolute Maximum Ratings ..................................... Handling Ratings....................................................... Recommended Operating Ratings............................ Thermal Information .................................................. Electrical Characteristics........................................... Switching Characteristics .......................................... Typical Characteristics .............................................. Detailed Description .............................................. 8 7.1 Overview ................................................................... 8 7.2 Functional Block Diagram ......................................... 8 7.3 Feature Description................................................... 9 7.4 Device Functional Modes........................................ 13 8 Application and Implementation ........................ 14 8.1 Application Information............................................ 14 8.2 Typical Application .................................................. 14 9 Power Supply Recommendations...................... 20 10 Layout................................................................... 20 10.1 Layout Guidelines ................................................. 20 10.2 Layout Example .................................................... 20 11 Device and Documentation Support ................. 21 11.1 Trademarks ........................................................... 21 11.2 Electrostatic Discharge Caution ............................ 21 11.3 Glossary ................................................................ 21 12 Mechanical, Packaging, and Orderable Information ........................................................... 21 4 Revision History Changes from Revision D (December 2013) to Revision E Page • Added Pin Configuration and Functions section, Handling Rating table, Switching Characteristics table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section ..................................................................................................................... 1 • CMS Request No.: C1411181 ................................................................................................................................................ 1 • Changed Thermal Information table ....................................................................................................................................... 4 • Changed Control Overview section ........................................................................................................................................ 9 • Changed Soft-Start Circuit, Isolated Fly-Buck Converter graphics. ..................................................................................... 13 • Deleted Lowest Part Count Isolated Application Schematic ............................................................................................... 19 Changes from Revision C (December 2013) to Revision D • Page Added Thermal Parameters ................................................................................................................................................... 4 Changes from Revision B (March 2013) to Revision C Page • Changed formatting to the TI standard................................................................................................................................... 1 • Changed minimum operating input voltage from 9 V to 7.5 V in Features, Typical Application, Pin Descriptions, Recommended Operating Ratings ........................................................................................................................................ 1 • Added Absolute Maximum Junction Temperature.................................................................................................................. 4 Changes from Revision A (March 2013) to Revision B • Added SW to RTN (100 ns transient) in Absolute Maximum Ratings ................................................................................... 4 Changes from Original (March 2013) to Revision A • 2 Page Page Changed layout of National Data Sheet to the TI standards................................................................................................ 20 Submit Documentation Feedback Copyright © 2012–2014, Texas Instruments Incorporated Product Folder Links: LM34926 LM34926 www.ti.com SNVS847E – JUNE 2012 – REVISED DECEMBER 2014 5 Pin Configuration and Functions 8-Pin HSOP DDA Package Top View RTN 1 VIN 2 8 SW 7 BST 6 VCC 5 FB HSOP UVLO 3 RON 4 Exp Pad 8-Pin WSON NGU Package Top View RTN 1 VIN 2 UVLO 3 RON 4 8 SW WSON-8 Exp Pad 7 BST 6 VCC 5 FB Pin Functions PIN I/O DESCRIPTION APPLICATION INFORMATION NO. NAME 1 RTN – Ground Ground connection of the integrated circuit. 2 VIN I Input Voltage Operating input range is 7.5 V to 100 V. Resistor divider from VIN to UVLO to GND programs the undervoltage detection threshold. An internal current source is enabled when UVLO is above 1.225 V to provide hysteresis. When UVLO pin is pulled below 0.66 V externally, the parts goes in shutdown mode. 3 UVLO I Input Pin of Undervoltage Comparator 4 RON I On-Time Control A resistor between this pin and VIN sets the switch on-time as a function of VIN. Minimum recommended on-time is 100 ns at max input voltage. 5 FB I Feedback This pin is connected to the inverting input of the internal regulation comparator. The regulation level is 1.225 V. 6 VCC O Output from the Internal High Voltage Series Pass Regulator. Regulated at 7.6 V. The internal VCC regulator provides bias supply for the gate drivers and other internal circuitry. A 1.0-μF decoupling capacitor is recommended. 7 BST I Bootstrap Capacitor An external capacitor is required between the BST and SW pins (0.01-μF ceramic). The BST pin capacitor is charged by the VCC regulator through an internal diode when the SW pin is low. 8 SW O Switching Node Power switching node. Connect to the output inductor and bootstrap capacitor. – EP – Exposed Pad Exposed pad must be connected to RTN pin. Connect to system ground plane on application board for reduced thermal resistance. Submit Documentation Feedback Copyright © 2012–2014, Texas Instruments Incorporated Product Folder Links: LM34926 3 LM34926 SNVS847E – JUNE 2012 – REVISED DECEMBER 2014 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings (1) (2) MIN MAX UNIT VIN, UVLO to RTN –0.3 100 V SW to RTN –1.5 VIN + 0.3 V –5 VIN + 0.3 V BST to VCC 100 V BST to SW 13 V SW to RTN (100 ns transient) RON to RTN –0.3 100 V VCC to RTN –0.3 13 V FB to RTN –0.3 5 V 200 °C 150 °C Lead Temperature (3) Maximum Junction Temperature (4) (1) (2) (3) (4) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The RTN pin is the GND reference electrically connected to the substrate. For detailed information on soldering plastic SO PowerPAD package, refer to the Packaging Data Book. Maximum solder time not to exceed 4 seconds. High junction temperatures degrade operating lifetimes. Operating lifetime is derated for junction temperatures greater than 125°C. 6.2 Handling Ratings Tstg Storage temperature range MIN MAX –55 150 °C 2 kV 750 V Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1) V(ESD) (1) (2) Electrostatic discharge Charged device model (CDM), per JEDEC specification JESD22C101, all pins (2) UNIT JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Ratings MIN MAX VIN Voltage 7.5 100 V Operating Junction Temperature (1) –40 125 °C (1) UNIT High junction temperatures degrade operating lifetimes. Operating lifetime is derated for junction temperatures greater than 125°C. 6.4 Thermal Information LM34926 THERMAL METRICS (1) NGU DDA UNIT 8 PINS RθJA Junction-to-ambient thermal resistance RθJC(bot) Junction-to-case (bottom) thermal resistance 3.2 2.4 ΨJB Junction-to-board thermal characteristic parameter 19.2 24.4 RθJB Junction-to-board thermal resistance 19.1 30.6 RθJC(top) Junction-to-case (top) thermal resistance 34.7 37.3 ΨJT Junction-to-top thermal characteristic parameter 0.3 6.7 (1) 4 41.3 41.1 °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report (SPRA953). Submit Documentation Feedback Copyright © 2012–2014, Texas Instruments Incorporated Product Folder Links: LM34926 LM34926 www.ti.com SNVS847E – JUNE 2012 – REVISED DECEMBER 2014 6.5 Electrical Characteristics Typical values correspond to TJ = 25°C. Minimum and maximum limits apply over –40°C to 125°C junction temperature range unless otherwise stated. VIN = 48V unless stated otherwise. See (1). PARAMETER TEST CONDITIONS MIN TYP MAX 6.25 7.6 8.55 UNIT VCC SUPPLY VCC Reg VCC Regulator Output VIN = 48 V, ICC = 20 mA VCC Current Limit VIN = 48 V (2) VCC UVLO Threshold (VCC increasing) 26 4.15 VCC UVLO Hysteresis V mA 4.5 4.9 300 V mV VCC Drop Out Voltage VIN = 8 V, ICC = 20 mA 2.3 V IIN Operating Current Nonswitching, FB = 3 V 1.75 mA IIN Shutdown Current UVLO = 0 V 50 225 µA UNDERVOLTAGE SENSING FUNCTION UV Threshold UV Rising 1.19 1.225 1.26 V UV Hysteresis Input Current UV = 2.5 V –10 –20 -29 µA Remote Shutdown Threshold Voltage at UVLO Falling 0.32 0.66 V 110 mV Remote Shutdown Hysteresis REGULATION AND OVERVOLTAGE COMPARATORS FB Regulation Level Internal Reference Trip Point for Switch ON FB Overvoltage Threshold Trip Point for Switch OFF 1.2 FB Bias Current 1.225 1.25 V 1.62 V 60 nA SWITCH CHARACTERISTICS Buck Switch RDS(ON) ITEST = 200 mA, BST-SW = 7 V Synchronous RDS(ON) ITEST = 200 mA Gate Drive UVLO VBST − VSW Rising 2.4 Gate Drive UVLO Hysteresis 0.8 1.8 Ω 0.45 1 Ω 3 3.6 260 V mV CURRENT LIMIT Current Limit Threshold 390 575 750 mA Current Limit Response Time Time to Switch Off 150 ns OFF-Time Generator (Test 1) FB = 0.1 V, VIN = 48 V 12 µs OFF-Time Generator (Test 2) FB = 1.0 V, VIN = 48 V 2.5 µs 165 °C 20 °C THERMAL SHUTDOWN Tsd Thermal Shutdown Temperature Thermal Shutdown Hysteresis (1) (2) All limits are specified by design. All electrical characteristics having room temperature limits are tested during production at TA = 25°C. All hot and cold limits are ensured by correlating the electrical characteristics to process and temperature variations and applying statistical process control. VCC provides self bias for the internal gate drive and control circuits. Device thermal limitations limit external loading. Submit Documentation Feedback Copyright © 2012–2014, Texas Instruments Incorporated Product Folder Links: LM34926 5 LM34926 SNVS847E – JUNE 2012 – REVISED DECEMBER 2014 www.ti.com 6.6 Switching Characteristics Typical values correspond to TJ = 25°C. Minimum and maximum limits apply over –40°C to 125°C junction temperature range unless otherwise stated. VIN = 48 V unless otherwise stated. MIN TYP MAX UNIT ON-TIME GENERATOR TON Test 1 VIN = 32 V, RON = 100 kΩ 270 350 460 ns TON Test 2 VIN = 48 V, RON = 100 kΩ 188 250 336 ns TON Test 3 VIN = 75 V, RON = 250 kΩ 250 370 500 ns TON Test 4 VIN = 10 V, RON = 250 kΩ 1880 3200 4425 ns MINIMUM OFF-TIME Minimum Off-Timer FB = 0 V 144 ns 6.7 Typical Characteristics 100 EFFICIENCY (%) 90 VIN=36V VIN=24V 80 VIN=48V 70 60 VOUT2=10V, IOUT1=0 50 50 6 100 150 200 250 LOAD CURRENT (mA) 300 Figure 1. Efficiency at 750 kHz, VOUT1 = 10 V Figure 2. VCC vs VIN Figure 3. VCC vs ICC Figure 4. ICC vs External VCC Submit Documentation Feedback Copyright © 2012–2014, Texas Instruments Incorporated Product Folder Links: LM34926 LM34926 www.ti.com SNVS847E – JUNE 2012 – REVISED DECEMBER 2014 Typical Characteristics (continued) Figure 5. TON vs VIN and RON Figure 6. TOFF (ILIM) vs VFB and VIN Figure 7. IIN vs VIN (Operating, Nonswitching) Figure 8. IIN vs VIN (Shutdown) Submit Documentation Feedback Copyright © 2012–2014, Texas Instruments Incorporated Product Folder Links: LM34926 7 LM34926 SNVS847E – JUNE 2012 – REVISED DECEMBER 2014 www.ti.com 7 Detailed Description 7.1 Overview The LM34926 step-down switching regulator features all the functions needed to implement a low-cost, efficient, isolated bias supply. This high-voltage regulator contains 100-V, N-channel buck and synchronous switches, is easy to implement, and is provided in thermally enhanced SO PowerPAD-8 and WSON-8 packages. The regulator operation is based on a constant on-time control scheme using an on-time inversely proportional to VIN. This control scheme does not require loop compensation. Current limit is implemented with forced off-time inversely proportional to VOUT. This scheme ensures short circuit protection while providing minimum foldback. The simplified block diagram of the LM34926 device is shown in Functional Block Diagram. The LM34926 device can be applied in numerous applications to efficiently regulate down higher voltages. This regulator is well suited for 48-V telecom and automotive power bus ranges. Protection features include: thermal shutdown, undervoltage lockout, minimum forced off-time, and an intelligent current limit. 7.2 Functional Block Diagram LM34926 START-UP REGULATOR VIN VCC V UVLO 20 µA 4.5V UVLO THERMAL SHUTDOWN UVLO 1.225V SD VDD REG BST 0.66V SHUTDOWN BG REF VIN DISABLE ON/OFF TIMERS RON 1.225V SW COT CONTROL LOGIC FEEDBACK FB OVER-VOLTAGE 1.62V RTN 8 CURRENT LIMIT ONE-SHOT ILIM COMPARATOR + VILIM Submit Documentation Feedback Copyright © 2012–2014, Texas Instruments Incorporated Product Folder Links: LM34926 LM34926 www.ti.com SNVS847E – JUNE 2012 – REVISED DECEMBER 2014 7.3 Feature Description 7.3.1 Control Overview The LM34926 regulator employs a control principle based on a comparator and a one-shot on-timer, with the output voltage feedback (FB) compared to an internal reference (1.225 V). If the FB voltage is below the reference the internal buck switch is switched on for the one-shot timer period, which is a function of the input voltage and the programming resistor (RT). Following the on-time the switch remains off until the FB voltage falls below the reference, and the forced minimum off-time has expired. When the FB pin voltage falls below the reference and the off-time one-shot period expires, the buck switch is then turned on for another on-time oneshot period. This continues until regulation is achieved and the FB voltage is approximately equal to 1.225 V (typical). In a synchronous buck converter, the low-side (sync) FET is on when the high-side (buck) FET is off. The inductor current ramps up when the high-side switch is on and ramps down when the high-side switch is off. There is no diode emulation feature in this IC, and therefore, the inductor current may ramp in the negative direction at light load. This causes the converter to operate in continuous conduction mode (CCM) regardless of the output loading. The operating frequency remains relatively constant with load and line variations. The operating frequency can be determined from Equation 1. VOUT1 f SW = .x RON where • K = 9 × 10–11 (1) The output voltage (VOUT) is set by two external resistors (RFB1, RFB2). The regulated output voltage is determined from Equation 2. VOUT = 1.225V x RFB2 + RFB1 RFB1 (2) This regulator regulates the output voltage based on ripple voltage at the feedback input, requiring a minimum amount of ESR for the output capacitor (COUT). A minimum of 25 mV of ripple voltage at the feedback pin (FB) is required for the LM34926 device. In cases where the capacitor ESR is too small, additional series resistance may be required (RC in Figure 9). For applications where lower output voltage ripple is required the output can be taken directly from a low ESR output capacitor, as shown in Figure 9. However, RC slightly degrades the load regulation. L1 VOUT SW LM34926 RFB2 FB RC + RFB1 COUT VOUT (low ripple) Figure 9. Low Ripple Output Configuration 7.3.2 VCC Regulator The LM34926 device contains an internal high-voltage linear regulator with a nominal output of 7.6 V. The input pin (VIN) can be connected directly to the line voltages up to 100 V. The VCC regulator is internally current limited to 30 mA. The regulator sources current into the external capacitor at VCC. This regulator supplies current to internal circuit blocks including the synchronous MOSFET driver and the logic circuits. When the voltage on the VCC pin reaches the UVLO threshold of 4.5 V, the IC is enabled. The VCC regulator contains an internal diode connection to the BST pin to replenish the charge in the gate drive boot capacitor when the SW pin is low. Submit Documentation Feedback Copyright © 2012–2014, Texas Instruments Incorporated Product Folder Links: LM34926 9 LM34926 SNVS847E – JUNE 2012 – REVISED DECEMBER 2014 www.ti.com Feature Description (continued) At high input voltages, the power dissipated in the high-voltage regulator is significant and can limit the overall achievable output power. As an example, with the input at 48 V and switching at high frequency, the VCC regulator may supply up to 7 mA of current resulting in 48 V × 7 mA = 336 mW of power dissipation. If the VCC voltage is driven externally by an alternate voltage source, from 8.55 V to 14 V, the internal regulator is disabled. This reduces the power dissipation in the IC. 7.3.3 Regulation Comparator The feedback voltage at FB is compared to an internal 1.225 V reference. In normal operation, when the output voltage is in regulation, an on-time period is initiated when the voltage at FB falls below 1.225 V. The high-side switch stays on for the on-time, causing the FB voltage to rise above 1.225 V. After the on-time period, the highside switch stays off until the FB voltage again falls below 1.225 V. During start-up, the FB voltage is below 1.225 V at the end of each on-time, causing the high-side switch to turn on immediately after the minimum forced off-time of 144 ns. The high-side switch can be turned off before the on-time is complete if peak current in the inductor reaches the current limit threshold. 7.3.4 Overvoltage Comparator The feedback voltage at FB is compared to an internal 1.62 V reference. If the voltage at FB rises above 1.62-V the on-time pulse is immediately terminated. This condition can occur if the input voltage and/or the output load changes suddenly. The high-side switch will not turn on again until the voltage at FB falls below 1.225 V. 7.3.5 On-Time Generator The on-time for the LM34926 device is determined by the RON resistor, and is inversely proportional to the input voltage (VIN), resulting in a nearly constant frequency as VIN is varied over its range. The on-time equation for the LM34926 is determined be Equation 3. TON = 10-10 x RON VIN (3) See Figure 5. RON should be selected for a minimum on-time (at maximum VIN) greater than 100 ns, for proper operation. This requirement limits the maximum frequency for each application. 7.3.6 Current Limit The LM34926 device contains an intelligent current limit off-timer. If the current in the buck switch exceeds 575 mA, the present cycle is immediately terminated, and a non-resetable off-timer is initiated. The length of offtime is controlled by the FB voltage and the input voltage VIN. As an example, when FB = 0 V and VIN = 48 V, a maximum off-time is set to 16 μs. This condition occurs when the output is shorted, and during the initial part of start-up. This amount of time ensures safe short circuit operation up to the maximum input voltage of 100 V. In cases of overload where the FB voltage is above zero volts (not a short circuit) the current limit off-time is reduced. Reducing the off-time during less severe overloads reduces the amount of foldback, recovery time, and start-up time. The off-time is calculated from Equation 4. 0.07 x VIN Ps TOFF(ILIM) = VFB + 0.2V (4) The current limit protection feature is peak limited, the maximum average output will be less than the peak. 7.3.7 N-Channel Buck Switch and Driver The LM34926 device integrates an N-channel buck switch and associated floating high voltage gate driver. The gate driver circuit works in conjunction with an external bootstrap capacitor and an internal high-voltage diode. A 0.01-uF ceramic capacitor connected between the BST and SW pins provides the voltage to the driver during the on-time. During each off-time, the SW pin is at approximately 0 V, and the bootstrap capacitor charges from VCC through the internal diode. The minimum off-timer, set to 144 ns, ensures a minimum time each cycle to recharge the bootstrap capacitor. 10 Submit Documentation Feedback Copyright © 2012–2014, Texas Instruments Incorporated Product Folder Links: LM34926 LM34926 www.ti.com SNVS847E – JUNE 2012 – REVISED DECEMBER 2014 Feature Description (continued) 7.3.8 Synchronous Rectifier The LM34926 device provides an internal synchronous N-Channel MOSFET rectifier. This MOSFET provides a path for the inductor current to flow when the high-side MOSFET is turned off. The synchronous rectifier has no diode emulation mode, and is designed to keep the regulator in continuous conduction mode even during light loads which would otherwise result in discontinuous operation. This feature specifically allows the user to design a secondary regulator using a transformer winding off the main inductor to generate the alternate regulated output voltage. 7.3.9 Undervoltage Detector The LM34926 device contains a dual-level UVLO circuit. A summary of threshold voltages and operational states is provided in Device Functional Modes. When the UVLO pin voltage is below 0.66 V, the controller is in a low current shutdown mode. When the UVLO pin voltage is greater than 0.66 V but less than 1.225 V, the controller is in standby mode. In standby mode the VCC bias regulator is active while the regulator output is disabled. When the VCC pin exceeds the VCC undervoltage thresholds and the UVLO pin voltage is greater than 1.225 V, normal operation begins. An external set-point voltage divider from VIN to GND can be used to set the minimum operating voltage of the regulator. UVLO hysteresis is accomplished with an internal 20-μA current source that is switched on or off into the impedance of the set-point divider. When the UVLO threshold is exceeded, the current source is activated to quickly raise the voltage at the UVLO pin. The hysteresis is equal to the value of this current times the resistance RUV2. If the UVLO pin is wired directly to the VIN pin, the regulator will begin operation once the VCC undervoltage is satisfied. VIN 2 VIN CIN + RUV2 LM34926 3 UVLO RUV1 Figure 10. UVLO Resistor Setting 7.3.10 Thermal Protection The LM34926 device should be operated so the junction temperature does not exceed 150°C during normal operation. An internal Thermal Shutdown circuit is provided to protect the LM34926 device in the event of a higher than normal junction temperature. When activated, typically at 165°C, the controller is forced into a lowpower reset state, disabling the buck switch and the VCC regulator. This feature prevents catastrophic failures from accidental device overheating. When the junction temperature falls below 145°C (typical hysteresis = 20°C), the VCC regulator is enabled, and normal operation is resumed. Submit Documentation Feedback Copyright © 2012–2014, Texas Instruments Incorporated Product Folder Links: LM34926 11 LM34926 SNVS847E – JUNE 2012 – REVISED DECEMBER 2014 www.ti.com Feature Description (continued) 7.3.11 Ripple Configuration LM34926 uses constant on-time (COT) control scheme, in which the on-time is terminated by an on-timer, and the off-time is terminated by the feedback voltage (VFB) falling below the reference voltage (VREF). Therefore, for stable operation, the feedback voltage must decrease monotonically, in phase with the inductor current during the off-time. Furthermore this change in feedback voltage (ΔVFB) during off-time must be large enough to suppress any noise component present at the feedback node. Table 1 shows three different methods for generating appropriate voltage ripple at the feedback node. Type 1 and Type 2 ripple circuits couple the ripple at the output of the converter to the feedback node (FB). The output voltage ripple has two components: 1. Capacitive ripple caused by the inductor current ripple charging and discharging the output capacitor. 2. Resistive ripple caused by the inductor current ripple flowing through the ESR of the output capacitor. The capacitive ripple is not in phase with the inductor current. As a result, the capacitive ripple does not decrease monotonically during the off-time. The resistive ripple is in phase with the inductor current and decreases monotonically during off-time. The resistive ripple must exceed the capacitive ripple at the output node (VOUT) for stable operation. If this condition is not satisfied, unstable switching behavior is observed in COT converters, with multiple on-time bursts in close succession followed by a long off-time. Type 3 ripple method uses Rr and Cr and the switch node (SW) voltage to generate a triangular ramp. This triangular ramp is AC-coupled using Cac to the feedback node (FB). Because this circuit does not use the output voltage ripple, it is ideally suited for applications where low output voltage ripple is required. See AN-1481 Controlling Output Ripple and Achieving ESR Independence in Constant On-Time (COT) Regulator Designs (SNVA166) for more details for each ripple generation method. Table 1. Ripple Configuration TYPE 1 LOWEST COST CONFIGURATION TYPE 2 REDUCED RIPPLE CONFIGURATION TYPE 3 MINIMUM RIPPLE CONFIGURATION VOUT VOUT L1 VOUT L1 L1 Cac R FB2 R FB2 RC To FB R FB1 R FB1 GND 25 mV VOUT x ûIL(MIN) VREF Cr R FB2 C OUT Cac To FB C OUT RC > Rr RC C OUT GND To FB R FB1 GND C> 5 gsw(RFB2||RFB1) 25 mV RC > ûIL(MIN) Cr = 3300 pF Cac = 100 nF (VIN(MIN) - VOUT) x TON R rC r < 25 mV 7.3.12 Soft Start A soft-start feature can be implemented with the LM34926 device using an external circuit. As shown in Figure 11, the soft-start circuit consists of one capacitor C1, two resistors R1 and R2, and a diode D. During the initial start-up, the VCC voltage is established before the VOUT voltage. Capacitor C1 is discharged and diode D is thereby forward biased to pull up the FB voltage. The FB voltage exceeds the reference voltage (1.225 V) and switching is therefore disabled. As capacitor C1 charges, the voltage at node B gradually decreases and switching commences. VOUT will gradually rise to maintain the FB voltage at the reference voltage. Once the voltage at node B is less than a diode drop above the FB voltage, the soft-start sequence is finished and D is reverse-biased. 12 Submit Documentation Feedback Copyright © 2012–2014, Texas Instruments Incorporated Product Folder Links: LM34926 LM34926 www.ti.com SNVS847E – JUNE 2012 – REVISED DECEMBER 2014 During the initial part of the start-up, the FB voltage can be approximated as shown in Equation 5. The effect of R1 has been ignored to simplify the calculation. VFB = (VCC - VD) x RFB1 x RFB2 R2 x (RFB1 + RFB2) + RFB1 x RFB2 (5) C1 is charged after the first start up. Diode D1 is optional and can be added to discharge C1 when the input voltage experiences a momentary drop to initialize the soft-start sequence. To achieve the desired soft start, the following design guidance is recommended: (1) R2 is selected so that VFB is higher than 1.225 V for a VCC of 4.5 V, but is lower than 5 V when VCC is 8.55 V. If an external VCC is used, VFB should not exceed 5 V at maximum VCC. (2) C1 is selected to achieve the desired start-up time which can be determined from . RFB1 x RFB2 ) tS = C1 x (R2 + RFB1 + RFB2 (3) R1 is used to maintain the node B voltage at zero after the soft start is finished. A value larger than the feedback resistor divider is preferred. The effect of resistor R1 is ignored. Using the component values shown in Figure 12, selecting C1 = 1 uF, R2 = 1 kΩ, R1 = 30 kΩ results in a softstart time of about 2 ms. VOUT VCC C1 RFB2 R2 To FB D D1 B RFB1 R1 Figure 11. Soft-Start Circuit 7.4 Device Functional Modes The UVLO pin controls the operating mode of the LM34926 device (see Table 2 for the detailed functional states). Table 2. UVLO Mode UVLO VCC MODE DESCRIPTION < 0.66 V Disabled Shutdown VCC regulator disabled. Switching disabled. 0.66 V — 1.225 V Enabled Standby VCC regulator enabled. Switching disabled. VCC < 4.5 V Standby VCC regulator enabled. Switching disabled. VCC > 4.5 V Operating > 1.225 V VCC enabled. Switching enabled. Submit Documentation Feedback Copyright © 2012–2014, Texas Instruments Incorporated Product Folder Links: LM34926 13 LM34926 SNVS847E – JUNE 2012 – REVISED DECEMBER 2014 www.ti.com 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information The LM34926 device is step-down DC-DC converter. The device is typically used to convert a higher DC voltage to a lower DC voltage with a maximum available output current of 300 mA. Use the following design procedure to select component values for the LM34926 device. Alternately, use the WEBENCH® software to generate a complete design. The WEBENCH software uses an iterative design procedure and accesses a comprehensive database of components when generating a design. This section presents a simplified discussion of the design process. 8.2 Typical Application Application Circuit: 20-V to 95-V Input and 10-V, 250-mA Output Isolated Fly-Buck™ Converter VOUT2 D1 + N2 COUT2 1 µF X1 LM34926 BST VIN 20V-95V 0.01 µF + CBST + 47 µH VOUT1 SW 46.4 kΩ 1 nF Rr Cr VIN CIN 1 µF N1 CBYP 0.1 µF + RON RUV2 127 kΩ RUV1 8.25 kΩ RON 130 kΩ 0.1 µF RTN COUT1 1 µF RFB2 VCC UVLO + Cac FB + D2 7.32 kΩ CVCC 1 µF RFB1 1 kΩ Figure 12. Isolated Fly-Buck Converter Using LM34926 14 Submit Documentation Feedback Copyright © 2012–2014, Texas Instruments Incorporated Product Folder Links: LM34926 LM34926 www.ti.com SNVS847E – JUNE 2012 – REVISED DECEMBER 2014 Typical Application (continued) 8.2.1 Design Requirements Selection of external components is illustrated through a design example. Table 3 lists the design example specifications. Table 3. Buck Converter Design Specifications DESIGN PARAMETERS VALUE Input Voltage Range 20 V to 95 V Primary Output Voltage 10 V Secondary (Isolated) Output Voltage 9.5 V Maximum Output Current (Primary + Secondary) 250 mA Maximum Power Output 2.5 W Nominal Switching Frequency 750 kHz 8.2.2 Detailed Design Procedure 8.2.2.1 Transformer Turns Ratio The transformer turns ratio is selected based on the ratio of the primary output voltage to the secondary (isolated) output voltage. In this design example, the two outputs are nearly equal and a 1:1 turns ratio transformer is selected. Therefore, N2 / N1 = 1. If the secondary (isolated) output voltage is significantly higher or lower than the primary output voltage, a turns ratio less than or greater than 1 is recommended. The primary output voltage is normally selected based on the input voltage range such that the duty cycle of the converter does not exceed 50% at the minimum input voltage. This condition is satisfied if VOUT1 < VIN_MIN / 2 8.2.2.2 Total IOUT The total primary referred load current is calculated by multiplying the isolated output loads by the turns ratio of the transformer as shown in Equation 6. N2 I OUT(MAX) = I OUT1 + I OUT2 ´ = 0.250 A (6) N1 8.2.2.3 RFB1, RFB2 The feedback resistors are selected to set the primary output voltage. The selected value for RFB1 is 1 kΩ. RFB2 can be calculated using the following equations to set VOUT1 to the specified value of 10 V. A standard resistor value of 7.32 kΩ is selected for RFB2. VOUT1 = 1.225V x (1 + RFB2 ) RFB1 (7) VOUT1 - 1) x RFB1 = 7.16 k: :RFB2 = ( 1.225 (8) 8.2.2.4 Frequency Selection Equation 1 is used to calculate the value of RON required to achieve the desired switching frequency. VOUT1 f SW = .x RON where • K = 9 × 10–11 (9) For VOUT1 of 10 V and fSW of 750 kHz, the calculated value of RON is 148 kΩ. A lower value of 130 kΩ is selected for this design to allow for second-order effects at high switching frequency that are not included in Equation 9. Submit Documentation Feedback Copyright © 2012–2014, Texas Instruments Incorporated Product Folder Links: LM34926 15 LM34926 SNVS847E – JUNE 2012 – REVISED DECEMBER 2014 www.ti.com 8.2.2.5 Transformer Selection A coupled inductor or a flyback-type transformer is required for this topology. Energy is transferred from primary to secondary when the low-side synchronous switch of the buck converter is conducting. The maximum inductor primary ripple current that can be tolerated without exceeding the buck switch peak current limit threshold (0.39-A minimum) is given by Equation 10. N2 ö æ DI L1 = ç 0.39 A - I OUT1 - I OUT2 ´ ´ 2 = 0.28 A N1 ÷ø è (10) Using the maximum peak-to-peak inductor ripple current ΔIL1 from Equation 10, the minimum inductor value is given by Equation 11. VIN(MAX) - VOUT VOUT ´ = 42.6 mH L1 = DI L1 ´ fSW VIN(MAX) (11) A higher value of 47 µH is selected to insure the high-side switch current does not exceed the minimum peak current limit threshold. 8.2.2.6 Primary Output Capacitor In a conventional buck converter the output ripple voltage is calculated as shown in Equation 12. f 'VOUT = 'IL1 x f x COUT1 (12) To limit the primary output ripple voltage ΔVOUT1 to approximately 50 mV, an output capcitor COUT1 of 0.93 µF is required. Figure 13 shows the primary winding current waveform (IL1) of a fly-buck converter. The reflected secondary winding current adds to the primary winding current during the buck switch off-time. Because of this increased current, the output voltage ripple is not the same as in conventional buck converter. The output capacitor value calculated in Equation 12 should be used as the starting point. Optimization of output capacitance over the entire line and load range must be done experimentally. If the majority of the load current is drawn from the secondary isolated output, a better approximation of the primary output voltage ripple is given by Equation 13. N2 ö æ ç I OUT2 ´ N1 ÷ ´ TON(MAX) è ø DVOUT1 = » 0.16 V COUT1 (13) TON(MAX) x IOUT2 x N2/N1 IL1 IOUT2 IL2 TON(MAX) x IOUT2 Figure 13. Current Waveforms for COUT1 Ripple Calculation A standard 1-µF, 25-V capacitor is selected for this design. If lower output voltage ripple is required, a higher value should be selected for COUT1 and/or COUT2. 16 Submit Documentation Feedback Copyright © 2012–2014, Texas Instruments Incorporated Product Folder Links: LM34926 LM34926 www.ti.com SNVS847E – JUNE 2012 – REVISED DECEMBER 2014 8.2.2.7 Secondary Output Capacitor A simplified waveform for secondary output current (IOUT2) is shown in Figure 14. IOUT2 IL2 TON(MAX) x IOUT2 Figure 14. Secondary Current Waveforms for COUT2 Ripple Calculation The secondary output current (IOUT2) is sourced by COUT2 during on-time of the buck switch, TON. Ignoring the current transition times in the secondary winding, the secondary output capacitor ripple voltage can be calculated using Equation 14. IOUT2 x TON (MAX) 'VOUT2 = COUT2 (14) For a 1:1 transformer turns ratio, the primary and secondary voltage ripple equations are identical. Therefore, COUT2 is chosen to be equal to COUT1 (1 µF) to achieve comparable ripple voltages on primary and secondary outputs. If lower output voltage ripple is required, a higher value should be selected for COUT1 and/or COUT2. 8.2.2.8 Type III Feedback Ripple Circuit Type III ripple circuit as described in Ripple Configuration is required for the Fly-Buck topology. Type I and Type II ripple circuits use series resistance and the triangular inductor ripple current to generate ripple at VOUT and the FB pin. The primary ripple current of a Fly-Buck is the combination or primary and reflected secondary currents as shown in Figure 13. In the fly-buck topology, Type I and Type II ripple circuits suffer from large jitter as the reflected load current affects the feedback ripple. VOUT L1 Rr Cac C OUT Cr R FB2 GND To FB R FB1 Figure 15. Type III Ripple Circuit Selecting the Type III ripple components using the equations from Ripple Configuration ensures that the FB pin ripple is be greater than the capacitive ripple from the primary output capacitor COUT1. The feedback ripple component values are chosen as shown in Equation 15. Cr = 1000 pF Cac = 0.1 PF RrCr d (VIN (MIN) - VOUT) x TON 50 mV (15) The calculated value for Rr is 66 kΩ. This value provides the minimum ripple for stable operation. A smaller resistance should be selected to allow for variations in TON, COUT1 and other components. For this design, Rr value of 46.4 kΩ is selected. Submit Documentation Feedback Copyright © 2012–2014, Texas Instruments Incorporated Product Folder Links: LM34926 17 LM34926 SNVS847E – JUNE 2012 – REVISED DECEMBER 2014 www.ti.com 8.2.2.9 Secondary Diode The reverse voltage across secondary-rectifier diode D1 when the high-side buck switch is off can be calculated using Equation 16. VD1 = N2 VIN N1 (16) For a VIN_MAX of 95 V and the 1:1 turns ratio of this design, a 100-V Schottky is selected. 8.2.2.10 VCC and Bootstrap Capacitor A 1-µF capacitor of 16-V or higher rating is recommended for the VCC regulator bypass capacitor. A good value for the BST pin bootstrap capacitor is 0.01-µF with a 16-V or higher rating. 8.2.2.11 Input Capacitor The input capacitor is typically a combination of a smaller bypass capacitor located near the regulator IC and a larger bulk capacitor. The total input capacitance should be large enough to limit the input voltage ripple to a desired amplitude. For input ripple voltage ΔVIN, CIN can be calculated using Equation 17. I OUT(MAX) CIN ³ 4 ´ f ´ DVIN (17) Choosing a ΔVIN of 0.5 V gives a minimum CIN of 0.167 μF. A standard value of 0.1 μF is selected for for CBYP in this design. A bulk capacitor of higher value reduces voltage spikes due to parasitic inductance between the power source to the converter. A standard value of 1 μF is selected for for CIN in this design. The voltage ratings of the two input capacitors should be greater than the maximum input voltage under all conditions. 8.2.2.12 UVLO Resistors UVLO resistors RUV1 and RUV2 set the undervoltage lockout threshold and hysteresis according to Equation 18 and Equation 19. VIN (HYS) = IHYS x RUV2 (18) VIN (UVLO, rising) = 1.225V x R ( RUV2 + 1) UV1 where • IHYS = 20 μA, typical (19) For a UVLO hysteresis of 2.5 V and UVLO rising threshold of 20 V, Equation 18 and Equation 19 require RUV1 of 8.25 kΩ and RUV2 of 127 kΩ and these values are selected for this design example. 8.2.2.13 VCC Diode Diode D2 is an optional diode connected between VOUT1 and the VCC regulator output pin. When VOUT1 is more than one diode drop greater than the VCC voltage, the VCC bias current is supplied from VOUT1. This results in reduced power losses in the internal VCC regulator which improves converter efficiency. VOUT1 must be set to a voltage at least one diode drop higher than 8.55 V (the maximum VCC voltage) if D2 is used to supply bias current. 18 Submit Documentation Feedback Copyright © 2012–2014, Texas Instruments Incorporated Product Folder Links: LM34926 LM34926 www.ti.com SNVS847E – JUNE 2012 – REVISED DECEMBER 2014 8.2.3 Application Curves VIN = 48 V IOUT1 = 0 mA VIN = 48 V IOUT1 = 0 Step Load on IOUT2 = 80 to 180 mA IOUT2 = 100 mA Figure 16. Steady State Waveform Figure 17. Step Load Response 100 EFFICIENCY (%) 90 VIN=36V VIN=24V 80 VIN=48V 70 60 VOUT2=10V, IOUT1=0 50 50 100 150 200 250 LOAD CURRENT (mA) 300 VOUT1 = 10 V Figure 18. Efficiency at 750 kHz Submit Documentation Feedback Copyright © 2012–2014, Texas Instruments Incorporated Product Folder Links: LM34926 19 LM34926 SNVS847E – JUNE 2012 – REVISED DECEMBER 2014 www.ti.com 9 Power Supply Recommendations LM34926 is a power-management device. The power supply for the device is any DC voltage source within the specified input range. 10 Layout 10.1 Layout Guidelines A proper layout is essential for optimum performance of the circuit. To ensure proper layout, observe the following guidelines: 1. CIN: The loop consisting of input capacitor (CIN), VIN pin, and RTN pin carries switching currents. Therefore, place the input capacitor close to the IC, directly across VIN and RTN pins, and the connections to these two pins should be direct to minimize the loop area. In general it is not possible to accommodate all of input capacitance near the IC. A good practice is to use a 0.1-μF or 0.47-μF capacitor directly across the VIN and RTN pins close to the IC, and the remaining bulk capacitor as close as possible (see Figure 19). 2. CVCC and CBST: The VCC and bootstrap (BST) bypass capacitors supply switching currents to the high and low-side gate drivers. Place these two capacitors as close to the IC as possible, and the connecting trace lengths and loop area should be minimized (see Figure 19). 3. The Feedback trace carries the output voltage information and a small ripple component that is necessary for proper operation of LM34926. Therefore take care while routing the feedback trace to avoid coupling any noise to this pin. In particular, feedback trace should not run close to magnetic components, or parallel to any other switching trace. 4. SW trace: SW node switches rapidly between VIN and GND every cycle and is therefore a possible source of noise. SW node area should be minimized. In particular SW node should not be inadvertently connected to a copper plane or pour. 10.2 Layout Example 8 SW 7 BST 3 6 VCC 4 5 FB RTN 1 VIN 2 UVLO RON CIN HSOP CVCC Figure 19. Placement of Bypass Capacitors 20 Submit Documentation Feedback Copyright © 2012–2014, Texas Instruments Incorporated Product Folder Links: LM34926 LM34926 www.ti.com SNVS847E – JUNE 2012 – REVISED DECEMBER 2014 11 Device and Documentation Support 11.1 Trademarks PowerPAD, Fly-Buck are trademarks of Texas Instruments. WEBENCH is a registered trademark of Texas Instruments. All other trademarks are the property of their respective owners. 11.2 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 11.3 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Documentation Feedback Copyright © 2012–2014, Texas Instruments Incorporated Product Folder Links: LM34926 21 PACKAGE OPTION ADDENDUM www.ti.com 20-Oct-2014 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) LM34926MR/NOPB ACTIVE SO PowerPAD DDA 8 95 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR S000XB LM34926MRX/NOPB ACTIVE SO PowerPAD DDA 8 2500 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR S000XB LM34926SD/NOPB ACTIVE WSON NGU 8 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM L34926 LM34926SDX/NOPB ACTIVE WSON NGU 8 4500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM L34926 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 20-Oct-2014 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 20-Oct-2014 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant LM34926MRX/NOPB SO Power PAD DDA 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 LM34926SD/NOPB WSON NGU 8 1000 178.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1 LM34926SDX/NOPB WSON NGU 8 4500 330.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 20-Oct-2014 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM34926MRX/NOPB LM34926SD/NOPB SO PowerPAD DDA 8 2500 367.0 367.0 35.0 WSON NGU 8 1000 210.0 185.0 35.0 LM34926SDX/NOPB WSON NGU 8 4500 367.0 367.0 35.0 Pack Materials-Page 2 MECHANICAL DATA DDA0008B MRA08B (Rev B) www.ti.com MECHANICAL DATA NGU0008B SDC08B (Rev A) www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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