ICST ICS271PGI Triple pll field programmable vcxo clock synthesizer Datasheet

PRELIMINARY INFORMATION
ICS271
Triple PLL Field Programmable VCXO Clock Synthesizer
Description
Features
The ICS271 field programmable VCXO clock
synthesizer generates up to six high-quality,
high-frequency clock outputs including multiple
reference clocks from a low-frequency crystal input. It
is designed to replace crystals and crystal oscillators in
most electronic systems.
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Using ICS’ VersaClockTM software to configure PLLs
and outputs, the ICS271 contains a One-Time
Programmable (OTP) ROM for field programmability.
Programming features include VCXO, eight selectable
configuration registers and up to two sets of three
low-skew outputs.
Each of the two output groups are powered by a
separate VDDO voltage. VDDO may vary from 1.8 V to
VDD.
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Packaged as 20-pin TSSOP
Eight addressable registers
Replaces multiple crystals and oscillators
Output frequencies up to 200 MHz at 3.3 V
Input crystal frequency of 5 to 27 MHz
Up to six reference outputs
Separate 1.8 to 3.3 V VDDO output level controls for
each bank of 3 outputs
Up to two sets of three low-skew outputs
Operating voltages of 3.3 V
Controllable output drive levels
Advanced, low-power CMOS process
Available in Pb (lead) free packaging
Using Phase-Locked Loop (PLL) techniques, the
device runs from a standard fundamental mode,
inexpensive crystal, or clock. It can replace VCXOs,
multiple crystals and oscillators, saving board space
and cost.
The ICS271 is also available in factory programmed
custom versions for high-volume applications.
Block Diagram
VDD
S2:S0
3
OTP
ROM
with
PLL
Values
3
VDDO1
PLL1
CLK1
CLK2
Divide
Logic
and
Output
Enable
Control
PLL2
VIN
CLK3
CLK4
CLK5
PLL3
X1
Voltage
Controlled
Crystal
Oscillator
Crystal
X2
CLK6
GND
External capacitors
are required.
2
VDDO2
PDTS
1
MDS 271 A
Integrated Circuit Systems, Inc.
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Revision 040705
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PRELIMINARY INFORMATION
ICS271
Triple PLL Field Programmable VCXO Clock Synthesizer
Pin Assignment
VIN
1
20
S2
S0
2
19
VDD
S1
VDD
3
18
PDTS
4
17
GND
VDDO1
5
16
CLK6
CLK1
6
15
CLK5
CLK2
7
14
CLK4
CLK3
GND
8
13
9
12
VDDO2
VDD
10
11
X2
X1
20 pin (173 mil) TSSOP
Pin Descriptions
Pin
Number
Pin
Name
Pin
Type
1
VIN
Input
2
S0
Input
3
S1
Input
4
VDD
Power
Select pin 1. Internal pull-up resistor.
Connect to +3.3 V.
5
VDDO1
Power
Power supply for outputs CLK1-CLK3. Must not exceed VDD.
6
CLK1
Output
Output clock 1. Weak internal pull-down when tri-state.
7
CLK2
Output
Output clock 2. Weak internal pull-down when tri-state.
8
CLK3
Output
Output clock 3. Weak internal pull-down when tri-state.
9
GND
Power
Connect to ground.
Pin Description
Voltage input to VCXO. Zero to 3.3 V signal which controls the VCXO
frequency
Select pin 0. Internal pull-up resistor.
10
X1
XI
Crystal input. Connect this pin to a crystal.
11
X2
XO
12
VDD
Power
Crystal Output. Connect this pin to a crystal.
Connect to +3.3 V.
13
VDDO2
Power
Power supply for outputs CLK4-CLK6. Must not exceed VDD.
14
CLK4
Output
Output clock 4. Weak internal pull-down when tri-state.
15
CLK5
Output
Output clock 5. Weak internal pull-down when tri-state.
16
CLK6
Output
Output clock 6. Weak internal pull-down when tri-state.
17
GND
Power
Connect to ground.
18
PDTS
Input
19
VDD
Power
Power-down tri-state. Powers down entire chip and tri-states clock outputs
when low. Internal pull-up resistor.
Connect to +3.3 V.
20
S2
Input
Select pin 2. Internal pull-up resistor.
2
MDS 271 A
Integrated Circuit Systems, Inc.
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525 Race Street, San Jose, CA 95126
Revision 040705
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PRELIMINARY INFORMATION
ICS271
Triple PLL Field Programmable VCXO Clock Synthesizer
External Components
Equivalent Series Resistance
The ICS271 requires a minimum number of external
components for proper operation.
Series Termination Resistor
Clock output traces over one inch should use series
termination. To series terminate a 50Ω trace (a
commonly used trace impedance), place a 33Ω resistor
in series with the clock line, as close to the clock output
pin as possible. The nominal impedance of the clock
output is 20Ω.
Decoupling Capacitors
As with any high-performance mixed-signal IC, the
ICS271 must be isolated from system power supply
noise to perform optimally.
Decoupling capacitors of 0.01µF must be connected
between each VDD, VDDO, and the PCB ground plane.
For optimum device performance, the decoupling
capacitor should be mounted on the component side of
the PCB. Avoid the use of vias on the decoupling
circuit.
Quartz Crystal
The ICS271 VCXO function consists of the external
crystal and the integrated VCXO oscillator circuit. To
assure the best system performance (frequency pull
range) and reliability, a crystal device with the
recommended parameters (shown below) must be
used, and the layout guidelines discussed in the
following section shown must be followed.
The frequency of oscillation of a quartz crystal is
determined by its “cut” and by the load capacitors
connected to it. The ICS271 incorporates on-chip
variable load capacitors that “pull” (change) the
frequency of the crystal. The crystal specified for use
with the ICS271 is designed to have zero frequency
error when the total of on-chip + stray capacitance is 14
pF.
Recommended Crystal Parameters:
Initial Accuracy at 25°C
Temperature Stability
Aging
Load Capacitance
Shunt Capacitance, C0
C0/C1 Ratio
The external crystal must be connected as close to the
chip as possible and should be on the same side of the
PCB as the ICS271. There should be no via’s between
the crystal pins and the X1 and X2 device pins. There
should be no signal traces underneath or close to the
crystal. See application note MAN05.
Crystal Tuning Load Capacitors
The crystal traces should include pads for small fixed
capacitors, one between X1 and ground, and another
between X2 and ground. Stuffing of these capacitors
on the PCB is optional. The need for these capacitors is
determined at system prototype evaluation, and is
influenced by the particular crystal used (manufacture
and frequency) and by PCB layout. The typical required
capacitor value is 1 to 4 pF.
To determine the need for and value of the crystal
adjustment capacitors, you will need a PC board of
your final layout, a frequency counter capable of about
1 ppm resolution and accuracy, two power supplies,
and some samples of the crystals which you plan to
use in production, along with measured initial accuracy
for each crystal at the specified crystal load
capacitance, CL.
To determine the value of the crystal capacitors:
1. Connect VDD of the ICS271 to 3.3 V. Connect pin 1
of the ICS271 to the second power supply. Adjust the
voltage on pin 1 to 0V. Measure and record the
frequency of the CLK output.
2. Adjust the voltage on pin 1 to 3.3 V. Measure and
record the frequency of the same output.
To calculate the centering error:
6 ( f3.0V – ft arg et ) + ( f0V – ft arg et )
Error = 10 x ----------------------------------------------------------------------- – errorxtal
ft arg et
Where:
ftarget = nominal crystal frequency
3
MDS 271 A
Integrated Circuit Systems, Inc.
±20 ppm
±30 ppm
±20 ppm
14 pf
7 pF Max
250 Max
35Ω Max
●
525 Race Street, San Jose, CA 95126
Revision 040705
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PRELIMINARY INFORMATION
ICS271
Triple PLL Field Programmable VCXO Clock Synthesizer
errorxtal =actual initial accuracy (in ppm) of the crystal
being measured
If the centering error is less than ±25 ppm, no
adjustment is needed. If the centering error is more
than 25 ppm negative, the PC board has excessive
stray capacitance and a new PCB layout should be
considered to reduce stray capacitance. (Alternately,
the crystal may be re-specified to a higher load
capacitance. Contact ICS for details.) If the centering
error is more than 25 ppm positive, add identical fixed
centering capacitors from each crystal pin to ground.
The value for each of these caps (in pF) is given by:
External Capacitor = 2 x (centering error)/(trim
sensitivity)
Trim sensitivity is a parameter which can be supplied by
your crystal vendor. If you do not know the value,
assume it is 30 ppm/pF. After any changes, repeat the
measurement to verify that the remaining error is
acceptably low (typically less than ±25 ppm).
ICS271 Configuration Capabilities
The architecture of the ICS271 allows the user to easily
configure the device to a wide range of output
frequencies, for a given input reference frequency.
The frequency multiplier PLL provides a high degree of
precision. The M/N values (the multiplier/divide values
available to generate the target VCO frequency) can be
set within the range of M = 1 to 1024 and N = 1 to
32,895.
The ICS271 also provides separate output divide
values, from 2 through 63, to allow the two output clock
banks to support widely differing frequency values from
the same PLL.
Each output frequency can be represented as:
OutputFreq
=
REFFreq
----⋅M
N
Each output clock bank has an separate voltage drive
control pin (VDDO1 and VDDO2) that sets the output
clock voltage swing.
Output Drive Control
The ICS271 has two output drive settings. For
VDDO=VDD, low drive should be selected when
outputs are less than 100 MHz. High drive should be
selected when outputs are greater than 100 MHz.
For VDDO<2.8 V, high drive should be selected for all
output frequencies.
(Consult the AC Electrical Characteristics for output
rise and fall times for each drive option.)
ICS VersaClock Software
ICS applies years of PLL optimization experience into a
user friendly software that accepts the user’s target
reference clock and output frequencies and generates
the lowest jitter, lowest power configuration, with only a
press of a button. The user does not need to have prior
PLL experience or determine the optimal VCO
frequency to support multiple output frequencies.
VersaClock software quickly evaluates accessible VCO
frequencies with available output divide values and
provides an easy to understand, bar code rating for the
target output frequencies. The user may evaluate
output accuracy, performance trade-off scenarios in
seconds.
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS271. These ratings, which
are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of the
device at these or any other conditions above those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can
affect product reliability. Electrical parameters are guaranteed only over the recommended operating
temperature range.
Parameter
Condition
Supply Voltage, VDD
Referenced to GND
Inputs
Referenced to GND
Clock Outputs
Referenced to GND
Typ.
Max.
Units
7
V
-0.5
VDD+0.5
V
-0.5
VDD+0.5
V
4
MDS 271 A
Integrated Circuit Systems, Inc.
Min.
●
525 Race Street, San Jose, CA 95126
Revision 040705
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tel (408) 297-1201
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PRELIMINARY INFORMATION
ICS271
Triple PLL Field Programmable VCXO Clock Synthesizer
Parameter
Condition
Min.
Storage Temperature
Typ.
Max.
Units
150
°C
260
°C
125
°C
-65
Soldering Temperature
Max 10 seconds
Junction Temperature
Recommended Operation Conditions
Parameter
Min.
Typ.
Max.
Units
Ambient Operating Temperature (ICS271PG/PGLF)
0
+70
°C
Ambient Operating Temperature (ICS271PGI/PGILF)
-40
+85
°C
Power Supply Voltage (measured in respect to GND)
+3.135
+3.465
V
4
ms
+3.3
Power Supply Ramp Time
Reference crystal parameters
Refer to page 3
DC Electrical Characteristics
Unless stated otherwise, VDD, VDDO = 3.3 V ±5%, Ambient Temperature -40 to +85°C
Parameter
Symbol
Operating Voltage
Conditions
Min.
VDD
VDDO Voltage
VDDO1 and VDDO2
Typ.
Max.
Units
3.135
3.465
V
1.80
VDD
V
Config. Dependent - See
VersaClockTM Estimates.
Operating Supply Current
Input High Voltage
IDD
mA
Six 33.3333 MHz outs,
VDD=VDDO=3.3 V;
PDTS = 1, no load, Note 1
25
mA
500
µA
V
Input High Voltage
VIH
PDTS = 0, no load
S2:S0
Input Low Voltage
VIL
S2:S0
Input High Voltage, PDTS
VIH
Input Low Voltage, PDTS
VIL
Input High Voltage
VIH
ICLK
Input Low Voltage
VIL
ICLK
Output High Voltage
(CMOS High)
VOH
IOH = -4 mA
Output High Voltage
VOH
IOH = -8 mA (Low Drive);
IOH = -12 mA (High Drive)
Output Low Voltage
VOL
IOL = 8 mA (Low Drive);
IOL = 12 mA (High Drive)
Short Circuit Current
IOS
Low Drive
±40
High Drive
±70
mA
20
Ω
Nom. Output Impedance
0.4
VDD-0.5
0.4
VDD/2+1
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525 Race Street, San Jose, CA 95126
V
V
VDD/2-1
V
VDD-0.4
V
2.4
VDDO-0.4
V
0.4
ZO
V
V
5
MDS 271 A
Integrated Circuit Systems, Inc.
VDD/2+1
V
Revision 040705
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PRELIMINARY INFORMATION
ICS271
Triple PLL Field Programmable VCXO Clock Synthesizer
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
Internal pull-up Resistor
RPUS
S2:S0, PDTS
190
kΩ
Internal pull-down
Resistor
RPD
CLK outputs
120
kΩ
Input Capacitance
CIN
Inputs
4
pF
Note 1: Example with 25 MHz crystal input with six outputs of 33.3 MHz, no load, and VDD = 3.3 V.
AC Electrical Characteristics
Unless stated otherwise, VDD, VDDO = 3.3 V ±5%, Ambient Temperature -40 to +85° C
Parameter
Symbol
Input Frequency
Conditions
FIN
Fundamental crystal
Output Frequency
Crystal Pullability
Min.
FP
Max. Units
5
27
MHz
VDDO=VDD
0.314
200
MHz
1.8V<VDDO<2.8
0.314
150
MHz
0V< VIN < 3.3 V, Note 1,
Config. Dependent
VCXO Gain
Typ.
100
ppm
VIN = VDD/2 + 1 V,
Note 1, Config.
Dependent
120
ppm/V
Output Rise/Fall Time
tOF
80% to 20%, high drive,
Note 2
1.0
ns
Output Rise/Fall Time
tOF
80% to 20%, low drive,
Note 2
2.0
ns
Output Clock Duty Cycle,
VDDO = 3.3 V
Note 3
40
49-51
60
%
4
10
ms
PDTS goes high until
stable CLK output
0.6
2
ms
Configuration Dependent
50
ps
Deviation from Mean.
Configuration Dependent
+200
ps
PLL lock-time from
power-up
Power-up time
One Sigma Clock Period Jitter
Maximum Absolute Jitter
tja
Pin-to-Pin Skew
Low Skew Outputs
-250
250
ps
Note 1: External crystal device must conform with Pullable Crystal Specifications listed on page 3.
Note 2: Measured with 15 pF load, VDDO = 3.3 V at VDDO/2.
Note 3: Duty Cycle is configuration dependent. Most configurations are min 45% / max 55%
6
MDS 271 A
Integrated Circuit Systems, Inc.
●
525 Race Street, San Jose, CA 95126
Revision 040705
●
tel (408) 297-1201
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PRELIMINARY INFORMATION
ICS271
Triple PLL Field Programmable VCXO Clock Synthesizer
Thermal Characteristics
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
Thermal Resistance Junction to
Ambient
θJA
Still air
93
°C/W
θJA
1 m/s air flow
78
°C/W
θJA
3 m/s air flow
65
°C/W
Thermal Resistance Junction to Case
θJC
20
°C/W
Marking Diagrams
Marking Diagrams (Pb free)
20
11
20
11
271PG
######
YYWW
271PGL
######
YYWW
1
10
1
10
20
11
20
11
271PGI
######
YYWW
271PGIL
######
YYWW
10
1
10
1
Notes:
1. ###### is the lot number.
2. YYWW is the last two digits of the year and week that the part was assembled.
3. “I” denotes industrial temperature range (if applicable).
4. “L” denotes Pb (lead) free package.
5. Bottom marking: country of origin.
7
MDS 271 A
Integrated Circuit Systems, Inc.
●
525 Race Street, San Jose, CA 95126
Revision 040705
●
tel (408) 297-1201
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PRELIMINARY INFORMATION
ICS271
Triple PLL Field Programmable VCXO Clock Synthesizer
Package Outline and Package Dimensions (20-pin TSSOP, 173 Mil. Body)
Package dimensions are kept current with JEDEC Publication No. 95
24
Millimeters
Symbol
E1
INDEX
AREA
Min
A
A1
A2
b
C
D
E
E1
e
L
α
E
1 2
D
Inches
Max
Min
—
1.20
0.05
0.15
0.80
1.05
0.19
0.30
0.09
0.20
6.40
6.60
6.40 BASIC
4.30
4.50
0.65 Basic
0.45
0.75
0°
8°
Max
—
.047
0.002
0.006
0.032
0.041
0.007
0.012
0.0035 0.008
0.252
0.260
0.252 BASIC
0.169
0.177
0.0256 Basic
.018
.030
0°
8°
A
A2
A1
c
- Ce
SEATING
PLANE
b
.10 (.004)
L
C
Ordering Information
Part / Order Number
Marking
Shipping Packaging
Package
Temperature
Tubes
20-pin TSSOP
0 to +70°C
ICS271PG
ICS271PGI
See page 7
Tubes
20-pin TSSOP
-40 to +85°C
ICS271PGLF
Tubes
20-pin TSSOP
0 to +70°C
ICS271PGILF
Tubes
20-pin TSSOP
-40 to +85°C
Parts that are ordered with a "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS)
assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would
result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial
applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary
environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any
circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or
critical medical instruments.
VersaClockTM is a trademark of Integrated Circuit Systems, Inc. All rights reserved.
8
MDS 271 A
Integrated Circuit Systems, Inc.
●
525 Race Street, San Jose, CA 95126
Revision 040705
●
tel (408) 297-1201
●
www.icst.com