CT O DU ODUC T R P PR TE O LE T I TU TE S E R I E S S B O XX UBS LE S CL7660X B I S I POS ERSIL INT ICL7662 CMOS Voltage Converter The Intersil ICL7662 is a monolithic high-voltage CMOS power supply circuit which offers unique performance advantages over previously available devices. The ICL7662 performs supply voltage conversion from positive to negative for an input range of +4.5V to +20.0V, resulting in complementary output voltages of -4.5V to -20V. Only 2 noncritical external capacitors are needed for the charge pump and charge reservoir functions. The ICL7662 can also function as a voltage doubler, and will generate output voltages up to +38.6V with a +20V input. Contained on chip are a series DC power supply regulator, RC oscillator, voltage level translator, four output power MOS switches. A unique logic element senses the most negative voltage in the device and ensures that the output NChannel switch source-substrate junctions are not forward biased. This assures latchup free operation. The oscillator, when unloaded, oscillates at a nominal frequency of 10kHz for an input supply voltage of 15.0V. This frequency can be lowered by the addition of an external capacitor to the “OSC” terminal, or the oscillator may be overdriven by an external clock. The “LV” terminal may be tied to GROUND to bypass the internal series regulator and improve low voltage (LV) operation. At medium to high voltages (+10V to +20V), the LV pin is left floating to prevent device latchup. DATASHEET FN3181 Rev.4.00 Jan 9, 2006 Features • No External Diode Needed Over Entire Temperature Range • Pin Compatible With ICL7660 • Simple Conversion of +15V Supply to -15V Supply • Simple Voltage Multiplication (VOUT = (-)nVIN) • 99.9% Typical Open Circuit Voltage Conversion Efficiency • 96% Typical Power Efficiency • Wide Operating Voltage Range 4.5V to 20.0V • Easy to Use - Requires Only 2 External Non-Critical Passive Components • Pb-Free Plus Anneal Available (RoHS Compliant) Applications • On Board Negative Supply for Dynamic RAMs • Localized Processor (8080 Type) Negative Supplies • Inexpensive Negative Supplies • Data Acquisition Systems • Up to -20V for Op Amps Pinouts ICL7662CBD-0 (SOIC) TOP VIEW TEST 1 NC 2 ICL7662CBD AND IBD (SOIC) TOP VIEW 14 V+ 13 OSC NC 1 14 V+ TEST 2 13 NC CAP+ 3 12 NC NC 3 NC 4 11 LV CAP+ 4 11 LV GND 5 10 NC GND 5 10 NC NC 6 9 NC NC 6 9 VOUT 8 VOUT NC 7 8 CAP- CAP- 7 12 OSC ICL7662 (PDIP) TOP VIEW FN3181 Rev.4.00 Jan 9, 2006 TEST 1 8 V+ CAP+ 2 7 OSC GND 3 6 LV CAP- 4 5 VOUT Page 1 of 11 ICL7662 Ordering Information PART NUMBER TEMP. RANGE (oC) PACKAGE PKG. DWG. # ICL7662CPA 0 to 70 8 Ld PDIP E8.3 ICL7662CPAZ (Note) 0 to 70 8 Ld PDIP* (Pb-free) E8.3 ICL7662CBD-0 0 to 70 14 Ld SOIC (N) M14.15 ICL7662CBD 0 to 70 14 Ld SOIC (N) M14.15 ICL7662IPA -40 to 85 8 Ld PDIP E8.3 ICL7662IBD -40 to 85 14 Ld SOIC (N) M14.15 *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing. applications. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. Functional Block Diagram V+ CAP+ RC OSCILLATOR 2 VOLTAGE LEVEL TRANSLATOR CAP- TEST VOUT P N OSC LV VOLTAGE REGULATOR FN3181 Rev.4.00 Jan 9, 2006 LOGIC NETWORK Page 2 of 11 ICL7662 Absolute Maximum Ratings Thermal Information Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22V Oscillator Input Voltage . . . . . . . . -0.3V to (V+ +0.3V) for V+ < 10V . . . . . . . . . . . . . . . . . (Note 2) (V+ -10V) to (V+ +0.3V) for V+ > 10V Current Into LV (Note 2). . . . . . . . . . . . . . . . . . . . 20A for V+ > 10V Output Short Duration . . . . . . . . . . . . . . . . . . . . . . . . . . .Continuous Thermal Resistance (Typical, Note 3) JA (oC/W) JC (oC/W) PDIP Package* . . . . . . . . . . . . . . . . . . 150 N/A Plastic SOIC Package . . . . . . . . . . . . . 120 N/A Maximum Lead Temperature (Soldering, 10s). . . . . . . . . . . . .300oC (SOIC - Lead Tips Only) *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing. applications. CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. Connecting any terminal to voltages greater than V+ or less than GND may cause destructive latchup. It is recommended that no inputs from sources operating from external supplies be applied prior to “power up” of ICL7660S. 2. JA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications PARAMETER V+ = 15V, TA = 25oC, COSC = 0, Unless Otherwise Specified. Refer to Figure 14. SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Supply Voltage Range - Lo V+L RL = 10k, LV = GND Min < TA < Max 4.5 - 11 V Supply Voltage Range - Hi V+H RL = 10k, LV = Open Min < TA < Max 9 - 20 V RL = , LV = Open TA = 25oC - 0.25 0.60 mA 0oC < TA < 70oC -40oC < TA < 85oC - 0.30 0.85 mA -55oC < TA < 125oC - 0.40 1.0 mA TA = 25oC - 60 100 0oC < TA < 70oC -40oC < TA < 85oC - 70 120 -55oC < TA < 125oC - 90 150 TA = 25oC - 20 150 A 0oC < TA < 70oC -40oC < TA < 85oC - 25 200 A -55oC < TA < 125oC - 30 250 A TA = 25oC - 125 200 0oC < TA < 70oC -40oC < TA < 85oC - 150 250 -55oC < TA < 125oC - 200 350 - 10 - kHz TA = 25oC 93 96 - % Min < TA < Max 90 95 - % Min < TA < Max 97 99.9 - % Supply Current Output Source Resistance Supply Current Output Source Resistance I+ RO I+ RO Oscillator Frequency FOSC Power Efficiency PEFF IO = 20mA, LV = Open V+ = 5V, RL = , LV = GND V+ = 5V, IO = 3mA, LV = GND RL = 2k Voltage Conversion Efficiency VoEf RL = Oscillator Sink or Source Current IOSC V+ = 5V (VOSC = 0V to +5V) - 0.5 - A V+ = 15V (VOSC = +5V to +15V) - 4.0 - A NOTE: 3. Pin 1 is a Test pin and is not connected in normal use. When the TEST pin is connected to V+, an internal transmission gate disconnects any external parasitic capacitance from the oscillator which would otherwise reduce the oscillator frequency from its nominal value. FN3181 Rev.4.00 Jan 9, 2006 Page 3 of 11 ICL7662 Typical Performance Curves (See Figure 14, Test Circuit) 190 LV = GND 150 130 110 90 70 50 150 130 110 90 70 30 2 4 6 8 10 12 V+ (V) 14 16 18 0 20 V+ = 5V IL = 3mA V+ = 15V IL = 20mA 25 6 70 125 OSCILLATOR FREQUENCY (Hz) OSCILLATOR FREQUENCY (kHz) 8 7 6 LV = GND 4 3 2 LV = OPEN 0 2 4 6 8 10 12 16 18 20 350 95 300 250 90 85 PEFF 200 RO 150 80 100 75 V+ = 5V IL = 3mA TA = 25oC 70 65 100 1K 10K 10K COSC = 0pF 5 14 50 100K FIGURE 4. POWER CONVERSION EFFICIENCY AND OUTPUT SOURCE RESISTANCE AS A FUNCTION OF OSCILLATOR FREQUENCY RL = TA = 25oC 9 12 FOSC (Hz) FIGURE 3. OUTPUT SOURCE RESISTANCE AS A FUNCTION OF TEMPERATURE 10 10 100 TEMPERATURE (oC) 11 8 FIGURE 2. OUTPUT SOURCE RESISTANCE AS A FUNCTION OF SUPPLY VOLTAGE POWER CONVERSION EFFICIENCY (%) 180 170 160 150 140 130 120 110 100 90 80 70 60 50 0 4 V+ (V) FIGURE 1. OUTPUT SOURCE RESISTANCE AS A FUNCTION OF SUPPLY VOLTAGE -20 2 V+ = 15V TA = 25oC RL = 1K 100 10 14 16 18 20 SUPPLY VOLTAGE (V) FIGURE 5. OSClLLATOR FREQUENCY vs SUPPLY VOLTAGE 1 10 100 1000 10K COSC (pF) FIGURE 6. FREQUENCY OF OSCILLATION AS A FUNCTION OF EXTERNAL OSCILLATOR CAPACITANCE NOTE: All typical values have been characterized but are not tested. FN3181 Rev.4.00 Jan 9, 2006 OUTPUT RESISTANCE () 0 OUTPUT RESISTANCE () LV = OPEN 50 LV = OPEN 30 -55 IL = 3mA TA = 25oC COSC = 0pF LV = GND 170 OUTPUT RESISTANCE () OUTPUT RESISTANCE () 170 190 IL = 20mA TA = 25oC COSC = 0pF Page 4 of 11 ICL7662 (See Figure 14, Test Circuit) (Continued) 15K V+ = 15V COSC = 0pF OUTPUT VOLTAGE VO (V) OSCILLATOR FREQUENCY (Hz) 14K 13K 12K 11K 10K 9K 8K 7K 6K 5K -55 -20 0 25 70 -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 -11 -12 -13 -14 -15 V+ = 15V TA = 25oC LV = OPEN SLOPE = 65 10 125 20 TEMPERATURE (oC) POWER CONVERSION EFFICIENCY (%) OUTPUT VOLTAGE VO (V) 100 0 -1 -2 -3 SLOPE = 14 -4 -5 2 4 6 8 10 12 14 LOAD CURRENT IL (mA) 16 18 V+ = 15V TA = 25oC 95 200 90 PBFF 85 160 I+ 80 120 75 80 70 40 65 0 10 20 30 40 50 60 70 80 LOAD CURRENT IL (mA) 90 100 FIGURE 11. SUPPLY CURRENT AND POWER CONVERSION EFFICIENCY AS A FUNCTION OF LOAD CURRENT FN3181 Rev.4.00 Jan 9, 2006 70 80 90 100 V+ = 5V TA = 25oC 95 90 40 PBFF 32 85 I+ 80 24 75 16 70 8 0 2 4 6 8 10 12 14 16 LOAD CURRENT IL (mA) 18 20 FIGURE 10. SUPPLY CURRENT AND POWER CONVERSION EFFICIENCY AS A FUNCTION OF LOAD SUPPLY CURRENT I+ (mA) POWER CONVERSION EFFICIENCY (%) FIGURE 9. OUTPUT VOLTAGE AS A FUNCTION OF LOAD CURRENT 100 60 65 20 OSCILLATOR FREQUENCY (kHz) 0 50 FIGURE 8. OUTPUT VOLTAGE AS A FUNCTION OF LOAD CURRENT V+ = 5V TA = 25oC LV = GND 1 40 LOAD CURRENT IL (mA) FIGURE 7. UNLOADED OSClLLATOR FREQUENCY AS A FUNCTION OF TEMPERATURE 2 30 SUPPLY CURRENT I+ (mA) Typical Performance Curves RL = TA = 25oC COSC = 0pF LV = GND 11 10 9 8 7 6 5 4 3 2 LV = OPEN 0 2 4 6 8 10 12 14 SUPPLY VOLTAGE (V) 16 18 FIGURE 12. FREQUENCY OF OSCILLATION AS A FUNCTION OF SUPPLY VOLTAGE Page 5 of 11 20 ICL7662 Typical Performance Curves (See Figure 14, Test Circuit) (Continued) SUPPLY CURRENT I+ (A) 150 140 130 120 110 100 90 80 70 60 50 40 30 20 10 10 100 1K OSCILLATOR FREQUENCY (Hz) 10K FIGURE 13. SUPPLY CURRENT AS A FUNCTION OF OSCILLATOR FREQUENCY NOTE: 4. These curves include in the supply current that current fed directly into the load RL from the V+ (See Figure 14). Thus, approximately half the supply current goes directly to the positive side of the load, and the other half, through the ICL7662, to the negative side of the load. Ideally, VOUT 2VIN, IS 2IL, so VIN x IS VOUT x IL. Circuit Description The ICL7662 contains all the necessary circuitry to complete a negative voltage converter, with the exception of 2 external capacitors which may be inexpensive 10F polarized electrolytic capacitors. The mode of operation of the device may be best understood by considering Figure 15, which shows an idealized negative voltage converter. Capacitor C1 is charged to a voltage, V+, for the half cycle when switches S1 and S3 are closed. (Note: Switches S2 and S4 are open during this half cycle.) During the second half cycle of operation, switches S2 and S4 are closed, with S1 and S3 open, thereby shifting capacitor C1 negatively by V+ volts. Charge is then transferred from C1 to C2 such that the voltage on C2 is exactly V+, assuming ideal switches and no load on C2. The lCL7662 approaches this ideal situation more closely than existing nonmechanical circuits. In the lCL7662, the 4 switches of Figure 15 are MOS power switches; S1 is a P-Channel device and S2, S3 and S4 are NChannel devices. The main difficulty with this approach is that in integrating the switches, the substrates of S3 and S4 must always remain reverse biased with respect to their sources, but not so much as to degrade their “ON” resistances. In addition, at circuit startup, and under output short circuit conditions (VOUT = V+), the output voltage must be sensed and the substrate bias adjusted accordingly. Failure to accomplish this would result in high power losses and probable device latchup. The voltage regulator portion of the ICL7662 is an integral part of the anti-latchup circuitry, however its inherent voltage drop can degrade operation at low voltages. Therefore, to improve low voltage operation the “LV” pin should be connected to GROUND, disabling the regulator. For supply voltages greater than 10V the LV terminal must be left open to insure latchup proof operation, and prevent device damage. IS 1 2 C1 + - ICL7662 7 3 6 4 5 V+ (+5V) 8 IL RL COSC (NOTE) -VOUT C2 10F + NOTE: For large value of COSC (> 1000pF) the values of C1 and C2 should be increased to 100F. FIGURE 14. ICL7662 TEST CIRCUIT This problem is eliminated in the ICL7662 by a logic network which senses the output voltage (VOUT) together with the level translators, and switches the substrates of S3 and S4 to the correct level to maintain necessary reverse bias. FN3181 Rev.4.00 Jan 9, 2006 Page 6 of 11 ICL7662 VIN S1 8 C1 3 A 1N914 or similar diode placed in parallel with C2 will prevent the device from latching up under these conditions. (Anode pin 5, Cathode pin 3). S2 2 3 Typical Applications Simple Negative Voltage Converter C2 S4 S3 VOUT = -VIN 4 5 7 FIGURE 15. IDEALIZED NEGATIVE CONVERTER Theoretical Power Efficiency Considerations In theory a voltage multiplier can approach 100% efficiency if certain conditions are met: 1. The drive circuitry consumes minimal power. 2. The output switches have extremely low ON resistance and virtually no offset. 3. The impedances of the pump and reservoir capacitors are negligible at the pump frequency. The ICL7662 approaches these conditions for negative voltage multiplication if large values of C1 and C2 are used. ENERGY IS LOST ONLY IN THE TRANSFER OF CHARGE BETWEEN CAPACITORS IF A CHANGE IN VOLTAGE OCCURS. The energy lost is defined by: E = 1/2C1 (V12 - V22) where V1 and V2 are the voltages on C1 during the pump and transfer cycles. If the impedances of C1 and C2 are relatively high at the pump frequency (refer to Figure 15) compared to the value of RL , there will be a substantial difference in the voltages V1 and V2 . Therefore it is not only desirable to make C2 as large as possible to eliminate output voltage ripple, but also to employ a correspondingly large value for C1 in order to achieve maximum efficiency of operation. Do’s and Don’ts 1. Do not exceed maximum supply voltages. 2. Do not connect LV terminal to GROUND for supply voltages greater than 10V. 3. When using polarized capacitors, the + terminal of C1 must be connected to pin 2 of the ICL7662 and the + terminal of C2 must be connected to GROUND. 4. If the voltage supply driving the 7662 has a large source impedance (25 - 30), then a 2.2F capacitor from pin 8 to ground may be required to limit rate of rise of input voltage to less than 2V/s. 5. User should insure that the output (pin 5) does not go more positive than GND (pin 3). Device latch up will occur under these conditions. FN3181 Rev.4.00 Jan 9, 2006 The majority of applications will undoubtedly utilize the ICL7662 for generation of negative supply voltages. Figure 16 shows typical connections to provide a negative supply where a positive supply of +4.5V to 20.0V is available. Keep in mind that pin 6 (LV) is tied to the supply negative (GND) for supply voltages below 10V. The output characteristics of the circuit in Figure 16A can be approximated by an ideal voltage source in series with a resistance as shown in Figure 16B. The voltage source has a value of -(V+). The output impedance (RO) is a function of the ON resistance of the internal MOS switches (shown in Figure 2), the switching frequency, the value of C1 and C2, and the ESR (equivalent series resistance) of C1 and C2. A good first order approximation for RO is: RO 2(RSW1 + RSW3 + ESRC1) + 2(RSW2 + RSW4 + ESRC1) + (fPUMP = fOSC , 2 1 fPUMP x C1 + ESRC2 RSWX = MOSFET switch resistance) Combining the four RSWX terms as RSW, we see that RO 2 x RSW + 1 fPUMP x C1 + 4 x ESRC1 + ESRC2 RSW , the total switch resistance, is a function of supply voltage and temperature (See the Output Source Resistance graphs), typically 24 at +25oC and 15V, and 53 at +25oC and 5V. Careful selection of C1 and C2 will reduce the remaining terms, minimizing the output impedance. High value capacitors will reduce the 1/(fPUMP x C1) component, and low FSR capacitors will lower the ESR term. Increasing the oscillator frequency will reduce the 1/(fPUMP x C1) term, but may have the side effect of a net increase in output impedance when C1 > 10F and there is no longer enough time to fully charge the capacitors every cycle. In a typical application where fOSC = 10kHz and C = C1 = C2 = 10F: RO 2 x 23 + 1 (5 x 103 x 10 x 10-6) + 4 ESRC1 + ESRC2 RO 46 + 20 + 5 x ESRC Since the ESRs of the capacitors are reflected in the output impedance multiplied by a factor of 5, a high value could potentially swamp out a low 1/(fPUMP x C1) term, rendering an increase in switching frequency or filter capacitance ineffective. Typical electrolytic capacitors may have ESRs as high as 10. Page 7 of 11 ICL7662 Again, a low ESR capacitor will result in a higher performance output. V+ 10F C1 + - 1 8 2 7 ICL7662 3 6 4 5 Paralleling Devices RO Any number of ICL7662 voltage converters may be paralleled (Figure 18) to reduce output resistance. The reservoir capacitor, C2, serves all devices while each device requires its own pump capacitor, C1. The resultant output resistance would be approximately: VOUT V+ VOUT = -V+ + C 10F + 2 16A. 16B. ROUT = FIGURE 16. SIMPLE NEGATIVE CONVERTER AND ITS OUTPUT EQUIVALENT ROUT (of ICL7662) n (number of devices) Cascading Devices The ICL7662 may be cascaded as shown in Figure 19 to produce larger negative multiplication of the initial supply voltage. However, due to the finite efficiency of each device, the practical limit is 10 devices for light loads. The output voltage is defined by: Output Ripple ESR also affects the ripple voltage seen at the output. The total ripple is determined by 2V, A and B, as shown in Figure 16. Segment A is the voltage drop across the ESR of C2 at the instant it goes from being charged by C1 (current flowing into C2) to being discharged through the load (current flowing out of C2). The magnitude of this current change is 2 x IOUT, hence the total drop is 2 x IOUT x ESRC2V. Segment B is the voltage change across C2 during time t2 , the half of the cycle when C2 supplies current the load. The drop at B is IOUT x t2 /C2V. The peak-to-peak ripple voltage is the sum of these voltage drops: VOUT = -n(VIN), where n is an integer representing the number of devices cascaded. The resulting output resistance would be approximately the weighted sum of the individual ICL7662 ROUT values. 1 V RIPPLE ----------------------------------------- + 2 ESRC 2 I OUT 2 f PUMP C 2 t1 t2 B 0 V A -(V+) FIGURE 17. OUTPUT RIPPLE V+ 1 2 C1 3 4 8 ICL7662 “1” 7 1 6 5 2 C1 3 8 ICL7662 “N” 4 RL 7 6 5 C + 2 FIGURE 18. PARALLELING DEVICES FN3181 Rev.4.00 Jan 9, 2006 Page 8 of 11 ICL7662 1 2 10F + 3 - V+ 8 7 ICL7662 “1” 1 6 4 5 2 10F + - 3 8 ICL7662 “N” 4 7 6 5 - 10F + + VOUT 10F FIGURE 19. CASCADING DEVICES FOR INCREASED OUTPUT VOLTAGE Changing the ICL7662 Oscillator Frequency V+ It may be desirable in some applications, due to noise or other considerations, to increase the oscillator frequency. This is achieved by overdriving the oscillator from an external clock, as shown in Figure 20. In order to prevent possible device latchup, a 1k resistor must be used in series with the clock output. In the situation where the designer has generated the external clock frequency using TTL logic, the addition of a 10k pullup resistor to V+ supply is required. Note that the pump frequency with external clocking, as with internal clocking, will be 1/2 of the clock frequency. Output transitions occur on the positive-going edge of the clock. V+ 1 2 10F + - 8 ICL7662 V+ 1k CMOS GATE 7 3 6 4 5 + VOUT 10F FIGURE 20. EXTERNAL CLOCKING It is also possible to increase the conversion efficiency of the ICL7662 at low load levels by lowering the oscillator frequency. This reduces the switching losses, and is achieved by connecting an additional capacitor, COSC, as shown in Figure 21. However, lowering the oscillator frequency will cause an undesirable increase in the impedance of the pump (C1) and reservoir (C2) capacitors; this is overcome by increasing the values of C1 and C2 by the same factor that the frequency has been reduced. For example, the addition of a 100pF capacitor between pin 7 (OSC) and V+ will lower the oscillator frequency to 1kHz from its nominal frequency of 10kHz (a multiple of 10), and thereby necessitate a corresponding increase in the value of C1 and C2 (from 10mF to 100mF). 1 2 + C1 - 8 ICL7662 COSC 7 3 6 4 5 + VOUT C2 FIGURE 21. LOWERING OSCILLATOR FREQUENCY Positive Voltage Doubling The ICL7662 may be employed to achieve positive voltage doubling using the circuit shown in Figure 22. In this application, the pump inverter switches of the ICL7662 are used to charge C1 to a voltage level of V+ -VF (where V+ is the supply voltage and VF is the forward voltage drop of diode D1). On the transfer cycle, the voltage on C1 plus the supply voltage (V+) is applied through diode C2 to capacitor C2. The voltage thus created on C2 becomes (2V+) (2VF) or twice the supply voltage minus the combined forward voltage drops of diodes D1 and D2. The source impedance of the output (VOUT) will depend on the output current, but for V+ = 15V and an output current of 10mA it will be approximately 70. V+ 1 2 8 ICL7662 7 3 6 4 5 D1 D2 VOUT = (2V+) - (2VF) + C1 - + - C2 NOTE: D1 and D2 can be any suitable diode. FIGURE 22. POSITIVE VOLTAGE DOUBLER FN3181 Rev.4.00 Jan 9, 2006 Page 9 of 11 ICL7662 Regulated Negative Voltage Supply V+ 1 2 C1 + - VOUT = - (nVIN - VFDX) 8 ICL7662 7 3 6 4 5 - + C2 D1 C + 3 D2 VOUT = (2V+) (VFD1) - (VFD2) + C - 4 FIGURE 23. COMBINED NEGATIVE CONVERTER AND POSITIVE DOUBLER Combined Negative Voltage Conversion and Positive Supply Doubling Figure 23 combines the functions shown in Figure 16 and Figure 22 to provide negative voltage conversion and positive voltage doubling simultaneously. This approach would be, for example, suitable for generating +9V and -5V from an existing +5V supply. In this instance capacitors C1 and C3 perform the pump and reservoir functions respectively for the generation of the negative voltage, while capacitors C2 and C4 are pump and reservoir respectively for the doubled positive voltage. There is a penalty in this configuration which combines both functions, however, in that the source impedances of the generated supplies will be somewhat higher due to the finite impedance of the common charge pump driver at pin 2 of the device. In some cases, the output impedance of the ICL7662 can be a problem, particularly if the load current varies substantially. The circuit of Figure 25 can be used to overcome this by controlling the input voltage, via an ICL7611 low-power CMOS op amp, in such a way as to maintain a nearly constant output voltage. Direct feedback is inadvisable, since the ICL7662s output does not respond instantaneously to a change in input, but only after the switching delay. The circuit shown supplies enough delay to accommodate the ICL7662, while maintaining adequate feedback. An increase in pump and storage capacitors is desirable, and the values shown provides an output impedance of less than 5 to a load of 10mA. Other Applications Further information on the operation and use of the ICL7662 may be found in AN051 “Principles and Applications of the ICL7660 CMOS Voltage Converter”. 1 V+ - VVOUT = 2 50F 8 2 + - RL2 + 50F 7 ICL7662 3 6 4 5 V- FIGURE 24. SPLITTING A SUPPLY IN HALF Voltage Splitting The bidirectional characteristics can also be used to split a higher supply in half, as shown in Figure 24. The combined load will be evenly shared between the two sides and, a high value resistor to the LV pin ensures start-up. Because the switches share the load in parallel, the output impedance is much lower than in the standard circuits, and higher currents can be drawn from the device. By using this circuit, and then the circuit of Figure 19, +30V can be converted (via +15V, and -15V) to a nominal -30V, although with rather high series output resistance (~250). 50F RL1 V+ + 50K +8V 56K - +8V 50K + 100 10F 100K ICL7611 + 1 2 ICL8069 100F + - 800K 8 7 ICL7662 3 6 4 5 250K VOLTAGE ADJUST VOUT 100F + FIGURE 25. REGULATING THE OUTPUT VOLTAGE FN3181 Rev.4.00 Jan 9, 2006 Page 10 of 11 ICL7662 © Copyright Intersil Americas LLC 2006. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN3181 Rev.4.00 Jan 9, 2006 Page 11 of 11